coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

New patch to review for coreboot: Documentation: x86 MTRR setup, TempRamExit and MTRR loading
by Leroy P Leahy 16 Mar '16

16 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14113 -gerrit commit e3fe47ed9d828198c6dbe0c27c5c9b1d2d3f8d5c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 31 12:19:13 2016 -0800 Documentation: x86 MTRR setup, TempRamExit and MTRR loading Document how to test TempRamExit and verify the MTRR setup and loading. TEST=None Change-Id: I57a604fa139edac4b05453547d3caf185db491e0 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/development.html | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index a36acaa..a2ba278 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -97,6 +97,7 @@ <li>Disable the <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a> </li> + <li>Enable CONFIG_DISPLAY_MTRRS to verify the MTRR configuration</li> <li> Implement the .init routine for the <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> @@ -115,6 +116,7 @@ Implement the <a target="_blank" href="SoC/soc.html#MemoryMap">memory map</a> </li> + <li>coreboot should now attempt to load the payload</li> </ol> @@ -185,6 +187,20 @@ <td>coreboot displays the memory map correctly during the BS_WRITE_TABLES state</td> </tr> <tr> + <td>MTRRs</td> + <td> + Set values: src/drivers/intel/fsp1_1/stack.c/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">setup_stack_and_mtrrs</a><br> + Load values: src/drivers/intel/fsp1_1/<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a> + </td> + <td>Set: Post code 0x91 + (<a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/cons…">POST_FSP_TEMP_RAM_EXIT</a>) + is displayed by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a><br> + Load: Post code 0x3C is displayed by + <a target="_blank" href="https://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/drivers/inte…">after_raminit.S</a><br> + and CONFIG_DISPLAY_MTRRS=y displays the correct memory regions</td> + </tr> + <tr> <td>PCI Device Support</td> <td>Implement a PCI <a target="_blank" href="SoC/soc.html#DeviceDrivers">device driver</a></td> <td>The device is detected by coreboot and usable by the payload</td>

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New patch to review for coreboot: Documentation: x86 shadow ROM disable
by Leroy P Leahy 16 Mar '16

16 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14112 -gerrit commit c55a0cb91caf68b3f4d5cf1a53ac346017ef037c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Jan 31 11:28:06 2016 -0800 Documentation: x86 shadow ROM disable Add documentation on disabling the SPI flash which is mapped (shadowed) into the x86 address space at 0x000e0000 - 0x000fffff. TEST=None Change-Id: I1d94d84c6cade97886a3274a7e7403f7b3275c5a Signed-off-by: Lee Leahy <Leroy.P.Leahy(a)intel.com> --- Documentation/Intel/SoC/soc.html | 14 +++++++++++++- Documentation/Intel/development.html | 12 +++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 2380cdf..8f1d75c 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -24,6 +24,7 @@ <li>Enable <a href="#SerialOutput">Serial Output"</a></li> <li>Get the <a href="#PreviousSleepState">Previous Sleep State</a></li> <li>Add the <a href="#MemoryInit">MemoryInit</a> Support</li> + <li>Disable the <a href="#DisableShadowRom">Shadow ROM</a></li> </ol> </li> <li><a href="#Ramstage">Ramstage</a> @@ -389,6 +390,17 @@ Use the following steps to debug the call to TempRamInit: </ol> +<h2><a name="DisableShadowRom">Disable Shadow ROM</a></h2> +<p> + A shadow of the SPI flash part is mapped from 0x000e0000 to 0x000fffff. + This shadow needs to be disabled to allow RAM to properly respond to + this address range. +</p> +<ol> + <li>Edit romstage/romstage.c and add the soc_after_ram_init routine</li> +</ol> + + <hr> <h1><a name="Ramstage">Ramstage</a></h1> @@ -717,6 +729,6 @@ Use the following steps to debug the call to TempRamInit: </table> <hr> -<p>Modified: 28 February 2016</p> +<p>Modified: 4 March 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 7b82321..a36acaa 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -94,6 +94,9 @@ </li> </ol> </li> + <li>Disable the + <a target="_blank" href="SoC/soc.html#DisableShadowRom">Shadow ROM</a> + </li> <li> Implement the .init routine for the <a target="_blank" href="SoC/soc.html#ChipOperations">chip operations</a> @@ -198,6 +201,13 @@ for the PCI devices on the bus. </td> </tr> + <tr> + <td>ROM Shadow<br>0x000E0000 - 0x000FFFFF</td> + <td> + Disable: src/soc/<Vendor>/<Chip Family>/romstage/romstage.c/<a target="_blank" href="SoC/soc.html#DisableShadowRom">soc_after_ram_init routine</a> + </td> + <td>Operates as RAM: Writes followed by a read to the 0x000E0000 - 0x000FFFFF region returns the value written</td> + </tr> <tr bgcolor="#c0ffc0"> @@ -346,6 +356,6 @@ <hr> -<p>Modified: 24 February 2016</p> +<p>Modified: 4 March 2016</p> </body> </html> \ No newline at end of file

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New patch to review for coreboot: coreboot_tables: Extend serial port description
by Leroy P Leahy 16 Mar '16

16 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14111 -gerrit commit 925172602a481ffe92734afcab5007e687cc788f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Mar 16 10:21:59 2016 -0700 coreboot_tables: Extend serial port description Extend the serial port description to include the input clock frequency and an identifier for the serial port. Without the input frequency it is impossible for the payload to compute the baud-rate divisor without making an assumption about the frequency. This breaks down when the UART is able to support multiple input clock frequencies. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Load the SPI driver stack * Testing is successful when CorebootPayloadPkg is able to properly initialize the serial port without using built-in values. Change-Id: I05a7e864afcd930916658e3efed53ff2efd403ec Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- payloads/libpayload/include/coreboot_tables.h | 2 ++ src/commonlib/include/commonlib/coreboot_tables.h | 2 ++ src/drivers/uart/Kconfig | 13 +++++++++++++ src/drivers/uart/oxpcie_early.c | 11 +++++++++++ src/drivers/uart/pl011.c | 2 ++ src/drivers/uart/uart8250io.c | 2 ++ src/drivers/uart/uart8250mem.c | 14 +++++++++++++- src/include/console/uart.h | 1 - src/lib/coreboot_table.c | 2 ++ src/soc/intel/quark/Kconfig | 10 ++++++++++ src/soc/intel/quark/uart_common.c | 7 ++----- 11 files changed, 59 insertions(+), 7 deletions(-) diff --git a/payloads/libpayload/include/coreboot_tables.h b/payloads/libpayload/include/coreboot_tables.h index 276f25f..06d1768 100644 --- a/payloads/libpayload/include/coreboot_tables.h +++ b/payloads/libpayload/include/coreboot_tables.h @@ -121,6 +121,8 @@ struct cb_serial { u32 baseaddr; u32 baud; u32 regwidth; + u32 input_hertz; + u32 id; }; #define CB_TAG_CONSOLE 0x00010 diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index 5c28791..3839028 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -173,6 +173,8 @@ struct lb_serial { uint32_t baseaddr; uint32_t baud; uint32_t regwidth; + uint32_t input_hertz; + uint32_t id; }; #define LB_TAG_CONSOLE 0x0010 diff --git a/src/drivers/uart/Kconfig b/src/drivers/uart/Kconfig index f4ad011..2a17893 100644 --- a/src/drivers/uart/Kconfig +++ b/src/drivers/uart/Kconfig @@ -41,3 +41,16 @@ config DRIVERS_UART_PL011 bool default n select HAVE_UART_SPECIAL + +config UART_INPUT_CLOCK_HERTZ + int + default 0 + help + UART divider's input clock frequency + +config UART_DEVICE_ID + hex + default 0 + help + ID to help the payload identify the proper UART + diff --git a/src/drivers/uart/oxpcie_early.c b/src/drivers/uart/oxpcie_early.c index eb91d31..0f322f7 100644 --- a/src/drivers/uart/oxpcie_early.c +++ b/src/drivers/uart/oxpcie_early.c @@ -85,6 +85,15 @@ void oxford_remap(u32 new_base) uart0_base = new_base + 0x1000; } +/* Return the clock frequency UART uses as reference clock for + * baudrate generator. */ +static inline unsigned int uart_divisor_clock(void) +{ + if (CONFIG_UART_INPUT_CLOCK_HERTZ) + return CONFIG_UART_INPUT_CLOCK_HERTZ; + return uart_platform_refclk(); +} + void uart_fill_lb(void *data) { struct lb_serial serial; @@ -92,6 +101,8 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + serial.input_hertz = uart_divisor_clock(); + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/pl011.c b/src/drivers/uart/pl011.c index aa55c68..8f51f18 100644 --- a/src/drivers/uart/pl011.c +++ b/src/drivers/uart/pl011.c @@ -48,6 +48,8 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + serial.input_hertz = CONFIG_UART_INPUT_CLOCK_HERTZ; + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/drivers/uart/uart8250io.c b/src/drivers/uart/uart8250io.c index 63bc42f..3a65b90 100644 --- a/src/drivers/uart/uart8250io.c +++ b/src/drivers/uart/uart8250io.c @@ -139,6 +139,8 @@ void uart_fill_lb(void *data) serial.baseaddr = uart_platform_base(CONFIG_UART_FOR_CONSOLE); serial.baud = default_baudrate(); serial.regwidth = 1; + serial.input_hertz = CONFIG_UART_INPUT_CLOCK_HERTZ; + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250, data); diff --git a/src/drivers/uart/uart8250mem.c b/src/drivers/uart/uart8250mem.c index 278ddb8..61ff817 100644 --- a/src/drivers/uart/uart8250mem.c +++ b/src/drivers/uart/uart8250mem.c @@ -110,6 +110,15 @@ static void uart8250_mem_init(void *base, unsigned divisor) uart8250_write(base, UART8250_LCR, CONFIG_TTYS0_LCS); } +/* Return the clock frequency UART uses as reference clock for + * baudrate generator. */ +static inline unsigned int uart_divisor_clock(void) +{ + if (CONFIG_UART_INPUT_CLOCK_HERTZ) + return CONFIG_UART_INPUT_CLOCK_HERTZ; + return uart_platform_refclk(); +} + void uart_init(int idx) { void *base = uart_platform_baseptr(idx); @@ -117,7 +126,8 @@ void uart_init(int idx) return; unsigned int div; - div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16); + div = uart_baudrate_divisor(default_baudrate(), uart_divisor_clock(), + 16); uart8250_mem_init(base, div); } @@ -156,6 +166,8 @@ void uart_fill_lb(void *data) serial.regwidth = sizeof(uint32_t); else serial.regwidth = sizeof(uint8_t); + serial.input_hertz = uart_divisor_clock(); + serial.id = CONFIG_UART_DEVICE_ID; lb_add_serial(&serial, data); lb_add_console(LB_TAG_CONSOLE_SERIAL8250MEM, data); diff --git a/src/include/console/uart.h b/src/include/console/uart.h index 8458086..24a8d4b 100644 --- a/src/include/console/uart.h +++ b/src/include/console/uart.h @@ -35,7 +35,6 @@ unsigned int default_baudrate(void); unsigned int uart_baudrate_divisor(unsigned int baudrate, unsigned int refclk, unsigned int oversample); - void uart_init(int idx); void uart_tx_byte(int idx, unsigned char data); void uart_tx_flush(int idx); diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 0cfb8ac..410270c 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -117,6 +117,8 @@ void lb_add_serial(struct lb_serial *new_serial, void *data) serial->baseaddr = new_serial->baseaddr; serial->baud = new_serial->baud; serial->regwidth = new_serial->regwidth; + serial->input_hertz = new_serial->input_hertz; + serial->id = new_serial->id; } void lb_add_console(uint16_t consoletype, void *data) diff --git a/src/soc/intel/quark/Kconfig b/src/soc/intel/quark/Kconfig index aab509a..8172be8 100644 --- a/src/soc/intel/quark/Kconfig +++ b/src/soc/intel/quark/Kconfig @@ -59,6 +59,16 @@ config TTYS0_LCS depends on ENABLE_BUILTIN_HSUART1 default 3 +config UART_INPUT_CLOCK_HERTZ + int + depends on ENABLE_BUILTIN_HSUART1 + default 44236800 + +config UART_DEVICE_ID + hex + depends on ENABLE_BUILTIN_HSUART1 + default 0x09368086 + ##### # Debug support # The following options provide debug support for the Quark coreboot diff --git a/src/soc/intel/quark/uart_common.c b/src/soc/intel/quark/uart_common.c index 4408d87..02d321d 100644 --- a/src/soc/intel/quark/uart_common.c +++ b/src/soc/intel/quark/uart_common.c @@ -16,12 +16,9 @@ */ #include <console/uart.h> +#include <device/pci_ids.h> #include <soc/iomap.h> - -unsigned int uart_platform_refclk(void) -{ - return 44236800; -} +#include <soc/pci_devs.h> uintptr_t uart_platform_base(int idx) {

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New patch to review for coreboot: soc/intel/quark: Disable the ROM shadow
by Leroy P Leahy 16 Mar '16

16 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14110 -gerrit commit fe469d8f234816afa941b21a86e443d67478be9c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Fri Mar 4 16:49:40 2016 -0800 soc/intel/quark: Disable the ROM shadow Disable the ROM shadow and enable RAM for 0x000e0000 - 0x000fffff. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Testing successful display of 0x000ffff0 - 0x000fffff does not match the end of the SPI flash. Change-Id: I6e0a50417815320333eae0b69b96280c39db7eaa Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/include/soc/QuarkNcSocId.h | 2 ++ src/soc/intel/quark/include/soc/romstage.h | 2 ++ src/soc/intel/quark/romstage/mtrr.c | 37 ++++++++++++++++---------- src/soc/intel/quark/romstage/romstage.c | 25 +++++++++++++++++ 4 files changed, 52 insertions(+), 14 deletions(-) diff --git a/src/soc/intel/quark/include/soc/QuarkNcSocId.h b/src/soc/intel/quark/include/soc/QuarkNcSocId.h index 1bf7e06..2232446 100644 --- a/src/soc/intel/quark/include/soc/QuarkNcSocId.h +++ b/src/soc/intel/quark/include/soc/QuarkNcSocId.h @@ -269,6 +269,8 @@ Definitions beginning with "N_" are the bit position // #define QNC_MSG_FSBIC_REG_HMISC 0x03 // Host Misellaneous Controls #define SMI_EN (BIT19) // SMI Global Enable (from Legacy Bridge) +#define FSEG_RD_DRAM (BIT2) // Enable RAM for 0x000f0000 - 0x000fffff +#define ESEG_RD_DRAM (BIT1) // Enable RAM for 0x000e0000 - 0x000effff #define QNC_MSG_FSBIC_REG_HSMMC 0x04 // Host SMM Control #define NON_HOST_SMM_WR_OPEN (BIT18) // SMM Writes OPEN #define NON_HOST_SMM_RD_OPEN (BIT17) // SMM Writes OPEN diff --git a/src/soc/intel/quark/include/soc/romstage.h b/src/soc/intel/quark/include/soc/romstage.h index 23c6270..c2c7e9c 100644 --- a/src/soc/intel/quark/include/soc/romstage.h +++ b/src/soc/intel/quark/include/soc/romstage.h @@ -30,6 +30,8 @@ void mcr_write(uint8_t opcode, uint8_t port, uint32_t reg_address); uint32_t mdr_read(void); void mdr_write(uint32_t value); void mea_write(uint32_t reg_address); +uint32_t port_reg_read(uint8_t port, uint32_t offset); +void port_reg_write(uint8_t port, uint32_t offset, uint32_t value); void report_platform_info(void); int set_base_address_and_enable_uart(u8 bus, u8 dev, u8 func, u32 mmio_base); diff --git a/src/soc/intel/quark/romstage/mtrr.c b/src/soc/intel/quark/romstage/mtrr.c index a0313fb..1528e17 100644 --- a/src/soc/intel/quark/romstage/mtrr.c +++ b/src/soc/intel/quark/romstage/mtrr.c @@ -73,6 +73,23 @@ static uint32_t mtrr_index_to_host_bridge_register_offset(unsigned long index) return offset; } +uint32_t port_reg_read(uint8_t port, uint32_t offset) +{ + /* Read the port register */ + offset = QNC_MSG_FSBIC_REG_HMISC; + mea_write(offset); + mcr_write(QUARK_OPCODE_READ, port, offset); + return mdr_read(); +} + +void port_reg_write(uint8_t port, uint32_t offset, uint32_t value) +{ + /* Write the port register */ + mea_write(offset); + mdr_write(value); + mcr_write(QUARK_OPCODE_WRITE, port, offset); +} + msr_t soc_mtrr_read(unsigned long index) { uint32_t offset; @@ -83,18 +100,14 @@ msr_t soc_mtrr_read(unsigned long index) /* Read the low 32-bits of the register */ offset = mtrr_index_to_host_bridge_register_offset(index); - mea_write(offset); - mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); - value.u64 = mdr_read(); + value.u64 = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); /* For 64-bit registers, read the upper 32-bits */ if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { offset += 1; - mea_write(offset); - mcr_write(QUARK_OPCODE_READ, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, - offset); - value.u64 |= mdr_read(); + value.u64 |= port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + offset); } return value.msr; } @@ -110,18 +123,14 @@ void soc_mtrr_write(unsigned long index, msr_t msr) /* Write the low 32-bits of the register */ value.msr = msr; offset = mtrr_index_to_host_bridge_register_offset(index); - mea_write(offset); - mdr_write(value.u32[0]); - mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset); + port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, value.u32[0]); /* For 64-bit registers, write the upper 32-bits */ if ((offset >= QUARK_NC_HOST_BRIDGE_MTRR_FIX64K_00000) && (offset <= QUARK_NC_HOST_BRIDGE_MTRR_FIX4K_F8000)) { offset += 1; - mea_write(offset); - mdr_write(value.u32[1]); - mcr_write(QUARK_OPCODE_WRITE, QUARK_NC_HOST_BRIDGE_SB_PORT_ID, - offset); + port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, offset, + value.u32[1]); } } diff --git a/src/soc/intel/quark/romstage/romstage.c b/src/soc/intel/quark/romstage/romstage.c index a089185..5bedb25 100644 --- a/src/soc/intel/quark/romstage/romstage.c +++ b/src/soc/intel/quark/romstage/romstage.c @@ -22,6 +22,7 @@ #include <device/pci_def.h> #include <fsp/car.h> #include <fsp/util.h> +#include <lib.h> #include <soc/intel/common/util.h> #include <soc/iomap.h> #include <soc/pci_devs.h> @@ -86,6 +87,30 @@ void soc_memory_init_params(struct romstage_params *params, config->PcdSmmTsegSize : 0; upd->PcdPlatformDataBaseAddress = (UINT32)pdat_file; upd->PcdPlatformDataMaxLen = (UINT32)pdat_file_len; + + /* Display the ROM shadow data */ + hexdump((void *)0x000ffff0, 0x10); +} + +void soc_after_ram_init(struct romstage_params *params) +{ + uint32_t data; + + /* Determine if the shadow ROM is enabled */ + data = port_reg_read(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + QNC_MSG_FSBIC_REG_HMISC); + printk(BIOS_DEBUG, "0x%08x: HMISC\n", data); + if ((data & (ESEG_RD_DRAM | FSEG_RD_DRAM)) + != (ESEG_RD_DRAM | FSEG_RD_DRAM)) { + + /* Disable the ROM shadow 0x000e0000 - 0x000fffff */ + data |= ESEG_RD_DRAM | FSEG_RD_DRAM; + port_reg_write(QUARK_NC_HOST_BRIDGE_SB_PORT_ID, + QNC_MSG_FSBIC_REG_HMISC, data); + } + + /* Display the DRAM data */ + hexdump((void *)0x000ffff0, 0x10); } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old,

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New patch to review for coreboot: mainboard/intel/galileo: Enable SPI controllers
by Leroy P Leahy 16 Mar '16

16 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14109 -gerrit commit 9c219dce6ad58fff9452a15c08dbd9ac09f66c4f Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Thu Mar 3 15:30:48 2016 -0800 mainboard/intel/galileo: Enable SPI controllers Enable the SPI controllers on the Quark SoC. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Load the SPI driver stack * Testing is successful when the time is able to be displayed on a set of seven-segment displays controlled by a Maxim MAX6950 SPI display controller. Change-Id: Ic9c4575730c5a9a27cf9a38a41e82d8462467f3f Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index c171aa0..05edffc 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -37,8 +37,8 @@ chip soc/intel/quark device pci 14.5 on end # 8086 0936 - HSUART 1 device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0 device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1 - device pci 15.0 off end # 8086 0935 - SPI controller 0 - device pci 15.1 off end # 8086 0935 - SPI controller 1 + device pci 15.0 on end # 8086 0935 - SPI controller 0 + device pci 15.1 on end # 8086 0935 - SPI controller 1 device pci 15.2 off end # 8086 0934 - I2C/GPIO controller device pci 17.0 on end # 8086 11C3 - PCIe Root Port 0 device pci 17.1 off end # 8086 11C4 - PCIe Root Port 1

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Patch merged into coreboot/master: cpu/x86: compile earlymtrr.c code for romstage as well
by gerrit＠coreboot.org 16 Mar '16

16 Mar '16

the following patch was just integrated into master: commit b4e5c5eb1efd9eb6141e2996845236e154a6ec0d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Mar 13 16:01:04 2016 -0700 cpu/x86: compile earlymtrr.c code for romstage as well In order to make this work earlymtrr.c needed to be removed from intel/truxton/romstage.c. It's not a ROMCC board so there's no reason to be including .c files. Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-on: https://review.coreboot.org/14094 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14094 for details. -gerrit

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Patch merged into coreboot/master: cpu/x86/mtrr: remove early_mtrr_* functions
by gerrit＠coreboot.org 16 Mar '16

16 Mar '16

the following patch was just integrated into master: commit 5fa5da1083d064e533b570e67370a7a477f02965 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 15 09:08:34 2016 -0500 cpu/x86/mtrr: remove early_mtrr_* functions I see no user of any of this code. Remove it. Change-Id: I776cd3d9ac6578ecb0fe6d98f15611e4463afb7a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14098 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14098 for details. -gerrit

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Patch merged into coreboot/master: cpu/x86/mtrr: move cache_ramstage() to its only user
by gerrit＠coreboot.org 16 Mar '16

16 Mar '16

the following patch was just integrated into master: commit 264bf0b27e6202dfca27c285c9dde10d08b8f023 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Mar 15 09:05:54 2016 -0500 cpu/x86/mtrr: move cache_ramstage() to its only user The Intel i3100 northbridge code is the only user of cache_ramstage(). Therefore, place it next to the sole consumer. Change-Id: If15fb8d84f98dce7f4de9e089ec33035622d8f74 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/14097 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/14097 for details. -gerrit

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New patch to review for coreboot: intel/kunimitsu: configure native mode for GPP_E21
by Patrick Georgi 16 Mar '16

16 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14108 -gerrit commit 2d10a8d23702db6ca312ad7284c81b59bb0d049f Author: Youvedeep Singh <youvedeep.singh(a)intel.com> Date: Fri Mar 11 11:08:38 2016 +0530 intel/kunimitsu: configure native mode for GPP_E21 GPP_E_21_DDPC_CTRLDATA is pulled low by default. This causes 2.5mW leakage from 3.3S to GND via R877. So configuring GPP_E21 in native mode. BUG=chrome-os-partner:50958 BRANCH=glados TEST=Build and boot. Measure Power at 3P3S(R955). Change-Id: I2bdcb698d0b0cd3228c2e59653ac3fb3b1a26951 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d01f932cda44b0b44c5494b316aefc43c8b84c52 Original-Change-Id: Ifd13ea4b16108ef98d09891365f0d17831ab5f65 Original-Signed-off-by: Youvedeep Singh <youvedeep.singh(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332369 Original-Commit-Ready: Rajneesh Bhardwaj <rajneesh.bhardwaj(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/kunimitsu/gpio.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/intel/kunimitsu/gpio.h b/src/mainboard/intel/kunimitsu/gpio.h index d310396..3d9fcfc 100644 --- a/src/mainboard/intel/kunimitsu/gpio.h +++ b/src/mainboard/intel/kunimitsu/gpio.h @@ -181,6 +181,7 @@ static const struct pad_config gpio_table[] = { /* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), /* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),

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New patch to review for coreboot: vboot: Handle S3 resume path for TPM initialization
by Patrick Georgi 16 Mar '16

16 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14107 -gerrit commit 15438fc5450a31863a233f8d53f158b497abee3d Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Mar 14 09:32:08 2016 -0700 vboot: Handle S3 resume path for TPM initialization When doing verification of memory init code in verstage vboot should issue a TPM_Startup(ST_STATE) instead of TPM_Startup(ST_CLEAR) in order to preserve the flags in TPM_STCLEAR_FLAGS which include things like physical presence. In doing so we can also skip the rest of the TPM init work in this function in the S3 resume path. BUG=chrome-os-partner:50633 BRANCH=glados TEST=S3 resume on chell and ensure TPM is resumed instead of being cleared and that 'tpmc getvf|getpf|getf' does not show any difference in flags between boot and resume. Change-Id: I7a48eaf7f57d2bc6ebc182178cbe60ceb2ad8863 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: f059f39a0f5c2f21e564b9554efacf26a41ad794 Original-Change-Id: I647869202d2f04328764155d3de4cad9edf10ae4 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Previous-Reviewed-on: https://chromium-review.googlesource.com/332434 Original-(cherry picked from commit 5fc7792e4104523569140cd84ce313da721ec34b) Original-Reviewed-on: https://chromium-review.googlesource.com/332542 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/antirollback.c | 8 ++++++++ src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 14 +++++++------- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/src/vendorcode/google/chromeos/vboot2/antirollback.c b/src/vendorcode/google/chromeos/vboot2/antirollback.c index 654fd34..fbc6d42 100644 --- a/src/vendorcode/google/chromeos/vboot2/antirollback.c +++ b/src/vendorcode/google/chromeos/vboot2/antirollback.c @@ -249,6 +249,14 @@ uint32_t setup_tpm(struct vb2_context *ctx) RETURN_ON_FAILURE(tlcl_lib_init()); + /* Handle special init for S3 resume path */ + if (ctx->flags & VB2_CONTEXT_S3_RESUME) { + result = tlcl_resume(); + if (result == TPM_E_INVALID_POSTINIT) + printk(BIOS_DEBUG, "TPM: Already initialized.\n"); + return TPM_SUCCESS; + } + #ifdef TEGRA_SOFT_REBOOT_WORKAROUND result = tlcl_startup(); if (result == TPM_E_INVALID_POSTINIT) { diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index d43fb27..a81a9c2 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -304,13 +304,6 @@ void verstage_main(void) /* Read nvdata from a non-volatile storage */ read_vbnv(ctx.nvdata); - /* Read secdata from TPM. Initialize TPM if secdata not found. We don't - * check the return value here because vb2api_fw_phase1 will catch - * invalid secdata and tell us what to do (=reboot). */ - timestamp_add_now(TS_START_TPMINIT); - antirollback_read_space_firmware(&ctx); - timestamp_add_now(TS_END_TPMINIT); - /* Set S3 resume flag if vboot should behave differently when selecting * which slot to boot. This is only relevant to vboot if the platform * does verification of memory init and thus must ensure it resumes with @@ -320,6 +313,13 @@ void verstage_main(void) vboot_platform_is_resuming()) ctx.flags |= VB2_CONTEXT_S3_RESUME; + /* Read secdata from TPM. Initialize TPM if secdata not found. We don't + * check the return value here because vb2api_fw_phase1 will catch + * invalid secdata and tell us what to do (=reboot). */ + timestamp_add_now(TS_START_TPMINIT); + antirollback_read_space_firmware(&ctx); + timestamp_add_now(TS_END_TPMINIT); + if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) && get_developer_mode_switch()) ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;

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coreboot-gerrit March 2016