coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage
by Patrick Georgi 16 Mar '16

16 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14106 -gerrit commit 4c2f3e3a9e9ba4fddbc0818eed6756aba36b604a Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Mon Mar 14 09:29:09 2016 -0700 intel/fsp1_1: Do not re-init TPM in romstage if already setup in verstage For platforms that do verification of memory init (and have verstage execute before romstage) FSP should not attempt to re-initialize the TPM again in romstage as it has already been done. BUG=chrome-os-partner:50633 BRANCH=glados TEST=boot and resume on chell and ensure TPM is not re-initialized Change-Id: Ied6f39dc8dacdbc3d76070b6135de2308196ff53 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: fefd4d4b3fde4c7fe4b6de304790914b7a2f87d8 Original-Change-Id: I60a2e4e2d73270697218f094527e09d444e6ab56 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Previous-Reviewed-on: https://chromium-review.googlesource.com/332433 Original-(cherry picked from commit 2de1fd57fe1db7960e0bb86c64dccf827fa55742) Original-Reviewed-on: https://chromium-review.googlesource.com/332299 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/fsp1_1/romstage.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/drivers/intel/fsp1_1/romstage.c b/src/drivers/intel/fsp1_1/romstage.c index bf84d66..3d698bb 100644 --- a/src/drivers/intel/fsp1_1/romstage.c +++ b/src/drivers/intel/fsp1_1/romstage.c @@ -173,8 +173,15 @@ void romstage_common(struct romstage_params *params) hard_reset(); } - if (IS_ENABLED(CONFIG_LPC_TPM)) - init_tpm(params->power_state->prev_sleep_state == SLEEP_STATE_S3); + /* + * Initialize the TPM, unless the TPM was already initialized + * in verstage and used to verify romstage. + */ + if (IS_ENABLED(CONFIG_LPC_TPM) && + !IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && + !IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK)) + init_tpm(params->power_state->prev_sleep_state == + SLEEP_STATE_S3); } void after_cache_as_ram_stage(void)

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New patch to review for coreboot: device: Add i2c read/write register field API
by Patrick Georgi 16 Mar '16

16 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14105 -gerrit commit 9168ae87188379711c86151d286ad6396c78dc32 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Tue Mar 15 14:38:44 2016 +0800 device: Add i2c read/write register field API i2c_read_field() - read the value from the specific register field i2c_write_field() - write the value to the specific register field BRANCH=none BUG=none TEST=none Change-Id: I2098715b4583c1936c93b3ff45ec330910964304 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 0817fc76d07491b39c066f1393a6435f0831b50c Original-Change-Id: I92c187a89d10cfcecf3dfd9291e0bc015459c393 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332712 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/device/Makefile.inc | 5 +++++ src/device/i2c.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ src/include/device/i2c.h | 5 +++++ 3 files changed, 56 insertions(+) diff --git a/src/device/Makefile.inc b/src/device/Makefile.inc index c2ade96..6bad0cd 100644 --- a/src/device/Makefile.inc +++ b/src/device/Makefile.inc @@ -31,3 +31,8 @@ bootblock-$(CONFIG_SOFTWARE_I2C) += software_i2c.c verstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c romstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c ramstage-$(CONFIG_SOFTWARE_I2C) += software_i2c.c + +bootblock-y += i2c.c +verstage-y += i2c.c +romstage-y += i2c.c +ramstage-y += i2c.c diff --git a/src/device/i2c.c b/src/device/i2c.c new file mode 100644 index 0000000..53bfdf0 --- /dev/null +++ b/src/device/i2c.c @@ -0,0 +1,46 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 MediaTek Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/i2c.h> + +int i2c_read_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t *data, + uint8_t mask, uint8_t shift) +{ + int ret; + uint8_t buf = 0; + + ret = i2c_readb(bus, chip, reg, &buf); + + buf &= (mask << shift); + *data = (buf >> shift); + + return ret; +} + +int i2c_write_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t data, + uint8_t mask, uint8_t shift) +{ + int ret; + uint8_t buf = 0; + + ret = i2c_readb(bus, chip, reg, &buf); + + buf &= ~(mask << shift); + buf |= (data << shift); + + ret |= i2c_writeb(bus, chip, reg, buf); + + return ret; +} diff --git a/src/include/device/i2c.h b/src/include/device/i2c.h index 8e59ba7..b152bb9 100644 --- a/src/include/device/i2c.h +++ b/src/include/device/i2c.h @@ -45,6 +45,11 @@ void software_i2c_wedge_ack(unsigned bus, u8 chip); void software_i2c_wedge_read(unsigned bus, u8 chip, u8 reg, int bit_count); void software_i2c_wedge_write(unsigned bus, u8 chip, u8 reg, int bit_count); +int i2c_read_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t *data, + uint8_t mask, uint8_t shift); +int i2c_write_field(unsigned bus, uint8_t chip, uint8_t reg, uint8_t data, + uint8_t mask, uint8_t shift); + /* * software_i2c is supposed to be a debug feature. It's usually not compiled in, * but when it is it can be dynamically enabled at runtime for certain busses.

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Patch set updated for coreboot: mediatek/mt8173: Enable ARM trusted firmware integration
by Patrick Georgi 16 Mar '16

16 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13968 -gerrit commit 9d43b5a8e68bf1f0a27bc3b4436ea8c474e777da Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Mar 8 21:42:00 2016 +0100 mediatek/mt8173: Enable ARM trusted firmware integration In Chromium OS downstream this was done together with adding the support for ATF, but unfortunately ATF upstream isn't ready yet. This commit is a reminder to enable things once ATF caught up. Change-Id: Id0d6908d906a1e54cdda4f232d572d996d9c556f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/mediatek/mt8173/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 91a8d4f..ec3481e 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8173 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING if SPI_FLASH

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New patch to review for coreboot: google/oak: Enable RAM_CODE_SUPPORT
by Patrick Georgi 16 Mar '16

16 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14104 -gerrit commit e01ecae9edf3cf8e554e8d3271122688382c0488 Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Mon Mar 14 10:06:46 2016 +0800 google/oak: Enable RAM_CODE_SUPPORT BRANCH=none BUG=chrome-os-partner:50820 TEST=check /proc/device-tree/firmware/coreboot/ram-code Change-Id: I5ecf45cada7f8999ad607487d5d9281c4fb659ed Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 79d2f0e183a2bde70817d673ae315709f46e3361 Original-Change-Id: I35e91b4e29f8e09acd74770715c96cf7320ac22c Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332564 Original-Reviewed-by: Milton Chiang <milton.chiang(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index cca9054..3bae9f7 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -26,6 +26,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_NATIVE_VGA_INIT select MAINBOARD_DO_NATIVE_VGA_INIT select MAINBOARD_HAS_CHROMEOS + select RAM_CODE_SUPPORT select SPI_FLASH config CHROMEOS

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New patch to review for coreboot: mediatek/mt8173: mt6391: set VSRMCA7 to HW control by SRCVOLTEN
by Patrick Georgi 16 Mar '16

16 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14103 -gerrit commit 0537973f71ddcc273353f1f44529108057faeb8f Author: henryc.chen <henryc.chen(a)mediatek.com> Date: Mon Mar 7 15:17:01 2016 +0800 mediatek/mt8173: mt6391: set VSRMCA7 to HW control by SRCVOLTEN When system enters suspend, SPM will pull SRCVOLTEN low to turn off some power rails. VSRMCA7 should follow this pin to turn on/off the power. BRANCH=none BUG=none TEST=verified on Oak rev5 Change-Id: I9d81f855a74fe02a59246ce0c6a7f0e162b9fd0a Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d92fb1029b810028138eb91b064b63a58b82602f Original-Change-Id: I37ff0694cbd7b17d5a1ae172c463b4e6aae2b99c Original-Signed-off-by: henryc.chen <henryc.chen(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/332345 Original-Commit-Ready: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/mediatek/mt8173/mt6391.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/soc/mediatek/mt8173/mt6391.c b/src/soc/mediatek/mt8173/mt6391.c index 9f5ed0a..ced86d7 100644 --- a/src/soc/mediatek/mt8173/mt6391.c +++ b/src/soc/mediatek/mt8173/mt6391.c @@ -299,7 +299,7 @@ static void mt6391_init_setting(void) /* [6:0]: VSRMCA7_VOSEL_SLEEP; */ mt6391_write(PMIC_RG_VSRMCA7_CON11, 0x18, 0x7F, 0); /* [8:8]: VSRMCA7_VSLEEP_EN; */ - mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x1, 0x1, 8); + mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x0, 0x1, 8); /* [5:4]: VSRMCA7_VOSEL_TRANS_EN; */ mt6391_write(PMIC_RG_VSRMCA7_CON18, 0x3, 0x3, 4); /* [8:8]: VDRM_VSLEEP_EN; */ @@ -362,6 +362,8 @@ static void mt6391_init_setting(void) mt6391_write(PMIC_RG_VPCA7_CON5, 0x0, 0x1, 1); /* [1:1]: VSRMCA7_VOSEL_CTRL; */ mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x0, 0x1, 1); + /* [0:0]: VSRMCA7_EN_CTRL; */ + mt6391_write(PMIC_RG_VSRMCA7_CON5, 0x1, 0x1, 0); /* [4:4]: VCA15_TRACK_ON_CTRL; DVFS tracking enable */ mt6391_write(PMIC_RG_VCA15_CON5, 0x1, 0x1, 4); /* [4:4]: VSRMCA15_TRACK_ON_CTRL; */

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Patch set updated for coreboot: mediatek/mt8173: Enable ARM trusted firmware integration
by Patrick Georgi 16 Mar '16

16 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13968 -gerrit commit d39ac30a2cd139e6a1b9a813e5db9304d780442a Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Mar 8 21:42:00 2016 +0100 mediatek/mt8173: Enable ARM trusted firmware integration In Chromium OS downstream this was done together with adding the support for ATF, but unfortunately ATF upstream isn't ready yet. This commit is a reminder to enable things once ATF caught up. Change-Id: Id0d6908d906a1e54cdda4f232d572d996d9c556f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/soc/mediatek/mt8173/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/mediatek/mt8173/Kconfig b/src/soc/mediatek/mt8173/Kconfig index 91a8d4f..ec3481e 100644 --- a/src/soc/mediatek/mt8173/Kconfig +++ b/src/soc/mediatek/mt8173/Kconfig @@ -6,6 +6,7 @@ config SOC_MEDIATEK_MT8173 select ARCH_RAMSTAGE_ARMV8_64 select ARCH_ROMSTAGE_ARMV8_64 select ARCH_VERSTAGE_ARMV8_64 + select ARM64_USE_ARM_TRUSTED_FIRMWARE select BOOTBLOCK_CONSOLE select HAVE_UART_SPECIAL select SPI_ATOMIC_SEQUENCING if SPI_FLASH

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Patch merged into coreboot/master: libpayload: recreate config files
by gerrit＠coreboot.org 16 Mar '16

16 Mar '16

the following patch was just integrated into master: commit 94534b31328311e3a3488a7f8201bc0abab9fb1d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 16:51:30 2016 -0800 libpayload: recreate config files Add all the default options with: for i in configs/* do cp $i .config make savedefconfig mv defconfig $i done This also switches to minimal config files instead of the full configuration files that were previously checked in. Change-Id: If18a32eca4df9e1dfeb0e212b652d972cea8e4b8 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14077 Reviewed-by: Martin Roth <martinroth(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/14077 for details. -gerrit

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Patch merged into coreboot/master: coreinfo: Rename libpayload variables
by gerrit＠coreboot.org 16 Mar '16

16 Mar '16

the following patch was just integrated into master: commit 62af53fe100f7618f178f12c57a098de19c4c86e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Mar 15 13:29:35 2016 -0700 coreinfo: Rename libpayload variables LIBCONFIG_PATH -> LIBPAYLOAD_PATH LIBPAYLOAD_DIR -> LIBPAYLOAD_OBJ Change-Id: Idd9947bac594f5b109b877aefac70b1a1d2336eb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14099 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14099 for details. -gerrit

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Patch merged into coreboot/master: rockchip: update make_idb.py
by gerrit＠coreboot.org 16 Mar '16

16 Mar '16

the following patch was just integrated into master: commit 1129f7f6366b6acc047673903cc22ad093d0a21f Author: huang lin <hl(a)rock-chips.com> Date: Wed Mar 2 16:02:45 2016 +0800 rockchip: update make_idb.py make_idb.py only support RK3288 before, add chip parameter, so we can support RK3399 either. Change-Id: I6811acb7f0cdaf1930af9942a70db54765d544d5 Signed-off-by: huang lin <hl(a)rock-chips.com> Reviewed-on: https://review.coreboot.org/13913 Reviewed-by: Vadim Bendebury <vbendeb(a)chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/13913 for details. -gerrit

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Patch set updated for coreboot: src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table.
by Martin Roth 16 Mar '16

16 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14102 -gerrit commit 41b0f73655bdb0fa6dd0ab3f25f20d27f57344f9 Author: Jacob Laska <jlaska(a)xes-inc.com> Date: Tue Mar 15 21:53:27 2016 -0500 src/arch/x86/acpi.c: Use correct host address width in DMAR ACPI table. The previous implementation assumed the CPU physical address size to be 40 which is not true of all platforms. Use an existing function to obtain the correct CPU physical address to report in the DMAR ACPI table. Change-Id: Ia79e9dadecc3f5f6a86ce3789b213222bef482b3 Signed-off-by: Jacob Laska <jlaska91(a)gmail.com> --- src/arch/x86/acpi.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/arch/x86/acpi.c b/src/arch/x86/acpi.c index a21bae2..5640ad0 100644 --- a/src/arch/x86/acpi.c +++ b/src/arch/x86/acpi.c @@ -411,7 +411,7 @@ void acpi_create_dmar(acpi_dmar_t *dmar, enum dmar_flags flags, header->length = sizeof(acpi_dmar_t); header->revision = 1; - dmar->host_address_width = 40 - 1; /* FIXME: == MTRR size? */ + dmar->host_address_width = cpu_phys_address_size() - 1; dmar->flags = flags; current = acpi_fill_dmar(current);

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coreboot-gerrit March 2016