coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: coreinfo: Rename libpayload variables
by Stefan Reinauer 15 Mar '16

15 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14099 -gerrit commit e9d3ca049b20bac14623ffa1ba5f4bd0119a6f98 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Mar 15 13:09:15 2016 -0700 coreinfo: Rename libpayload variables LIBCONFIG_PATH -> LIBPAYLOAD_PATH LIBPAYLOAD_DIR -> LIBPAYLOAD_OBJ Change-Id: Idd9947bac594f5b109b877aefac70b1a1d2336eb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/Makefile | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index a9988cc..e62cdda 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -47,13 +47,13 @@ HOSTCXX ?= g++ HOSTCFLAGS := -I$(srck) -I$(objk) HOSTCXXFLAGS := -I$(srck) -I$(objk) -LIBCONFIG_PATH := ../libpayload -LIBPAYLOAD_DIR := $(coreinfo_obj)/libpayload -HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_DIR)/lib/libpayload.a) +LIBPAYLOAD_PATH := ../libpayload +LIBPAYLOAD_OBJ := $(coreinfo_obj)/libpayload +HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_OBJ)/lib/libpayload.a) LIBPAYLOAD_CONFIG ?= configs/defconfig-tinycurses OBJCOPY ?= objcopy -INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_DIR)/include/kconfig.h +INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_OBJ)/include/kconfig.h OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \ nvram_module.o bootlog_module.o ramdump_module.o \ multiboot_module.o cbfs_module.o coreinfo.o @@ -78,8 +78,8 @@ CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) OBJCOPY := $(OBJCOPY_$(ARCH-y)) -LPCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/bin/lpgcc -LPAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas +LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc +LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas CFLAGS += -Wall -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) @@ -112,13 +112,13 @@ defaultbuild: ifneq ($(strip $(HAVE_LIBPAYLOAD)),) libpayload: - printf "Found Libpayload $(LIBPAYLOAD_DIR).\n" + printf "Found Libpayload $(LIBPAYLOAD_OBJ).\n" else libpayload: - printf "Building libpayload @ $(LIBCONFIG_PATH).\n" - $(MAKE) -C $(LIBCONFIG_PATH) distclean coreinfo_obj=$(coreinfo_obj)/libptmp + printf "Building libpayload @ $(LIBPAYLOAD_PATH).\n" + $(MAKE) -C $(LIBPAYLOAD_PATH) distclean coreinfo_obj=$(coreinfo_obj)/libptmp $(MAKE) -C $(LIBPAYLOAD_PATH) defconfig KBUILD_DEFCONFIG=$(LIBPAYLOAD_CONFIG) - $(MAKE) -C $(LIBCONFIG_PATH) install DESTDIR=$(coreinfo_obj) + $(MAKE) -C $(LIBPAYLOAD_PATH) install DESTDIR=$(coreinfo_obj) endif $(coreinfo_obj)/config.h:

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Patch set updated for coreboot: coreinfo: Use tinycurses
by Stefan Reinauer 15 Mar '16

15 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14067 -gerrit commit ed3b3dacb474f7eeebced3fa6adcc1dbbfb4597d Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 11:47:00 2016 -0800 coreinfo: Use tinycurses When using PDcurses over a serial line, the background of coreinfo is not properly cleared. Hence use tinycurses, which was the only option when coreinfo was developed. Change-Id: I15bb6eb552cf924de98d09ef63be33ecf336c526 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 96acecc..a9988cc 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -50,7 +50,7 @@ HOSTCXXFLAGS := -I$(srck) -I$(objk) LIBCONFIG_PATH := ../libpayload LIBPAYLOAD_DIR := $(coreinfo_obj)/libpayload HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_DIR)/lib/libpayload.a) -LIB_CONFIG ?= defconfig +LIBPAYLOAD_CONFIG ?= configs/defconfig-tinycurses OBJCOPY ?= objcopy INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_DIR)/include/kconfig.h @@ -117,7 +117,7 @@ else libpayload: printf "Building libpayload @ $(LIBCONFIG_PATH).\n" $(MAKE) -C $(LIBCONFIG_PATH) distclean coreinfo_obj=$(coreinfo_obj)/libptmp - $(MAKE) -C $(LIBCONFIG_PATH) $(LIB_CONFIG) + $(MAKE) -C $(LIBPAYLOAD_PATH) defconfig KBUILD_DEFCONFIG=$(LIBPAYLOAD_CONFIG) $(MAKE) -C $(LIBCONFIG_PATH) install DESTDIR=$(coreinfo_obj) endif

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New patch to review for coreboot: coreinfo: Rename libpayload variables
by Stefan Reinauer 15 Mar '16

15 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14099 -gerrit commit 414aaebb0c26e83c033a0fd8ff68c54a451cbefe Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Tue Mar 15 12:56:04 2016 -0700 coreinfo: Rename libpayload variables LIBCONFIG_PATH -> LIBPAYLOAD_PATH LIBPAYLOAD_DIR -> LIBPAYLOAD_OBJ Change-Id: Idd9947bac594f5b109b877aefac70b1a1d2336eb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/Makefile | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index f6d2cee..fc55e57 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -47,14 +47,14 @@ HOSTCXX ?= g++ HOSTCFLAGS := -I$(srck) -I$(objk) HOSTCXXFLAGS := -I$(srck) -I$(objk) -LIBCONFIG_PATH := ../libpayload -LIBPAYLOAD_DIR := $(coreinfo_obj)/libpayload -HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_DIR)/lib/libpayload.a) +LIBPAYLOAD_PATH := ../libpayload +LIBPAYLOAD_OBJ := $(coreinfo_obj)/libpayload +HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_OBJ)/lib/libpayload.a) LIBPAYLOAD_CONFIG ?= defconfig LIBPAYLOAD_KBUILD_DEFCONFIG ?= configs/defconfig-tinycurses OBJCOPY ?= objcopy -INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_DIR)/include/kconfig.h +INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_OBJ)/include/kconfig.h OBJECTS = cpuinfo_module.o cpuid.S.o pci_module.o coreboot_module.o \ nvram_module.o bootlog_module.o ramdump_module.o \ multiboot_module.o cbfs_module.o coreinfo.o @@ -79,8 +79,8 @@ CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) OBJCOPY := $(OBJCOPY_$(ARCH-y)) -LPCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/bin/lpgcc -LPAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas +LPCC := CC="$(CC)" $(LIBPAYLOAD_OBJ)/bin/lpgcc +LPAS := AS="$(AS)" $(LIBPAYLOAD_OBJ)/bin/lpas CFLAGS += -Wall -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES) @@ -113,13 +113,13 @@ defaultbuild: ifneq ($(strip $(HAVE_LIBPAYLOAD)),) libpayload: - printf "Found Libpayload $(LIBPAYLOAD_DIR).\n" + printf "Found Libpayload $(LIBPAYLOAD_OBJ).\n" else libpayload: - printf "Building libpayload @ $(LIBCONFIG_PATH).\n" - $(MAKE) -C $(LIBCONFIG_PATH) distclean coreinfo_obj=$(coreinfo_obj)/libptmp - $(MAKE) -C $(LIBCONFIG_PATH) $(LIBPAYLOAD_CONFIG) KBUILD_DEFCONFIG=$(LIBPAYLOAD_KBUILD_DEFCONFIG) - $(MAKE) -C $(LIBCONFIG_PATH) install DESTDIR=$(coreinfo_obj) + printf "Building libpayload @ $(LIBPAYLOAD_PATH).\n" + $(MAKE) -C $(LIBPAYLOAD_PATH) distclean coreinfo_obj=$(coreinfo_obj)/libptmp + $(MAKE) -C $(LIBPAYLOAD_PATH) $(LIBPAYLOAD_CONFIG) KBUILD_DEFCONFIG=$(LIBPAYLOAD_KBUILD_DEFCONFIG) + $(MAKE) -C $(LIBPAYLOAD_PATH) install DESTDIR=$(coreinfo_obj) endif $(coreinfo_obj)/config.h:

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Patch merged into coreboot/master: libpayload: Move base address, stack and heap size to Kconfig
by gerrit＠coreboot.org 15 Mar '16

15 Mar '16

the following patch was just integrated into master: commit 821844534c78c60041402e732892f79865636650 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 16:18:17 2016 -0800 libpayload: Move base address, stack and heap size to Kconfig This will allow more payloads to use the standard linker script instead of implementing their own. Change-Id: Ie60120769829f427ceb722109d85859b61dbde31 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14074 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14074 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Make comment into help text
by gerrit＠coreboot.org 15 Mar '16

15 Mar '16

the following patch was just integrated into master: commit 347a7529aa7bf58ac58c3e0e3e563697a4d3f846 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 11:48:44 2016 -0800 libpayload: Make comment into help text Change-Id: I8c8669e73e335e12cb3785cf84b878c305dd5929 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14068 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14068 for details. -gerrit

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Patch set updated for coreboot: coreinfo: Use tinycurses
by Stefan Reinauer 15 Mar '16

15 Mar '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14067 -gerrit commit 316afdb510e2755186c2512859a312faeffb78b3 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 11:47:00 2016 -0800 coreinfo: Use tinycurses When using PDcurses over a serial line, the background of coreinfo is not properly cleared. Hence use tinycurses, which was the only option when coreinfo was developed. Change-Id: I15bb6eb552cf924de98d09ef63be33ecf336c526 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- payloads/coreinfo/Makefile | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index 96acecc..f6d2cee 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -50,7 +50,8 @@ HOSTCXXFLAGS := -I$(srck) -I$(objk) LIBCONFIG_PATH := ../libpayload LIBPAYLOAD_DIR := $(coreinfo_obj)/libpayload HAVE_LIBPAYLOAD := $(wildcard $(LIBPAYLOAD_DIR)/lib/libpayload.a) -LIB_CONFIG ?= defconfig +LIBPAYLOAD_CONFIG ?= defconfig +LIBPAYLOAD_KBUILD_DEFCONFIG ?= configs/defconfig-tinycurses OBJCOPY ?= objcopy INCLUDES = -I$(coreinfo_obj) -include $(LIBPAYLOAD_DIR)/include/kconfig.h @@ -117,7 +118,7 @@ else libpayload: printf "Building libpayload @ $(LIBCONFIG_PATH).\n" $(MAKE) -C $(LIBCONFIG_PATH) distclean coreinfo_obj=$(coreinfo_obj)/libptmp - $(MAKE) -C $(LIBCONFIG_PATH) $(LIB_CONFIG) + $(MAKE) -C $(LIBCONFIG_PATH) $(LIBPAYLOAD_CONFIG) KBUILD_DEFCONFIG=$(LIBPAYLOAD_KBUILD_DEFCONFIG) $(MAKE) -C $(LIBCONFIG_PATH) install DESTDIR=$(coreinfo_obj) endif

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Patch set updated for coreboot: nb/intel/sandybridge/raminit: always use mrccache
by Patrick Rudolph 15 Mar '16

15 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14082 -gerrit commit f3c8a14276de9a9d721dabed4e186bf75ab3e88d Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Mar 13 11:07:45 2016 +0100 nb/intel/sandybridge/raminit: always use mrccache Always use MRC cache if possible. Added a CRC16 array to make sure the DIMMs haven't been replaced. In case one of the CRC's doesn't match, start normal RAM training. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I974c5bce70692a706410180c2a512eb071364be0 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 75 +++++++++++++++++++++-------- 1 file changed, 55 insertions(+), 20 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 0b27fe5..152e881 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -135,6 +135,7 @@ struct ram_rank_timings { struct ramctr_timing_st; typedef struct ramctr_timing_st { + u16 spd_crc[NUM_CHANNELS][NUM_SLOTS]; int mobile; u16 cas_supported; @@ -316,6 +317,23 @@ static void report_memory_config(void) } } +/* + * Return CRC16 match for all SPDs. + */ +static int verify_crc16_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl) { + int channel, slot, spd_slot; + int match = 1; + + FOR_ALL_CHANNELS { + for (slot = 0; slot < NUM_SLOTS; slot++) { + spd_slot = 2 * channel + slot; + match &= ctrl->spd_crc[channel][slot] == + spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + } + } + return match; +} + void read_spd(spd_raw_data * spd, u8 addr) { int j; @@ -368,6 +386,9 @@ static void dram_find_spds_ddr3(spd_raw_data * spd, dimm_info * dimm, spd_decode_ddr3(&dimm->dimm[channel][slot], spd[spd_slot]); } + /* fill in CRC16 for MRC cache */ + ctrl->spd_crc[channel][slot] = spd_ddr3_calc_crc(spd[spd_slot], sizeof(spd_raw_data)); + if (dimm->dimm[channel][slot].dram_type != SPD_MEMORY_TYPE_SDRAM_DDR3) { // set dimm invalid dimm->dimm[channel][slot].ranks = 0; @@ -3943,6 +3964,10 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, { int me_uma_size; int cbmem_was_inited; + int fast_boot; + ramctr_timing ctrl; + struct mrc_data_container *mrc_cache; + ramctr_timing *ctrl_cached; dimm_info info; MCHBAR32(0x5f00) |= 1; @@ -3971,32 +3996,42 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, halt(); } - ramctr_timing ctrl; - memset(&ctrl, 0, sizeof (ctrl)); early_pch_init_native(); early_thermal_init(); - ctrl.mobile = mobile; - ctrl.tCK = min_tck; - - /* FIXME: for non-S3 we should be able to use timing caching with - proper verification. Right now we use timings only for S3 case. - */ - if (s3resume) { - struct mrc_data_container *mrc_cache; - - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { + /* try to find timings in MRC cache */ + mrc_cache = find_current_mrc_cache(); + if (!mrc_cache || mrc_cache->mrc_data_size < sizeof (ctrl)) { + if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); halt(); } - memcpy(&ctrl, mrc_cache->mrc_data, sizeof (ctrl)); + ctrl_cached = NULL; + } else { + ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; } - if (!s3resume) { + /* verify MRC cache for fast boot */ + if (ctrl_cached) { + /* check SPD CRC16 to make sure the DIMMs haven't been replaced */ + fast_boot = verify_crc16_spds_ddr3(spds, ctrl_cached); + if (!fast_boot) + printk(BIOS_DEBUG, "Stored timings CRC16 mismatch.\n"); + } else + fast_boot = 0; + + if (fast_boot) { + printk(BIOS_DEBUG, "Using stored timings. Skipping RAM training.\n"); + memcpy(&ctrl, ctrl_cached, sizeof(ctrl)); + } else { + ctrl.mobile = mobile; + ctrl.tCK = min_tck; + + printk(BIOS_DEBUG, "No valid stored timings found. Starting RAM training.\n"); + /* Get DDR3 SPD data */ dram_find_spds_ddr3(spds, &info, &ctrl); @@ -4009,7 +4044,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Set MCU frequency */ dram_freq(&ctrl); - if (!s3resume) { + if (!fast_boot) { /* Calculate timings */ dram_timing(&ctrl); } @@ -4052,7 +4087,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, udelay(1); - if (s3resume) { + if (fast_boot) { restore_timings(&ctrl); } else { /* Do jedec ddr3 reset sequence */ @@ -4090,7 +4125,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, write_controller_mr(&ctrl); - if (!s3resume) { + if (!fast_boot) { channel_test(&ctrl); } @@ -4106,7 +4141,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, /* Zone config */ dram_zones(&ctrl, 0); - if (!s3resume) + if (!fast_boot) quick_ram_check(); intel_early_me_status(); @@ -4116,7 +4151,7 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, report_memory_config(); cbmem_was_inited = !cbmem_recovery(s3resume); - if (!s3resume) + if (!fast_boot) save_timings(&ctrl); if (s3resume && !cbmem_was_inited) { /* Failed S3 resume, reset to come up cleanly */

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Patch set updated for coreboot: nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS
by Patrick Rudolph 15 Mar '16

15 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14096 -gerrit commit bfd390b0b084bdb9cbbd1ff763a82143b34dcf62 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Mar 15 07:44:49 2016 +0100 nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS Set MMCONF_BASE_ADDRESS to 0xf8000000. It was already done for some boards, but not all. The sandybridge chipset code assumes 64 pci buses behind MMCONF. Therefore, only 64MiB of physical address space is required. Increasing the address allows to use additional 128MiB of MMIO space and to use the Intel IGD and a PEG at the same time. Previously it wasn't possible to use both at the same time, as two 256MiB areas won't fit into MMIO space. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Onboard GPU Intel IvyBridge Desktop * PEG GPU AMD RV770 Change-Id: I3bf72439056c8089ada6899bb0605e5cd9d89cd6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/apple/macbookair4_2/Kconfig | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 2 +- src/mainboard/google/butterfly/Kconfig | 2 +- src/mainboard/google/link/Kconfig | 2 +- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/intel/emeraldlake2/Kconfig | 2 +- src/mainboard/kontron/ktqm77/Kconfig | 2 +- src/mainboard/lenovo/t420s/Kconfig | 2 +- src/mainboard/lenovo/t430s/Kconfig | 2 +- src/mainboard/lenovo/t520/Kconfig | 2 +- src/mainboard/lenovo/t530/Kconfig | 2 +- src/mainboard/lenovo/x220/Kconfig | 2 +- src/mainboard/lenovo/x230/Kconfig | 2 +- src/mainboard/samsung/lumpy/Kconfig | 2 +- src/mainboard/samsung/stumpy/Kconfig | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index e0cf022..08e7166 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -49,7 +49,7 @@ config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 987c8b7..e53b68c 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 320981a..4115a79 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 9c7fb5e..e61bba0 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 56ebf86..3483a81 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -31,7 +31,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 197099e..0aafc48 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 90b40ac..7671c30 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -26,7 +26,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 781833b..9f4d514 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -23,7 +23,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index dc279027..f5e99e7 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -40,7 +40,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 4e55eda..0c1d959 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index d5cee9e..664ce62 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -40,7 +40,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 257621f..fc94c20 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -42,7 +42,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index d30cbdc..0ef6689 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 3db0338..16e34ff 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 5f0f49f..14db934 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -33,7 +33,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index e511d83..4f14a6c 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -31,7 +31,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int

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Patch merged into coreboot/master: libpayload: Fix ARM workaround code
by gerrit＠coreboot.org 15 Mar '16

15 Mar '16

the following patch was just integrated into master: commit 805d44f2c73edc59bfa03e1c9df954fe8313421e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 16:38:17 2016 -0800 libpayload: Fix ARM workaround code _LDFLAGS+="foo" did not work in my shell (bash on Ubuntu 15.10), so change it to _LDFLAGS="$_LDFLAGS foo". I'm mildly surprised that this ever worked. Change-Id: I59c10f34992240c6df2ec7f24aebc6daafb76493 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14076 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14076 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Add comment about ARM64 exception stack
by gerrit＠coreboot.org 15 Mar '16

15 Mar '16

the following patch was just integrated into master: commit f0acf47ae1c680a83b13b225172e0ab04d3e4bba Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 16:36:57 2016 -0800 libpayload: Add comment about ARM64 exception stack Change-Id: I8b74cbf6bdde32c90ad0510e14e899711269e57f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14075 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14075 for details. -gerrit

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coreboot-gerrit March 2016