coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

Patch set updated for coreboot: libpayload: mmu: Assuming that memory 0-4GiB is device memory
by Lin Huang 15 Mar '16

15 Mar '16

Lin Huang (hl(a)rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13914 -gerrit commit 4ef157d50a6b87b5e69e62558633d7ead18be5c6 Author: huang lin <hl(a)rock-chips.com> Date: Thu Mar 3 15:29:34 2016 +0800 libpayload: mmu: Assuming that memory 0-4GiB is device memory in some platform(like rk3399), mmio space start 0xf8000000, exceed 2GB, so fix it. Change-Id: I39da4ce247422f67451711ac0ed5a5e1119ed836 Signed-off-by: huang lin <hl(a)rock-chips.com> --- payloads/libpayload/arch/arm64/mmu.c | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/payloads/libpayload/arch/arm64/mmu.c b/payloads/libpayload/arch/arm64/mmu.c index f07e4c4..9bb402b 100644 --- a/payloads/libpayload/arch/arm64/mmu.c +++ b/payloads/libpayload/arch/arm64/mmu.c @@ -260,7 +260,7 @@ void mmu_config_range(void *start, size_t size, uint64_t tag) * Desc : Initialize mmu based on the mmu_memrange passed. ttb_buffer is used as * the base address for xlat tables. TTB_DEFAULT_SIZE defines the max number of * tables that can be used - * Assuming that memory 0-2GiB is device memory. + * Assuming that memory 0-4GiB is device memory. */ uint64_t mmu_init(struct mmu_ranges *mmu_ranges) { @@ -275,8 +275,7 @@ uint64_t mmu_init(struct mmu_ranges *mmu_ranges) printf("Libpayload ARM64: TTB_BUFFER: 0x%p Max Tables: %d\n", (void*)xlat_addr, max_tables); - mmu_config_range(NULL, 0x80000000, TYPE_DEV_MEM); - + mmu_config_range(NULL, 0x100000000, TYPE_DEV_MEM); for (; i < mmu_ranges->used; i++) mmu_config_range((void *)mmu_ranges->entries[i].base, mmu_ranges->entries[i].size,

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Patch set updated for coreboot: rockchip: update make_idb.py
by Lin Huang 15 Mar '16

15 Mar '16

Lin Huang (hl(a)rock-chips.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13913 -gerrit commit 24be1179d432ad00292c62cda47ff22f01281810 Author: huang lin <hl(a)rock-chips.com> Date: Wed Mar 2 16:02:45 2016 +0800 rockchip: update make_idb.py make_idb.py only support RK3288 before, add chip parameter, so we can support RK3399 either. Change-Id: I6811acb7f0cdaf1930af9942a70db54765d544d5 Signed-off-by: huang lin <hl(a)rock-chips.com> --- src/soc/rockchip/rk3288/Makefile.inc | 2 +- util/rockchip/make_idb.py | 12 ++++++++---- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/soc/rockchip/rk3288/Makefile.inc b/src/soc/rockchip/rk3288/Makefile.inc index 0ce6425..0df7eb7 100644 --- a/src/soc/rockchip/rk3288/Makefile.inc +++ b/src/soc/rockchip/rk3288/Makefile.inc @@ -74,6 +74,6 @@ CPPFLAGS_common += -Isrc/soc/rockchip/rk3288/include/ $(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin @printf "Generating: $(subst $(obj)/,,$(@))\n" @mkdir -p $(dir $@) - @$(IDBTOOL) --from=$< --to=$@ --enable-align + @$(IDBTOOL) --from=$< --to=$@ --enable-align --chip=RK32 endif diff --git a/util/rockchip/make_idb.py b/util/rockchip/make_idb.py index 12ef83c..1ffb910 100755 --- a/util/rockchip/make_idb.py +++ b/util/rockchip/make_idb.py @@ -29,7 +29,7 @@ class IDBTool: k = (S[i] + S[j]) % 256 buf[x] = struct.pack('B', ord(buf[x]) ^ S[k]) - def makeIDB(self, from_file, to_file, rc4_flag = False, align_flag = False): + def makeIDB(self, chip, from_file, to_file, rc4_flag = False, align_flag = False): try: fin = open(from_file, 'rb') except: @@ -52,7 +52,7 @@ class IDBTool: sectors = pages * PAGE_ALIGN; buf = [B'\0'] * sectors * SECTOR_SIZE - buf[:4] = "RK32" + buf[:4] = chip buf[4 : 4+data_len] = data idblock = [B'\0'] * 4 * SECTOR_SIZE @@ -95,11 +95,13 @@ class IDBTool: print "DONE" def usage(): - print "Usage: make_idb.py [--enable-rc4] [--enable-align] [--to=out] --from=in" + print "Usage: make_idb.py [--chip=RKXX] [--enable-rc4] [--enable-align] [--to=out] --from=in" + print " --chip: default is RK32" if __name__ == '__main__': rc4_flag = align_flag = False to_file = "IDBlock.bin" + chip = "RK32" for para in sys.argv[1:]: if (para == "--enable-rc4"): @@ -110,6 +112,8 @@ if __name__ == '__main__': to_file = para.split('=')[1] elif (para.startswith("--from=")): from_file = para.split('=')[1] + elif (para.startswith("--chip=")): + chip = para.split('=')[1] elif (para == "--help" or para == "-h"): usage() sys.exit() @@ -121,4 +125,4 @@ if __name__ == '__main__': sys.exit() idbtool = IDBTool() - idbtool.makeIDB(from_file, to_file, rc4_flag, align_flag) + idbtool.makeIDB(chip, from_file, to_file, rc4_flag, align_flag)

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New patch to review for coreboot: nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS
by Patrick Rudolph 15 Mar '16

15 Mar '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14096 -gerrit commit 395c84b11f0967b96ac33d8b3506d8112e6e762a Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Mar 15 07:44:49 2016 +0100 nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS Set MMCONF_BASE_ADDRESS to 0xf8000000. It was already done for some boards, but not all. Increasing the address allows to use additional 128MiB of MMIO space and to use the Intel IGD and a PEG at the same time. Previously it wasn't possible two use both at the same time, as two 256MiB areas won't fit into MMIO space. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Onboard GPU Intel IvyBridge Desktop * PEG GPU AMD RV770 Change-Id: I3bf72439056c8089ada6899bb0605e5cd9d89cd6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/apple/macbookair4_2/Kconfig | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 2 +- src/mainboard/google/butterfly/Kconfig | 2 +- src/mainboard/google/link/Kconfig | 2 +- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/intel/emeraldlake2/Kconfig | 2 +- src/mainboard/kontron/ktqm77/Kconfig | 2 +- src/mainboard/lenovo/t420s/Kconfig | 2 +- src/mainboard/lenovo/t430s/Kconfig | 2 +- src/mainboard/lenovo/t520/Kconfig | 2 +- src/mainboard/lenovo/t530/Kconfig | 2 +- src/mainboard/lenovo/x220/Kconfig | 2 +- src/mainboard/lenovo/x230/Kconfig | 2 +- src/mainboard/samsung/lumpy/Kconfig | 2 +- src/mainboard/samsung/stumpy/Kconfig | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index e0cf022..08e7166 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -49,7 +49,7 @@ config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 987c8b7..e53b68c 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 320981a..4115a79 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 9c7fb5e..e61bba0 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 56ebf86..3483a81 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -31,7 +31,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 197099e..0aafc48 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 90b40ac..7671c30 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -26,7 +26,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 781833b..9f4d514 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -23,7 +23,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index dc279027..f5e99e7 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -40,7 +40,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 4e55eda..0c1d959 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index d5cee9e..664ce62 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -40,7 +40,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 257621f..fc94c20 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -42,7 +42,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index d30cbdc..0ef6689 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 3db0338..16e34ff 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 5f0f49f..14db934 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -33,7 +33,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index e511d83..4f14a6c 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -31,7 +31,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int

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Patch set updated for coreboot: soc/apollolake: Tear down cache-as-ram very early in ramstage
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13364 -gerrit commit 99f8bf54b8223eb83407e9ab4f1acc3f3e62ac6e Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 10 15:02:02 2016 -0800 soc/apollolake: Tear down cache-as-ram very early in ramstage Because of the reasons explained in the file, teardown of CAR needs to be done in ramstage. This patch addresses that issues in a way designed to minimize boot time. Change-Id: I6a0cb07f5b35ad42537da688e376ac96612990a6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/bootblock/cache_as_ram.S | 7 +- src/soc/intel/apollolake/car_teardown.c | 135 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 7 +- 4 files changed, 144 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..6bbfe57 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c +ramstage-y += car_teardown.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index c81fe0a..cc021dc 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -16,8 +16,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> - -#define EVICT_CTL_MSR 0x2e0 +#include <soc/cpu.h> .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -96,7 +95,7 @@ clear_var_mtrr: mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr @@ -112,7 +111,7 @@ clear_var_mtrr: post_code(0x27) /* Disable cache eviction (run stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr diff --git a/src/soc/intel/apollolake/car_teardown.c b/src/soc/intel/apollolake/car_teardown.c new file mode 100644 index 0000000..77d0dd4 --- /dev/null +++ b/src/soc/intel/apollolake/car_teardown.c @@ -0,0 +1,135 @@ +/* + * Cache-as-ram teardown for apollolake SOC. See detailed explanation below. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cbmem.h> +#include <memrange.h> +#include <soc/cpu.h> +#include <symbols.h> + +#define CACHELINE_SIZE 64 +/* + * The CAR teardown on apollolake is more complicated than the standard x86 + * teardown paths because romstage executes in CAR. That means romstage cannot + * do the teardown. For performance reasons, the cache is also used as a backing + * store for RAM after raminit. + * + * This results in a cache with both a CAR region, and memory-backed regions: + * - Invalidating the entire cache will evict stack and code that has not yet + * been commited, to RAM, resulting in a crash. + * - A 'wbinvd' will result in a crash during the write-back phase because + * the CAR region has no backing store. + * + * This teardown path resolves these problems by first flushing important data + * out of cache, to memory. After this operation, it is safe to invalidate the + * entire cache, which is then followed by standard MTRR housekeeping. + * + * For performance reasons, only the memory regions which may have been written + * to are flushed. This includes ramstage code and cbmem. A complete flush of + * all RAM ranges would take several seconds. + */ + +static void clflush(uintptr_t addr) +{ + __asm__ volatile ("clflush (%0)"::"r" (addr)); +} + +static void clflush_mem_range(uintptr_t start, uintptr_t end) +{ + end = ALIGN_UP(end, CACHELINE_SIZE); + + for (start = ALIGN_DOWN(start, CACHELINE_SIZE); start < end; + start += CACHELINE_SIZE) + clflush(start); +} + +static void flush_ram_cache_and_invalidate(void) +{ + uintptr_t cbmem_base; + size_t cbmem_size; + struct memranges ctx; + struct range_entry entries[3]; + const struct range_entry *r; + const struct cbmem_entry *fsp_rsvd_mem; + + memranges_init_empty(&ctx, entries, ARRAY_SIZE(entries)); + + /* Figure out where ramstage resides; this is inclusive of the stack */ + memranges_insert(&ctx, (uintptr_t)&_program, _program_size, 0); + + /* It's okay if CBMEM and ramstage overlap. */ + cbmem_region_used(&cbmem_base, &cbmem_size); + memranges_insert(&ctx, cbmem_base, cbmem_size, 0); + + /* + * FSP reserved memory was written before caching was enabled. Thus it + * does not need to be flushed. This saves about 10ms of boot time. + */ + fsp_rsvd_mem = cbmem_entry_find(CBMEM_ID_FSP_RESERVED_MEMORY); + if (fsp_rsvd_mem) { + memranges_create_hole(&ctx, + (uintptr_t)cbmem_entry_start(fsp_rsvd_mem), + cbmem_entry_size(fsp_rsvd_mem) + ); + } + + /* Flush ramstage code and stack */ + memranges_each_entry(r, &ctx) + clflush_mem_range(range_entry_base(r), range_entry_end(r)); + + /* Now that important data is flushed, invalidate all caches */ + invd(); +} + +static void disable_car_region_and_no_evict_mode(void) +{ + msr_t msr; + + /* Disable variable and fixed MTRRs */ + msr.lo = msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* Disable CAR MTRR */ + wrmsr(MTRR_PHYS_BASE(0), msr); + wrmsr(MTRR_PHYS_MASK(0), msr); + + /* Switch out of "no evict" mode */ + msr = rdmsr(MSR_EVICT_CTL); + msr.lo &= ~2; + wrmsr(MSR_EVICT_CTL, msr); + + msr.lo &= ~1; + wrmsr(MSR_EVICT_CTL, msr); + + /* Re-enable remaining MTRRs */ + msr.lo = MTRR_DEF_TYPE_EN; + msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); +} + +static void tear_down_car(void *unused_arg) +{ + (void) unused_arg; + + flush_ram_cache_and_invalidate(); + disable_car_region_and_no_evict_mode(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, tear_down_car, NULL); diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 765be70..b7b2fcc 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -13,19 +13,22 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ +#ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> #include <device/device.h> +void apollolake_init_cpus(struct device *dev); +#endif + #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 #define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_EVICT_CTL 0x2e0 #define BASE_CLOCK_MHZ 100 -void apollolake_init_cpus(struct device *dev); - #endif /* _SOC_APOLLOLAKE_CPU_H_ */

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Patch set updated for coreboot: soc/apollolake: Tear down cache-as-ram very early in ramstage
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13364 -gerrit commit 13f1a32a6ead5f5045c79936713e5206af8e8e0c Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 10 15:02:02 2016 -0800 soc/apollolake: Tear down cache-as-ram very early in ramstage Because of the reasons explained in the file, teardown of CAR needs to be done in ramstage. This patch addresses that issues in a way designed to minimize boot time. Change-Id: I6a0cb07f5b35ad42537da688e376ac96612990a6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/bootblock/cache_as_ram.S | 7 +- src/soc/intel/apollolake/car_teardown.c | 134 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 7 +- 4 files changed, 143 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..6bbfe57 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c +ramstage-y += car_teardown.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index c81fe0a..cc021dc 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -16,8 +16,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> - -#define EVICT_CTL_MSR 0x2e0 +#include <soc/cpu.h> .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -96,7 +95,7 @@ clear_var_mtrr: mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr @@ -112,7 +111,7 @@ clear_var_mtrr: post_code(0x27) /* Disable cache eviction (run stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr diff --git a/src/soc/intel/apollolake/car_teardown.c b/src/soc/intel/apollolake/car_teardown.c new file mode 100644 index 0000000..b866443 --- /dev/null +++ b/src/soc/intel/apollolake/car_teardown.c @@ -0,0 +1,134 @@ +/* + * Cache-as-ram teardown for apollolake SOC. See detailed explanation below. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cbmem.h> +#include <memrange.h> +#include <symbols.h> + +#define CACHELINE_SIZE 64 +/* + * The CAR teardown on apollolake is more complicated than the standard x86 + * teardown paths because romstage executes in CAR. That means romstage cannot + * do the teardown. For performance reasons, the cache is also used as a backing + * store for RAM after raminit. + * + * This results in a cache with both a CAR region, and memory-backed regions: + * - Invalidating the entire cache will evict stack and code that has not yet + * been commited, to RAM, resulting in a crash. + * - A 'wbinvd' will result in a crash during the write-back phase because + * the CAR region has no backing store. + * + * This teardown path resolves these problems by first flushing important data + * out of cache, to memory. After this operation, it is safe to invalidate the + * entire cache, which is then followed by standard MTRR housekeeping. + * + * For performance reasons, only the memory regions which may have been written + * to are flushed. This includes ramstage code and cbmem. A complete flush of + * all RAM ranges would take several seconds. + */ + +static void clflush(uintptr_t addr) +{ + __asm__ volatile ("clflush (%0)"::"r" (addr)); +} + +static void clflush_mem_range(uintptr_t start, uintptr_t end) +{ + end = ALIGN_UP(end, CACHELINE_SIZE); + + for (start = ALIGN_DOWN(start, CACHELINE_SIZE); start < end; + start += CACHELINE_SIZE) + clflush(start); +} + +static void flush_ram_cache_and_invalidate(void) +{ + uintptr_t cbmem_base; + size_t cbmem_size; + struct memranges ctx; + struct range_entry entries[3]; + const struct range_entry *r; + const struct cbmem_entry *fsp_rsvd_mem; + + memranges_init_empty(&ctx, entries, ARRAY_SIZE(entries)); + + /* Figure out where ramstage resides; this is inclusive of the stack */ + memranges_insert(&ctx, (uintptr_t)&_program, _program_size, 0); + + /* It's okay if CBMEM and ramstage overlap. */ + cbmem_region_used(&cbmem_base, &cbmem_size); + memranges_insert(&ctx, cbmem_base, cbmem_size, 0); + + /* + * FSP reserved memory was written before caching was enabled. Thus it + * does not need to be flushed. This saves about 10ms of boot time. + */ + fsp_rsvd_mem = cbmem_entry_find(CBMEM_ID_FSP_RESERVED_MEMORY); + if (fsp_rsvd_mem) { + memranges_create_hole(&ctx, + (uintptr_t)cbmem_entry_start(fsp_rsvd_mem), + cbmem_entry_size(fsp_rsvd_mem) + ); + } + + /* Flush ramstage code and stack */ + memranges_each_entry(r, &ctx) + clflush_mem_range(range_entry_base(r), range_entry_end(r)); + + /* Now that important data is flushed, invalidate all caches */ + invd(); +} + +static void disable_car_region_and_no_evict_mode(void) +{ + msr_t msr; + + /* Disable variable and fixed MTRRs */ + msr.lo = msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* Disable CAR MTRR */ + wrmsr(MTRR_PHYS_BASE(0), msr); + wrmsr(MTRR_PHYS_MASK(0), msr); + + /* Switch out of "no evict" mode */ + msr = rdmsr(MSR_EVICT_CTL); + msr.lo &= ~2; + wrmsr(MSR_EVICT_CTL, msr); + + msr.lo &= ~1; + wrmsr(MSR_EVICT_CTL, msr); + + /* Re-enable remaining MTRRs */ + msr.lo = MTRR_DEF_TYPE_EN; + msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); +} + +static void tear_down_car(void *unused_arg) +{ + (void) unused_arg; + + flush_ram_cache_and_invalidate(); + disable_car_region_and_no_evict_mode(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, tear_down_car, NULL); diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 765be70..b7b2fcc 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -13,19 +13,22 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ +#ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> #include <device/device.h> +void apollolake_init_cpus(struct device *dev); +#endif + #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 #define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_EVICT_CTL 0x2e0 #define BASE_CLOCK_MHZ 100 -void apollolake_init_cpus(struct device *dev); - #endif /* _SOC_APOLLOLAKE_CPU_H_ */

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Patch set updated for coreboot: soc/intel/apollolake: enable RAM cache for cbmem region in ramstage
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14095 -gerrit commit c400cdcb9d8db3598b164482b681d72bd8a1337b Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Mar 13 16:01:55 2016 -0700 soc/intel/apollolake: enable RAM cache for cbmem region in ramstage Since ramstage code as well as FSP code is run in cbmem that is placed in DRAM, it is imporant to have that region cached for performance reasons. This patch enables WB cache for 16MiB below cbmem top which is a safe bet ramstage is covered. Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 7c8924d..45899fd 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -15,6 +15,7 @@ #include <arch/symbols.h> #include <cbfs.h> #include <cbmem.h> +#include <cpu/x86/mtrr.h> #include <console/console.h> #include <device/pci_def.h> #include <fsp/api.h> @@ -80,6 +81,7 @@ asmlinkage void car_stage_entry(void) void *hob_list_ptr; struct range_entry fsp_mem; struct range_entry reg_car; + uintptr_t top_of_ram; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -95,6 +97,24 @@ asmlinkage void car_stage_entry(void) die("FSP memory init failed. Giving up."); } + /* + * Cache 16 MiB area right below cbmem, so that ramstage and FSP + * reserved memory ran cached. This assumes address is at least + * 16 MiB aligned. + * + * After this call we get: + * - Non-evict mode (NEM) is enabled + * - Write-back cache is active for small window in DRAM + * + * Since NEM mode blocks cache fills, memory operations do not make + * it into L2 cache. L1D cache however works in normal mode. Since + * L1 size is smaller than the actual working set, we are slower than + * fully fledged L2. However it is still about 10x faster than non- + * cached memory. + */ + top_of_ram = (uintptr_t) cbmem_top(); + set_var_mtrr(1, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); + fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */

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New patch to review for coreboot: soc/intel/apollolake: enable WB cache for cbmem region in romstage
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14095 -gerrit commit cecad57bcadecf45ae46b73f5ae6dab21aca01fd Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Mar 13 16:01:55 2016 -0700 soc/intel/apollolake: enable WB cache for cbmem region in romstage Since ramstage is run in cbmem that is placed in DRAM, it is imporant to have that region cached. This patch tries to cache 8MiB right below cbmem_top which is a safe bet ramstage is covered. Change-Id: I3f2f6e82f3b9060c7350ddff754cd3dbcf457671 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/romstage.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 7c8924d..159535c 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -15,6 +15,7 @@ #include <arch/symbols.h> #include <cbfs.h> #include <cbmem.h> +#include <cpu/x86/mtrr.h> #include <console/console.h> #include <device/pci_def.h> #include <fsp/api.h> @@ -80,6 +81,7 @@ asmlinkage void car_stage_entry(void) void *hob_list_ptr; struct range_entry fsp_mem; struct range_entry reg_car; + uintptr_t top_of_ram; printk(BIOS_DEBUG, "Starting romstage...\n"); @@ -95,6 +97,14 @@ asmlinkage void car_stage_entry(void) die("FSP memory init failed. Giving up."); } + /* + * Cache 16 MiB area right below cbmem, so that ramstage will be + * decompressed and ran from cached memory. This assumes address + * is at least 16 MiB aligned. + */ + top_of_ram = (uintptr_t) cbmem_top(); + set_var_mtrr(1, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); + fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); /* initialize cbmem by adding FSP reserved memory first thing */

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New patch to review for coreboot: cpu/x86: compile earlymtrr.c code for romstage as well
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14094 -gerrit commit 2cc74b375c8e677861368f1a6cfaccedefc51b2f Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Sun Mar 13 16:01:04 2016 -0700 cpu/x86: compile earlymtrr.c code for romstage as well Change-Id: If4f5494a53773454b97b90fb856f7e52cadb3f44 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/cpu/x86/mtrr/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/cpu/x86/mtrr/Makefile.inc b/src/cpu/x86/mtrr/Makefile.inc index cecb826..9b7207b 100644 --- a/src/cpu/x86/mtrr/Makefile.inc +++ b/src/cpu/x86/mtrr/Makefile.inc @@ -1 +1,2 @@ ramstage-y += mtrr.c +romstage-y += earlymtrr.c

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Patch set updated for coreboot: soc/apollolake: Tear down cache-as-ram very early in ramstage
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13364 -gerrit commit efd91b5651a9af3fdd072d8f987f3fa2c87060a9 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 10 15:02:02 2016 -0800 soc/apollolake: Tear down cache-as-ram very early in ramstage Because of the reasons explained in the file, teardown of CAR needs to be done in ramstage. This patch addresses that issues in a way designed to minimize boot time. Teardown currently takes about 7 ms. Change-Id: I6a0cb07f5b35ad42537da688e376ac96612990a6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/bootblock/cache_as_ram.S | 7 +- src/soc/intel/apollolake/car_teardown.c | 135 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 7 +- 4 files changed, 144 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..6bbfe57 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c +ramstage-y += car_teardown.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index c81fe0a..cc021dc 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -16,8 +16,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> - -#define EVICT_CTL_MSR 0x2e0 +#include <soc/cpu.h> .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -96,7 +95,7 @@ clear_var_mtrr: mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr @@ -112,7 +111,7 @@ clear_var_mtrr: post_code(0x27) /* Disable cache eviction (run stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr diff --git a/src/soc/intel/apollolake/car_teardown.c b/src/soc/intel/apollolake/car_teardown.c new file mode 100644 index 0000000..d2df7f7 --- /dev/null +++ b/src/soc/intel/apollolake/car_teardown.c @@ -0,0 +1,135 @@ +/* + * Cache-as-ram teardown for apollolake SOC. See detailed explanation below. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cbmem.h> +#include <memrange.h> +#include <symbols.h> + +#define EVICT_CTL_MSR 0x2e0 +#define CACHELINE_SIZE 64 +/* + * The CAR teardown on apollolake is more complicated than the standard x86 + * teardown paths because romstage executes in CAR. That means romstage cannot + * do the teardown. For performance reasons, the cache is also used as a backing + * store for RAM after raminit. + * + * This results in a cache with both a CAR region, and memory-backed regions: + * - Invalidating the entire cache will evict stack and code that has not yet + * been commited, to RAM, resulting in a crash. + * - A 'wbinvd' will result in a crash during the write-back phase because + * the CAR region has no backing store. + * + * This teardown path resolves these problems by first flushing important data + * out of cache, to memory. After this operation, it is safe to invalidate the + * entire cache, which is then followed by standard MTRR housekeeping. + * + * For performance reasons, only the memory regions which may have been written + * to are flushed. This includes ramstage code and cbmem. A complete flush of + * all RAM ranges would take several seconds. + */ + +static void clflush(uintptr_t addr) +{ + __asm__ volatile ("clflush (%0)"::"r" (addr)); +} + +static void clflush_mem_range(uintptr_t start, uintptr_t end) +{ + end = ALIGN_UP(end, CACHELINE_SIZE); + + for (start = ALIGN_DOWN(start, CACHELINE_SIZE); start < end; + start += CACHELINE_SIZE) + clflush(start); +} + +static void flush_ram_cache_and_invalidate(void) +{ + uintptr_t cbmem_base; + size_t cbmem_size; + struct memranges ctx; + struct range_entry entries[3]; + const struct range_entry *r; + const struct cbmem_entry *fsp_rsvd_mem; + + memranges_init_empty(&ctx, entries, ARRAY_SIZE(entries)); + + /* Figure out where ramstage resides; this is inclusive of the stack */ + memranges_insert(&ctx, (uintptr_t)&_program, _program_size, 0); + + /* It's okay if CBMEM and ramstage overlap. */ + cbmem_region_used(&cbmem_base, &cbmem_size); + memranges_insert(&ctx, cbmem_base, cbmem_size, 0); + + /* + * FSP reserved memory was written before caching was enabled. Thus it + * does not need to be flushed. This saves about 10ms of boot time. + */ + fsp_rsvd_mem = cbmem_entry_find(CBMEM_ID_FSP_RESERVED_MEMORY); + if (fsp_rsvd_mem) { + memranges_create_hole(&ctx, + (uintptr_t)cbmem_entry_start(fsp_rsvd_mem), + cbmem_entry_size(fsp_rsvd_mem) + ); + } + + /* Flush ramstage code and stack */ + memranges_each_entry(r, &ctx) + clflush_mem_range(range_entry_base(r), range_entry_end(r)); + + /* Now that important data is flushed, invalidate all caches */ + invd(); +} + +static void disable_car_region_and_no_evict_mode(void) +{ + msr_t msr; + + /* Disable variable and fixed MTRRs */ + msr.lo = msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* Disable CAR MTRR */ + wrmsr(MTRR_PHYS_BASE(0), msr); + wrmsr(MTRR_PHYS_MASK(0), msr); + + /* Switch out of "no evict" mode */ + msr = rdmsr(EVICT_CTL_MSR); + msr.lo &= ~2; + wrmsr(EVICT_CTL_MSR, msr); + + msr.lo &= ~1; + wrmsr(EVICT_CTL_MSR, msr); + + /* Re-enable remaining MTRRs */ + msr.lo = MTRR_DEF_TYPE_EN; + msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); +} + +static void tear_down_car(void *unused_arg) +{ + (void) unused_arg; + + flush_ram_cache_and_invalidate(); + disable_car_region_and_no_evict_mode(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, tear_down_car, NULL); diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 765be70..b7b2fcc 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -13,19 +13,22 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ +#ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> #include <device/device.h> +void apollolake_init_cpus(struct device *dev); +#endif + #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 #define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_EVICT_CTL 0x2e0 #define BASE_CLOCK_MHZ 100 -void apollolake_init_cpus(struct device *dev); - #endif /* _SOC_APOLLOLAKE_CPU_H_ */

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Patch set updated for coreboot: soc/apollolake: Add skeleton ACPI entry
by Lijian Zhao 15 Mar '16

15 Mar '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13348 -gerrit commit b4ddbdd0376ff457e962bbec0be3f8085df21fd6 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 9 17:06:34 2015 -0800 soc/apollolake: Add skeleton ACPI entry Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 1 + src/mainboard/intel/apollolake_rvp/acpi_tables.c | 17 +++++++++++++ src/mainboard/intel/apollolake_rvp/dsdt.asl | 29 ++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 31 +++++++++++++----------- src/soc/intel/apollolake/acpi.c | 22 +++++++++++++++++ 5 files changed, 86 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 9920b46..5006695 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c new file mode 100644 index 0000000..fb3e9c4 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ +} diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl new file mode 100644 index 0000000..1736cea --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + +} diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..7efb3ba 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -6,34 +6,37 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache -bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/bootblock_car.c bootblock-y += gpio.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += bootblock/early_chipset_config.S bootblock-y += mmap_boot.c -bootblock-y += placeholders.c bootblock-y += tsc_freq.c -bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +bootblock-y += uart_early.c -romstage-y += placeholders.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += gpio.c -romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c +romstage-y += romstage/romstage.c +romstage-y += tsc_freq.c +romstage-y += uart_early.c -smm-y += placeholders.c -ramstage-y += cpu.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c -ramstage-y += placeholders.c +ramstage-y += cpu.c ramstage-y += gpio.c -ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += tsc_freq.c ramstage-y += uart.c -ramstage-y += northbridge.c + +romstage-y += placeholders.c +smm-y += placeholders.c +ramstage-y += placeholders.c + +# cpu_microcode_bins += ??? CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..d5624c6 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return 0; +} +unsigned long acpi_fill_madt(unsigned long current) +{ + return 0; +}

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coreboot-gerrit March 2016