coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

Patch merged into coreboot/master: coreinfo: Pretty print RAM addresses
by gerrit＠coreboot.org 15 Mar '16

15 Mar '16

the following patch was just integrated into master: commit 31575f6391912ff32eca4b990de55e771662998b Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 12:17:48 2016 -0800 coreinfo: Pretty print RAM addresses Instead of 500, print 0x00000500 in the ram dump module. Change-Id: Id250bd99f36dad4088ab88953fb371c400b4231b Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14072 Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14072 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Move MEMMAP_RAM_ONLY to generic options
by gerrit＠coreboot.org 15 Mar '16

15 Mar '16

the following patch was just integrated into master: commit 1e6b86b8b664e05f5b2672dce46fd2fec8a47c71 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 12:14:46 2016 -0800 libpayload: Move MEMMAP_RAM_ONLY to generic options MEMMAP_RAM_ONLY is not an architecture specific option, hence move it out of the architecture specific menu. Change-Id: Iaeef03ed8cbff930a580ad03b1e712087b48714e Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14071 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14071 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Drop CONFIG_LP_CHROMEOS
by gerrit＠coreboot.org 15 Mar '16

15 Mar '16

the following patch was just integrated into master: commit 8fda04449f5ff89af6fd2a7b1ca071806bc7def7 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 12:12:14 2016 -0800 libpayload: Drop CONFIG_LP_CHROMEOS This is adding complexity to the code more than it saves space, plus some of the tables could potentially be interesting outside of the ChromeOS context. Change-Id: I4bf24608f3e26d3b7871a5031ae8f03bc2c8c21f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14070 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14070 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Unify defconfigs
by gerrit＠coreboot.org 15 Mar '16

15 Mar '16

the following patch was just integrated into master: commit 96d14ac1c9b81cf1347c3f2c66f847d6d4527b8e Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Mar 12 11:51:18 2016 -0800 libpayload: Unify defconfigs Bring defconfig and defconfig-tinycurses in sync, so that defconfig and defconfig-tinycurses only differ in the selection of the curses implementation. Change-Id: I739c5122b5aaaa2681055c845905721a0b2a11c1 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: https://review.coreboot.org/14069 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/14069 for details. -gerrit

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Patch set updated for coreboot: soc/apollolake: Add skeleton ACPI entry
by Lijian Zhao 15 Mar '16

15 Mar '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13348 -gerrit commit f321d656fe4935dbd65b88e7597ad314813769a1 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 9 17:06:34 2015 -0800 soc/apollolake: Add skeleton ACPI entry Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 1 + src/mainboard/intel/apollolake_rvp/acpi_tables.c | 17 ++++++++++++++ src/mainboard/intel/apollolake_rvp/dsdt.asl | 29 ++++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 27 ++++++++++------------ src/soc/intel/apollolake/acpi.c | 22 ++++++++++++++++++ 5 files changed, 81 insertions(+), 15 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 9920b46..5006695 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c new file mode 100644 index 0000000..95de1f5 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ +} diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl new file mode 100644 index 0000000..7b9fe29 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + +} diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..422f80a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -6,34 +6,31 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S -bootblock-y += bootblock/bootblock.c -bootblock-y += gpio.c -bootblock-y += mmap_boot.c -bootblock-y += placeholders.c -bootblock-y += tsc_freq.c -bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c -romstage-y += placeholders.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c -romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c +romstage-y += romstage.c +romstage-y += tsc_freq.c +romstage-y += uart_early.c -smm-y += placeholders.c -ramstage-y += cpu.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c -ramstage-y += placeholders.c +ramstage-y += cpu.c ramstage-y += gpio.c -ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += tsc_freq.c ramstage-y += uart.c -ramstage-y += northbridge.c + +romstage-y += placeholders.c +smm-y += placeholders.c +ramstage-y += placeholders.c + +# cpu_microcode_bins += ??? CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..d7249c2 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return 0; +} +unsigned long acpi_fill_madt(unsigned long current) +{ + return 0; +}

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Patch set updated for coreboot: soc/apollolake: Add skeleton ACPI entry
by Lijian Zhao 15 Mar '16

15 Mar '16

Lijian Zhao (lijian.zhao(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13348 -gerrit commit e199921f475cce65f59de454ce3c84aff751f1c5 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 9 17:06:34 2015 -0800 soc/apollolake: Add skeleton ACPI entry Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 1 + src/mainboard/intel/apollolake_rvp/acpi_tables.c | 17 +++++++++++++ src/mainboard/intel/apollolake_rvp/dsdt.asl | 29 ++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 31 +++++++++++++----------- src/soc/intel/apollolake/acpi.c | 22 +++++++++++++++++ 5 files changed, 86 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 9920b46..5006695 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c new file mode 100644 index 0000000..95de1f5 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ +} diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl new file mode 100644 index 0000000..7b9fe29 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + +} diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..7efb3ba 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -6,34 +6,37 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache -bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/bootblock_car.c bootblock-y += gpio.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += bootblock/early_chipset_config.S bootblock-y += mmap_boot.c -bootblock-y += placeholders.c bootblock-y += tsc_freq.c -bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +bootblock-y += uart_early.c -romstage-y += placeholders.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += gpio.c -romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c +romstage-y += romstage/romstage.c +romstage-y += tsc_freq.c +romstage-y += uart_early.c -smm-y += placeholders.c -ramstage-y += cpu.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c -ramstage-y += placeholders.c +ramstage-y += cpu.c ramstage-y += gpio.c -ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += tsc_freq.c ramstage-y += uart.c -ramstage-y += northbridge.c + +romstage-y += placeholders.c +smm-y += placeholders.c +ramstage-y += placeholders.c + +# cpu_microcode_bins += ??? CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..d7249c2 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return 0; +} +unsigned long acpi_fill_madt(unsigned long current) +{ + return 0; +}

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Patch set updated for coreboot: soc/apollolake: Add skeleton ACPI entry
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13348 -gerrit commit f1acb810c3917ae354bb6abd9d52037a8f649da8 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 9 17:06:34 2015 -0800 soc/apollolake: Add skeleton ACPI entry Add skeletion ACPI tables, including DSDT and entry of FADT, FACS. Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 1 + src/mainboard/intel/apollolake_rvp/acpi_tables.c | 17 +++++++++++++ src/mainboard/intel/apollolake_rvp/dsdt.asl | 29 ++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 31 +++++++++++++----------- src/soc/intel/apollolake/acpi.c | 22 +++++++++++++++++ 5 files changed, 86 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 9920b46..5006695 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c new file mode 100644 index 0000000..9812ac2 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ +} diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl new file mode 100644 index 0000000..53f92b4 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + +} diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..7efb3ba 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -6,34 +6,37 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache -bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/bootblock_car.c bootblock-y += gpio.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += bootblock/early_chipset_config.S bootblock-y += mmap_boot.c -bootblock-y += placeholders.c bootblock-y += tsc_freq.c -bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +bootblock-y += uart_early.c -romstage-y += placeholders.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += gpio.c -romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c +romstage-y += romstage/romstage.c +romstage-y += tsc_freq.c +romstage-y += uart_early.c -smm-y += placeholders.c -ramstage-y += cpu.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c -ramstage-y += placeholders.c +ramstage-y += cpu.c ramstage-y += gpio.c -ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += tsc_freq.c ramstage-y += uart.c -ramstage-y += northbridge.c + +romstage-y += placeholders.c +smm-y += placeholders.c +ramstage-y += placeholders.c + +# cpu_microcode_bins += ??? CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..b945e40 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return 0; +} +unsigned long acpi_fill_madt(unsigned long current) +{ + return 0; +}

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Patch set updated for coreboot: soc/apollolake: Add skeleton ACPI entry
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13348 -gerrit commit 7fb01b49ae764776865f65709cf0154e5c945e08 Author: Lance Zhao <lijian.zhao(a)intel.com> Date: Mon Nov 9 17:06:34 2015 -0800 soc/apollolake: Add skeleton ACPI entry Change-Id: Ib127af5392ca2b349480f5b21fad2186b444d7e6 Signed-off-by: Lance Zhao <lijian.zhao(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 1 + src/mainboard/intel/apollolake_rvp/acpi_tables.c | 17 +++++++++++++ src/mainboard/intel/apollolake_rvp/dsdt.asl | 29 ++++++++++++++++++++++ src/soc/intel/apollolake/Makefile.inc | 31 +++++++++++++----------- src/soc/intel/apollolake/acpi.c | 22 +++++++++++++++++ 5 files changed, 86 insertions(+), 14 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 9920b46..5006695 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -4,6 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y select SOC_INTEL_APOLLOLAKE select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES config MAINBOARD_DIR string diff --git a/src/mainboard/intel/apollolake_rvp/acpi_tables.c b/src/mainboard/intel/apollolake_rvp/acpi_tables.c new file mode 100644 index 0000000..9812ac2 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/acpi_tables.c @@ -0,0 +1,17 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt) +{ +} diff --git a/src/mainboard/intel/apollolake_rvp/dsdt.asl b/src/mainboard/intel/apollolake_rvp/dsdt.asl new file mode 100644 index 0000000..53f92b4 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/dsdt.asl @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + +} diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..7efb3ba 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -6,34 +6,37 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc -subdirs-y += ../../../cpu/x86/cache -bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S -bootblock-y += bootblock/bootblock.c +bootblock-y += bootblock/bootblock_car.c bootblock-y += gpio.c +bootblock-y += bootblock/cache_as_ram.S +bootblock-y += bootblock/early_chipset_config.S bootblock-y += mmap_boot.c -bootblock-y += placeholders.c bootblock-y += tsc_freq.c -bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +bootblock-y += uart_early.c -romstage-y += placeholders.c -romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += gpio.c -romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += memmap.c romstage-y += mmap_boot.c +romstage-y += romstage/romstage.c +romstage-y += tsc_freq.c +romstage-y += uart_early.c -smm-y += placeholders.c -ramstage-y += cpu.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c -ramstage-y += placeholders.c +ramstage-y += cpu.c ramstage-y += gpio.c -ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += memmap.c ramstage-y += mmap_boot.c +ramstage-y += tsc_freq.c ramstage-y += uart.c -ramstage-y += northbridge.c + +romstage-y += placeholders.c +smm-y += placeholders.c +ramstage-y += placeholders.c + +# cpu_microcode_bins += ??? CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c new file mode 100644 index 0000000..b945e40 --- /dev/null +++ b/src/soc/intel/apollolake/acpi.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/acpi.h> + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + return 0; +} +unsigned long acpi_fill_madt(unsigned long current) +{ + return 0; +}

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Patch set updated for coreboot: nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS
by Martin Roth 15 Mar '16

15 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14096 -gerrit commit 56e23e80059f164f0e2c41518d065226f5928051 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Mar 15 07:44:49 2016 +0100 nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS Set MMCONF_BASE_ADDRESS to 0xf8000000. It was already done for some boards, but not all. Increasing the address allows to use additional 128MiB of MMIO space and to use the Intel IGD and a PEG at the same time. Previously it wasn't possible two use both at the same time, as two 256MiB areas won't fit into MMIO space. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Onboard GPU Intel IvyBridge Desktop * PEG GPU AMD RV770 Change-Id: I3bf72439056c8089ada6899bb0605e5cd9d89cd6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/mainboard/apple/macbookair4_2/Kconfig | 2 +- src/mainboard/gigabyte/ga-b75m-d3h/Kconfig | 2 +- src/mainboard/google/butterfly/Kconfig | 2 +- src/mainboard/google/link/Kconfig | 2 +- src/mainboard/google/parrot/Kconfig | 2 +- src/mainboard/google/stout/Kconfig | 2 +- src/mainboard/intel/emeraldlake2/Kconfig | 2 +- src/mainboard/kontron/ktqm77/Kconfig | 2 +- src/mainboard/lenovo/t420s/Kconfig | 2 +- src/mainboard/lenovo/t430s/Kconfig | 2 +- src/mainboard/lenovo/t520/Kconfig | 2 +- src/mainboard/lenovo/t530/Kconfig | 2 +- src/mainboard/lenovo/x220/Kconfig | 2 +- src/mainboard/lenovo/x230/Kconfig | 2 +- src/mainboard/samsung/lumpy/Kconfig | 2 +- src/mainboard/samsung/stumpy/Kconfig | 2 +- 16 files changed, 16 insertions(+), 16 deletions(-) diff --git a/src/mainboard/apple/macbookair4_2/Kconfig b/src/mainboard/apple/macbookair4_2/Kconfig index e0cf022..08e7166 100644 --- a/src/mainboard/apple/macbookair4_2/Kconfig +++ b/src/mainboard/apple/macbookair4_2/Kconfig @@ -49,7 +49,7 @@ config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig index 987c8b7..e53b68c 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig +++ b/src/mainboard/gigabyte/ga-b75m-d3h/Kconfig @@ -20,7 +20,7 @@ config BOARD_SPECIFIC_OPTIONS config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config DRAM_RESET_GATE_GPIO int diff --git a/src/mainboard/google/butterfly/Kconfig b/src/mainboard/google/butterfly/Kconfig index 320981a..4115a79 100644 --- a/src/mainboard/google/butterfly/Kconfig +++ b/src/mainboard/google/butterfly/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/google/link/Kconfig b/src/mainboard/google/link/Kconfig index 9c7fb5e..e61bba0 100644 --- a/src/mainboard/google/link/Kconfig +++ b/src/mainboard/google/link/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/google/parrot/Kconfig b/src/mainboard/google/parrot/Kconfig index 56ebf86..3483a81 100644 --- a/src/mainboard/google/parrot/Kconfig +++ b/src/mainboard/google/parrot/Kconfig @@ -31,7 +31,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/google/stout/Kconfig b/src/mainboard/google/stout/Kconfig index 197099e..0aafc48 100644 --- a/src/mainboard/google/stout/Kconfig +++ b/src/mainboard/google/stout/Kconfig @@ -30,7 +30,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/intel/emeraldlake2/Kconfig b/src/mainboard/intel/emeraldlake2/Kconfig index 90b40ac..7671c30 100644 --- a/src/mainboard/intel/emeraldlake2/Kconfig +++ b/src/mainboard/intel/emeraldlake2/Kconfig @@ -26,7 +26,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 781833b..9f4d514 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -23,7 +23,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index dc279027..f5e99e7 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -40,7 +40,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index 4e55eda..0c1d959 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index d5cee9e..664ce62 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -40,7 +40,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index 257621f..fc94c20 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -42,7 +42,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/x220/Kconfig b/src/mainboard/lenovo/x220/Kconfig index d30cbdc..0ef6689 100644 --- a/src/mainboard/lenovo/x220/Kconfig +++ b/src/mainboard/lenovo/x220/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/lenovo/x230/Kconfig b/src/mainboard/lenovo/x230/Kconfig index 3db0338..16e34ff 100644 --- a/src/mainboard/lenovo/x230/Kconfig +++ b/src/mainboard/lenovo/x230/Kconfig @@ -41,7 +41,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/samsung/lumpy/Kconfig b/src/mainboard/samsung/lumpy/Kconfig index 5f0f49f..14db934 100644 --- a/src/mainboard/samsung/lumpy/Kconfig +++ b/src/mainboard/samsung/lumpy/Kconfig @@ -33,7 +33,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int diff --git a/src/mainboard/samsung/stumpy/Kconfig b/src/mainboard/samsung/stumpy/Kconfig index e511d83..4f14a6c 100644 --- a/src/mainboard/samsung/stumpy/Kconfig +++ b/src/mainboard/samsung/stumpy/Kconfig @@ -31,7 +31,7 @@ config MAINBOARD_PART_NUMBER config MMCONF_BASE_ADDRESS hex - default 0xf0000000 + default 0xf8000000 config MAX_CPUS int

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Patch set updated for coreboot: soc/apollolake: Tear down cache-as-ram very early in ramstage
by Andrey Petrov 15 Mar '16

15 Mar '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13364 -gerrit commit 33abbe28dabdad33c1d4803e7d344557e00bd9a5 Author: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Date: Thu Mar 10 15:02:02 2016 -0800 soc/apollolake: Tear down cache-as-ram very early in ramstage Because of the reasons explained in the file, teardown of CAR needs to be done in ramstage. This patch addresses that issues in a way designed to minimize boot time. Change-Id: I6a0cb07f5b35ad42537da688e376ac96612990a6 Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/bootblock/cache_as_ram.S | 7 +- src/soc/intel/apollolake/car_teardown.c | 135 ++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/cpu.h | 7 +- 4 files changed, 144 insertions(+), 6 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4e05726..6bbfe57 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -25,6 +25,7 @@ romstage-y += memmap.c romstage-y += mmap_boot.c smm-y += placeholders.c +ramstage-y += car_teardown.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram.S b/src/soc/intel/apollolake/bootblock/cache_as_ram.S index c81fe0a..cc021dc 100644 --- a/src/soc/intel/apollolake/bootblock/cache_as_ram.S +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram.S @@ -16,8 +16,7 @@ #include <cpu/x86/cache.h> #include <cpu/x86/cr.h> #include <cpu/x86/post_code.h> - -#define EVICT_CTL_MSR 0x2e0 +#include <soc/cpu.h> .global bootblock_pre_c_entry bootblock_pre_c_entry: @@ -96,7 +95,7 @@ clear_var_mtrr: mov %eax, %cr0 /* Disable cache eviction (setup stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x1, %eax wrmsr @@ -112,7 +111,7 @@ clear_var_mtrr: post_code(0x27) /* Disable cache eviction (run stage) */ - mov $EVICT_CTL_MSR, %ecx + mov $MSR_EVICT_CTL, %ecx rdmsr or $0x2, %eax wrmsr diff --git a/src/soc/intel/apollolake/car_teardown.c b/src/soc/intel/apollolake/car_teardown.c new file mode 100644 index 0000000..77d0dd4 --- /dev/null +++ b/src/soc/intel/apollolake/car_teardown.c @@ -0,0 +1,135 @@ +/* + * Cache-as-ram teardown for apollolake SOC. See detailed explanation below. + * + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <bootstate.h> +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/msr.h> +#include <cpu/x86/tsc.h> +#include <cbmem.h> +#include <memrange.h> +#include <soc/cpu.h> +#include <symbols.h> + +#define CACHELINE_SIZE 64 +/* + * The CAR teardown on apollolake is more complicated than the standard x86 + * teardown paths because romstage executes in CAR. That means romstage cannot + * do the teardown. For performance reasons, the cache is also used as a backing + * store for RAM after raminit. + * + * This results in a cache with both a CAR region, and memory-backed regions: + * - Invalidating the entire cache will evict stack and code that has not yet + * been commited, to RAM, resulting in a crash. + * - A 'wbinvd' will result in a crash during the write-back phase because + * the CAR region has no backing store. + * + * This teardown path resolves these problems by first flushing important data + * out of cache, to memory. After this operation, it is safe to invalidate the + * entire cache, which is then followed by standard MTRR housekeeping. + * + * For performance reasons, only the memory regions which may have been written + * to are flushed. This includes ramstage code and cbmem. A complete flush of + * all RAM ranges would take several seconds. + */ + +static void clflush(uintptr_t addr) +{ + __asm__ volatile ("clflush (%0)"::"r" (addr)); +} + +static void clflush_mem_range(uintptr_t start, uintptr_t end) +{ + end = ALIGN_UP(end, CACHELINE_SIZE); + + for (start = ALIGN_DOWN(start, CACHELINE_SIZE); start < end; + start += CACHELINE_SIZE) + clflush(start); +} + +static void flush_ram_cache_and_invalidate(void) +{ + uintptr_t cbmem_base; + size_t cbmem_size; + struct memranges ctx; + struct range_entry entries[3]; + const struct range_entry *r; + const struct cbmem_entry *fsp_rsvd_mem; + + memranges_init_empty(&ctx, entries, ARRAY_SIZE(entries)); + + /* Figure out where ramstage resides; this is inclusive of the stack */ + memranges_insert(&ctx, (uintptr_t)&_program, _program_size, 0); + + /* It's okay if CBMEM and ramstage overlap. */ + cbmem_region_used(&cbmem_base, &cbmem_size); + memranges_insert(&ctx, cbmem_base, cbmem_size, 0); + + /* + * FSP reserved memory was written before caching was enabled. Thus it + * does not need to be flushed. This saves about 10ms of boot time. + */ + fsp_rsvd_mem = cbmem_entry_find(CBMEM_ID_FSP_RESERVED_MEMORY); + if (fsp_rsvd_mem) { + memranges_create_hole(&ctx, + (uintptr_t)cbmem_entry_start(fsp_rsvd_mem), + cbmem_entry_size(fsp_rsvd_mem) + ); + } + + /* Flush ramstage code and stack */ + memranges_each_entry(r, &ctx) + clflush_mem_range(range_entry_base(r), range_entry_end(r)); + + /* Now that important data is flushed, invalidate all caches */ + invd(); +} + +static void disable_car_region_and_no_evict_mode(void) +{ + msr_t msr; + + /* Disable variable and fixed MTRRs */ + msr.lo = msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); + /* Disable CAR MTRR */ + wrmsr(MTRR_PHYS_BASE(0), msr); + wrmsr(MTRR_PHYS_MASK(0), msr); + + /* Switch out of "no evict" mode */ + msr = rdmsr(MSR_EVICT_CTL); + msr.lo &= ~2; + wrmsr(MSR_EVICT_CTL, msr); + + msr.lo &= ~1; + wrmsr(MSR_EVICT_CTL, msr); + + /* Re-enable remaining MTRRs */ + msr.lo = MTRR_DEF_TYPE_EN; + msr.hi = 0; + wrmsr(MTRR_DEF_TYPE_MSR, msr); +} + +static void tear_down_car(void *unused_arg) +{ + (void) unused_arg; + + flush_ram_cache_and_invalidate(); + disable_car_region_and_no_evict_mode(); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, tear_down_car, NULL); diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index 765be70..b7b2fcc 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -13,19 +13,22 @@ #ifndef _SOC_APOLLOLAKE_CPU_H_ #define _SOC_APOLLOLAKE_CPU_H_ +#ifndef __ASSEMBLER__ #include <cpu/x86/msr.h> #include <device/device.h> +void apollolake_init_cpus(struct device *dev); +#endif + #define CPUID_APOLLOLAKE_A0 0x506c8 #define CPUID_APOLLOLAKE_B0 0x506c9 #define MSR_PLATFORM_INFO 0xce #define MSR_POWER_MISC 0x120 #define MSR_CORE_THREAD_COUNT 0x35 +#define MSR_EVICT_CTL 0x2e0 #define BASE_CLOCK_MHZ 100 -void apollolake_init_cpus(struct device *dev); - #endif /* _SOC_APOLLOLAKE_CPU_H_ */

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coreboot-gerrit March 2016