coreboot-gerrit March 2016

coreboot-gerrit@coreboot.org

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1119 discussions

New patch to review for coreboot: google/chell: Update DPTF thermal parameters
by Patrick Georgi 17 Mar '16

17 Mar '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14119 -gerrit commit 902dcd4ba7b7a0c44409f6d8fa05bddfdc849ce8 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Mar 15 16:42:07 2016 -0700 google/chell: Update DPTF thermal parameters MinPL1: 2.5W MaxPL1: 7W StepPL1: 0.25W _PSV(TSR2): 51C _TRT(TSR2): 9 second BUG=chrome-os-partner:49859 BRANCH=glados TEST=build and boot on chell Change-Id: I69de1d66fb0d52ad0ad77eb51ca56f50fc44c255 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 845f1d046a5143057d683b2bd9cf5dab2ab2ef34 Original-Change-Id: I8a161c979a22621f5f854926677cb7835f8ce88b Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/332857 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-(cherry picked from commit 4d5023524591fc6b651a199874ed990bd5be1d50) Original-Reviewed-on: https://chromium-review.googlesource.com/333071 --- src/mainboard/google/chell/acpi/dptf.asl | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/chell/acpi/dptf.asl b/src/mainboard/google/chell/acpi/dptf.asl index d3549a7..5af788d 100644 --- a/src/mainboard/google/chell/acpi/dptf.asl +++ b/src/mainboard/google/chell/acpi/dptf.asl @@ -29,7 +29,7 @@ #define DPTF_TSR2_SENSOR_ID 3 #define DPTF_TSR2_SENSOR_NAME "DRAM" -#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_PASSIVE 51 #define DPTF_TSR2_CRITICAL 75 #define DPTF_TSR3_SENSOR_ID 4 @@ -63,7 +63,7 @@ Name (DTRT, Package () { Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 2 */ - Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 90, 0, 0, 0, 0 }, /* Charger Effect on Temp Sensor 2 */ Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 }, @@ -77,11 +77,11 @@ Name (MPPC, Package () 0x2, /* Revision */ Package () { /* Power Limit 1 */ 0, /* PowerLimitIndex, 0 for Power Limit 1 */ - 1600, /* PowerLimitMinimum */ - 6000, /* PowerLimitMaximum */ + 2500, /* PowerLimitMinimum */ + 7000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ - 200 /* StepSize */ + 250 /* StepSize */ }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */

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Patch set updated for coreboot: lint: Update board status script to look at the whole tree
by Martin Roth 17 Mar '16

17 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14118 -gerrit commit 3ea1c39007dbd1a71fa1fd32e64f27c2777a4bd2 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 15:58:23 2016 -0600 lint: Update board status script to look at the whole tree The board status script wasn't checking the entire tree to make sure that all boards had board_info.txt files. Also it would only print out the first issue that was found. Change-Id: I5f2fa9e564c805c6dbee7a35cab80c1c342567a5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-005-board-status | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status index 61813ea..952a9b5 100755 --- a/util/lint/lint-stable-005-board-status +++ b/util/lint/lint-stable-005-board-status @@ -16,11 +16,11 @@ # DESCR: Check that every board has a meaningful board_info.txt LC_ALL=C export LC_ALL -for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do +for mobodir in $(git ls-files src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do board_info="$mobodir/board_info.txt" if ! [ -f "$board_info" ]; then echo "No $board_info found" - exit 1 + continue fi category="$(sed -n 's#^Category: $.*$$#\1#p' < "$board_info")" case "$category" in @@ -28,11 +28,11 @@ for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n ;; "") echo "$board_info doesn't contain 'Category' tag" - exit 1 + continue ;; *) echo "$board_info specifies unknown category '$category'" - exit 1 + continue ;; esac done

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Patch set updated for coreboot: google/intel mainboards: Add missing board_info.txt files
by Martin Roth 17 Mar '16

17 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14117 -gerrit commit bec87ff253db9de2d96839843ef70fc928bdf0c5 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 18:36:35 2016 -0600 google/intel mainboards: Add missing board_info.txt files The lint script didn't catch that these mainboard directories didn't have board_info files. Add all missing board_info.txt files Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/auron_paine/board_info.txt | 6 ++++++ src/mainboard/google/chell/board_info.txt | 6 ++++++ src/mainboard/google/cosmos/board_info.txt | 5 +++++ src/mainboard/google/cyan/board_info.txt | 6 ++++++ src/mainboard/google/foster/board_info.txt | 6 ++++++ src/mainboard/google/glados/board_info.txt | 6 ++++++ src/mainboard/google/jecht/board_info.txt | 6 ++++++ src/mainboard/google/lars/board_info.txt | 6 ++++++ src/mainboard/google/nyan_blaze/board_info.txt | 6 ++++++ src/mainboard/google/oak/board_info.txt | 6 ++++++ src/mainboard/google/purin/board_info.txt | 6 ++++++ src/mainboard/google/rush/board_info.txt | 5 +++++ src/mainboard/google/rush_ryu/board_info.txt | 5 +++++ src/mainboard/google/smaug/board_info.txt | 5 +++++ src/mainboard/google/storm/board_info.txt | 5 +++++ src/mainboard/google/urara/board_info.txt | 5 +++++ src/mainboard/google/veyron/board_info.txt | 5 +++++ src/mainboard/google/veyron_brain/board_info.txt | 5 +++++ src/mainboard/google/veyron_danger/board_info.txt | 5 +++++ src/mainboard/google/veyron_emile/board_info.txt | 5 +++++ src/mainboard/google/veyron_mickey/board_info.txt | 5 +++++ src/mainboard/google/veyron_rialto/board_info.txt | 5 +++++ src/mainboard/google/veyron_romy/board_info.txt | 5 +++++ src/mainboard/intel/apollolake_rvp/board_info.txt | 6 ++++++ src/mainboard/intel/kunimitsu/board_info.txt | 6 ++++++ src/mainboard/intel/strago/board_info.txt | 6 ++++++ 26 files changed, 143 insertions(+) diff --git a/src/mainboard/google/auron_paine/board_info.txt b/src/mainboard/google/auron_paine/board_info.txt new file mode 100644 index 0000000..2c6971b --- /dev/null +++ b/src/mainboard/google/auron_paine/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Auron Paine Broadwell chromebook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/chell/board_info.txt b/src/mainboard/google/chell/board_info.txt new file mode 100644 index 0000000..be33f44 --- /dev/null +++ b/src/mainboard/google/chell/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Chell Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cosmos/board_info.txt b/src/mainboard/google/cosmos/board_info.txt new file mode 100644 index 0000000..15e52fd --- /dev/null +++ b/src/mainboard/google/cosmos/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Cosmos Marvell BG4CD reference board +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/cyan/board_info.txt b/src/mainboard/google/cyan/board_info.txt new file mode 100644 index 0000000..8815b36 --- /dev/null +++ b/src/mainboard/google/cyan/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Cyan Braswell reference board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/foster/board_info.txt b/src/mainboard/google/foster/board_info.txt new file mode 100644 index 0000000..1a4f42d --- /dev/null +++ b/src/mainboard/google/foster/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Foster Nvidia Tegra210 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/glados/board_info.txt b/src/mainboard/google/glados/board_info.txt new file mode 100644 index 0000000..958df10 --- /dev/null +++ b/src/mainboard/google/glados/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Glados Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/jecht/board_info.txt b/src/mainboard/google/jecht/board_info.txt new file mode 100644 index 0000000..67697e0 --- /dev/null +++ b/src/mainboard/google/jecht/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Jecht Broadwell Chromebox +Category: settop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/lars/board_info.txt b/src/mainboard/google/lars/board_info.txt new file mode 100644 index 0000000..8547dda --- /dev/null +++ b/src/mainboard/google/lars/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Lars Skylake chromebook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/nyan_blaze/board_info.txt b/src/mainboard/google/nyan_blaze/board_info.txt new file mode 100644 index 0000000..79a250a --- /dev/null +++ b/src/mainboard/google/nyan_blaze/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Nyan Blaze Nvidia Tegra T124 Chromebook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/oak/board_info.txt b/src/mainboard/google/oak/board_info.txt new file mode 100644 index 0000000..ddd05bc --- /dev/null +++ b/src/mainboard/google/oak/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Oak MediaTek MT8173 reference board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/purin/board_info.txt b/src/mainboard/google/purin/board_info.txt new file mode 100644 index 0000000..878db18 --- /dev/null +++ b/src/mainboard/google/purin/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Purin Broadcom Cygnus reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/rush/board_info.txt b/src/mainboard/google/rush/board_info.txt new file mode 100644 index 0000000..4f45e43 --- /dev/null +++ b/src/mainboard/google/rush/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Rush Nvidia Tegra132 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/rush_ryu/board_info.txt b/src/mainboard/google/rush_ryu/board_info.txt new file mode 100644 index 0000000..8317850 --- /dev/null +++ b/src/mainboard/google/rush_ryu/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Rush Ryu Nvidia Tegra132 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/smaug/board_info.txt b/src/mainboard/google/smaug/board_info.txt new file mode 100644 index 0000000..996dae9 --- /dev/null +++ b/src/mainboard/google/smaug/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Smaug Nvidia Tegra210 tablet +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/storm/board_info.txt b/src/mainboard/google/storm/board_info.txt new file mode 100644 index 0000000..98e4126 --- /dev/null +++ b/src/mainboard/google/storm/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Storm Qualcomm IPQ806X board +Category: settop +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/urara/board_info.txt b/src/mainboard/google/urara/board_info.txt new file mode 100644 index 0000000..0458abd --- /dev/null +++ b/src/mainboard/google/urara/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Urara Imgtec Pistachio reference board +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron/board_info.txt b/src/mainboard/google/veyron/board_info.txt new file mode 100644 index 0000000..a6f725f --- /dev/null +++ b/src/mainboard/google/veyron/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Rockchip RK3288 boards +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_brain/board_info.txt b/src/mainboard/google/veyron_brain/board_info.txt new file mode 100644 index 0000000..b67d96c --- /dev/null +++ b/src/mainboard/google/veyron_brain/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Brain Rockchip RK3288 chromebox +Category: settop +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_danger/board_info.txt b/src/mainboard/google/veyron_danger/board_info.txt new file mode 100644 index 0000000..4cb29be --- /dev/null +++ b/src/mainboard/google/veyron_danger/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Danger Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_emile/board_info.txt b/src/mainboard/google/veyron_emile/board_info.txt new file mode 100644 index 0000000..d4c19be --- /dev/null +++ b/src/mainboard/google/veyron_emile/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Emile Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_mickey/board_info.txt b/src/mainboard/google/veyron_mickey/board_info.txt new file mode 100644 index 0000000..b92b74d --- /dev/null +++ b/src/mainboard/google/veyron_mickey/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Mickey Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_rialto/board_info.txt b/src/mainboard/google/veyron_rialto/board_info.txt new file mode 100644 index 0000000..6a53ca4 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Rialto Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_romy/board_info.txt b/src/mainboard/google/veyron_romy/board_info.txt new file mode 100644 index 0000000..658e2fe --- /dev/null +++ b/src/mainboard/google/veyron_romy/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Romy Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/intel/apollolake_rvp/board_info.txt b/src/mainboard/intel/apollolake_rvp/board_info.txt new file mode 100644 index 0000000..eb95944 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Apollolake RVP Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/kunimitsu/board_info.txt b/src/mainboard/intel/kunimitsu/board_info.txt new file mode 100644 index 0000000..acf033c --- /dev/null +++ b/src/mainboard/intel/kunimitsu/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Kunimitsu Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/strago/board_info.txt b/src/mainboard/intel/strago/board_info.txt new file mode 100644 index 0000000..3da4aa9 --- /dev/null +++ b/src/mainboard/intel/strago/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Strago Braswell Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y

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New patch to review for coreboot: lint: Update board status script to look at the whole tree
by Martin Roth 17 Mar '16

17 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14118 -gerrit commit 993075db6b0ecaf4b9278a9fbc2694139adcc860 Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 15:58:23 2016 -0600 lint: Update board status script to look at the whole tree The board status script wasn't checking the entire tree to make sure that all boards had board_info.txt files. Also it would only print out the first issue that was found. Change-Id: I5f2fa9e564c805c6dbee7a35cab80c1c342567a5 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-stable-005-board-status | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/util/lint/lint-stable-005-board-status b/util/lint/lint-stable-005-board-status index 61813ea..952a9b5 100755 --- a/util/lint/lint-stable-005-board-status +++ b/util/lint/lint-stable-005-board-status @@ -16,11 +16,11 @@ # DESCR: Check that every board has a meaningful board_info.txt LC_ALL=C export LC_ALL -for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do +for mobodir in $(git ls-files src/mainboard | sed -n 's,^$src/mainboard/[^/]*/[^/]*$/.*$,\1,p'|sort|uniq); do board_info="$mobodir/board_info.txt" if ! [ -f "$board_info" ]; then echo "No $board_info found" - exit 1 + continue fi category="$(sed -n 's#^Category: $.*$$#\1#p' < "$board_info")" case "$category" in @@ -28,11 +28,11 @@ for mobodir in $(git diff --diff-filter ACMR --name-only src/mainboard | sed -n ;; "") echo "$board_info doesn't contain 'Category' tag" - exit 1 + continue ;; *) echo "$board_info specifies unknown category '$category'" - exit 1 + continue ;; esac done

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New patch to review for coreboot: google/intel mainboards: Add missing board_info.txt files
by Martin Roth 17 Mar '16

17 Mar '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14117 -gerrit commit c71d7b57f9ff17b36045955ec23ece60caaa901a Author: Martin Roth <martinroth(a)google.com> Date: Wed Mar 16 18:36:35 2016 -0600 google/intel mainboards: Add missing board_info.txt files The lint script didn't catch that these mainboard directories didn't have board_info files. Add all missing board_info.txt files Change-Id: Ib1d61a3c04e91b22480527885faf60c22093d98a Signed-off-by: Martin Roth <martinroth(a)google.com> --- src/mainboard/google/auron_paine/board_info.txt | 6 ++++++ src/mainboard/google/chell/board_info.txt | 6 ++++++ src/mainboard/google/cosmos/board_info.txt | 5 +++++ src/mainboard/google/cyan/board_info.txt | 6 ++++++ src/mainboard/google/foster/board_info.txt | 6 ++++++ src/mainboard/google/glados/board_info.txt | 6 ++++++ src/mainboard/google/jecht/board_info.txt | 6 ++++++ src/mainboard/google/lars/board_info.txt | 6 ++++++ src/mainboard/google/nyan_blaze/board_info.txt | 6 ++++++ src/mainboard/google/oak/board_info.txt | 6 ++++++ src/mainboard/google/purin/board_info.txt | 6 ++++++ src/mainboard/google/rush/board_info.txt | 5 +++++ src/mainboard/google/rush_ryu/board_info.txt | 5 +++++ src/mainboard/google/smaug/board_info.txt | 5 +++++ src/mainboard/google/storm/board_info.txt | 5 +++++ src/mainboard/google/urara/board_info.txt | 5 +++++ src/mainboard/google/veyron/board_info.txt | 5 +++++ src/mainboard/google/veyron_brain/board_info.txt | 5 +++++ src/mainboard/google/veyron_danger/board_info.txt | 5 +++++ src/mainboard/google/veyron_emile/board_info.txt | 5 +++++ src/mainboard/google/veyron_mickey/board_info.txt | 5 +++++ src/mainboard/google/veyron_rialto/board_info.txt | 5 +++++ src/mainboard/google/veyron_romy/board_info.txt | 5 +++++ src/mainboard/intel/apollolake_rvp/board_info.txt | 6 ++++++ src/mainboard/intel/kunimitsu/board_info.txt | 6 ++++++ src/mainboard/intel/strago/board_info.txt | 6 ++++++ 26 files changed, 143 insertions(+) diff --git a/src/mainboard/google/auron_paine/board_info.txt b/src/mainboard/google/auron_paine/board_info.txt new file mode 100644 index 0000000..2c6971b --- /dev/null +++ b/src/mainboard/google/auron_paine/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Auron Paine Broadwell chromebook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/chell/board_info.txt b/src/mainboard/google/chell/board_info.txt new file mode 100644 index 0000000..be33f44 --- /dev/null +++ b/src/mainboard/google/chell/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Chell Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cosmos/board_info.txt b/src/mainboard/google/cosmos/board_info.txt new file mode 100644 index 0000000..15e52fd --- /dev/null +++ b/src/mainboard/google/cosmos/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Cosmos Marvell BG4CD reference board +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/cyan/board_info.txt b/src/mainboard/google/cyan/board_info.txt new file mode 100644 index 0000000..8815b36 --- /dev/null +++ b/src/mainboard/google/cyan/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Cyan Braswell reference board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/foster/board_info.txt b/src/mainboard/google/foster/board_info.txt new file mode 100644 index 0000000..1a4f42d --- /dev/null +++ b/src/mainboard/google/foster/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Foster Nvidia Tegra210 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/glados/board_info.txt b/src/mainboard/google/glados/board_info.txt new file mode 100644 index 0000000..958df10 --- /dev/null +++ b/src/mainboard/google/glados/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Glados Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/jecht/board_info.txt b/src/mainboard/google/jecht/board_info.txt new file mode 100644 index 0000000..67697e0 --- /dev/null +++ b/src/mainboard/google/jecht/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Jecht Broadwell Chromebox +Category: settop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/lars/board_info.txt b/src/mainboard/google/lars/board_info.txt new file mode 100644 index 0000000..8547dda --- /dev/null +++ b/src/mainboard/google/lars/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Lars Skylake chromebook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/nyan_blaze/board_info.txt b/src/mainboard/google/nyan_blaze/board_info.txt new file mode 100644 index 0000000..79a250a --- /dev/null +++ b/src/mainboard/google/nyan_blaze/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Nyan Blaze Nvidia Tegra T124 Chromebook +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/oak/board_info.txt b/src/mainboard/google/oak/board_info.txt new file mode 100644 index 0000000..ddd05bc --- /dev/null +++ b/src/mainboard/google/oak/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Oak MediaTek MT8173 reference board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/purin/board_info.txt b/src/mainboard/google/purin/board_info.txt new file mode 100644 index 0000000..d01ecb8 --- /dev/null +++ b/src/mainboard/google/purin/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Purin Broadcom Cygnus reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/rush/board_info.txt b/src/mainboard/google/rush/board_info.txt new file mode 100644 index 0000000..4f45e43 --- /dev/null +++ b/src/mainboard/google/rush/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Rush Nvidia Tegra132 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/rush_ryu/board_info.txt b/src/mainboard/google/rush_ryu/board_info.txt new file mode 100644 index 0000000..8317850 --- /dev/null +++ b/src/mainboard/google/rush_ryu/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Rush Ryu Nvidia Tegra132 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/smaug/board_info.txt b/src/mainboard/google/smaug/board_info.txt new file mode 100644 index 0000000..996dae9 --- /dev/null +++ b/src/mainboard/google/smaug/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Smaug Nvidia Tegra210 tablet +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/storm/board_info.txt b/src/mainboard/google/storm/board_info.txt new file mode 100644 index 0000000..98e4126 --- /dev/null +++ b/src/mainboard/google/storm/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Storm Qualcomm IPQ806X board +Category: settop +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/urara/board_info.txt b/src/mainboard/google/urara/board_info.txt new file mode 100644 index 0000000..0458abd --- /dev/null +++ b/src/mainboard/google/urara/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Urara Imgtec Pistachio reference board +Category: eval +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron/board_info.txt b/src/mainboard/google/veyron/board_info.txt new file mode 100644 index 0000000..a6f725f --- /dev/null +++ b/src/mainboard/google/veyron/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Rockchip RK3288 boards +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_brain/board_info.txt b/src/mainboard/google/veyron_brain/board_info.txt new file mode 100644 index 0000000..b67d96c --- /dev/null +++ b/src/mainboard/google/veyron_brain/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Brain Rockchip RK3288 chromebox +Category: settop +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_danger/board_info.txt b/src/mainboard/google/veyron_danger/board_info.txt new file mode 100644 index 0000000..4cb29be --- /dev/null +++ b/src/mainboard/google/veyron_danger/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Danger Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_emile/board_info.txt b/src/mainboard/google/veyron_emile/board_info.txt new file mode 100644 index 0000000..d4c19be --- /dev/null +++ b/src/mainboard/google/veyron_emile/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Emile Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_mickey/board_info.txt b/src/mainboard/google/veyron_mickey/board_info.txt new file mode 100644 index 0000000..b92b74d --- /dev/null +++ b/src/mainboard/google/veyron_mickey/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Mickey Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_rialto/board_info.txt b/src/mainboard/google/veyron_rialto/board_info.txt new file mode 100644 index 0000000..6a53ca4 --- /dev/null +++ b/src/mainboard/google/veyron_rialto/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Rialto Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/google/veyron_romy/board_info.txt b/src/mainboard/google/veyron_romy/board_info.txt new file mode 100644 index 0000000..658e2fe --- /dev/null +++ b/src/mainboard/google/veyron_romy/board_info.txt @@ -0,0 +1,5 @@ +Vendor name: Google +Board name: Veyron Romy Rockchip RK3288 board +Category: misc +ROM protocol: SPI +ROM socketed: n diff --git a/src/mainboard/intel/apollolake_rvp/board_info.txt b/src/mainboard/intel/apollolake_rvp/board_info.txt new file mode 100644 index 0000000..eb95944 --- /dev/null +++ b/src/mainboard/intel/apollolake_rvp/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Apollolake RVP Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/kunimitsu/board_info.txt b/src/mainboard/intel/kunimitsu/board_info.txt new file mode 100644 index 0000000..acf033c --- /dev/null +++ b/src/mainboard/intel/kunimitsu/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Kunimitsu Skylake Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/strago/board_info.txt b/src/mainboard/intel/strago/board_info.txt new file mode 100644 index 0000000..3da4aa9 --- /dev/null +++ b/src/mainboard/intel/strago/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Strago Braswell Reference Board +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y

1 0

New patch to review for coreboot: gpio: Add support for binary_first base3 number system
by Julius Werner 17 Mar '16

17 Mar '16

Julius Werner (jwerner(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14116 -gerrit commit 76fc774f902b268a71df30c881c9210fa9cca155 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Mar 16 17:11:55 2016 -0700 gpio: Add support for binary_first base3 number system This patch adds support for an alternative ternary number system which a group of GPIOs can be interpreted in. In this system, the digit combinations that would form a binary number (i.e. that contain no 'Z' state) come first in their normal binary order, and all the combinations that do contain a 'Z' come afterwards. We can use this for boards that originally get strapped with binary board IDs but eventually require more revisions than that representation allows. We can switch their code to binary_first base3 and all old revisions with already produced boards will still get read as the correct numbers. Credit for the algorithm idea goes to Haran Talmon. BRANCH=None BUG=None TEST=Stubbed out the actual GPIO reading and simulated all combinations of 4 ternary digits for both number systems. Change-Id: Ib5127656455f97f890ce2999ba5ac5f58a20cf93 Signed-off-by: Julius Werner <jwerner(a)chromium.org> --- src/include/gpio.h | 35 ++++++++++++++++++++++++++++++++++- src/lib/gpio.c | 49 +++++++++++++++++++++++++++++++++++++++++++++---- 2 files changed, 79 insertions(+), 5 deletions(-) diff --git a/src/include/gpio.h b/src/include/gpio.h index ea03a23..443a580 100644 --- a/src/include/gpio.h +++ b/src/include/gpio.h @@ -29,6 +29,7 @@ void gpio_input_pulldown(gpio_t gpio); void gpio_input_pullup(gpio_t gpio); void gpio_input(gpio_t gpio); void gpio_output(gpio_t gpio, int value); +int _gpio_base3_value(gpio_t gpio[], int num_gpio, int binary_first); /* * Read the value presented by the set of GPIOs, when each pin is interpreted @@ -48,6 +49,38 @@ int gpio_base2_value(gpio_t gpio[], int num_gpio); * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. * num_gpio: number of pins to read. */ -int gpio_base3_value(gpio_t gpio[], int num_gpio); +static inline int gpio_base3_value(gpio_t gpio[], int num_gpio) +{ + return _gpio_base3_value(gpio, num_gpio, 0); +} + +/* + * Read the value presented by the set of GPIOs, when each pin is interpreted + * as a base-3 digit (LOW = 0, HIGH = 1, Z/floating = 2) in a non-standard + * ternary number system where the first 2^n natural numbers are represented + * as they would be in a binary system (without any Z digits), and the following + * 3^n-2^n use the remaining ternary representations in their normal order. + * This is useful for boards which initially used a binary board ID and later + * decided to switch to tri-state after some revisions have already been built. + * Example: For num_gpio = 2 we get the following representation: + * + * Number X1 X0 + * 0 0 0 + * 1 0 1 + * 2 1 0 + * 3 1 1 + * 4 0 2 // Skipping 00 and 01 which are already used up + * 5 1 2 // Skipping 10 and 11 which are already used up + * 6 2 0 + * 7 2 1 + * 8 2 2 + * + * gpio[]: pin positions to read. gpio[0] is less significant than gpio[1]. + * num_gpio: number of pins to read. + */ +static inline int gpio_binary_first_base3_value(gpio_t gpio[], int num_gpio) +{ + return _gpio_base3_value(gpio, num_gpio, 1); +} #endif /* __SRC_INCLUDE_GPIO_H__ */ diff --git a/src/lib/gpio.c b/src/lib/gpio.c index 5147cfe..97733b8 100644 --- a/src/lib/gpio.c +++ b/src/lib/gpio.c @@ -35,7 +35,7 @@ int gpio_base2_value(gpio_t gpio[], int num_gpio) return result; } -int gpio_base3_value(gpio_t gpio[], int num_gpio) +int _gpio_base3_value(gpio_t gpio[], int num_gpio, int binary_first) { /* * GPIOs which are tied to stronger external pull up or pull down @@ -49,7 +49,11 @@ int gpio_base3_value(gpio_t gpio[], int num_gpio) static const char tristate_char[] = {[0] = '0', [1] = '1', [Z] = 'Z'}; int temp; int index; - int result = 0; + int result; + int ternary = 0; + int binary = 0; + int has_z = 0; + int binary_below = 0; char value[32]; assert(num_gpio <= 32); @@ -84,9 +88,46 @@ int gpio_base3_value(gpio_t gpio[], int num_gpio) temp = gpio_get(gpio[index]); temp |= ((value[index] ^ temp) << 1); printk(BIOS_DEBUG, "%c ", tristate_char[temp]); - result = (result * 3) + temp; + ternary = (ternary * 3) + temp; + + /* + * For binary_first we keep track of both the binary and the + * normal ternary result, and whether we found any pin that was + * a Z. We also determine the amount of numbers that can be + * represented with only binary digits (no Z) that come below + * the current value in normal ternary representation. Counting + * from the left, we add 2^i for any '1' digit to account for + * the binary numbers that would come below it if all following + * digits were '0'. As soon as we find a '2' digit we can total + * the remaining binary numbers below as 2^(i+1). + * + * Example: 1 0 2 1 (counting from the left / most significant) + * '1' at 3: Add 2^3 = 8 to account for binaries 0000-0111 + * '0' at 2: Ignore (not all binaries 1000-1100 are below us) + * '2' at 1: Add 2^(1+1) = 4 to account for binaries 1000-1011 + * Stop adding for lower digits, all already accounted now. We + * know that there can be no binary numbers in 1020-102X. + */ + if (binary_first) { + binary = (binary * 2) + temp; + if (!has_z && temp == 1) + binary_below += 1 << index; + if (!has_z && temp == 2) { + binary_below += 1 << (index + 1); + has_z = 1; + } + } } - printk(BIOS_DEBUG, "= %d\n", result); + + if (!binary_first) + result = ternary; + else if (has_z) + result = ternary + (1 << num_gpio) - binary_below; + else + result = binary; + + printk(BIOS_DEBUG, "= %d (%s base3 number system)\n", result, + binary_first ? "binary_first" : "standard"); /* Disable pull up / pull down to conserve power */ for (index = 0; index < num_gpio; ++index)

1 0

Patch set updated for coreboot: mtrr: Define a function for obtaining free var mtrr
by Furquan Shaikh 17 Mar '16

17 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14115 -gerrit commit c2726de58dc27ce7d0c0cb9ff0895a5b293bd2d4 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Mar 16 16:12:06 2016 -0700 mtrr: Define a function for obtaining free var mtrr Instead of hard-coding var mtrr numbers in code, use this function to identify the first available variable mtrr. If no such mtrr is available, the function will return -1. Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/cpu/x86/mtrr/earlymtrr.c | 24 ++++++++++++++++++++++++ src/include/cpu/x86/mtrr.h | 1 + 2 files changed, 25 insertions(+) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index a84ecf8..eae6ba6 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -2,6 +2,30 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +/* Get first available variable MTRR. + * Returns var# if available, else returns -1. + */ +int get_free_var_mtrr(void) +{ + msr_t msr, maskm; + int vcnt; + int i; + + /* Read MTRRCap and get vcnt - variable memory type ranges. */ + msr = rdmsr(MTRR_CAP_MSR); + vcnt = msr.lo & 0xff; + + /* Identify the first var mtrr which is not valid. */ + for (i = 0; i < vcnt; i++) { + maskm = rdmsr(MTRR_PHYS_MASK(i)); + if ((maskm.lo & MTRR_PHYS_MASK_VALID) == 0) + return i; + } + + /* No free var mtrr. */ + return -1; +} + #ifdef __ROMCC__ static #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index d158735..4eb4f13 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -81,6 +81,7 @@ void x86_mtrr_check(void); #if !defined(__ASSEMBLER__) && defined(__PRE_RAM__) && !defined(__ROMCC__) void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type); +int get_free_var_mtrr(void); #endif /* Align up to next power of 2, suitable for ROMCC and assembler too.

1 0

Patch set updated for coreboot: mtrr: Define a function for obtaining free var mtrr
by Furquan Shaikh 17 Mar '16

17 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14115 -gerrit commit 7d5754b2f646e8dbc304e26bd344f2fd499a063e Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Mar 16 16:12:06 2016 -0700 mtrr: Define a function for obtaining free var mtrr Instead of hard-coding var mtrr numbers in code, use this function to identify the first available variable mtrr. If no such mtrr is available, the function will return -1. Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/cpu/x86/mtrr/earlymtrr.c | 24 ++++++++++++++++++++++++ src/include/cpu/x86/mtrr.h | 1 + 2 files changed, 25 insertions(+) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index a84ecf8..bc16a29 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -2,6 +2,30 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +/* Get first available variable MTRR. + * Returns var# if available, else returns -1. + */ +int get_free_var_mtrr(void) +{ + msr_t msr, maskm; + int vcnt; + int i; + + /* Read MTRRCap and get vcnt - variable memory type ranges. */ + msr = rdmsr(MTRR_CAP_MSR); + vcnt = msr.lo & 0xff; + + /* Identify the first var mtrr which is not valid. */ + for (i = 0; i < vcnt; i++) { + maskm = rdmsr(MTRR_PHYS_MASK(i)); + if (maskm.lo & MTRR_PHYS_MASK_VALID) + return i; + } + + /* No free var mtrr. */ + return -1; +} + #ifdef __ROMCC__ static #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index d158735..4eb4f13 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -81,6 +81,7 @@ void x86_mtrr_check(void); #if !defined(__ASSEMBLER__) && defined(__PRE_RAM__) && !defined(__ROMCC__) void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type); +int get_free_var_mtrr(void); #endif /* Align up to next power of 2, suitable for ROMCC and assembler too.

1 0

New patch to review for coreboot: mtrr: Define a function for obtaining free var mtrr
by Furquan Shaikh 17 Mar '16

17 Mar '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14115 -gerrit commit 6557c4b6ef689a441df5fad0d25a1190a3322a47 Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Mar 16 16:12:06 2016 -0700 mtrr: Define a function for obtaining free var mtrr Instead of hard-coding var mtrr numbers in code, use this function to identify the first available variable mtrr. If no such mtrr is available, the function will return -1. Change-Id: I2a1e02cdb45c0ab7e30609641977471eaa2431fd Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- src/cpu/x86/mtrr/earlymtrr.c | 24 ++++++++++++++++++++++++ src/include/cpu/x86/mtrr.h | 1 + 2 files changed, 25 insertions(+) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index a84ecf8..54c09c0 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -2,6 +2,30 @@ #include <cpu/x86/mtrr.h> #include <cpu/x86/msr.h> +/* Get first available variable MTRR. + * Returns var# if available, else returns -1. + */ +int get_free_var_mtrr(void) +{ + msr_t msr, maskm; + int vcnt; + int i; + + /* Read MTRRCap and get vcnt - variable memory type ranges. */ + msr = rdmsr(MTRR_CAP_MSR); + vcnt = msr.lo & 0xff; + + /* Identify the first var mtrr which is not valid. */ + for (i = 0; i < vcn5Bt; i++) { + maskm = rdmsr(MTRR_PHYS_MASK(i)); + if (maskm.lo & MTRR_PHYS_MASK_VALID) + return i; + } + + /* No free var mtrr. */ + return -1; +} + #ifdef __ROMCC__ static #endif diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index d158735..4eb4f13 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -81,6 +81,7 @@ void x86_mtrr_check(void); #if !defined(__ASSEMBLER__) && defined(__PRE_RAM__) && !defined(__ROMCC__) void set_var_mtrr(unsigned reg, unsigned base, unsigned size, unsigned type); +int get_free_var_mtrr(void); #endif /* Align up to next power of 2, suitable for ROMCC and assembler too.

1 0

New patch to review for coreboot: Documentation/Intel: Add more Galileo Gen2 links
by Leroy P Leahy 16 Mar '16

16 Mar '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/14114 -gerrit commit 9854a77ad426f107df383977ba4044741069c425 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Wed Mar 16 08:58:01 2016 -0700 Documentation/Intel: Add more Galileo Gen2 links Add datasheet links for the components supporting GPIO. This includes I2C I/O ports, I2C PWMs, bus buffers and multiplexers. TEST=None Change-Id: I0a1d222d6f9bdbd824b78edf2338cd797e83ebba Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/Board/galileo.html | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/Intel/Board/galileo.html b/Documentation/Intel/Board/galileo.html index 1cc77dc..3ed6672 100644 --- a/Documentation/Intel/Board/galileo.html +++ b/Documentation/Intel/Board/galileo.html @@ -57,7 +57,13 @@ <li>Components <ul> <li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li> + <li>I2C 16-channel, 12-bit PWM: NXP Semiconductors <a target="_blank" href="http://cache.nxp.com/documents/data_sheet/PCA9685.pdf">PCA9685</a></li> + <li>I2C I/O Ports: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/PCAL9535A.pdf">PCAL9535A</a></li> + <li>Octal Buffer/Driver: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv541at.pdf">SN74LV541AT</a></li> + <li>Quadruple Bus Buffer: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lv125a.pdf">SN74LV125A</a></li> + <li>Quadruple Bus Buffer with 3-State Outputs: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/sn74lvc126a.pdf">SN74LVC126A</a></li> <li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li> + <li>Single 2-input multiplexer: NXP Semiconductors <a target="_blank" href="http://www.nxp.com/documents/data_sheet/74LVC1G157.pdf">74LVC1G157</a></li> <li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li> </ul> </li>

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coreboot-gerrit March 2016