coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: vboot: Update to current master to support S3 resume signalling
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13844 -gerrit commit d6491855ce27b5d52019b7391bd20541b1b56afb Author: Patrick Georgi <pgeorgi(a)google.com> Date: Fri Feb 26 15:27:20 2016 -0800 vboot: Update to current master to support S3 resume signalling This is used in coreboot-side vboot code now, to keep booting from the same RW section after wakeup - necessary when romstage is in RW and its use of the RAM init configuration cache may differ between versions. Change-Id: Ie531cf3ddc980154f48772b3ff87e23473010721 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 933c4e7..d187cd3 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 933c4e7aa4b873f0ad9cd4c348a1ea4f37f66aa7 +Subproject commit d187cd3fc792f8bcefbee4587c83eafbd08441fc

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Patch set updated for coreboot: google/chell: Update GPIOs for DVT2
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13841 -gerrit commit 7a3b9ad87f36d4e1893f58c6984d817525899591 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 08:53:40 2016 -0800 google/chell: Update GPIOs for DVT2 Add new GPIOs for touchscreen enable and reset pins and define the one missing unconnected pin for GPP_E10. BUG=chrome-os-partner:50518 BRANCH=glados TEST=build and boot on chell DVT1 Change-Id: I565a742ff266ee65a5d33f052606fe77c24b6ac8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 32a890af8c32aa30adac256d2c4ceaeefa30bd0d Original-Change-Id: I16546d38cc4e926e169f61ae1843106d1e14936b Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329297 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/gpio.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 01b4e31..0503e3e 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -87,7 +87,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), /* VRALERT# */ PAD_CFG_NC(GPP_B2), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ @@ -158,14 +158,14 @@ static const struct pad_config gpio_table[] = { /* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ -/* USB2_OC1# */ /* GPP_E10 */ +/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */

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Patch set updated for coreboot: Skylake boards: Enabling HWP
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13843 -gerrit commit 7b331bb90396de80eb56476b658626e8c37d900a Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 8 17:19:10 2016 +0530 Skylake boards: Enabling HWP This patch provides config options to enable/disable Intel SST. BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 3 +++ src/mainboard/google/glados/devicetree.cb | 3 +++ src/mainboard/google/lars/devicetree.cb | 3 +++ src/mainboard/intel/kunimitsu/devicetree.cb | 3 +++ 4 files changed, 12 insertions(+) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index ac3a5c1..bb925ce 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 894f0e1..89fcff8 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index cf3649a..50b3e1e 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index d2a70c8..62a0c26 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1"

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Patch set updated for coreboot: google/chell: Update DPTF configuration
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13842 -gerrit commit b705d698c9d3aacb339fe5eb5eece35c56625c31 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 10:07:10 2016 -0800 google/chell: Update DPTF configuration Update the DPTF configuration for the chell mainboard: 1) Enable DPTF charger control, set max current to 1975mA according to the battery specification. 2) Enable charger effect on charger temp sensor in TRT 3) Set PL2 to 15W which is the same value configured in the CPU. BUG=chrome-os-partner:49859,chrome-os-partner:50306 BRANCH=glados TEST=build and boot on chell Change-Id: I644256b9596cc5295513c48f5e3a18e6ce8b0a6b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: c19740a227f932bf80e9243341ec81763779719c Original-Change-Id: Icff5edc9d659bea6370ff8de1334ebf0983340da Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329187 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/acpi/dptf.asl | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/chell/acpi/dptf.asl b/src/mainboard/google/chell/acpi/dptf.asl index c8362b7..d3549a7 100644 --- a/src/mainboard/google/chell/acpi/dptf.asl +++ b/src/mainboard/google/chell/acpi/dptf.asl @@ -37,12 +37,21 @@ #define DPTF_TSR3_PASSIVE 55 #define DPTF_TSR3_CRITICAL 70 -/* SKL-Y EC already has a custom charge profile based on temperature. */ -#undef DPTF_ENABLE_CHARGER - /* SKL-Y is Fanless design. */ #undef DPTF_ENABLE_FAN_CONTROL +/* Enable DPTF charger control */ +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x7b7, "mA", 0 }, /* 1975mA (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1500mA */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0mA */ +}) + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, @@ -56,6 +65,9 @@ Name (DTRT, Package () { /* CPU Effect on Temp Sensor 2 */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 }, + /* CPU Effect on Temp Sensor 3 */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, }) @@ -73,8 +85,8 @@ Name (MPPC, Package () }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */

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Patch set updated for coreboot: nyan: Fix timestamps and CBFS SPI integration
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13832 -gerrit commit e276f102427dda298d7a9142ec8db6ac8152efc1 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Feb 17 16:12:46 2016 -0800 nyan: Fix timestamps and CBFS SPI integration Nyan is an old board that was committed before several core code modernizations to timestamp and CBFS code. Not all of those later patches were correctly integrated with old boards like this, and the core code has evolved to a point where it doesn't actually boot anymore. This patch fixes that issue and brings the Nyan boards more in line with how later ARM platforms look. BRANCH=None BUG=None TEST=My Blaze boots again. Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717 Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328543 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/nyan/Kconfig | 3 + src/mainboard/google/nyan_big/Kconfig | 3 + src/mainboard/google/nyan_blaze/Kconfig | 3 + src/soc/nvidia/tegra124/bootblock.c | 3 + src/soc/nvidia/tegra124/include/soc/memlayout.ld | 3 +- src/soc/nvidia/tegra124/spi.c | 92 ------------------------ 6 files changed, 14 insertions(+), 93 deletions(-) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 8f0c9de..d03f4d7 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -26,12 +26,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config CHROMEOS select CHROMEOS_VBNV_EC select EC_SOFTWARE_SYNC select VIRTUAL_DEV_SWITCH + select COMMON_CBFS_SPI_WRAPPER config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index b6f84f6..3ba61d5 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -27,12 +27,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config CHROMEOS select EC_SOFTWARE_SYNC select CHROMEOS_VBNV_EC select VIRTUAL_DEV_SWITCH + select COMMON_CBFS_SPI_WRAPPER config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 0fd763d..07d3374 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -28,12 +28,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config CHROMEOS select EC_SOFTWARE_SYNC select CHROMEOS_VBNV_EC select VIRTUAL_DEV_SWITCH + select COMMON_CBFS_SPI_WRAPPER config MAINBOARD_DIR string diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index cebe405..2a526a7 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -24,6 +24,7 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <soc/pinmux.h> #include <soc/power.h> +#include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> static void run_next_stage(void *entry) @@ -81,6 +82,8 @@ void main(void) PINMUX_PWR_INT_N_FUNC_PMICINTR | PINMUX_INPUT_ENABLE); + timestamp_init(0); + run_romstage(); } diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index c3f5f4e..5bab362 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -33,7 +33,8 @@ SECTIONS STACK(0x4000E000, 8K) BOOTBLOCK(0x40010000, 24K) VERSTAGE(0x40016000, 72K) - ROMSTAGE(0x40028000, 96K) + ROMSTAGE(0x40028000, 95K) + TIMESTAMP(0x4003FC00, 1K) SRAM_END(0x40040000) DRAM_START(0x80000000) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index d5f7861..d5be4a6 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -798,69 +798,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return ret; } -#define JEDEC_READ 0x03 -#define JEDEC_READ_OUTSIZE 0x04 -#define JEDEC_FAST_READ_DUAL 0x3b -#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05 - -static struct spi_slave *boot_slave; - -static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest, - size_t offset, size_t count) -{ - u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE]; - unsigned int read_cmd_bytes; - int ret = count; - struct tegra_spi_channel *channel; - - channel = to_tegra_spi(boot_slave->bus); - - if (channel->dual_mode) { - /* - * Command 0x3b will interleave data only, command 0xbb will - * interleave the address as well. It's nice to see the address - * plainly when debugging, and we're mostly concerned with - * large transfers so the optimization of using 0xbb isn't - * really worthwhile. - */ - spi_read_cmd[0] = JEDEC_FAST_READ_DUAL; - spi_read_cmd[4] = 0x00; /* dummy byte */ - read_cmd_bytes = JEDEC_FAST_READ_DUAL_OUTSIZE; - } else { - spi_read_cmd[0] = JEDEC_READ; - read_cmd_bytes = JEDEC_READ_OUTSIZE; - } - spi_read_cmd[1] = (offset >> 16) & 0xff; - spi_read_cmd[2] = (offset >> 8) & 0xff; - spi_read_cmd[3] = offset & 0xff; - - spi_claim_bus(boot_slave); - - if (spi_xfer(boot_slave, spi_read_cmd, - read_cmd_bytes, NULL, 0) < 0) { - ret = -1; - printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", - __func__, sizeof(spi_read_cmd)); - goto tegra_spi_cbfs_read_exit; - } - - if (channel->dual_mode) { - setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); - } - if (spi_xfer(boot_slave, NULL, 0, dest, count)) { - ret = -1; - printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", - __func__, count); - } - if (channel->dual_mode) - clrbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); - -tegra_spi_cbfs_read_exit: - /* de-assert /CS */ - spi_release_bus(boot_slave); - return ret; -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { struct tegra_spi_channel *channel = to_tegra_spi(bus); @@ -869,32 +806,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) return &channel->slave; } - -static const struct region_device_ops tegra_spi_ops = { - .mmap = mmap_helper_rdev_mmap, - .munmap = mmap_helper_rdev_munmap, - .readat = tegra_spi_readat, -}; - -static struct mmap_helper_region_device mdev = - MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} - -void boot_device_init(void) -{ - struct tegra_spi_channel *boot_chan; - - boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1]; - boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT; - -#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1 - boot_chan->dual_mode = 1; -#endif - boot_slave = &boot_chan->slave; - - mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size); -}

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Patch set updated for coreboot: vboot: Set S3_RESUME flag for vboot context if necessary
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13834 -gerrit commit 32b347d053a3e5bd346b48dbf7bd70613c187acb Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Feb 19 20:26:07 2016 -0800 vboot: Set S3_RESUME flag for vboot context if necessary If a platform does verification of the memory init step, and it must resume with the same slot that it booted from then it needs to set the vboot context flag when resuming instead of booting. This will affect the slot that is selected to verify and resume from. BUG=chromium:577269 BRANCH=glados TEST=manually tested on chell: 1) ensure that booting from slot A resumes from slot A. 2) ensure that booting from slot B resumes from slot B. 3) do RW update while booted from slot A (so the flags are set to try slot B) and ensure that suspend/resume still functions properly using current slot A. 4) do RW update while booted from slot B (so the flags are set to try slot A) and ensure that suspend/resume still functions properly using current slot B. Change-Id: I77e6320e36b4d2cbc308cfb39f0d4999e3497be3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 4c84af7eae7b2a52a28cc3ef8a80649301215a68 Original-Change-Id: I395e5abaccd6f578111f242d1e85e28dced469ea Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328775 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index a4829c0..d43fb27 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -311,6 +311,15 @@ void verstage_main(void) antirollback_read_space_firmware(&ctx); timestamp_add_now(TS_END_TPMINIT); + /* Set S3 resume flag if vboot should behave differently when selecting + * which slot to boot. This is only relevant to vboot if the platform + * does verification of memory init and thus must ensure it resumes with + * the same slot that it booted from. */ + if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && + IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && + vboot_platform_is_resuming()) + ctx.flags |= VB2_CONTEXT_S3_RESUME; + if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) && get_developer_mode_switch()) ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;

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Patch set updated for coreboot: Skylake: Support Intel Speed Shift Technology based on config
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13835 -gerrit commit 0b99f1399a1ba40200e567031e53913281055a69 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 8 17:15:29 2016 +0530 Skylake: Support Intel Speed Shift Technology based on config Intel Speed Shift Technology is a new mechanism that replaces Legacy P-state. ISST allows OS hints about energy/performance preference. H/W performs the actual P-state control (autonomous) 1. Optimization frequency seclection for low residency workloads, no longer a static knee point. 2. Optimized frequency selection for best energy to performance trade offs. 3. Kick down frequency (from idle) fpr best responsiveness while taking energy consumption init account. Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes and enable HWP accordingly. BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu and verify HWP getting enabled/disabled using Intel P-state driver. Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313107 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com> --- src/soc/intel/skylake/chip.h | 2 ++ src/soc/intel/skylake/cpu.c | 29 +++++++++++++++++++++++++++++ src/soc/intel/skylake/include/soc/msr.h | 3 +++ 3 files changed, 34 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 0b87f2d..6203916 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -326,6 +326,8 @@ struct soc_intel_skylake_config { /* PL2 Override value in Watts */ u32 tdp_pl2_override; u8 PmTimerDisabled; + /* Intel Speed Shift Technology */ + u8 speed_shift_enable; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 2fa8582..327bee9 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -207,6 +207,32 @@ static void configure_thermal_target(void) } } +static void configure_isst(void) +{ + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + msr_t msr; + + if (conf->speed_shift_enable) { + /* + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + is supported or not. Coreboot needs to configure MSR 0x1AA + which is then reflected in the CPUID register. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } else { + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } +} + static void configure_misc(void) { msr_t msr; @@ -335,6 +361,9 @@ static void cpu_core_init(device_t cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); + /* Configure Intel Speed Shift */ + configure_isst(); + /* Thermal throttle activation offset */ configure_thermal_target(); diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index db154b7..4d295e1 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -36,6 +36,9 @@ #define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MISC_PWR_MGMT_ISST_EN (1 << 6) +#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) +#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_PERF_CTL 0x199

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Patch set updated for coreboot: lib: Implement framework for retrieving WiFi regulatory domain
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13836 -gerrit commit bbfd6a60729484656338f80d390ae7c294b9a210 Author: Felix Durairaj <felixx.durairaj(a)intel.com> Date: Fri Nov 20 15:51:35 2015 -0800 lib: Implement framework for retrieving WiFi regulatory domain Platforms that need to initialize WRDD package with the regulatory domain information should implement function wifi_regulatory_domain. A weak implementation is provided here. Signed-off-by: fdurairx <felixx.durairaj(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/314384 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Tested-by: Hannah Williams <hannah.williams(a)intel.com> (cherry picked from commit c25d7221679d1fab830d614eeabfa3436bce6ac1) BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: I1cbdf4e940b009c74ee8ed8f4fca85f4f5c943b2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 27bba336e620a2d3d331e350d4f46164e337fabc Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Change-Id: I84e2acd748856437b40bbf997bf23f158c711712 Original-Reviewed-on: https://chromium-review.googlesource.com/329291 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/Makefile.inc | 1 + src/lib/wrdd.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 7d1d146..646fefa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -114,6 +114,7 @@ ramstage-y += cbfs.c ramstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c +ramstage-y += wrdd.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c diff --git a/src/lib/wrdd.c b/src/lib/wrdd.c new file mode 100644 index 0000000..da082f8 --- /dev/null +++ b/src/lib/wrdd.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <wrdd.h> + +uint16_t __attribute__((weak)) wifi_regulatory_domain(void) +{ + return WRDD_DEFAULT_REGULATORY_DOMAIN; +}

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Patch set updated for coreboot: Chromeos: Modify wifi_regulatory_domain to use "region" key in VPD
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13837 -gerrit commit 585c99b30a486f5418dc1ee4335f48d0aae5fe0c Author: Huang, Huki <huki.huang(a)intel.com> Date: Thu Jan 21 10:17:06 2016 +0800 Chromeos: Modify wifi_regulatory_domain to use "region" key in VPD In ChromeOS VPD spec the right name is "region". Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/322851 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: mukesh agrawal <quiche(a)chromium.org> (cherry picked from commit 21ea0663e7f3ffe3aaea6b6ce0e1216fcd9ca23e) BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: I4ba9a9c65af3732fa263030640495ab5bea91d1f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 848f18e731eb11dd3037d12607d7364f95e64e34 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Change-Id: Ib96036f9cd76449f170af5c3dd6ef6e8e91ded94 Original-Reviewed-on: https://chromium-review.googlesource.com/329293 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/cros_vpd.h | 2 +- src/vendorcode/google/chromeos/wrdd.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h index ca9c320..96ca8af 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.h +++ b/src/vendorcode/google/chromeos/cros_vpd.h @@ -7,7 +7,7 @@ #ifndef __CROS_VPD_H__ #define __CROS_VPD_H__ -#define CROS_VPD_WIFI_DOMAINKEY "regions" +#define CROS_VPD_REGION_NAME "region" /* * Reads VPD string value by key. diff --git a/src/vendorcode/google/chromeos/wrdd.c b/src/vendorcode/google/chromeos/wrdd.c index ab27cc0..ad80992 100644 --- a/src/vendorcode/google/chromeos/wrdd.c +++ b/src/vendorcode/google/chromeos/wrdd.c @@ -26,6 +26,7 @@ * The first part is the ISO 3166-1 alpha-2 code of the country; * The second part is a string of up to three alphanumeric characters */ +#define VARIANT_SEPARATOR '.' struct wrdd_code_value_pair { const char *code; u16 value; @@ -50,21 +51,27 @@ uint16_t wifi_regulatory_domain(void) .value = WRDD_REGULATORY_DOMAIN_INDONESIA } }; - const char *wrdd_domain_key = CROS_VPD_WIFI_DOMAINKEY; + const char *wrdd_domain_key = CROS_VPD_REGION_NAME; int i; struct wrdd_code_value_pair *p; /* wrdd_domain_value is ISO 3166-2 */ char wrdd_domain_code[7]; + char *separator; /* If not found for any reason fall backto the default value */ if (!cros_vpd_gets(wrdd_domain_key, wrdd_domain_code, - sizeof(wrdd_domain_code))) { + ARRAY_SIZE(wrdd_domain_code))) { printk(BIOS_DEBUG, "Error: Could not locate '%s' in VPD\n", wrdd_domain_key); return WRDD_DEFAULT_REGULATORY_DOMAIN; } printk(BIOS_DEBUG, "Found '%s'='%s' in VPD\n", wrdd_domain_key, wrdd_domain_code); + separator = memchr(wrdd_domain_code, VARIANT_SEPARATOR, + ARRAY_SIZE(wrdd_domain_code)); + if (separator) { + *separator = '\0'; + } for (i = 0; i < ARRAY_SIZE(wrdd_table); i++) { p = &wrdd_table[i];

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Patch set updated for coreboot: intel/wifi: Add WRDD ACPI method
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13838 -gerrit commit beac442fed758b0ee8f93b9a705a5aae860339cc Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 08:44:06 2016 -0800 intel/wifi: Add WRDD ACPI method Add an ACPI file containing a generic WRDD method that is used by Intel wireless kernel drivers to determine the country code to be used for regulatory domain configuration of the wireless radios. This requires an NVS variable called 'CID1' to provide an ISO-3166-2 alpha-2 country code or it will just return 0 instead. This is implemented as a bare method because this needs to be included directly into the wifi device that is defined by the mainboard as it may have board-specific settings like _PRW that need to be provided as well. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Change-Id: I27a5e27f65d05ff62a0e79a87a32c1ef0c5d0ef3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 2da0cf76ca3cc5e3dfbc4a0859733523de780cf5 Original-Change-Id: I9d83c3938cceafc77ef8747a5c47f586ee84437e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329294 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/wifi/acpi/wrdd.asl | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/drivers/intel/wifi/acpi/wrdd.asl b/src/drivers/intel/wifi/acpi/wrdd.asl new file mode 100644 index 0000000..6f071ad --- /dev/null +++ b/src/drivers/intel/wifi/acpi/wrdd.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This method is used by the Intel wireless kernel drivers to determine + * the proper country code for regulatory domain configuration. + * + * It requires an NVS field called CID1 to be present that provides the + * ISO-3166-2 alpha-2 country code. + */ +Method (WRDD, 0, Serialized) +{ + Name (WRDX, Package () { + 0, /* Revision */ + Package () { + 0x00000007, /* Domain Type, 0x7:WiFi */ + 0x00000000, /* No Default Country Identifier */ + } + }) + + /* Replace Country Identifier with value from NVS */ + Store (\CID1, Index (DeRefOf (Index (WRDX, 1)), 1)) + Return (WRDX) +}

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coreboot-gerrit February 2016