coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: Chromeos: Modify wifi_regulatory_domain to use "region" key in VPD
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13837 -gerrit commit b0551785046f1a27272138f6a5b22308d9e57abc Author: Huang, Huki <huki.huang(a)intel.com> Date: Thu Jan 21 10:17:06 2016 +0800 Chromeos: Modify wifi_regulatory_domain to use "region" key in VPD In ChromeOS VPD spec the right name is "region". Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/322851 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: mukesh agrawal <quiche(a)chromium.org> (cherry picked from commit 21ea0663e7f3ffe3aaea6b6ce0e1216fcd9ca23e) BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: I4ba9a9c65af3732fa263030640495ab5bea91d1f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 848f18e731eb11dd3037d12607d7364f95e64e34 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Change-Id: Ib96036f9cd76449f170af5c3dd6ef6e8e91ded94 Original-Reviewed-on: https://chromium-review.googlesource.com/329293 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/cros_vpd.h | 2 +- src/vendorcode/google/chromeos/wrdd.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h index ca9c320..96ca8af 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.h +++ b/src/vendorcode/google/chromeos/cros_vpd.h @@ -7,7 +7,7 @@ #ifndef __CROS_VPD_H__ #define __CROS_VPD_H__ -#define CROS_VPD_WIFI_DOMAINKEY "regions" +#define CROS_VPD_REGION_NAME "region" /* * Reads VPD string value by key. diff --git a/src/vendorcode/google/chromeos/wrdd.c b/src/vendorcode/google/chromeos/wrdd.c index ab27cc0..ad80992 100644 --- a/src/vendorcode/google/chromeos/wrdd.c +++ b/src/vendorcode/google/chromeos/wrdd.c @@ -26,6 +26,7 @@ * The first part is the ISO 3166-1 alpha-2 code of the country; * The second part is a string of up to three alphanumeric characters */ +#define VARIANT_SEPARATOR '.' struct wrdd_code_value_pair { const char *code; u16 value; @@ -50,21 +51,27 @@ uint16_t wifi_regulatory_domain(void) .value = WRDD_REGULATORY_DOMAIN_INDONESIA } }; - const char *wrdd_domain_key = CROS_VPD_WIFI_DOMAINKEY; + const char *wrdd_domain_key = CROS_VPD_REGION_NAME; int i; struct wrdd_code_value_pair *p; /* wrdd_domain_value is ISO 3166-2 */ char wrdd_domain_code[7]; + char *separator; /* If not found for any reason fall backto the default value */ if (!cros_vpd_gets(wrdd_domain_key, wrdd_domain_code, - sizeof(wrdd_domain_code))) { + ARRAY_SIZE(wrdd_domain_code))) { printk(BIOS_DEBUG, "Error: Could not locate '%s' in VPD\n", wrdd_domain_key); return WRDD_DEFAULT_REGULATORY_DOMAIN; } printk(BIOS_DEBUG, "Found '%s'='%s' in VPD\n", wrdd_domain_key, wrdd_domain_code); + separator = memchr(wrdd_domain_code, VARIANT_SEPARATOR, + ARRAY_SIZE(wrdd_domain_code)); + if (separator) { + *separator = '\0'; + } for (i = 0; i < ARRAY_SIZE(wrdd_table); i++) { p = &wrdd_table[i];

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Patch set updated for coreboot: intel/wifi: Add WRDD ACPI method
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13838 -gerrit commit bb5c57e5ce0847b241a1be85059972ba354a70af Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 08:44:06 2016 -0800 intel/wifi: Add WRDD ACPI method Add an ACPI file containing a generic WRDD method that is used by Intel wireless kernel drivers to determine the country code to be used for regulatory domain configuration of the wireless radios. This requires an NVS variable called 'CID1' to provide an ISO-3166-2 alpha-2 country code or it will just return 0 instead. This is implemented as a bare method because this needs to be included directly into the wifi device that is defined by the mainboard as it may have board-specific settings like _PRW that need to be provided as well. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Change-Id: I27a5e27f65d05ff62a0e79a87a32c1ef0c5d0ef3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 2da0cf76ca3cc5e3dfbc4a0859733523de780cf5 Original-Change-Id: I9d83c3938cceafc77ef8747a5c47f586ee84437e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329294 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/wifi/acpi/wrdd.asl | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/drivers/intel/wifi/acpi/wrdd.asl b/src/drivers/intel/wifi/acpi/wrdd.asl new file mode 100644 index 0000000..6f071ad --- /dev/null +++ b/src/drivers/intel/wifi/acpi/wrdd.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This method is used by the Intel wireless kernel drivers to determine + * the proper country code for regulatory domain configuration. + * + * It requires an NVS field called CID1 to be present that provides the + * ISO-3166-2 alpha-2 country code. + */ +Method (WRDD, 0, Serialized) +{ + Name (WRDX, Package () { + 0, /* Revision */ + Package () { + 0x00000007, /* Domain Type, 0x7:WiFi */ + 0x00000000, /* No Default Country Identifier */ + } + }) + + /* Replace Country Identifier with value from NVS */ + Store (\CID1, Index (DeRefOf (Index (WRDX, 1)), 1)) + Return (WRDX) +}

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Patch set updated for coreboot: skylake: Add and fill out CID1 NVS field
by Patrick Georgi 27 Feb '16

27 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13839 -gerrit commit 77f84906f9f518365050806ed1d507a0ff9be5bf Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 08:45:43 2016 -0800 skylake: Add and fill out CID1 NVS field Add a country identifier field to NVS and populate it with the call to wifi_regulatory_domain() which will (by default) do a lookup for the 'region' identifier in VPD on a Chrome OS device. BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: Ie7531848e620095732772c22156a85b7f8a6df5c Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: dafdb3760a0302e3effdc0e83977c1bfd5c9d3b2 Original-Change-Id: Ic83ab008045a469d0e0756f7e4d42f1b3894c529 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329295 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 4 ++++ src/soc/intel/skylake/acpi/globalnvs.asl | 1 + src/soc/intel/skylake/include/soc/nvs.h | 3 ++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 678e0a9..934d7b5 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -41,6 +41,7 @@ #include <string.h> #include <types.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <wrdd.h> /* * List of suported C-states in this processor. @@ -193,6 +194,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; + + /* Fill in the Wifi Region id */ + gnvs->cid1 = wifi_regulatory_domain(); } unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 1ea7e53..2bff7d3 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -63,6 +63,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) DPTE, 8, // 0x30 - Enable DPTF NHLA, 64, // 0x31 - NHLT Address NHLL, 32, // 0x39 - NHLT Length + CID1, 16, // 0x3d - Wifi Country Identifier /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 032068f..f9d5b71 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -53,7 +53,8 @@ typedef struct { u8 dpte; /* 0x30 - Enable DPTF */ u64 nhla; /* 0x31 - NHLT Address */ u32 nhll; /* 0x39 - NHLT Length */ - u8 unused[195]; + u16 cid1; /* 0x3d - Wifi Country Identifier */ + u8 unused[193]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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New patch to review for coreboot: Skylake boards: Enabling HWP
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13843 -gerrit commit 3eae1fdd1f1db2f4b7090f424fbb858cca699d00 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 8 17:19:10 2016 +0530 Skylake boards: Enabling HWP This patch provides config options to enable/disable Intel SST. BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu/lars, verified HWP driver load successfully. CQ-DEPEND=CL:313107 Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/326650 Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Benson Leung <bleung(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 3 +++ src/mainboard/google/glados/devicetree.cb | 3 +++ src/mainboard/google/lars/devicetree.cb | 3 +++ src/mainboard/intel/kunimitsu/devicetree.cb | 3 +++ 4 files changed, 12 insertions(+) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index ac3a5c1..bb925ce 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/glados/devicetree.cb b/src/mainboard/google/glados/devicetree.cb index 894f0e1..89fcff8 100644 --- a/src/mainboard/google/glados/devicetree.cb +++ b/src/mainboard/google/glados/devicetree.cb @@ -16,6 +16,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/google/lars/devicetree.cb b/src/mainboard/google/lars/devicetree.cb index cf3649a..50b3e1e 100644 --- a/src/mainboard/google/lars/devicetree.cb +++ b/src/mainboard/google/lars/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1" diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index d2a70c8..62a0c26 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -15,6 +15,9 @@ chip soc/intel/skylake # EC host command range is in 0x800-0x8ff register "gen1_dec" = "0x00fc0801" + # Enable "Intel Speed Shift Technology" + register "speed_shift_enable" = "1" + # Enable DPTF register "dptf_enable" = "1"

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New patch to review for coreboot: google/chell: Update DPTF configuration
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13842 -gerrit commit 09d9946aeb6b8ee6c797307ecb1b11163760d815 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 10:07:10 2016 -0800 google/chell: Update DPTF configuration Update the DPTF configuration for the chell mainboard: 1) Enable DPTF charger control, set max current to 1975mA according to the battery specification. 2) Enable charger effect on charger temp sensor in TRT 3) Set PL2 to 15W which is the same value configured in the CPU. BUG=chrome-os-partner:49859,chrome-os-partner:50306 BRANCH=glados TEST=build and boot on chell Change-Id: I644256b9596cc5295513c48f5e3a18e6ce8b0a6b Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: c19740a227f932bf80e9243341ec81763779719c Original-Change-Id: Icff5edc9d659bea6370ff8de1334ebf0983340da Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329187 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/acpi/dptf.asl | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/chell/acpi/dptf.asl b/src/mainboard/google/chell/acpi/dptf.asl index c8362b7..d3549a7 100644 --- a/src/mainboard/google/chell/acpi/dptf.asl +++ b/src/mainboard/google/chell/acpi/dptf.asl @@ -37,12 +37,21 @@ #define DPTF_TSR3_PASSIVE 55 #define DPTF_TSR3_CRITICAL 70 -/* SKL-Y EC already has a custom charge profile based on temperature. */ -#undef DPTF_ENABLE_CHARGER - /* SKL-Y is Fanless design. */ #undef DPTF_ENABLE_FAN_CONTROL +/* Enable DPTF charger control */ +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0x7b7, "mA", 0 }, /* 1975mA (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1500mA */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1000mA */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 500mA */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0mA */ +}) + Name (DTRT, Package () { /* CPU Throttle Effect on CPU */ Package () { \_SB.PCI0.B0D4, \_SB.PCI0.B0D4, 100, 50, 0, 0, 0, 0 }, @@ -56,6 +65,9 @@ Name (DTRT, Package () { /* CPU Effect on Temp Sensor 2 */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, + /* Charger Effect on Temp Sensor 2 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR2, 200, 600, 0, 0, 0, 0 }, + /* CPU Effect on Temp Sensor 3 */ Package () { \_SB.PCI0.B0D4, \_SB.DPTF.TSR3, 100, 600, 0, 0, 0, 0 }, }) @@ -73,8 +85,8 @@ Name (MPPC, Package () }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ + 15000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */

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New patch to review for coreboot: google/chell: Update GPIOs for DVT2
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13841 -gerrit commit d24f610387acfbcd99052bbe0ec03a42f9ce3c01 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 08:53:40 2016 -0800 google/chell: Update GPIOs for DVT2 Add new GPIOs for touchscreen enable and reset pins and define the one missing unconnected pin for GPP_E10. BUG=chrome-os-partner:50518 BRANCH=glados TEST=build and boot on chell DVT1 Change-Id: I565a742ff266ee65a5d33f052606fe77c24b6ac8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 32a890af8c32aa30adac256d2c4ceaeefa30bd0d Original-Change-Id: I16546d38cc4e926e169f61ae1843106d1e14936b Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329297 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/gpio.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index 01b4e31..0503e3e 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -87,7 +87,7 @@ static const struct pad_config gpio_table[] = { /* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), /* VRALERT# */ PAD_CFG_NC(GPP_B2), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */ -/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), +/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */ /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ @@ -158,14 +158,14 @@ static const struct pad_config gpio_table[] = { /* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ /* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), /* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), -/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */ /* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), /* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), /* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */ /* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ -/* USB2_OC1# */ /* GPP_E10 */ +/* USB2_OC1# */ PAD_CFG_NC(GPP_E10), /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* USB_C0_DP_HPD */

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New patch to review for coreboot: mainboard/skylake: Include WRDD method in WIFI ACPI device
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13840 -gerrit commit a5c5d2184b11b5f20cc273c74975847249764293 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 08:49:00 2016 -0800 mainboard/skylake: Include WRDD method in WIFI ACPI device Include the code to add the WRDD method to the existing WiFi Device in the mainboard ACPI code. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Compile for the other platforms that are modified. Change-Id: Ibcff7585744071ba9018d0ba50e274e63365b150 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: b74bb553415f7ce224ddcb0c2c5ae509b8fed516 Original-Change-Id: Ieb24e0e64974ee3686d14a234e148f5d07fc8b12 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329296 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/chell/acpi/mainboard.asl | 2 ++ src/mainboard/google/glados/acpi/mainboard.asl | 2 ++ src/mainboard/google/lars/acpi/mainboard.asl | 2 ++ src/mainboard/intel/kunimitsu/acpi/mainboard.asl | 2 ++ 4 files changed, 8 insertions(+) diff --git a/src/mainboard/google/chell/acpi/mainboard.asl b/src/mainboard/google/chell/acpi/mainboard.asl index 0714582..a7c7bfe 100644 --- a/src/mainboard/google/chell/acpi/mainboard.asl +++ b/src/mainboard/google/chell/acpi/mainboard.asl @@ -64,6 +64,8 @@ Scope (\_SB.PCI0.RP01) Name (_ADR, 0x00000000) Name (_DDN, "Wireless LAN") Name (_PRW, Package () { GPE_WLAN_WAKE, 3 }) + + #include <drivers/intel/wifi/acpi/wrdd.asl> } } diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index 1b37329..3fbe332 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -63,6 +63,8 @@ Scope (\_SB.PCI0.RP01) Name (_ADR, 0x00000000) Name (_DDN, "Wireless LAN") Name (_PRW, Package () { GPE_WLAN_WAKE, 3 }) + + #include <drivers/intel/wifi/acpi/wrdd.asl> } } diff --git a/src/mainboard/google/lars/acpi/mainboard.asl b/src/mainboard/google/lars/acpi/mainboard.asl index e8397a1..d6299a5 100644 --- a/src/mainboard/google/lars/acpi/mainboard.asl +++ b/src/mainboard/google/lars/acpi/mainboard.asl @@ -104,6 +104,8 @@ Scope (\_SB.PCI0.RP01) Name (_ADR, 0x00000000) Name (_DDN, "Wireless LAN") Name (_PRW, Package () { GPE_WLAN_WAKE, 3 }) + + #include <drivers/intel/wifi/acpi/wrdd.asl> } } diff --git a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl index 8692c58..f44e362 100644 --- a/src/mainboard/intel/kunimitsu/acpi/mainboard.asl +++ b/src/mainboard/intel/kunimitsu/acpi/mainboard.asl @@ -108,6 +108,8 @@ Scope (\_SB.PCI0.RP01) Name (_ADR, 0x00000000) Name (_DDN, "Wireless LAN") Name (_PRW, Package () { GPE_WLAN_WAKE, 3 }) + + #include <drivers/intel/wifi/acpi/wrdd.asl> } }

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New patch to review for coreboot: skylake: Add and fill out CID1 NVS field
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13839 -gerrit commit 84cac7c4be318a30f66e5eadf2d92c52658d2f0f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 08:45:43 2016 -0800 skylake: Add and fill out CID1 NVS field Add a country identifier field to NVS and populate it with the call to wifi_regulatory_domain() which will (by default) do a lookup for the 'region' identifier in VPD on a Chrome OS device. BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: Ie7531848e620095732772c22156a85b7f8a6df5c Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: dafdb3760a0302e3effdc0e83977c1bfd5c9d3b2 Original-Change-Id: Ic83ab008045a469d0e0756f7e4d42f1b3894c529 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329295 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 4 ++++ src/soc/intel/skylake/acpi/globalnvs.asl | 1 + src/soc/intel/skylake/include/soc/nvs.h | 3 ++- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 678e0a9..934d7b5 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -41,6 +41,7 @@ #include <string.h> #include <types.h> #include <vendorcode/google/chromeos/gnvs.h> +#include <wrdd.h> /* * List of suported C-states in this processor. @@ -193,6 +194,9 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* Enable DPTF based on mainboard configuration */ gnvs->dpte = config->dptf_enable; + + /* Fill in the Wifi Region id */ + gnvs->cid1 = wifi_regulatory_domain(); } unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 1ea7e53..2bff7d3 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -63,6 +63,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) DPTE, 8, // 0x30 - Enable DPTF NHLA, 64, // 0x31 - NHLT Address NHLL, 32, // 0x39 - NHLT Length + CID1, 16, // 0x3d - Wifi Country Identifier /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index 032068f..f9d5b71 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -53,7 +53,8 @@ typedef struct { u8 dpte; /* 0x30 - Enable DPTF */ u64 nhla; /* 0x31 - NHLT Address */ u32 nhll; /* 0x39 - NHLT Length */ - u8 unused[195]; + u16 cid1; /* 0x3d - Wifi Country Identifier */ + u8 unused[193]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos;

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New patch to review for coreboot: intel/wifi: Add WRDD ACPI method
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13838 -gerrit commit b36ac74af0243558e8e22890006c675b8e930d95 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Feb 25 08:44:06 2016 -0800 intel/wifi: Add WRDD ACPI method Add an ACPI file containing a generic WRDD method that is used by Intel wireless kernel drivers to determine the country code to be used for regulatory domain configuration of the wireless radios. This requires an NVS variable called 'CID1' to provide an ISO-3166-2 alpha-2 country code or it will just return 0 instead. This is implemented as a bare method because this needs to be included directly into the wifi device that is defined by the mainboard as it may have board-specific settings like _PRW that need to be provided as well. BUG=chrome-os-partner:50516 BRANCH=glados TEST=boot on chell with 'region'='us' in VPD and see that it is properly read out by calling WRDD method on the WiFi device. Change-Id: I27a5e27f65d05ff62a0e79a87a32c1ef0c5d0ef3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 2da0cf76ca3cc5e3dfbc4a0859733523de780cf5 Original-Change-Id: I9d83c3938cceafc77ef8747a5c47f586ee84437e Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/329294 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/drivers/intel/wifi/acpi/wrdd.asl | 37 ++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/src/drivers/intel/wifi/acpi/wrdd.asl b/src/drivers/intel/wifi/acpi/wrdd.asl new file mode 100644 index 0000000..6f071ad --- /dev/null +++ b/src/drivers/intel/wifi/acpi/wrdd.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Google Inc. + * Copyright (C) 2016 Intel Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * This method is used by the Intel wireless kernel drivers to determine + * the proper country code for regulatory domain configuration. + * + * It requires an NVS field called CID1 to be present that provides the + * ISO-3166-2 alpha-2 country code. + */ +Method (WRDD, 0, Serialized) +{ + Name (WRDX, Package () { + 0, /* Revision */ + Package () { + 0x00000007, /* Domain Type, 0x7:WiFi */ + 0x00000000, /* No Default Country Identifier */ + } + }) + + /* Replace Country Identifier with value from NVS */ + Store (\CID1, Index (DeRefOf (Index (WRDX, 1)), 1)) + Return (WRDX) +}

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New patch to review for coreboot: Chromeos: Modify wifi_regulatory_domain to use "region" key in VPD
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13837 -gerrit commit eae6de757e5d5e0e899bfdb59d273a544037df06 Author: Huang, Huki <huki.huang(a)intel.com> Date: Thu Jan 21 10:17:06 2016 +0800 Chromeos: Modify wifi_regulatory_domain to use "region" key in VPD In ChromeOS VPD spec the right name is "region". Signed-off-by: Hannah Williams <hannah.williams(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/322851 Reviewed-by: Hung-Te Lin <hungte(a)chromium.org> Reviewed-by: mukesh agrawal <quiche(a)chromium.org> (cherry picked from commit 21ea0663e7f3ffe3aaea6b6ce0e1216fcd9ca23e) BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: I4ba9a9c65af3732fa263030640495ab5bea91d1f Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 848f18e731eb11dd3037d12607d7364f95e64e34 Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Change-Id: Ib96036f9cd76449f170af5c3dd6ef6e8e91ded94 Original-Reviewed-on: https://chromium-review.googlesource.com/329293 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/cros_vpd.h | 2 +- src/vendorcode/google/chromeos/wrdd.c | 11 +++++++++-- 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/src/vendorcode/google/chromeos/cros_vpd.h b/src/vendorcode/google/chromeos/cros_vpd.h index ca9c320..96ca8af 100644 --- a/src/vendorcode/google/chromeos/cros_vpd.h +++ b/src/vendorcode/google/chromeos/cros_vpd.h @@ -7,7 +7,7 @@ #ifndef __CROS_VPD_H__ #define __CROS_VPD_H__ -#define CROS_VPD_WIFI_DOMAINKEY "regions" +#define CROS_VPD_REGION_NAME "region" /* * Reads VPD string value by key. diff --git a/src/vendorcode/google/chromeos/wrdd.c b/src/vendorcode/google/chromeos/wrdd.c index ab27cc0..ad80992 100644 --- a/src/vendorcode/google/chromeos/wrdd.c +++ b/src/vendorcode/google/chromeos/wrdd.c @@ -26,6 +26,7 @@ * The first part is the ISO 3166-1 alpha-2 code of the country; * The second part is a string of up to three alphanumeric characters */ +#define VARIANT_SEPARATOR '.' struct wrdd_code_value_pair { const char *code; u16 value; @@ -50,21 +51,27 @@ uint16_t wifi_regulatory_domain(void) .value = WRDD_REGULATORY_DOMAIN_INDONESIA } }; - const char *wrdd_domain_key = CROS_VPD_WIFI_DOMAINKEY; + const char *wrdd_domain_key = CROS_VPD_REGION_NAME; int i; struct wrdd_code_value_pair *p; /* wrdd_domain_value is ISO 3166-2 */ char wrdd_domain_code[7]; + char *separator; /* If not found for any reason fall backto the default value */ if (!cros_vpd_gets(wrdd_domain_key, wrdd_domain_code, - sizeof(wrdd_domain_code))) { + ARRAY_SIZE(wrdd_domain_code))) { printk(BIOS_DEBUG, "Error: Could not locate '%s' in VPD\n", wrdd_domain_key); return WRDD_DEFAULT_REGULATORY_DOMAIN; } printk(BIOS_DEBUG, "Found '%s'='%s' in VPD\n", wrdd_domain_key, wrdd_domain_code); + separator = memchr(wrdd_domain_code, VARIANT_SEPARATOR, + ARRAY_SIZE(wrdd_domain_code)); + if (separator) { + *separator = '\0'; + } for (i = 0; i < ARRAY_SIZE(wrdd_table); i++) { p = &wrdd_table[i];

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coreboot-gerrit February 2016