coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: amdfwtool: Reserve one more dword in PSP2 header
by Zheng Bao 26 Feb '16

26 Feb '16

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13810 -gerrit commit c3227aced5df78e53f2c8e20cecd777c6e18b33f Author: zbao <fishbaozi(a)gmail.com> Date: Fri Feb 26 22:25:32 2016 +0800 amdfwtool: Reserve one more dword in PSP2 header Spec says that. It is validated. Change-Id: Ied699309f98841f10966b7a5b9697800a25ab27a Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 7e70012..2272052 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -46,6 +46,8 @@ * +------------+---------------+----------------+------------+ * | 'PSP2' | Fletcher | Count |Look up mode| * +------------+---------------+----------------+------------+ + * | R e s e r v e d | + * +------------+---------------+----------------+------------+ * | ID-Sel | PSP ID | PSPDIR ADDR | | 2nd PSP directory * +------------+---------------+----------------+------------+ * | ID-Sel | PSP ID | PSPDIR ADDR | | 3rd PSP directory @@ -555,11 +557,11 @@ int main(int argc, char **argv) psp2count = 1; /* Start from 1. */ /* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */ /* Now the psp2dir is psp combo dir. */ - psp2dir[psp2count*4 + 0] = 0; /* 0 -Compare PSP ID, 1 -Compare chip family ID */ - psp2dir[psp2count*4 + 1] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */ - psp2dir[psp2count*4 + 2] = current + ROM_BASE_ADDRESS; + psp2dir[psp2count*4 + 0 + 4] = 0; /* 0 -Compare PSP ID, 1 -Compare chip family ID */ + psp2dir[psp2count*4 + 1 + 4] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */ + psp2dir[psp2count*4 + 2 + 4] = current + ROM_BASE_ADDRESS; pspdir = rom + current; - psp2dir[psp2count*4 + 3] = 0; + psp2dir[psp2count*4 + 3 + 4] = 0; current += 0x200; /* Add conservative size of pspdir. Start of PSP entries. */ current = integrate_psp_firmwares(rom, current, pspdir, amd_psp2_fw_table); @@ -568,8 +570,12 @@ int main(int argc, char **argv) /* fill the PSP combo head */ psp2dir[0] = 0x50535032; /* 'PSP2' */ psp2dir[2] = psp2count; /* Count */ - psp2dir[3] = 0; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */ - psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2); + psp2dir[3] = 1; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */ + psp2dir[4] = 0; /* reserved 4 dwords. */ + psp2dir[5] = 0; + psp2dir[6] = 0; + psp2dir[7] = 0; + psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 32)/2 - 2); #else current = integrate_psp_firmwares(rom, current, psp2dir, amd_psp2_fw_table); #endif

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Patch set updated for coreboot: soc/intel/apollolake: Enable using FSP 2.0 driver
by Andrey Petrov 26 Feb '16

26 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13806 -gerrit commit b330ac6c6c89e980dbc4cb28f7e6ac01792a335d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 18:39:38 2016 -0800 soc/intel/apollolake: Enable using FSP 2.0 driver Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 1633dbe..1877472 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,8 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select NO_UART_ON_SUPERIO select DRIVERS_UART_8250MEM_32 + select PLATFORM_USES_FSP2_0 + select ADD_FSP_BINARIES config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address"

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Patch set updated for coreboot: amdfwtool: Fix some PSP2 issues
by Zheng Bao 26 Feb '16

26 Feb '16

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13808 -gerrit commit 597defefc5ce6921db27e8286342becd523ae624 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Feb 26 20:48:13 2016 +0800 amdfwtool: Fix some PSP2 issues 1. Change the function which pushed one firmware to the one which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 189 +++++++++++++++++++++++---------------------- 1 file changed, 95 insertions(+), 94 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 073c138..6cb168e 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -166,6 +166,7 @@ typedef enum _amd_fw_type { AMD_FW_IMC, AMD_FW_GEC, AMD_FW_XHCI, + AMD_FW_INVALID, } amd_fw_type; typedef struct _amd_fw_entry { @@ -187,6 +188,7 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, { .type = AMD_FW_PSP_SMUSCS }, { .type = AMD_PSP_FUSE_CHAIN }, + { .type = AMD_FW_INVALID }, }; #if PSP2 @@ -204,6 +206,7 @@ amd_fw_entry amd_psp2_fw_table[] = { { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, { .type = AMD_FW_PSP_SMUSCS }, { .type = AMD_PSP_FUSE_CHAIN }, + { .type = AMD_FW_INVALID }, }; #endif @@ -211,6 +214,7 @@ amd_fw_entry amd_fw_table[] = { { .type = AMD_FW_XHCI }, { .type = AMD_FW_IMC }, { .type = AMD_FW_GEC }, + { .type = AMD_FW_INVALID }, }; void fill_psp_head(uint32_t *pspdir, int count) @@ -221,70 +225,76 @@ void fill_psp_head(uint32_t *pspdir, int count) pspdir[1] = fletcher32((uint16_t *)&pspdir[1], (count *16 + 16)/2 - 2); } -uint32_t integerate_one_fw(void *base, uint32_t pos, uint32_t *romsig, int i) +uint32_t integrate_firmwares(void *base, uint32_t pos, uint32_t *romsig, amd_fw_entry *fw_table) { int fd; struct stat fd_stat; + int i; - if (amd_fw_table[i].filename != NULL) { - fd = open (amd_fw_table[i].filename, O_RDONLY); - fstat(fd, &fd_stat); - - switch (amd_fw_table[i].type) { - case AMD_FW_IMC: - pos = ALIGN(pos, 0x10000); - romsig[1] = pos + ROM_BASE_ADDRESS; - break; - case AMD_FW_GEC: - romsig[2] = pos + ROM_BASE_ADDRESS; - break; - case AMD_FW_XHCI: - romsig[3] = pos + ROM_BASE_ADDRESS; - break; - default: - /* Error */ - break; - } + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i ++) { + if (fw_table[i].filename != NULL) { + fd = open (fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + + switch (fw_table[i].type) { + case AMD_FW_IMC: + pos = ALIGN(pos, 0x10000); + romsig[1] = pos + ROM_BASE_ADDRESS; + break; + case AMD_FW_GEC: + romsig[2] = pos + ROM_BASE_ADDRESS; + break; + case AMD_FW_XHCI: + romsig[3] = pos + ROM_BASE_ADDRESS; + break; + default: + /* Error */ + break; + } - read (fd, base+pos, fd_stat.st_size); + read (fd, base+pos, fd_stat.st_size); - pos += fd_stat.st_size; - pos = ALIGN(pos, 0x100); - close (fd); + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } } return pos; } -uint32_t integerate_one_psp(void *base, uint32_t pos, uint32_t *pspdir, int i) +uint32_t integrate_psp_firmwares(void *base, uint32_t pos, uint32_t *pspdir, amd_fw_entry *fw_table) { int fd; struct stat fd_stat; + int i; - if (amd_psp_fw_table[i].type == AMD_PSP_FUSE_CHAIN) { - pspdir[4+4*i+0] = amd_psp_fw_table[i].type; - pspdir[4+4*i+1] = 0xFFFFFFFF; - pspdir[4+4*i+2] = 1; - pspdir[4+4*i+3] = 0; - } else if (amd_psp_fw_table[i].filename != NULL) { - pspdir[4+4*i+0] = amd_psp_fw_table[i].type; - - fd = open (amd_psp_fw_table[i].filename, O_RDONLY); - fstat(fd, &fd_stat); - pspdir[4+4*i+1] = fd_stat.st_size; - - pspdir[4+4*i+2] = pos + ROM_BASE_ADDRESS; - pspdir[4+4*i+3] = 0; - - read (fd, base+pos, fd_stat.st_size); - - pos += fd_stat.st_size; - pos = ALIGN(pos, 0x100); - close (fd); - } else { - /* This APU doesn't have this firmware. */ + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i ++) { + if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { + pspdir[4+4*i+0] = fw_table[i].type; + pspdir[4+4*i+1] = 0xFFFFFFFF; + pspdir[4+4*i+2] = 1; + pspdir[4+4*i+3] = 0; + } else if (fw_table[i].filename != NULL) { + pspdir[4+4*i+0] = fw_table[i].type; + + fd = open (fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + pspdir[4+4*i+1] = fd_stat.st_size; + + pspdir[4+4*i+2] = pos + ROM_BASE_ADDRESS; + pspdir[4+4*i+3] = 0; + + read (fd, base+pos, fd_stat.st_size); + + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } else { + /* This APU doesn't have this firmware. */ + } } - + fill_psp_head(pspdir, i); return pos; } @@ -363,12 +373,15 @@ void register_fw_filename(amd_fw_type type, char filename[], int pspflag) int main(int argc, char **argv) { - int c, count, pspflag = 0; + int c, pspflag = 0; #if PSP2 int psp2flag = 0; - int psp2count; uint32_t *psp2dir; #endif +#if PSP_COMBO + int psp2count; +#endif + void *rom = NULL; uint32_t current; uint32_t *amd_romsig, *pspdir; @@ -519,9 +532,7 @@ int main(int argc, char **argv) } current = ALIGN(current, 0x100); - for (count = 0; count < sizeof(amd_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_fw(rom, current, amd_romsig, count); - } + current = integrate_firmwares(rom, current, amd_romsig, amd_fw_table); if (pspflag == 1) { current = ALIGN(current, 0x10000); @@ -529,51 +540,41 @@ int main(int argc, char **argv) amd_romsig[4] = current + ROM_BASE_ADDRESS; current += 0x200; /* Conservative size of pspdir */ - for (count = 0; count < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_psp(rom, current, pspdir, count); - } - - fill_psp_head(pspdir, count); + current = integrate_psp_firmwares(rom, current, pspdir, amd_psp_fw_table); + } #if PSP2 - if (psp2flag == 1) { - current = ALIGN(current, 0x10000); /* PSP2 dir */ - psp2dir = rom + current; - amd_romsig[5] = current + ROM_BASE_ADDRESS; - current += 0x100; /* Add conservative size of psp2dir. */ - - #if PSP_COMBO - /* TODO: remove the hardcode. */ - psp2count = 1; /* Start from 1. */ - /* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */ - /* Now the psp2dir is psp combo dir. */ - psp2dir[psp2count*4 + 0] = 0; /* 0 -Compare PSP ID, 1 -Compare chip family ID */ - psp2dir[psp2count*4 + 1] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */ - psp2dir[psp2count*4 + 2] = current + ROM_BASE_ADDRESS; - pspdir = rom + current; - psp2dir[psp2count*4 + 3] = 0; - - current += 0x200; /* Add conservative size of pspdir. Start of PSP entries. */ - for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_psp(rom, current, pspdir, count); - } - fill_psp_head(pspdir, count); - /* } */ /* End of loop */ - - /* fill the PSP combo head */ - psp2dir[0] = 0x50535032; /* 'PSP2' */ - psp2dir[2] = psp2count; /* Count */ - psp2dir[3] = 0; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */ - psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2); - #else - for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_psp(rom, current, psp2dir, count); - } - fill_psp_head(psp2dir, count); - #endif - } + if (psp2flag == 1) { + current = ALIGN(current, 0x10000); /* PSP2 dir */ + psp2dir = rom + current; + amd_romsig[5] = current + ROM_BASE_ADDRESS; + current += 0x100; /* Add conservative size of psp2dir. */ + +#if PSP_COMBO + /* TODO: remove the hardcode. */ + psp2count = 1; /* Start from 1. */ + /* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */ + /* Now the psp2dir is psp combo dir. */ + psp2dir[psp2count*4 + 0] = 0; /* 0 -Compare PSP ID, 1 -Compare chip family ID */ + psp2dir[psp2count*4 + 1] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */ + psp2dir[psp2count*4 + 2] = current + ROM_BASE_ADDRESS; + pspdir = rom + current; + psp2dir[psp2count*4 + 3] = 0; + + current += 0x200; /* Add conservative size of pspdir. Start of PSP entries. */ + current = integrate_psp_firmwares(rom, current, pspdir, amd_psp2_fw_table); + /* } */ /* End of loop */ + + /* fill the PSP combo head */ + psp2dir[0] = 0x50535032; /* 'PSP2' */ + psp2dir[2] = psp2count; /* Count */ + psp2dir[3] = 0; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */ + psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2); +#else + current = integrate_psp_firmwares(rom, current, psp2dir, amd_psp2_fw_table); #endif } +#endif targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); write(targetfd, amd_romsig, current - AMD_ROMSIG_OFFSET);

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Patch set updated for coreboot: amdfwtool: change the ambiguous options to specific ones.
by Zheng Bao 26 Feb '16

26 Feb '16

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13809 -gerrit commit 433e65c81205cb8d4524bf4ab12f4a52565cedc0 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Feb 26 20:50:55 2016 +0800 amdfwtool: change the ambiguous options to specific ones. Change-Id: Ia9045887ef80a4675755744fbf76ef0ed30d0a08 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 6cb168e..7e70012 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -314,23 +314,23 @@ static struct option long_options[] = { {"securedebug", required_argument, 0, 'd' }, {"trustlets", required_argument, 0, 't' }, {"trustletkey", required_argument, 0, 'u' }, - {"smufirmware2", required_argument, 0, 'w' }, + {"smufirmwaretwo", required_argument, 0, 'w' }, {"smuscs", required_argument, 0, 'm' }, /* TODO: PSP2 */ #if PSP2 - {"pubkey2", required_argument, 0, 'P' }, - {"bootloader2", required_argument, 0, 'B' }, - {"smufirmware2", required_argument, 0, 'S' }, - {"recovery2", required_argument, 0, 'R' }, - {"rtmpubkey2", required_argument, 0, 'K' }, - {"secureos2", required_argument, 0, 'C' }, - {"nvram2", required_argument, 0, 'N' }, - {"securedebug2", required_argument, 0, 'D' }, - {"trustlets2", required_argument, 0, 'T' }, - {"trustletkey2", required_argument, 0, 'U' }, - {"smufirmware2_2",required_argument, 0, 'W' }, - {"smuscs2", required_argument, 0, 'M' }, + {"pubkeypsp2", required_argument, 0, 'P' }, + {"bootloaderpsp2", required_argument, 0, 'B' }, + {"smufirmwarepsp2", required_argument, 0, 'S' }, + {"recoverypsp2", required_argument, 0, 'R' }, + {"rtmpubkeypsp2", required_argument, 0, 'K' }, + {"secureospsp2", required_argument, 0, 'C' }, + {"nvrampsp2", required_argument, 0, 'N' }, + {"securedebugpsp2", required_argument, 0, 'D' }, + {"trustletspsp2", required_argument, 0, 'T' }, + {"trustletkeypsp2", required_argument, 0, 'U' }, + {"smufirmwaretwopsp2",required_argument, 0, 'W' }, + {"smuscspsp2", required_argument, 0, 'M' }, #endif {"output", required_argument, 0, 'o' },

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New patch to review for coreboot: amdfwtool: change the ambiguous options to specific ones.
by Zheng Bao 26 Feb '16

26 Feb '16

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13809 -gerrit commit 6a32f880890371b04f5abf075874df449a5736b8 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Feb 26 20:50:55 2016 +0800 amdfwtool: change the ambiguous options to specific ones. Change-Id: Ia9045887ef80a4675755744fbf76ef0ed30d0a08 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 0e13f44..ccfc905 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -314,23 +314,23 @@ static struct option long_options[] = { {"securedebug", required_argument, 0, 'd' }, {"trustlets", required_argument, 0, 't' }, {"trustletkey", required_argument, 0, 'u' }, - {"smufirmware2", required_argument, 0, 'w' }, + {"smufirmwaretwo", required_argument, 0, 'w' }, {"smuscs", required_argument, 0, 'm' }, /* TODO: PSP2 */ #if PSP2 - {"pubkey2", required_argument, 0, 'P' }, - {"bootloader2", required_argument, 0, 'B' }, - {"smufirmware2", required_argument, 0, 'S' }, - {"recovery2", required_argument, 0, 'R' }, - {"rtmpubkey2", required_argument, 0, 'K' }, - {"secureos2", required_argument, 0, 'C' }, - {"nvram2", required_argument, 0, 'N' }, - {"securedebug2", required_argument, 0, 'D' }, - {"trustlets2", required_argument, 0, 'T' }, - {"trustletkey2", required_argument, 0, 'U' }, - {"smufirmware2_2",required_argument, 0, 'W' }, - {"smuscs2", required_argument, 0, 'M' }, + {"pubkeypsp2", required_argument, 0, 'P' }, + {"bootloaderpsp2", required_argument, 0, 'B' }, + {"smufirmwarepsp2", required_argument, 0, 'S' }, + {"recoverypsp2", required_argument, 0, 'R' }, + {"rtmpubkeypsp2", required_argument, 0, 'K' }, + {"secureospsp2", required_argument, 0, 'C' }, + {"nvrampsp2", required_argument, 0, 'N' }, + {"securedebugpsp2", required_argument, 0, 'D' }, + {"trustletspsp2", required_argument, 0, 'T' }, + {"trustletkeypsp2", required_argument, 0, 'U' }, + {"smufirmwaretwopsp2",required_argument, 0, 'W' }, + {"smuscspsp2", required_argument, 0, 'M' }, #endif {"output", required_argument, 0, 'o' },

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New patch to review for coreboot: amdfwtool: Fix some PSP2 issues
by Zheng Bao 26 Feb '16

26 Feb '16

Zheng Bao (zheng.bao(a)amd.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13808 -gerrit commit c7b67a2bb903bb684ef1fa08d1e73918c7909651 Author: zbao <fishbaozi(a)gmail.com> Date: Fri Feb 26 20:48:13 2016 +0800 amdfwtool: Fix some PSP2 issues 1. Change the function which pushed one firmware to the one which pushes the whole group. Use fw_table as a parameter instead of using the global table name. 2. Let PSP2 and PSP1 not dependent on the other. It turns out PSP2 can exist without PSP1. For some APU, the PSP directory has to be put in PSP2 field (ROMSIG 0x14). Change-Id: I834630d9596d7fb941e2cad5d00ac3af04a537b5 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- util/amdfwtool/amdfwtool.c | 189 +++++++++++++++++++++++---------------------- 1 file changed, 95 insertions(+), 94 deletions(-) diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 073c138..0e13f44 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -166,6 +166,7 @@ typedef enum _amd_fw_type { AMD_FW_IMC, AMD_FW_GEC, AMD_FW_XHCI, + AMD_FW_INVALID, } amd_fw_type; typedef struct _amd_fw_entry { @@ -187,6 +188,7 @@ amd_fw_entry amd_psp_fw_table[] = { { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, { .type = AMD_FW_PSP_SMUSCS }, { .type = AMD_PSP_FUSE_CHAIN }, + { .type = AMD_FW_INVALID }, }; #if PSP2 @@ -204,6 +206,7 @@ amd_fw_entry amd_psp2_fw_table[] = { { .type = AMD_FW_PSP_SMU_FIRMWARE2 }, { .type = AMD_FW_PSP_SMUSCS }, { .type = AMD_PSP_FUSE_CHAIN }, + { .type = AMD_FW_INVALID }, }; #endif @@ -211,6 +214,7 @@ amd_fw_entry amd_fw_table[] = { { .type = AMD_FW_XHCI }, { .type = AMD_FW_IMC }, { .type = AMD_FW_GEC }, + { .type = AMD_FW_INVALID }, }; void fill_psp_head(uint32_t *pspdir, int count) @@ -221,70 +225,76 @@ void fill_psp_head(uint32_t *pspdir, int count) pspdir[1] = fletcher32((uint16_t *)&pspdir[1], (count *16 + 16)/2 - 2); } -uint32_t integerate_one_fw(void *base, uint32_t pos, uint32_t *romsig, int i) +uint32_t integrate_firmwares(void *base, uint32_t pos, uint32_t *romsig, amd_fw_entry *fw_table) { int fd; struct stat fd_stat; + int i; - if (amd_fw_table[i].filename != NULL) { - fd = open (amd_fw_table[i].filename, O_RDONLY); - fstat(fd, &fd_stat); - - switch (amd_fw_table[i].type) { - case AMD_FW_IMC: - pos = ALIGN(pos, 0x10000); - romsig[1] = pos + ROM_BASE_ADDRESS; - break; - case AMD_FW_GEC: - romsig[2] = pos + ROM_BASE_ADDRESS; - break; - case AMD_FW_XHCI: - romsig[3] = pos + ROM_BASE_ADDRESS; - break; - default: - /* Error */ - break; - } + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i ++) { + if (amd_fw_table[i].filename != NULL) { + fd = open (amd_fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + + switch (amd_fw_table[i].type) { + case AMD_FW_IMC: + pos = ALIGN(pos, 0x10000); + romsig[1] = pos + ROM_BASE_ADDRESS; + break; + case AMD_FW_GEC: + romsig[2] = pos + ROM_BASE_ADDRESS; + break; + case AMD_FW_XHCI: + romsig[3] = pos + ROM_BASE_ADDRESS; + break; + default: + /* Error */ + break; + } - read (fd, base+pos, fd_stat.st_size); + read (fd, base+pos, fd_stat.st_size); - pos += fd_stat.st_size; - pos = ALIGN(pos, 0x100); - close (fd); + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } } return pos; } -uint32_t integerate_one_psp(void *base, uint32_t pos, uint32_t *pspdir, int i) +uint32_t integrate_psp_firmwares(void *base, uint32_t pos, uint32_t *pspdir, amd_fw_entry *fw_table) { int fd; struct stat fd_stat; + int i; - if (amd_psp_fw_table[i].type == AMD_PSP_FUSE_CHAIN) { - pspdir[4+4*i+0] = amd_psp_fw_table[i].type; - pspdir[4+4*i+1] = 0xFFFFFFFF; - pspdir[4+4*i+2] = 1; - pspdir[4+4*i+3] = 0; - } else if (amd_psp_fw_table[i].filename != NULL) { - pspdir[4+4*i+0] = amd_psp_fw_table[i].type; - - fd = open (amd_psp_fw_table[i].filename, O_RDONLY); - fstat(fd, &fd_stat); - pspdir[4+4*i+1] = fd_stat.st_size; - - pspdir[4+4*i+2] = pos + ROM_BASE_ADDRESS; - pspdir[4+4*i+3] = 0; - - read (fd, base+pos, fd_stat.st_size); - - pos += fd_stat.st_size; - pos = ALIGN(pos, 0x100); - close (fd); - } else { - /* This APU doesn't have this firmware. */ + for (i = 0; fw_table[i].type != AMD_FW_INVALID; i ++) { + if (fw_table[i].type == AMD_PSP_FUSE_CHAIN) { + pspdir[4+4*i+0] = fw_table[i].type; + pspdir[4+4*i+1] = 0xFFFFFFFF; + pspdir[4+4*i+2] = 1; + pspdir[4+4*i+3] = 0; + } else if (fw_table[i].filename != NULL) { + pspdir[4+4*i+0] = fw_table[i].type; + + fd = open (fw_table[i].filename, O_RDONLY); + fstat(fd, &fd_stat); + pspdir[4+4*i+1] = fd_stat.st_size; + + pspdir[4+4*i+2] = pos + ROM_BASE_ADDRESS; + pspdir[4+4*i+3] = 0; + + read (fd, base+pos, fd_stat.st_size); + + pos += fd_stat.st_size; + pos = ALIGN(pos, 0x100); + close (fd); + } else { + /* This APU doesn't have this firmware. */ + } } - + fill_psp_head(pspdir, i); return pos; } @@ -363,12 +373,15 @@ void register_fw_filename(amd_fw_type type, char filename[], int pspflag) int main(int argc, char **argv) { - int c, count, pspflag = 0; + int c, pspflag = 0; #if PSP2 int psp2flag = 0; - int psp2count; uint32_t *psp2dir; #endif +#if PSP_COMBO + int psp2count; +#endif + void *rom = NULL; uint32_t current; uint32_t *amd_romsig, *pspdir; @@ -519,9 +532,7 @@ int main(int argc, char **argv) } current = ALIGN(current, 0x100); - for (count = 0; count < sizeof(amd_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_fw(rom, current, amd_romsig, count); - } + current = integrate_firmwares(rom, current, amd_romsig, amd_fw_table); if (pspflag == 1) { current = ALIGN(current, 0x10000); @@ -529,51 +540,41 @@ int main(int argc, char **argv) amd_romsig[4] = current + ROM_BASE_ADDRESS; current += 0x200; /* Conservative size of pspdir */ - for (count = 0; count < sizeof(amd_psp_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_psp(rom, current, pspdir, count); - } - - fill_psp_head(pspdir, count); + current = integrate_psp_firmwares(rom, current, pspdir, amd_psp_fw_table); + } #if PSP2 - if (psp2flag == 1) { - current = ALIGN(current, 0x10000); /* PSP2 dir */ - psp2dir = rom + current; - amd_romsig[5] = current + ROM_BASE_ADDRESS; - current += 0x100; /* Add conservative size of psp2dir. */ - - #if PSP_COMBO - /* TODO: remove the hardcode. */ - psp2count = 1; /* Start from 1. */ - /* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */ - /* Now the psp2dir is psp combo dir. */ - psp2dir[psp2count*4 + 0] = 0; /* 0 -Compare PSP ID, 1 -Compare chip family ID */ - psp2dir[psp2count*4 + 1] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */ - psp2dir[psp2count*4 + 2] = current + ROM_BASE_ADDRESS; - pspdir = rom + current; - psp2dir[psp2count*4 + 3] = 0; - - current += 0x200; /* Add conservative size of pspdir. Start of PSP entries. */ - for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_psp(rom, current, pspdir, count); - } - fill_psp_head(pspdir, count); - /* } */ /* End of loop */ - - /* fill the PSP combo head */ - psp2dir[0] = 0x50535032; /* 'PSP2' */ - psp2dir[2] = psp2count; /* Count */ - psp2dir[3] = 0; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */ - psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2); - #else - for (count = 0; count < sizeof(amd_psp2_fw_table) / sizeof(amd_fw_entry); count ++) { - current = integerate_one_psp(rom, current, psp2dir, count); - } - fill_psp_head(psp2dir, count); - #endif - } + if (psp2flag == 1) { + current = ALIGN(current, 0x10000); /* PSP2 dir */ + psp2dir = rom + current; + amd_romsig[5] = current + ROM_BASE_ADDRESS; + current += 0x100; /* Add conservative size of psp2dir. */ + +#if PSP_COMBO + /* TODO: remove the hardcode. */ + psp2count = 1; /* Start from 1. */ + /* for (; psp2count <= PSP2COUNT; psp2count++, current=ALIGN(current, 0x100)) { */ + /* Now the psp2dir is psp combo dir. */ + psp2dir[psp2count*4 + 0] = 0; /* 0 -Compare PSP ID, 1 -Compare chip family ID */ + psp2dir[psp2count*4 + 1] = 0x10220B00; /* TODO: PSP ID. Documentation is needed. */ + psp2dir[psp2count*4 + 2] = current + ROM_BASE_ADDRESS; + pspdir = rom + current; + psp2dir[psp2count*4 + 3] = 0; + + current += 0x200; /* Add conservative size of pspdir. Start of PSP entries. */ + current = integrate_psp_firmwares(rom, current, pspdir, amd_psp2_fw_table); + /* } */ /* End of loop */ + + /* fill the PSP combo head */ + psp2dir[0] = 0x50535032; /* 'PSP2' */ + psp2dir[2] = psp2count; /* Count */ + psp2dir[3] = 0; /* 0-Dynamic look up through all entries, 1-PSP/chip ID match */ + psp2dir[1] = fletcher32((uint16_t *)&psp2dir[1], (psp2count*16 + 16)/2 - 2); +#else + current = integrate_psp_firmwares(rom, current, psp2dir, amd_psp2_fw_table); #endif } +#endif targetfd = open(output, O_RDWR | O_CREAT | O_TRUNC, 0666); write(targetfd, amd_romsig, current - AMD_ROMSIG_OFFSET);

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Patch merged into coreboot/master: nvramtool: Print computed and stored checksum in case of mismatch.
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit 9c44b256458e8d203200f06dbf4a471afaabdf0c Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat Feb 20 18:49:13 2016 +0100 nvramtool: Print computed and stored checksum in case of mismatch. This is to make it easier to fix checksum issues. Example: # nvramtool -a [...] nvramtool: Warning: Coreboot CMOS checksum is bad. Computed checksum: 0xfa. Stored checksum: 0x0 # nvramtool -c 0xfa Change-Id: Ifacb68b5693afbdfcb521acd6937e270ead85186 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: https://review.coreboot.org/13770 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/13770 for details. -gerrit

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Patch merged into coreboot/master: tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))"
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit 0e92bb010f8bd45b2543f2553a4d3c2f35dffc09 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sat Feb 20 17:32:03 2016 +0100 tree wide: Convert "if (CONFIG_.*_TPM.*)" to "if (IS_ENABLED(...))" Change-Id: Ib73abb0ada7dfdfab3487c005719e19f51ef1812 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: https://review.coreboot.org/13779 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/13779 for details. -gerrit

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Patch merged into coreboot/master: util: Add a very simple utility to test POST cards.
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit bfe07899e372ac41c0a6dd4efac25458f5d48c9c Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Sun Feb 21 14:27:21 2016 +0100 util: Add a very simple utility to test POST cards. It was tested with a mini-PCI POST card on a Toshiba Satellite 1410 laptop with the stock BIOS. Change-Id: Icdc0860e2c72b17862601c2cc59eaf0f3d8a0e54 Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: https://review.coreboot.org/13763 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13763 for details. -gerrit

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New patch to review for coreboot: During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width.
by Timothy Pearson 26 Feb '16

26 Feb '16

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13807 -gerrit commit 9da1177c09d6748817964fad31d73b7658e9138f Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 25 23:20:14 2016 -0600 During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/drivers/aspeed/common/ast_main.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/aspeed/common/ast_main.c b/src/drivers/aspeed/common/ast_main.c index 071e49c..264ef9d 100644 --- a/src/drivers/aspeed/common/ast_main.c +++ b/src/drivers/aspeed/common/ast_main.c @@ -232,7 +232,7 @@ static int ast_get_dram_info(struct drm_device *dev) data = ast_read32(ast, 0x10004); - if (data & 0x400) + if (data & 0x40) ast->dram_bus_width = 16; else ast->dram_bus_width = 32;

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coreboot-gerrit February 2016