coreboot-gerrit February 2016

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Patch set updated for coreboot: soc/intel/apollolake: Add romstage that calls FSP2.0 driver
by Andrey Petrov 26 Feb '16

26 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13805 -gerrit commit 0b6393780f1cd2467d2f5da5df72e4d32997a8a2 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 17:42:25 2016 -0800 soc/intel/apollolake: Add romstage that calls FSP2.0 driver This romstage is minimalistic. Its goal is to set up some BARs that FSP expects to be set and then invoke FSP driver to train memory. Change-Id: I3fa56aafe99cf6cf062a46dece3a0febeafdbfad Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 7 + src/soc/intel/apollolake/Makefile.inc | 3 + src/soc/intel/apollolake/include/fsp/FspUpd.h | 37 ++ src/soc/intel/apollolake/include/fsp/FspmUpd.h | 569 ++++++++++++++++++++++++ src/soc/intel/apollolake/include/fsp/FspsUpd.h | 565 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/iomap.h | 27 ++ src/soc/intel/apollolake/include/soc/romstage.h | 22 + src/soc/intel/apollolake/romstage/entry.inc | 26 ++ src/soc/intel/apollolake/romstage/romstage.c | 154 +++++++ 9 files changed, 1410 insertions(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 401535f..1633dbe 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -83,4 +83,11 @@ config C_ENV_BOOTBLOCK_SIZE config X86_TOP4G_BOOTMEDIA_MAP bool default n + +config ROMSTAGE_CAR_ADDR + hex + default 0xfef2e000 + help + The base address (in CAR) where romstage should be linked + endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 17ddaec..fcb5c57 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -16,10 +16,13 @@ bootblock-y += placeholders.c bootblock-y += tsc_freq.c bootblock-y += uart_early.c +cpu_incs-$(PLATFORM_USES_FSP2_0) += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += placeholders.c +romstage-$(PLATFORM_USES_FSP2_0) += romstage/romstage.c romstage-y += gpio.c romstage-y += mmap_boot.c romstage-y += uart_early.c +LDFLAGS_romstage += --section-start=.text=$(CONFIG_ROMSTAGE_CAR_ADDR) smm-y += placeholders.c ramstage-y += placeholders.c diff --git a/src/soc/intel/apollolake/include/fsp/FspUpd.h b/src/soc/intel/apollolake/include/fsp/FspUpd.h new file mode 100644 index 0000000..da3486d --- /dev/null +++ b/src/soc/intel/apollolake/include/fsp/FspUpd.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP_API_H_ +#define _FSP_API_H_ + +/** FSP UPD Header +**/ +struct FSP_UPD_HEADER { + +/** Offset 0x00 to 0x07 - UPD Region Signature + The signature will be + "FSPT_UPD" for FSP-T + "FSPM_UPD" for FSP-M + "FSPS_UPD" for FSP-S +**/ + uint64_t Signature; + +/** Offset 0x08 - Revision +**/ + uint8_t Revision; + +/** Offset 0x09 to 0x1F - ReservedUpd +**/ + uint8_t ReservedUpd[23]; +} __attribute__((packed)); + +#endif /* _FSP_API_H_ */ diff --git a/src/soc/intel/apollolake/include/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/fsp/FspmUpd.h new file mode 100644 index 0000000..c7b2607 --- /dev/null +++ b/src/soc/intel/apollolake/include/fsp/FspmUpd.h @@ -0,0 +1,569 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include "FspUpd.h" + + +typedef union { + uint32_t PadCnf0; + struct { + uint32_t GPIOTxState:1; ///< 0 GPIO TX State + uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO + uint32_t Reserved1:6; ///< 2-7 Reserved, RO + uint32_t GPIORxTxDis:2; ///< 8-9 GPIO RX Disable[9], GPIO TX Disable[8] + uint32_t PMode:3; ///< 10-12 Pad Mode, 0h = GPIO Controller controls the Pad; 1h = Native Function 1, if applicable, controls the pad; 2h = Native Function 2, if applicable, controls the pad, etc. + uint32_t Reserved2:4; ///< 13-16 Reserved, RO + uint32_t GPIRout:4; ///< 17-20 Route to IOxAPIC[20], SCI[19], SMI[18], NMI[17] + uint32_t RXTXEnCfg:2; ///< 21-22 RX/TX Enable Config (RXTXEnCfg) RO + uint32_t RXINV:1; ///< 23 RX Invert, 0 = No inversion; 1 = Inversion + uint32_t PreGfRXSel:1; ///< 24 Pre Glitch Filter Stage RX Pad State Select, RO, not support in BXT + uint32_t RxEvCfg:2; ///< 25-26 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge), 2h = Disabled ,3h = Either rising edge or falling edge + uint32_t Reserved3:1; ///< 27 RO + uint32_t RXRAW1:1; ///< 28 Override the RX to 1 + uint32_t RXPadStSel:1; ///< 29 RX Pad State Select + uint32_t PadRstCfg:2; ///< 30-31 Pad Reset Config + } r; +} BL_CONF_PAD0; + +typedef union { + uint32_t PadCnf1; + struct { + uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO + uint32_t Reserved:1; ///< 7 Reserved. + uint32_t IOSTerm:2; ///< 8-9 I/O Standby Termination (IOSTerm) RW + uint32_t Term:4; ///< 10-13 Termination, + ///< 0 000: none;0 010: 5k wpd;0 100: 20k wpd;1 000: none;1 001: 1k wpu;1 011: 2k wpu;1 010: 5k wpu; + ///< 1 100: 20k wpu;1 101: 1k & 2k wpu;1 111: (optional) Native controller selected by Pad Mode controls the Termination + uint32_t IOSState:4; ///< 14-17 I/O Standby State, I/O Standby is not implemented in BXT, RW + uint32_t CFIOPadCfg:14; ///< 18-31 For BXT, this is done thru Family Register if necessary. RO + } r; +} BL_CONF_PAD1; + +struct BL_GPIO_PAD_INIT { + BL_CONF_PAD0 PadConfg0; + BL_CONF_PAD1 PadConfg1; + uint8_t Community; + uint16_t MmioAddress; + bool HostSw; + bool WakeEnabled; + wchar_t *PadName; +} __attribute__((packed)); + + +/** Fsp M Architectural UPD +**/ +struct FSP_M_ARCH_UPD { + +/** Offset 0x0020 +**/ + uint8_t Revision; + +/** Offset 0x0021 +**/ + uint8_t Reserved[3]; + +/** Offset 0x0024 +**/ + void* NvsBufferPtr; + +/** Offset 0x0028 - StackBase + To hold the stack base. +**/ + void* StackBase; + +/** Offset 0x002C - StackSize + To hold the stack size. +**/ + uint32_t StackSize; + +/** Offset 0x0030 - BootLoaderTolumSize + To pass Bootloader Tolum size. +**/ + uint32_t BootLoaderTolumSize; + +/** Offset 0x0034 - Bootmode + To maintain Bootmode details. +**/ + uint32_t Bootmode; + +/** Offset 0x0038 +**/ + uint8_t ReservedFspmArchUpd[8]; +} __attribute__((packed)); + +/** Fsp M Configuration +**/ +struct FSP_M_CONFIG { + +/** Offset 0x0040 - Debug Serial Port Base + Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. +**/ + uint32_t SerialDebugPortAddress; + +/** Offset 0x0044 - Debug Serial Port Type + 16550 compatible debug serial port resource type. NONE means no serial port support. + 0:NONE, 1:I/O, 2:MMIO +**/ + uint8_t SerialDebugPortType; + +/** Offset 0x0045 - Serial Port Debug Device + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. + 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device +**/ + uint8_t SerialDebugPortDevice; + +/** Offset 0x0046 - Debug Serial Port Stride Size + Debug serial port register map stride size in bytes. + 0:1, 2:4 +**/ + uint8_t SerialDebugPortStrideSize; + +/** Offset 0x0047 - Memory Fast Boot + Enable/Disable MRC fast boot support. + $EN_DIS +**/ + uint8_t MrcFastBoot; + +/** Offset 0x0048 - Integrated Graphics Device + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. + $EN_DIS +**/ + uint8_t Igd; + +/** Offset 0x0049 - DVMT Pre-Allocated + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. + 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, 0x0F:480 MB, 0x10:512 MB +**/ + uint8_t IgdDvmt50PreAlloc; + +/** Offset 0x004A - Aperture Size + Select the Aperture Size used by the Internal Graphics Device. + 0x1:128 MB, 0x2:256 MB, 0x3:512 MB +**/ + uint8_t IgdApertureSize; + +/** Offset 0x004B - GTT Size + Select the GTT Size used by the Internal Graphics Device. + 0x1:2 MB, 0x2:4 MB, 0x3:8 MB +**/ + uint8_t GttSize; + +/** Offset 0x004C - Primary Display + Select which of IGD/PCI Graphics device should be Primary Display. + 0x0:AUTO, 0x2:IGD, 0x3:PCI +**/ + uint8_t PrimaryVideoAdaptor; + +/** Offset 0x004D - Package + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. + 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD +**/ + uint8_t Package; + +/** Offset 0x004E - Profile + Profile list + 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 +**/ + uint8_t Profile; + +/** Offset 0x004F - MemoryDown + Memory Down. + 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 +**/ + uint8_t MemoryDown; + +/** Offset 0x0050 - DDR3LPageSize + NOTE: Only for memory down or downgrade DDR3L frequency. + 0x1:1KB, 0x2:2KB +**/ + uint8_t DDR3LPageSize; + +/** Offset 0x0051 - DDR3LASR + NOTE: Only for memory down. + 0x0:Not Supported, 0x1:Supported +**/ + uint8_t DDR3LASR; + +/** Offset 0x0052 - ScramblerSupport + Scrambler Support. + $EN_DIS +**/ + uint8_t ScramblerSupport; + +/** Offset 0x0053 - ChannelHashMask + Channel Hash Mask. +**/ + uint16_t ChannelHashMask; + +/** Offset 0x0055 - SliceHashMask + Slice Hash Mask. +**/ + uint16_t SliceHashMask; + +/** Offset 0x0057 - InterleavedMode + Interleaved Mode. + $EN_DIS +**/ + uint8_t InterleavedMode; + +/** Offset 0x0058 - ChannelsSlicesEnable + Channels Slices Enable. + $EN_DIS +**/ + uint8_t ChannelsSlicesEnable; + +/** Offset 0x0059 - MinRefRate2xEnable + Provided as a means to defend against Row-Hammer attacks. + $EN_DIS +**/ + uint8_t MinRefRate2xEnable; + +/** Offset 0x005A - DualRankSupportEnable + Dual Rank Support Enable. + $EN_DIS +**/ + uint8_t DualRankSupportEnable; + +/** Offset 0x005B - RmtMode + Rank Margin Tool Mode. + $EN_DIS +**/ + uint8_t RmtMode; + +/** Offset 0x005C - MemorySizeLimit + Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t MemorySizeLimit; + +/** Offset 0x005E - LowMemoryMaxValue + Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t LowMemoryMaxValue; + +/** Offset 0x0060 - DisableFastBoot + 00: Disabled; Used saved training data (if valid)\n01: Enabled; Full re-train of memory. + $EN_DIS +**/ + uint8_t DisableFastBoot; + +/** Offset 0x0061 - HighMemoryMaxValue + High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t HighMemoryMaxValue; + +/** Offset 0x0063 - DIMM0SPDAddress + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM0SPDAddress; + +/** Offset 0x0064 - DIMM1SPDAddress + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM1SPDAddress; + +/** Offset 0x0065 - Ch0_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch0_RankEnable; + +/** Offset 0x0066 - Ch0_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch0_DeviceWidth; + +/** Offset 0x0067 - Ch0_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch0_DramDensity; + +/** Offset 0x0068 - Ch0_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch0_Option; + +/** Offset 0x0069 - Ch0_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch0_OdtConfig; + +/** Offset 0x006A - Ch0_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\n Boolean value. +**/ + uint8_t Ch0_TristateClk1; + +/** Offset 0x006B - Ch0_Mode2N + [0] 2N Mode.\n Boolean value. +**/ + uint8_t Ch0_Mode2N; + +/** Offset 0x006C - Ch0_OdtLevels + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch0_OdtLevels; + +/** Offset 0x006D - Ch1_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch1_RankEnable; + +/** Offset 0x006E - Ch1_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch1_DeviceWidth; + +/** Offset 0x006F - Ch1_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch1_DramDensity; + +/** Offset 0x0070 - Ch1_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch1_Option; + +/** Offset 0x0071 - Ch1_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch1_OdtConfig; + +/** Offset 0x0072 - Ch1_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. +**/ + uint8_t Ch1_TristateClk1; + +/** Offset 0x0073 - Ch1_Mode2N + [0] 2N Mode.\nBoolean value. +**/ + uint8_t Ch1_Mode2N; + +/** Offset 0x0074 - Ch1_OdtLevels + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t Ch1_OdtLevels; + +/** Offset 0x0075 - Ch2_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch2_RankEnable; + +/** Offset 0x0076 - Ch2_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch2_DeviceWidth; + +/** Offset 0x0077 - Ch2_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch2_DramDensity; + +/** Offset 0x0078 - Ch2_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch2_Option; + +/** Offset 0x0079 - Ch2_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch2_OdtConfig; + +/** Offset 0x007A - Ch2_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. +**/ + uint8_t Ch2_TristateClk1; + +/** Offset 0x007B - Ch2_Mode2N + [0] 2N Mode.\nBoolean value. +**/ + uint8_t Ch2_Mode2N; + +/** Offset 0x007C - Ch2_OdtLevels + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t Ch2_OdtLevels; + +/** Offset 0x007D - Ch3_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch3_RankEnable; + +/** Offset 0x007E - Ch3_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch3_DeviceWidth; + +/** Offset 0x007F - Ch3_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch3_DramDensity; + +/** Offset 0x0080 - Ch3_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch3_Option; + +/** Offset 0x0081 - Ch3_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch3_OdtConfig; + +/** Offset 0x0082 - Ch3_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. +**/ + uint8_t Ch3_TristateClk1; + +/** Offset 0x0083 - Ch3_Mode2N + [0] 2N Mode.\nBoolean value. +**/ + uint8_t Ch3_Mode2N; + +/** Offset 0x0084 - Ch3_OdtLevels + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t Ch3_OdtLevels; + +/** Offset 0x0085 - RmtCheckRun + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t RmtCheckRun; + +/** Offset 0x0086 - Ch0_Bit_swizzling + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch0_Bit_swizzling[32]; + +/** Offset 0x00A6 - Ch1_Bit_swizzling + Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch1_Bit_swizzling[32]; + +/** Offset 0x00C6 - Ch2_Bit_swizzling + Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch2_Bit_swizzling[32]; + +/** Offset 0x00E6 - Ch3_Bit_swizzling + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch3_Bit_swizzling[32]; + +/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint16_t RmtMarginCheckScaleHighThreshold; + +/** Offset 0x0108 - MsgLevelMask + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint32_t MsgLevelMask; + +/** Offset 0x010C - FIT Table Pointer + FIT table pointer. +**/ + uint32_t FitTablePtr; + +/** Offset 0x0110 - GPIO Table Pointer + GPIO table pointer to a BL_GPIO_PAD_INIT structure. +**/ + struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; + +/** Offset 0x0114 +**/ + uint8_t ReservedFspmUpd[60]; +} __attribute__((packed)); + +/** Fsp M Test Configuration +**/ +struct FSP_M_TEST_CONFIG { + +/** Offset 0x0150 +**/ + uint32_t Signature; + +/** Offset 0x0154 +**/ + uint8_t ReservedFspmTestUpd[28]; +} __attribute__((packed)); + +/** Fsp M Restricted Configuration +**/ +struct FSP_M_RESTRICTED_CONFIG { + +/** Offset 0x0170 +**/ + uint32_t Signature; + +/** Offset 0x0174 +**/ + uint8_t ReservedFspmRestrictedUpd[138]; +} __attribute__((packed)); + +#define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ + +struct FSPM_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSP_M_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + struct FSP_M_CONFIG FspmConfig; + +/** Offset 0x0150 +**/ + struct FSP_M_TEST_CONFIG FspmTestConfig; + +/** Offset 0x0170 +**/ + struct FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; + +/** Offset 0x01FE +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/apollolake/include/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/fsp/FspsUpd.h new file mode 100644 index 0000000..f2f867b --- /dev/null +++ b/src/soc/intel/apollolake/include/fsp/FspsUpd.h @@ -0,0 +1,565 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include "FspUpd.h" + + +/** Fsp S Configuration +**/ +struct FSP_S_CONFIG { + +/** Offset 0x0020 - ActiveProcessorCores + Number of active cores. +**/ + uint8_t ActiveProcessorCores; + +/** Offset 0x0021 - Disable Core1 + Disable/Enable Core1. + $EN_DIS +**/ + uint8_t DisableCore1; + +/** Offset 0x0022 - Disable Core2 + Disable/Enable Core2. + $EN_DIS +**/ + uint8_t DisableCore2; + +/** Offset 0x0023 - Disable Core3 + Disable/Enable Core3. + $EN_DIS +**/ + uint8_t DisableCore3; + +/** Offset 0x0024 - VMX Enable + Enable or Disable VMX. + $EN_DIS +**/ + uint8_t VmxEnable; + +/** Offset 0x0025 - Memory region allocation for Processor Trace + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); 0xFF: Disable. +**/ + uint8_t ProcTraceMemSize; + +/** Offset 0x0026 - Enable Processor Trace + Enable or Disable Processor Trace feature. + $EN_DIS +**/ + uint8_t ProcTraceEnable; + +/** Offset 0x0027 - Eist + Enable or Disable Intel SpeedStep Technology. + $EN_DIS +**/ + uint8_t Eist; + +/** Offset 0x0028 - Boot PState + Boot PState with HFM or LFM. 0: HFM; 1: LFM. +**/ + uint8_t BootPState; + +/** Offset 0x0029 - CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t EnableCx; + +/** Offset 0x002A - Enhanced C-states + Enable or Disable Enhanced C-states. 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t C1e; + +/** Offset 0x002B - Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t BiProcHot; + +/** Offset 0x002C - Max Pkg Cstate + Max Pkg Cstate. 0:PkgC0C1; 1:PkgC2; 2:PkgC3; 3:PkgC6; 4:PkgC7; 5:PkgC7s; 6:PkgC8; 7:PkgC9; 8:PkgC10; 9:PkgCMax; 254:PkgCpuDefault; 255:PkgAuto. +**/ + uint8_t PkgCStateLimit; + +/** Offset 0x002D +**/ + uint8_t UnusedUpdSpace0; + +/** Offset 0x002E - C-State auto-demotion + C-State Auto Demotion. 0:Disable C1 and C3 Auto-demotion; 1:Enable C3/C6/C7 Auto-demotion to C1; 2:Enable C6/C7 Auto-demotion to C3; 3:Enable C6/C7 Auto-demotion to C1 and C3. +**/ + uint8_t CStateAutoDemotion; + +/** Offset 0x002F - C-State un-demotion + C-State un-demotion. 0:Disable C1 and C3 Un-demotion; 1:Enable C1 Un-demotion; 2:Enable C3 Un-demotion; 3:Enable C1 and C3 Un-demotion. +**/ + uint8_t CStateUnDemotion; + +/** Offset 0x0030 - Max Core C-State + Max Core C-State. 0:Unlimited;1:C1;2:C3;3:C6;4:C7;5:C8;6:C9;7:C10;8:CCx. +**/ + uint8_t MaxCoreCState; + +/** Offset 0x0031 - Package C-State Demotion + Enable or Disable Package Cstate Demotion. 0:Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PkgCStateDemotion; + +/** Offset 0x0032 - Package C-State Un-demotion + Enable or Disable Package Cstate UnDemotion. 0:Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PkgCStateUnDemotion; + +/** Offset 0x0033 - Turbo Mode + Enable or Disable long duration Turbo Mode. 0:Disable; 1: Enable. + $EN_DIS +**/ + uint8_t TurboMode; + +/** Offset 0x0034 +**/ + uint8_t UnusedUpdSpace1[12]; + +/** Offset 0x0040 - HD-Audio I/O Buffer Ownership + Set HD-Audio I/O Buffer Ownership. + 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers +**/ + uint8_t HdAudioIoBufferOwnership; + +/** Offset 0x0041 +**/ + uint8_t UnusedUpdSpace2[5]; + +/** Offset 0x0046 - Enable SD controller + Enable/disable SD Card controller. + $EN_DIS +**/ + uint8_t SdcardEnabled; + +/** Offset 0x0047 - Enable SDIO controller + Enable/disable SDIO controller. + $EN_DIS +**/ + uint8_t SdioEnabled; + +/** Offset 0x0048 - Enable eMMC controller + Enable/disable eMMC controller. + $EN_DIS +**/ + uint8_t eMMCEnabled; + +/** Offset 0x0049 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + uint8_t EnableSata; + +/** Offset 0x004A - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + uint8_t SataMode; + +/** Offset 0x004B - Aggressive SATA LPM Support + Enable SOC to aggressively enter link power state for SATA. + $EN_DIS +**/ + uint8_t SataSalpSupport; + +/** Offset 0x004C - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsEnable[2]; + +/** Offset 0x004E - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsDevSlp[2]; + +/** Offset 0x0050 - Enable PCIE RP + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRootPortEn[6]; + +/** Offset 0x0056 - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRpClkReqNumber[6]; + +/** Offset 0x005C +**/ + uint8_t UnusedUpdSpace3[16]; + +/** Offset 0x006C - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb20Enable[8]; + +/** Offset 0x0074 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb30Enable[6]; + +/** Offset 0x007A - Enable XHCI SSIC ports + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. +**/ + uint8_t SsicPortEnable[2]; + +/** Offset 0x007C - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + uint8_t SmbusEnable; + +/** Offset 0x007D - SC HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + uint8_t HdaVerbTableEntryNum; + +/** Offset 0x007E - SC HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + uint32_t HdaVerbTablePtr; + +/** Offset 0x0082 +**/ + uint8_t UnusedUpdSpace4[14]; + +/** Offset 0x0090 - Enable/Disable P2SB device hidden. + Enable/Disable P2SB device hidden. + $EN_DIS +**/ + uint8_t HideP2sb; + +/** Offset 0x0091 - Ufs Enable/Disable + Enable/Disable Ufs. + $EN_DIS +**/ + uint8_t UfsEnabled; + +/** Offset 0x0092 - IPU Enable/Disable + Enable/Disable IPU Device. + $EN_DIS +**/ + uint8_t IpuEn; + +/** Offset 0x0093 - IMGU ACPI mode selection + 0=Auto, 1(Default)=IGFX Child device, 2=ACPI device + 0:Disable, 1:IGFX Child device, 2:ACPI device +**/ + uint8_t IpuAcpiMode; + +/** Offset 0x0094 - ResetSelect + ResetSelect. 0x6:warm reset; 0xE:cold reset +**/ + uint8_t ResetSelect; + +/** Offset 0x0095 - CRIDSettings + PMC CRID setting. 0:Disable;1:CRID_1;2:CRID_2;3:CRID_3 +**/ + uint8_t CRIDSettings; + +/** Offset 0x0096 - Enable HPET + Enable/disable HPET. + $EN_DIS +**/ + uint8_t Hpet; + +/** Offset 0x0097 - Enable PCIE Clock Gating + Enable/disable PCIE Clock Gating.0:Enable;1:Disable + $EN_DIS +**/ + uint8_t PcieClockGatingDisabled; + +/** Offset 0x0098 - Enable PCIE Root Port 8xh Decode + Enable/disable PCIE Root Port 8xh Decode.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PcieRootPort8xhDecode; + +/** Offset 0x0099 - PCIE 8xh Decode Port Index + PCIE 8xh Decode Port Index. +**/ + uint8_t Pcie8xhDecodePortIndex; + +/** Offset 0x009A - Enable PCIE Root Port Peer Memory Write + Enable/disable PCIE root port peer memory write.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PcieRootPortPeerMemoryWriteEnable; + +/** Offset 0x009B - Enable SC Gaussian Mixture Models + Enable/disable SC Gaussian Mixture Models.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t Gmm; + +/** Offset 0x009C - GttMmAdr + GttMmAdr structure for initialization. +**/ + uint32_t GttMmAdr; + +/** Offset 0x00A0 +**/ + uint8_t UnusedUpdSpace5[96]; + +/** Offset 0x0100 - Enable S0ix + Enable/disable S0ix.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t S0ix; + +/** Offset 0x0101 - GmAdr + GmAdr structure for initialization. +**/ + uint32_t GmAdr; + +/** Offset 0x0105 - Enable ForceWake + Enable/disable ForceWake Models.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t ForceWake; + +/** Offset 0x0106 - Enable PavpLock + Enable/disable PavpLock.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PavpLock; + +/** Offset 0x0107 - Enable GraphicsFreqModify + Enable/disable GraphicsFreqModify.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t GraphicsFreqModify; + +/** Offset 0x0108 - Enable GraphicsFreqReq + Enable/disable GraphicsFreqReq.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t GraphicsFreqReq; + +/** Offset 0x0109 - Enable GraphicsVideoFreq + Enable/disable GraphicsVideoFreq.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t GraphicsVideoFreq; + +/** Offset 0x010A - Enable PmLock + Enable/disable PmLock.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PmLock; + +/** Offset 0x010B +**/ + uint8_t UnusedUpdSpace6[5]; + +/** Offset 0x0110 - Enable DopClockGating + Enable/disable DopClockGating.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t DopClockGating; + +/** Offset 0x0111 - Enable UnsolicitedAttackOverride + Enable/disable UnsolicitedAttackOverride.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t UnsolicitedAttackOverride; + +/** Offset 0x0112 - Enable WOPCMSupport + Enable/disable WOPCMSupport.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t WOPCMSupport; + +/** Offset 0x0113 - Enable WOPCMSize + Enable/disable WOPCMSize.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t WOPCMSize; + +/** Offset 0x0114 - Enable PowerGating + Enable/disable PowerGating.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PowerGating; + +/** Offset 0x0115 - Enable UnitLevelClockGating + Enable/disable UnitLevelClockGating.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t UnitLevelClockGating; + +/** Offset 0x0116 - Enable FastBoot + Enable/disable FastBoot.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t FastBoot; + +/** Offset 0x0117 - Enable DynSR + Enable/disable DynSR.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t DynSR; + +/** Offset 0x0118 - Enable SaIpuEnable + Enable/disable SaIpuEnable.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t SaIpuEnable; + +/** Offset 0x0119 - Enable VtdEnable + Enable/disable VtdEnable.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t VtdEnable; + +/** Offset 0x011A - BMP Logo Data Size + BMP logo data buffer size. +**/ + uint32_t LogoSize; + +/** Offset 0x011E - BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. +**/ + uint32_t LogoPtr; + +/** Offset 0x0122 - Graphics Configuration Data Pointer + Graphics configuration data used for initialization. +**/ + uint32_t GraphicsConfigPtr; + +/** Offset 0x0126 - GT PM Support + Enable/Disable GT power management support. + $EN_DIS +**/ + uint8_t PmSupport; + +/** Offset 0x0127 - RC6(Render Standby) + Enable/Disable render standby support. + $EN_DIS +**/ + uint8_t EnableRenderStandby; + +/** Offset 0x0128 - PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). + $EN_DIS +**/ + uint8_t PavpEnable; + +/** Offset 0x0129 - PAVP PR3 + Enable/Disable PAVP PR3 + $EN_DIS +**/ + uint8_t PavpPr3; + +/** Offset 0x012A - CdClock Frequency selection + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4(Default): 624 MHz + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +**/ + uint8_t CdClock; + +/** Offset 0x012B - Enable/Disable PeiGraphicsPeimInit + Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit + $EN_DIS +**/ + uint8_t PeiGraphicsPeimInit; + +/** Offset 0x012C - Enable/Disable Timer 8254 Clock Setting + Enable/Disable Timer 8254 Clock + $EN_DIS +**/ + uint8_t Timer8254ClkSetting; + +/** Offset 0x012D +**/ + uint8_t ReservedFspsUpd[211]; +} __attribute__((packed)); + +/** Fsp S Test Configuration +**/ +struct FSP_S_TEST_CONFIG { + +/** Offset 0x0200 +**/ + uint32_t Signature; + +/** Offset 0x0204 +**/ + uint8_t ReservedFspsTestUpd[12]; +} __attribute__((packed)); + +/** Fsp S Restricted Configuration +**/ +struct FSP_S_RESTRICTED_CONFIG { + +/** Offset 0x0210 +**/ + uint32_t Signature; + +/** Offset 0x0214 +**/ + uint8_t ReservedFspsRestrictedUpd[12]; +} __attribute__((packed)); + +#define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ + +struct FSPS_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSP_S_CONFIG FspsConfig; + +/** Offset 0x0200 +**/ + struct FSP_S_TEST_CONFIG FspsTestConfig; + +/** Offset 0x0210 +**/ + struct FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; + +/** Offset 0x0220 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h new file mode 100644 index 0000000..d12eb19 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_IOMAP_H_ +#define _SOC_APOLLOLAKE_IOMAP_H_ + +#define P2SB_BAR 0xd0000000 +#define MCH_BASE_ADDR 0xfed10000 +#define MCH_BASE_SIZE (32 * KiB) + +#define ACPI_PMIO_BASE 0x400 +#define R_ACPI_PM1_TMR 0x8 + +/* Accesses to these BARs are hardcoded in FSP */ +#define PMC_BAR0 0xfe042000 +#define PMC_BAR1 0xfe044000 + +#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h new file mode 100644 index 0000000..1ab9ffd --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ROMSTAGE_H_ +#define _SOC_APOLLOLAKE_ROMSTAGE_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +asmlinkage void romstage_entry(void); +void mainboard_memory_init_params(struct FSPM_UPD *memupd); + +#endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/romstage/entry.inc b/src/soc/intel/apollolake/romstage/entry.inc new file mode 100644 index 0000000..8855948 --- /dev/null +++ b/src/soc/intel/apollolake/romstage/entry.inc @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +apollolake_entry: + + /* reset stack pointer to CAR stack */ + mov $_car_stack_end, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + call romstage_entry diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c new file mode 100644 index 0000000..87b41fd --- /dev/null +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/early_variables.h> +#include <arch/io.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <fsp/FspmUpd.h> +#include <fsp/util.h> +#include <device/resource.h> +#include <string.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/northbridge.h> +#include <soc/romstage.h> +#include <soc/uart.h> + +/* + * Enables several BARs and devices which are needed for memory init + * - MCH_BASE_ADDR is needed in order to talk to the memory controller + * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded) + * Once raminit is done, we can safely let the allocator re-assign them + * - HPET is enabled because FSP wants to store a pointer to global data in the + * HPET comparator register + */ +static void soc_early_romstage_init(void) +{ + device_t pmc = PMC_DEV; + + /* Set MCH base address and enable bit */ + pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); + + /* Set PMC base address */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); + pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ + + /* PMIO BAR4 was already set earlier, hence the COMMAND_IO below */ + pci_write_config32(pmc, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + + /* Enable decoding for HPET. Needed for FSP global pointer storage */ + pci_write_config32(P2SB_DEV, 0x60, 1<<7); +} + +static void disable_watchdog(void) +{ + uint32_t reg; + device_t dev = PMC_DEV; + + /* Open up an IO window */ + pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + /* We don't have documentation for this bit, but it prevents reboots */ + reg = inl(ACPI_PMIO_BASE + 0x68); + reg |= 1 << 11; + outl(reg, ACPI_PMIO_BASE + 0x68); +} + + +asmlinkage void romstage_entry(void) +{ + void *hob_list_ptr; + struct resource fsp_mem; + struct range_entry reg_car; + + /* Be careful. Bootblock might already have initialized the console */ + if (!IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + lpss_console_uart_init(); + console_init(); + } + + printk(BIOS_DEBUG, "Starting romstage...\n"); + + disable_watchdog(); + + soc_early_romstage_init(); + + /* We will load FSP blob into CAR, but only in the free region */ + reg_car.begin = (uint32_t) _car_data_end; + reg_car.end = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE ; + + if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) { + die("FSP memory init failed. Giving up."); + } + + fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); + + /* initialize cbmem by adding FSP reserved memory first thing */ + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_mem.size); + + /* make sure FSP memory is reserved in cbmem */ + if (fsp_mem.base != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) + die("Failed to accommodate FSP reserved memory request"); + + /* Now that CBMEM is up, save the list so ramstage can use it */ + fsp_save_hob_list(hob_list_ptr); + + run_ramstage(); +} + +static void fill_console_params(struct FSPM_UPD *memupd) +{ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + memupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; + memupd->FspmConfig.SerialDebugPortType = 2; + memupd->FspmConfig.SerialDebugPortStrideSize = 2; + memupd->FspmConfig.SerialDebugPortAddress = 0; + } else { + memupd->FspmConfig.SerialDebugPortType = 0; + } +} + +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *memupd) +{ + fill_console_params(memupd); + mainboard_memory_init_params(memupd); + + /* Do NOT let FSP do any GPIO pad configuration */ + memupd->FspmConfig.GpioPadInitTablePtr = NULL; + /* This is somewhere in SRAM */ + memupd->FspmConfig.FitTablePtr = read32(&fit_pointer); + /* Reserve enough memory under TOLUD to save CBMEM header */ + memupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); + /* + /* It has nothing to with our stack size. We just ask FSP not to + /* tromp over our car data. + */ + memupd->FspmArchUpd.StackBase = (void *) CONFIG_DCACHE_RAM_BASE; + memupd->FspmArchUpd.StackSize = _car_data_end - _car_data_start; +} + +__attribute__ ((weak)) +void mainboard_memory_init_params(struct FSPM_UPD *memupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +}

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Patch set updated for coreboot: soc/intel/apollolake: Enable using FSP 2.0 driver
by Andrey Petrov 26 Feb '16

26 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13806 -gerrit commit 4bf764b46eba7273bb04143ff3ec098edc324bd7 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 18:39:38 2016 -0800 soc/intel/apollolake: Enable using FSP 2.0 driver Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 1633dbe..4a23d79 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select NO_UART_ON_SUPERIO select DRIVERS_UART_8250MEM_32 + select PLATFORM_USES_FSP2_0 config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address"

1 0

Patch set updated for coreboot: FSP2.0: Add coreboot<->FSP header files
by Andrey Petrov 26 Feb '16

26 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13796 -gerrit commit 741d430138337eb5936d213dc0f13fad83f87d58 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:13:12 2016 -0800 FSP2.0: Add coreboot<->FSP header files This adds important header files that specify calling interface between coreboot and FSP. Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/Kconfig | 1 + src/drivers/intel/Makefile.inc | 1 + src/drivers/intel/fsp2_0/Kconfig | 42 +++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 11 +++ src/drivers/intel/fsp2_0/include/fsp/api.h | 101 +++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/info_header.h | 45 +++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 42 +++++++++ 7 files changed, 243 insertions(+) diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig index 19986f4..e5525d8 100644 --- a/src/drivers/intel/Kconfig +++ b/src/drivers/intel/Kconfig @@ -14,5 +14,6 @@ ## source src/drivers/intel/fsp1_1/Kconfig +source src/drivers/intel/fsp2_0/Kconfig source src/drivers/intel/gma/Kconfig source src/drivers/intel/i210/Kconfig diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index e54f07b..67c1163 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -2,4 +2,5 @@ subdirs-y += gma subdirs-$(CONFIG_GENERATE_SMBIOS_TABLES) += wifi subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0 subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1 +subdirs-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0 subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig new file mode 100644 index 0000000..a05d8de --- /dev/null +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -0,0 +1,42 @@ +config PLATFORM_USES_FSP2_0 + bool + help + Include FSP 2.0 wrappers and functionality + +if PLATFORM_USES_FSP2_0 + +comment "Intel FSP 2.0" + +config ADD_FSP_BINARIES + bool "Add Intel FSP 2.0 binaries to CBFS" + help + Add the FSP-M and FSP-S binaries to CBFS. Note that coreboot does not + use the FSP-T binary, so that will not be included. + +config FSP_M_FILE + string "Intel FSP-M (memory init) binary path and filename" + depends on ADD_FSP_BINARIES + help + The path and filename of the Intel FSP-M binary for this platform. + +config FSP_S_FILE + string "Intel FSP-S (silicon init) binary path and filename" + depends on ADD_FSP_BINARIES + help + The path and filename of the Intel FSP-S binary for this platform. + + +config ADD_VBT_DATA_FILE + bool "Add a Video Bios Table (VBT) binary to CBFS" + help + Add a VBT file data file to CBFS. The VBT describes the integrated + GPU and connections, and is needed by FSP in order to initialize the + display. + +config VBT_FILE + string "VBT binary path and filename" + depends on ADD_VBT_DATA_FILE + help + The path and filename of the VBT binary for this platform. + +endif # PLATFORM_USES_FSP2_0 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc new file mode 100644 index 0000000..61faefa --- /dev/null +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -0,0 +1,11 @@ +romstage-y += hand_off_block.c +romstage-y += util.c +romstage-y += memory_init.c + +ramstage-y += graphics.c +ramstage-y += hand_off_block.c +ramstage-y += notify.c +ramstage-y += silicon_init.c +ramstage-y += util.c + +CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h new file mode 100644 index 0000000..aae17e8 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_API_H_ +#define _FSP2_0_API_H_ + +#include <stddef.h> +#include <memrange.h> + +enum fsp_status { + FSP_SUCCESS = 0x00000000, + FSP_INVALID_PARAMETER = 0x80000002, + FSP_UNSUPPORTED = 0x80000003, + FSP_NOT_READY = 0x80000006, + FSP_DEVICE_ERROR = 0x80000007, + FSP_OUT_OF_RESOURCES = 0x80000009, + FSP_VOLUME_CORRUPTED = 0x8000000a, + FSP_NOT_FOUND = 0x8000000a, + FSP_TIMEOUT = 0x80000012, + FSP_ABORTED = 0x80000015, + FSP_INCOMPATIBLE_VERSION = 0x80000010, + FSP_SECURITY_VIOLATION = 0x8000001a, + FSP_CRC_ERROR = 0x8000001b, +}; + +enum fsp_notify_phase { + AFTER_PCI_ENUM = 0x20, + READY_TO_BOOT = 0x40 +}; + + +/* Opaque structures. These are platform-specific. */ +struct FSPM_UPD; +struct FSPS_UPD; + +/* Main FSP stages */ +enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r); +enum fsp_status fsp_silicon_init(struct range_entry *r); +enum fsp_status fsp_notify(enum fsp_notify_phase phase); + +/* Callbacks for updating stage-specific parameters */ +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *memupd); +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd); + +/* + * # DOCUMENTATION: + * + * This file defines the interface between coreboot and the FSP 2.0 wrapper + * fsp_memory_init(), fsp_silicon_init(), and fsp_notify() are the main entry + * points and map 1:1 to the FSP entry points of the same name. + * + * ### fsp_memory_init(): + * - hob_list: retuns a pointer to the HOB storage area created by FSP + * - r: memory range that the binary is allowed to be loaded into + * + * This function is responsible for loading and executing the memory + * initialization code from the FSP-M binary. It expects this binary to reside + * in cbfs as FSP_M_FILE. + * + * The function takes one parameter, which is described below, but does not + * take in memory parameters as an argument. The memory parameters can be filled + * in with platform_fsp_memory_init_params_cb(). This is a callback symbol + * that fsp_memory_init() will call. The platform must provide this symbol. + * + * FSP returns information about the memory layout in a series of structures + * called hand-off-blocks (HOB). The "hob_list" output parameter will point to + * the start of the HOB list. The fsp reserved region will also be described by + * one of the HOBs. For more information on parsing these structures, see + * fsp/util.h + * + * + * ### fsp_silicon_init(): + * - r: memory range that the binary is allowed to be loaded into + * + * This function is responsible for loading and executing the silicon + * initialization code from the FSP-S binary. It expects this binary to reside + * in cbfs as FSP_S_FILE. + * + * Like fsp_memory_init(), it provides a callback to fill in FSP-specific + * parameters, via platform_fsp_silicon_init_params_cb(). The platform must + * also provide this symbol. + * + * + * ### fsp_notify(): + * - phase: Which FSP notification phase + * + * This function is responsible for loading and executing the notify code from + * the FSP-S binary. It expects that fsp_silicon_init() has already been called + * succesfully, and that the FSP-S binary is still loaded into memory. + */ + +#endif /* _FSP2_0_API_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h new file mode 100644 index 0000000..a6cc49f --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_INFO_HEADER_H_ +#define _FSP2_0_INFO_HEADER_H_ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#define FSP_HDR_OFFSET 0x94 +#define FSP_HDR_LEN 0x48 +#define FSP_HDR_SIGNATURE "FSPH" +#define FSP_HDR_ATTRIB_FSPT (0b0001 << 28) +#define FSP_HDR_ATTRIB_FSPM (0b0010 << 28) +#define FSP_HDR_ATTRIB_FSPS (0b0011 << 28) + +struct fsp_header { + uint32_t fsp_revision; + size_t image_size; + uintptr_t image_base; + uint32_t image_attribute; + size_t cfg_region_offset; + size_t cfg_region_size; + size_t notify_phase_entry_offset; + size_t memory_init_entry_offset; + size_t silicon_init_entry_offset; + char image_id[sizeof(uint64_t) + 1]; + uint8_t revision; +}; + +enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); +void fsp_print_header_info(const struct fsp_header *hdr); +void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob); + +#endif /* _FSP2_0_INFO_HEADER_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h new file mode 100644 index 0000000..69e545e --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_UTIL_H_ +#define _FSP2_0_UTIL_H_ + +#include <boot/coreboot_tables.h> +#include <fsp/info_header.h> +#include <device/resource.h> +#include <memrange.h> + +/* + * Hand-off-block handling functions that depend on CBMEM, and thus can only + * be used after cbmem_initialize(). + */ +void fsp_save_hob_list(void *hob_list_ptr); +const void *fsp_get_hob_list(void); +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size); +enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +/* + * Hand-off-block utilities which do not depend on CBMEM, but need to be passed + * the HOB list explicitly. + */ +void fsp_find_reserved_memory(struct resource *res, const void *hob_list); +void fsp_print_memory_resource_hobs(const void *hob_list); + +/* Load an FSP binary into CBFS, and fill the associated fsp_header struct */ +enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name, + struct range_entry *r); +/* Load a vbt.bin file for graphics. Returns 0 if a valid VBT is not found. */ +uintptr_t fsp_load_vbt(void); + +#endif /* _FSP2_0_UTIL_H_ */

1 0

New patch to review for coreboot: soc/intel/apollolake: Enable using FSP 2.0 driver
by Andrey Petrov 26 Feb '16

26 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13806 -gerrit commit de724b5be3f3483226e532406089b88c1d1fce88 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 18:39:38 2016 -0800 soc/intel/apollolake: Enable using FSP 2.0 driver Change-Id: I5d50fecca51e89aed597e1cfafbcd4515d4d4388 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 401535f..6d5bc59 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -39,6 +39,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select NO_UART_ON_SUPERIO select DRIVERS_UART_8250MEM_32 + select PLATFORM_USES_FSP2_0 config MMCONF_BASE_ADDRESS hex "PCI MMIO Base Address"

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add romstage that calls FSP2.0 driver
by Andrey Petrov 26 Feb '16

26 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13805 -gerrit commit 7ed9d2e489f72dd7a731bc2cfb486a0cd4c90111 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 17:42:25 2016 -0800 soc/intel/apollolake: Add romstage that calls FSP2.0 driver This romstage is minimalistic. Its goal is to set up some BARs that FSP expects to be set and then invoke FSP driver to train memory. Change-Id: I3fa56aafe99cf6cf062a46dece3a0febeafdbfad Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 2 + src/soc/intel/apollolake/include/fsp/FspUpd.h | 37 ++ src/soc/intel/apollolake/include/fsp/FspmUpd.h | 569 ++++++++++++++++++++++++ src/soc/intel/apollolake/include/fsp/FspsUpd.h | 565 +++++++++++++++++++++++ src/soc/intel/apollolake/include/soc/iomap.h | 27 ++ src/soc/intel/apollolake/include/soc/romstage.h | 22 + src/soc/intel/apollolake/romstage/entry.inc | 26 ++ src/soc/intel/apollolake/romstage/romstage.c | 154 +++++++ 8 files changed, 1402 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 17ddaec..a0a102a 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -16,7 +16,9 @@ bootblock-y += placeholders.c bootblock-y += tsc_freq.c bootblock-y += uart_early.c +cpu_incs-y += $(src)/soc/intel/apollolake/romstage/entry.inc romstage-y += placeholders.c +romstage-y += romstage/romstage.c romstage-y += gpio.c romstage-y += mmap_boot.c romstage-y += uart_early.c diff --git a/src/soc/intel/apollolake/include/fsp/FspUpd.h b/src/soc/intel/apollolake/include/fsp/FspUpd.h new file mode 100644 index 0000000..da3486d --- /dev/null +++ b/src/soc/intel/apollolake/include/fsp/FspUpd.h @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP_API_H_ +#define _FSP_API_H_ + +/** FSP UPD Header +**/ +struct FSP_UPD_HEADER { + +/** Offset 0x00 to 0x07 - UPD Region Signature + The signature will be + "FSPT_UPD" for FSP-T + "FSPM_UPD" for FSP-M + "FSPS_UPD" for FSP-S +**/ + uint64_t Signature; + +/** Offset 0x08 - Revision +**/ + uint8_t Revision; + +/** Offset 0x09 to 0x1F - ReservedUpd +**/ + uint8_t ReservedUpd[23]; +} __attribute__((packed)); + +#endif /* _FSP_API_H_ */ diff --git a/src/soc/intel/apollolake/include/fsp/FspmUpd.h b/src/soc/intel/apollolake/include/fsp/FspmUpd.h new file mode 100644 index 0000000..c7b2607 --- /dev/null +++ b/src/soc/intel/apollolake/include/fsp/FspmUpd.h @@ -0,0 +1,569 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPMUPD_H__ +#define __FSPMUPD_H__ + +#include "FspUpd.h" + + +typedef union { + uint32_t PadCnf0; + struct { + uint32_t GPIOTxState:1; ///< 0 GPIO TX State + uint32_t GPIORxState:1; ///< 1 GPIO RX State, RO + uint32_t Reserved1:6; ///< 2-7 Reserved, RO + uint32_t GPIORxTxDis:2; ///< 8-9 GPIO RX Disable[9], GPIO TX Disable[8] + uint32_t PMode:3; ///< 10-12 Pad Mode, 0h = GPIO Controller controls the Pad; 1h = Native Function 1, if applicable, controls the pad; 2h = Native Function 2, if applicable, controls the pad, etc. + uint32_t Reserved2:4; ///< 13-16 Reserved, RO + uint32_t GPIRout:4; ///< 17-20 Route to IOxAPIC[20], SCI[19], SMI[18], NMI[17] + uint32_t RXTXEnCfg:2; ///< 21-22 RX/TX Enable Config (RXTXEnCfg) RO + uint32_t RXINV:1; ///< 23 RX Invert, 0 = No inversion; 1 = Inversion + uint32_t PreGfRXSel:1; ///< 24 Pre Glitch Filter Stage RX Pad State Select, RO, not support in BXT + uint32_t RxEvCfg:2; ///< 25-26 0h = Level 1h = Edge (RxInv=0 for rising edge; 1 for falling edge), 2h = Disabled ,3h = Either rising edge or falling edge + uint32_t Reserved3:1; ///< 27 RO + uint32_t RXRAW1:1; ///< 28 Override the RX to 1 + uint32_t RXPadStSel:1; ///< 29 RX Pad State Select + uint32_t PadRstCfg:2; ///< 30-31 Pad Reset Config + } r; +} BL_CONF_PAD0; + +typedef union { + uint32_t PadCnf1; + struct { + uint32_t IntSel:7; ///< 0-6 Interrupt Select. RO + uint32_t Reserved:1; ///< 7 Reserved. + uint32_t IOSTerm:2; ///< 8-9 I/O Standby Termination (IOSTerm) RW + uint32_t Term:4; ///< 10-13 Termination, + ///< 0 000: none;0 010: 5k wpd;0 100: 20k wpd;1 000: none;1 001: 1k wpu;1 011: 2k wpu;1 010: 5k wpu; + ///< 1 100: 20k wpu;1 101: 1k & 2k wpu;1 111: (optional) Native controller selected by Pad Mode controls the Termination + uint32_t IOSState:4; ///< 14-17 I/O Standby State, I/O Standby is not implemented in BXT, RW + uint32_t CFIOPadCfg:14; ///< 18-31 For BXT, this is done thru Family Register if necessary. RO + } r; +} BL_CONF_PAD1; + +struct BL_GPIO_PAD_INIT { + BL_CONF_PAD0 PadConfg0; + BL_CONF_PAD1 PadConfg1; + uint8_t Community; + uint16_t MmioAddress; + bool HostSw; + bool WakeEnabled; + wchar_t *PadName; +} __attribute__((packed)); + + +/** Fsp M Architectural UPD +**/ +struct FSP_M_ARCH_UPD { + +/** Offset 0x0020 +**/ + uint8_t Revision; + +/** Offset 0x0021 +**/ + uint8_t Reserved[3]; + +/** Offset 0x0024 +**/ + void* NvsBufferPtr; + +/** Offset 0x0028 - StackBase + To hold the stack base. +**/ + void* StackBase; + +/** Offset 0x002C - StackSize + To hold the stack size. +**/ + uint32_t StackSize; + +/** Offset 0x0030 - BootLoaderTolumSize + To pass Bootloader Tolum size. +**/ + uint32_t BootLoaderTolumSize; + +/** Offset 0x0034 - Bootmode + To maintain Bootmode details. +**/ + uint32_t Bootmode; + +/** Offset 0x0038 +**/ + uint8_t ReservedFspmArchUpd[8]; +} __attribute__((packed)); + +/** Fsp M Configuration +**/ +struct FSP_M_CONFIG { + +/** Offset 0x0040 - Debug Serial Port Base + Debug serial port base address. This option will be used only when the 'Serial Port Debug Device' option is set to 'External Device'. +**/ + uint32_t SerialDebugPortAddress; + +/** Offset 0x0044 - Debug Serial Port Type + 16550 compatible debug serial port resource type. NONE means no serial port support. + 0:NONE, 1:I/O, 2:MMIO +**/ + uint8_t SerialDebugPortType; + +/** Offset 0x0045 - Serial Port Debug Device + Select active serial port device for debug. For SOC UART devices,'Debug Serial Port Base' options will be ignored. + 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device +**/ + uint8_t SerialDebugPortDevice; + +/** Offset 0x0046 - Debug Serial Port Stride Size + Debug serial port register map stride size in bytes. + 0:1, 2:4 +**/ + uint8_t SerialDebugPortStrideSize; + +/** Offset 0x0047 - Memory Fast Boot + Enable/Disable MRC fast boot support. + $EN_DIS +**/ + uint8_t MrcFastBoot; + +/** Offset 0x0048 - Integrated Graphics Device + Enable : Enable Integrated Graphics Device (IGD) when selected as the Primary Video Adaptor. Disable: Always disable IGD. + $EN_DIS +**/ + uint8_t Igd; + +/** Offset 0x0049 - DVMT Pre-Allocated + Select DVMT 5.0 Pre-Allocated (Fixed) Graphics Memory size used by the Internal Graphics Device. + 0x02:64 MB, 0x03:96 MB, 0x04:128 MB, 0x05:160 MB, 0x06:192 MB, 0x07:224 MB, 0x08:256 MB, 0x09:288 MB, 0x0A:320 MB, 0x0B:352 MB, 0x0C:384 MB, 0x0D:416 MB, 0x0E:448 MB, 0x0F:480 MB, 0x10:512 MB +**/ + uint8_t IgdDvmt50PreAlloc; + +/** Offset 0x004A - Aperture Size + Select the Aperture Size used by the Internal Graphics Device. + 0x1:128 MB, 0x2:256 MB, 0x3:512 MB +**/ + uint8_t IgdApertureSize; + +/** Offset 0x004B - GTT Size + Select the GTT Size used by the Internal Graphics Device. + 0x1:2 MB, 0x2:4 MB, 0x3:8 MB +**/ + uint8_t GttSize; + +/** Offset 0x004C - Primary Display + Select which of IGD/PCI Graphics device should be Primary Display. + 0x0:AUTO, 0x2:IGD, 0x3:PCI +**/ + uint8_t PrimaryVideoAdaptor; + +/** Offset 0x004D - Package + NOTE: First option is CoPOP if LPDDR3/LPDDR4 is being used. It is SODIMM if DDR3L is being used. + 0x0:CoPop, 0x1:BGA, 0x2:LP3 ACRD +**/ + uint8_t Package; + +/** Offset 0x004E - Profile + Profile list + 0x1:WIO2_800_7_8_8, 0x2:WIO2_1066_9_10_10, 0x3:LPDDR3_1066_8_10_10, 0x4:LPDDR3_1333_10_12_12, 0x5:LPDDR3_1600_12_15_15, 0x6:LPDDR3_1866_14_17_17, 0x7:LPDDR3_2133_16_20_20, 0x8:LPDDR4_1066_10_10_10, 0x9:LPDDR4_1600_14_15_15, 0xA:LPDDR4_2133_20_20_20, 0xB:LPDDR4_2400_24_22_22, 0xC:LPDDR4_2666_24_24_24, 0xD:LPDDR4_2933_28_27_27, 0xE:LPDDR4_3200_28_29_29, 0xF:DDR3_1066_6_6_6, 0x10:DDR3_1066_7_7_7, 0x11:DDR3_1066_8_8_8, 0x12:DDR3_1333_7_7_7, 0x13:DDR3_1333_8_8_8, 0x14:DDR3_1333_9_9_9, 0x15:DDR3_1333_10_10_10, 0x16:DDR3_1600_8_8_8, 0x17:DDR3_1600_9_9_9, 0x18:DDR3_1600_10_10_10, 0x19:DDR3_1600_11_11_11, 0x1A:DDR3_1866_10_10_10, 0x1B:DDR3_1866_11_11_11, 0x1C:DDR3_1866_12_12_12, 0x1D:DDR3_1866_13_13_13, 0x1E:DDR3_2133_11_11_11, 0x1F:DDR3_2133_12_12_12, 0x20:DDR3_2133_13_13_13, 0x21:DDR3_2133_14_14_14, 0x22:DDR4_1333_10_10_10, 0x23:DDR4_1600_10_10_10, 0x24:DDR4_1600_11_11_11, 0x25:DDR4_1600_12_12_12, 0x26:DDR4_1866_12_12_12, 0x27:DDR4_1866_13_13_13, 0x28:DDR4_1866_14_14_14, 0x29:DDR4_2133_14_14_14, 0x2A:DDR4_2133_15_15_15, 0x2B:DDR4_2133_16_16_16, 0x2C:DDR4_2400_15_15_15, 0x2D:DDR4_2400_16_16_16, 0x2E:DDR4_2400_17_17_17, 0x2F:DDR4_2400_18_18_18 +**/ + uint8_t Profile; + +/** Offset 0x004F - MemoryDown + Memory Down. + 0x0:No, 0x1:Yes, 0x2:1MD+SODIMM (for DDR3L only) ACRD, 0x3:1x32 LPDDR4 +**/ + uint8_t MemoryDown; + +/** Offset 0x0050 - DDR3LPageSize + NOTE: Only for memory down or downgrade DDR3L frequency. + 0x1:1KB, 0x2:2KB +**/ + uint8_t DDR3LPageSize; + +/** Offset 0x0051 - DDR3LASR + NOTE: Only for memory down. + 0x0:Not Supported, 0x1:Supported +**/ + uint8_t DDR3LASR; + +/** Offset 0x0052 - ScramblerSupport + Scrambler Support. + $EN_DIS +**/ + uint8_t ScramblerSupport; + +/** Offset 0x0053 - ChannelHashMask + Channel Hash Mask. +**/ + uint16_t ChannelHashMask; + +/** Offset 0x0055 - SliceHashMask + Slice Hash Mask. +**/ + uint16_t SliceHashMask; + +/** Offset 0x0057 - InterleavedMode + Interleaved Mode. + $EN_DIS +**/ + uint8_t InterleavedMode; + +/** Offset 0x0058 - ChannelsSlicesEnable + Channels Slices Enable. + $EN_DIS +**/ + uint8_t ChannelsSlicesEnable; + +/** Offset 0x0059 - MinRefRate2xEnable + Provided as a means to defend against Row-Hammer attacks. + $EN_DIS +**/ + uint8_t MinRefRate2xEnable; + +/** Offset 0x005A - DualRankSupportEnable + Dual Rank Support Enable. + $EN_DIS +**/ + uint8_t DualRankSupportEnable; + +/** Offset 0x005B - RmtMode + Rank Margin Tool Mode. + $EN_DIS +**/ + uint8_t RmtMode; + +/** Offset 0x005C - MemorySizeLimit + Memory Size Limit: This value is used to restrict the total amount of memory and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t MemorySizeLimit; + +/** Offset 0x005E - LowMemoryMaxValue + Low Memory Max Value: This value is used to restrict the amount of memory below 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t LowMemoryMaxValue; + +/** Offset 0x0060 - DisableFastBoot + 00: Disabled; Used saved training data (if valid)\n01: Enabled; Full re-train of memory. + $EN_DIS +**/ + uint8_t DisableFastBoot; + +/** Offset 0x0061 - HighMemoryMaxValue + High Memory Max Value: This value is used to restrict the amount of memory above 4GB and the calculations based on it. Value is in MB\nExample encodings are: 0x400 = 1GB, 0x800 = 2GB, 0x1000 = 4GB, 0x2000 8GB. +**/ + uint16_t HighMemoryMaxValue; + +/** Offset 0x0063 - DIMM0SPDAddress + DIMM0 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM0SPDAddress; + +/** Offset 0x0064 - DIMM1SPDAddress + DIMM1 SPD Address (NOTE: Only for DDR3L only. Please put 0 for MemoryDown. +**/ + uint8_t DIMM1SPDAddress; + +/** Offset 0x0065 - Ch0_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch0_RankEnable; + +/** Offset 0x0066 - Ch0_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch0_DeviceWidth; + +/** Offset 0x0067 - Ch0_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch0_DramDensity; + +/** Offset 0x0068 - Ch0_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch0_Option; + +/** Offset 0x0069 - Ch0_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch0_OdtConfig; + +/** Offset 0x006A - Ch0_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\n Boolean value. +**/ + uint8_t Ch0_TristateClk1; + +/** Offset 0x006B - Ch0_Mode2N + [0] 2N Mode.\n Boolean value. +**/ + uint8_t Ch0_Mode2N; + +/** Offset 0x006C - Ch0_OdtLevels + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch0_OdtLevels; + +/** Offset 0x006D - Ch1_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch1_RankEnable; + +/** Offset 0x006E - Ch1_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch1_DeviceWidth; + +/** Offset 0x006F - Ch1_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch1_DramDensity; + +/** Offset 0x0070 - Ch1_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch1_Option; + +/** Offset 0x0071 - Ch1_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch1_OdtConfig; + +/** Offset 0x0072 - Ch1_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. +**/ + uint8_t Ch1_TristateClk1; + +/** Offset 0x0073 - Ch1_Mode2N + [0] 2N Mode.\nBoolean value. +**/ + uint8_t Ch1_Mode2N; + +/** Offset 0x0074 - Ch1_OdtLevels + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t Ch1_OdtLevels; + +/** Offset 0x0075 - Ch2_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch2_RankEnable; + +/** Offset 0x0076 - Ch2_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch2_DeviceWidth; + +/** Offset 0x0077 - Ch2_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch2_DramDensity; + +/** Offset 0x0078 - Ch2_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch2_Option; + +/** Offset 0x0079 - Ch2_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch2_OdtConfig; + +/** Offset 0x007A - Ch2_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. +**/ + uint8_t Ch2_TristateClk1; + +/** Offset 0x007B - Ch2_Mode2N + [0] 2N Mode.\nBoolean value. +**/ + uint8_t Ch2_Mode2N; + +/** Offset 0x007C - Ch2_OdtLevels + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t Ch2_OdtLevels; + +/** Offset 0x007D - Ch3_RankEnable + NOTE: Only for memory down\n[0] Enable Rank 0: Must be set to 1 to enable use of this rank.\n[1] Enable Rank 1: Must be set to 1 to enable use of this rank. +**/ + uint8_t Ch3_RankEnable; + +/** Offset 0x007E - Ch3_DeviceWidth + NOTE: Only for memory down\nDRAM Device Data Width populated on Ranks 0 and 1. + 0b0000:x8, 0b0001:x16, 0b0010:x32, 0b0011:x64 +**/ + uint8_t Ch3_DeviceWidth; + +/** Offset 0x007F - Ch3_DramDensity + NOTE: Only for memory down\nDRAM Device Density populated on Ranks 0 and 1. + 0b0000:4Gb, 0b0001:6Gb, 0b0010:8Gb, 0b0011:12Gb, 0b0100:16Gb +**/ + uint8_t Ch3_DramDensity; + +/** Offset 0x0080 - Ch3_Option + [0] Rank Select Interleaving Enable. See Address Mapping section for full description.\n0 - Rank Select Interleaving disabled\n1 - Rank Select Interleaving enabled\n[1] Bank Address Hashing Enable. See Address Mapping section for full description.\n0 - Bank Address Hashing disabled\n1 - Bank Address Hashing enabled\n[3:2] Reserved\n[5:4] This register specifies the address mapping to be used:\n00 - 1KB (A)\n01 - 2KB (B). +**/ + uint8_t Ch3_Option; + +/** Offset 0x0081 - Ch3_OdtConfig + [0] ODT configuration control.\n0 - WEAK_ODT_CONFIG\n1 - STRONG_ODT_CONFIG\n. +**/ + uint8_t Ch3_OdtConfig; + +/** Offset 0x0082 - Ch3_TristateClk1 + [0] Parameter used to determine whether to tristate CLK1.\nBoolean value. +**/ + uint8_t Ch3_TristateClk1; + +/** Offset 0x0083 - Ch3_Mode2N + [0] 2N Mode.\nBoolean value. +**/ + uint8_t Ch3_Mode2N; + +/** Offset 0x0084 - Ch3_OdtLevels + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t Ch3_OdtLevels; + +/** Offset 0x0085 - RmtCheckRun + [0] Parameter used to determine if ODT will be held high or low.\n0 - Use MRC default\n1 - ODT_AB_HIGH_HIGH\n3 - ODT_AB_HIGH_LOW. +**/ + uint8_t RmtCheckRun; + +/** Offset 0x0086 - Ch0_Bit_swizzling + Channel 0 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch0_Bit_swizzling[32]; + +/** Offset 0x00A6 - Ch1_Bit_swizzling + Channel 1 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch1_Bit_swizzling[32]; + +/** Offset 0x00C6 - Ch2_Bit_swizzling + Channel 2 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch2_Bit_swizzling[32]; + +/** Offset 0x00E6 - Ch3_Bit_swizzling + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint8_t Ch3_Bit_swizzling[32]; + +/** Offset 0x0106 - RmtMarginCheckScaleHighThreshold + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint16_t RmtMarginCheckScaleHighThreshold; + +/** Offset 0x0108 - MsgLevelMask + Channel 3 PHY to DUnit DQ mapping (only used if not 1-1 mapping)Range: 0-32. +**/ + uint32_t MsgLevelMask; + +/** Offset 0x010C - FIT Table Pointer + FIT table pointer. +**/ + uint32_t FitTablePtr; + +/** Offset 0x0110 - GPIO Table Pointer + GPIO table pointer to a BL_GPIO_PAD_INIT structure. +**/ + struct BL_GPIO_PAD_INIT* GpioPadInitTablePtr; + +/** Offset 0x0114 +**/ + uint8_t ReservedFspmUpd[60]; +} __attribute__((packed)); + +/** Fsp M Test Configuration +**/ +struct FSP_M_TEST_CONFIG { + +/** Offset 0x0150 +**/ + uint32_t Signature; + +/** Offset 0x0154 +**/ + uint8_t ReservedFspmTestUpd[28]; +} __attribute__((packed)); + +/** Fsp M Restricted Configuration +**/ +struct FSP_M_RESTRICTED_CONFIG { + +/** Offset 0x0170 +**/ + uint32_t Signature; + +/** Offset 0x0174 +**/ + uint8_t ReservedFspmRestrictedUpd[138]; +} __attribute__((packed)); + +#define FSPM_UPD_SIGNATURE 0x4450555F4D505346 /* 'FSPM_UPD' */ + +struct FSPM_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSP_M_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + struct FSP_M_CONFIG FspmConfig; + +/** Offset 0x0150 +**/ + struct FSP_M_TEST_CONFIG FspmTestConfig; + +/** Offset 0x0170 +**/ + struct FSP_M_RESTRICTED_CONFIG FspmRestrictedConfig; + +/** Offset 0x01FE +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/apollolake/include/fsp/FspsUpd.h b/src/soc/intel/apollolake/include/fsp/FspsUpd.h new file mode 100644 index 0000000..5eee01e --- /dev/null +++ b/src/soc/intel/apollolake/include/fsp/FspsUpd.h @@ -0,0 +1,565 @@ +/** @file + +Copyright (c) 2016, Intel Corporation. All rights reserved. + +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + +#ifndef __FSPSUPD_H__ +#define __FSPSUPD_H__ + +#include "FspUpd.h" + + +/** Fsp S Configuration +**/ +struct FSP_S_CONFIG { + +/** Offset 0x0020 - ActiveProcessorCores + Number of active cores. +**/ + uint8_t ActiveProcessorCores; + +/** Offset 0x0021 - Disable Core1 + Disable/Enable Core1. + $EN_DIS +**/ + uint8_t DisableCore1; + +/** Offset 0x0022 - Disable Core2 + Disable/Enable Core2. + $EN_DIS +**/ + uint8_t DisableCore2; + +/** Offset 0x0023 - Disable Core3 + Disable/Enable Core3. + $EN_DIS +**/ + uint8_t DisableCore3; + +/** Offset 0x0024 - VMX Enable + Enable or Disable VMX. + $EN_DIS +**/ + uint8_t VmxEnable; + +/** Offset 0x0025 - Memory region allocation for Processor Trace + Memory region allocation for Processor Trace, allowed range is from 4K (0x0) to 128MB (0xF); 0xFF: Disable. +**/ + uint8_t ProcTraceMemSize; + +/** Offset 0x0026 - Enable Processor Trace + Enable or Disable Processor Trace feature. + $EN_DIS +**/ + uint8_t ProcTraceEnable; + +/** Offset 0x0027 - Eist + Enable or Disable Intel SpeedStep Technology. + $EN_DIS +**/ + uint8_t Eist; + +/** Offset 0x0028 - Boot PState + Boot PState with HFM or LFM. 0: HFM; 1: LFM. +**/ + uint8_t BootPState; + +/** Offset 0x0029 - CPU power states (C-states) + Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t EnableCx; + +/** Offset 0x002A - Enhanced C-states + Enable or Disable Enhanced C-states. 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t C1e; + +/** Offset 0x002B - Bi-Directional PROCHOT# + Enable or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable. + $EN_DIS +**/ + uint8_t BiProcHot; + +/** Offset 0x002C - Max Pkg Cstate + Max Pkg Cstate. 0:PkgC0C1; 1:PkgC2; 2:PkgC3; 3:PkgC6; 4:PkgC7; 5:PkgC7s; 6:PkgC8; 7:PkgC9; 8:PkgC10; 9:PkgCMax; 254:PkgCpuDefault; 255:PkgAuto. +**/ + uint8_t PkgCStateLimit; + +/** Offset 0x002D +**/ + uint8_t UnusedUpdSpace0; + +/** Offset 0x002E - C-State auto-demotion + C-State Auto Demotion. 0:Disable C1 and C3 Auto-demotion; 1:Enable C3/C6/C7 Auto-demotion to C1; 2:Enable C6/C7 Auto-demotion to C3; 3:Enable C6/C7 Auto-demotion to C1 and C3. +**/ + uint8_t CStateAutoDemotion; + +/** Offset 0x002F - C-State un-demotion + C-State un-demotion. 0:Disable C1 and C3 Un-demotion; 1:Enable C1 Un-demotion; 2:Enable C3 Un-demotion; 3:Enable C1 and C3 Un-demotion. +**/ + uint8_t CStateUnDemotion; + +/** Offset 0x0030 - Max Core C-State + Max Core C-State. 0:Unlimited;1:C1;2:C3;3:C6;4:C7;5:C8;6:C9;7:C10;8:CCx. +**/ + uint8_t MaxCoreCState; + +/** Offset 0x0031 - Package C-State Demotion + Enable or Disable Package Cstate Demotion. 0:Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PkgCStateDemotion; + +/** Offset 0x0032 - Package C-State Un-demotion + Enable or Disable Package Cstate UnDemotion. 0:Disable; 1: Enable. + $EN_DIS +**/ + uint8_t PkgCStateUnDemotion; + +/** Offset 0x0033 - Turbo Mode + Enable or Disable long duration Turbo Mode. 0:Disable; 1: Enable. + $EN_DIS +**/ + uint8_t TurboMode; + +/** Offset 0x0034 +**/ + uint8_t UnusedUpdSpace1[12]; + +/** Offset 0x0040 - HD-Audio I/O Buffer Ownership + Set HD-Audio I/O Buffer Ownership. + 0:HD-Audio link owns all the I/O buffers, 1:HD-Audio link owns 4 I/O buffers and I2S port owns 4 I/O buffers, 3:I2S port owns all the I/O buffers +**/ + uint8_t HdAudioIoBufferOwnership; + +/** Offset 0x0041 +**/ + uint8_t UnusedUpdSpace2[5]; + +/** Offset 0x0046 - Enable SD controller + Enable/disable SD Card controller. + $EN_DIS +**/ + uint8_t SdcardEnabled; + +/** Offset 0x0047 - Enable SDIO controller + Enable/disable SDIO controller. + $EN_DIS +**/ + uint8_t SdioEnabled; + +/** Offset 0x0048 - Enable eMMC controller + Enable/disable eMMC controller. + $EN_DIS +**/ + uint8_t eMMCEnabled; + +/** Offset 0x0049 - Enable SATA + Enable/disable SATA controller. + $EN_DIS +**/ + uint8_t EnableSata; + +/** Offset 0x004A - SATA Mode + Select SATA controller working mode. + 0:AHCI, 1:RAID +**/ + uint8_t SataMode; + +/** Offset 0x004B - Aggressive SATA LPM Support + Enable SOC to aggressively enter link power state for SATA. + $EN_DIS +**/ + uint8_t SataSalpSupport; + +/** Offset 0x004C - Enable SATA ports + Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsEnable[2]; + +/** Offset 0x004E - Enable SATA DEVSLP Feature + Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t SataPortsDevSlp[2]; + +/** Offset 0x0050 - Enable PCIE RP + Enable/disable PCIE Root Ports. 0: disable, 1: enable. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRootPortEn[6]; + +/** Offset 0x0056 - Configure CLKREQ Number + Configure Root Port CLKREQ Number if CLKREQ is supported. Each value in array can be between 0-6. One byte for each port, byte0 for port1, byte1 for port2, and so on. +**/ + uint8_t PcieRpClkReqNumber[6]; + +/** Offset 0x005C +**/ + uint8_t UnusedUpdSpace3[16]; + +/** Offset 0x006C - Enable USB2 ports + Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb20Enable[8]; + +/** Offset 0x0074 - Enable USB3 ports + Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for port1, and so on. +**/ + uint8_t PortUsb30Enable[6]; + +/** Offset 0x007A - Enable XHCI SSIC ports + Enable/disable XHCI SSIC ports. One byte for each port, byte0 for port0, byte1 for port1. +**/ + uint8_t SsicPortEnable[2]; + +/** Offset 0x007C - Enable SMBus + Enable/disable SMBus controller. + $EN_DIS +**/ + uint8_t SmbusEnable; + +/** Offset 0x007D - SC HDA Verb Table Entry Number + Number of Entries in Verb Table. +**/ + uint8_t HdaVerbTableEntryNum; + +/** Offset 0x007E - SC HDA Verb Table Pointer + Pointer to Array of pointers to Verb Table. +**/ + uint32_t HdaVerbTablePtr; + +/** Offset 0x0082 +**/ + uint8_t UnusedUpdSpace4[14]; + +/** Offset 0x0090 - Enable/Disable P2SB device hidden. + Enable/Disable P2SB device hidden. + $EN_DIS +**/ + uint8_t HideP2sb; + +/** Offset 0x0091 - Ufs Enable/Disable + Enable/Disable Ufs. + $EN_DIS +**/ + uint8_t UfsEnabled; + +/** Offset 0x0092 - IPU Enable/Disable + Enable/Disable IPU Device. + $EN_DIS +**/ + uint8_t IpuEn; + +/** Offset 0x0093 - IMGU ACPI mode selection + 0=Auto, 1(Default)=IGFX Child device, 2=ACPI device + 0:Disable, 1:IGFX Child device, 2:ACPI device +**/ + uint8_t IpuAcpiMode; + +/** Offset 0x0094 - ResetSelect + ResetSelect. 0x6:warm reset; 0xE:cold reset +**/ + uint8_t ResetSelect; + +/** Offset 0x0095 - CRIDSettings + PMC CRID setting. 0:Disable;1:CRID_1;2:CRID_2;3:CRID_3 +**/ + uint8_t CRIDSettings; + +/** Offset 0x0096 - Enable HPET + Enable/disable HPET. + $EN_DIS +**/ + uint8_t Hpet; + +/** Offset 0x0097 - Enable PCIE Clock Gating + Enable/disable PCIE Clock Gating.0:Enable;1:Disable + $EN_DIS +**/ + uint8_t PcieClockGatingDisabled; + +/** Offset 0x0098 - Enable PCIE Root Port 8xh Decode + Enable/disable PCIE Root Port 8xh Decode.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PcieRootPort8xhDecode; + +/** Offset 0x0099 - PCIE 8xh Decode Port Index + PCIE 8xh Decode Port Index. +**/ + uint8_t Pcie8xhDecodePortIndex; + +/** Offset 0x009A - Enable PCIE Root Port Peer Memory Write + Enable/disable PCIE root port peer memory write.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PcieRootPortPeerMemoryWriteEnable; + +/** Offset 0x009B - Enable SC Gaussian Mixture Models + Enable/disable SC Gaussian Mixture Models.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t Gmm; + +/** Offset 0x009C - GttMmAdr + GttMmAdr structure for initialization. +**/ + uint32_t GttMmAdr; + +/** Offset 0x00A0 +**/ + uint8_t UnusedUpdSpace5[96]; + +/** Offset 0x0100 - Enable S0ix + Enable/disable S0ix.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t S0ix; + +/** Offset 0x0101 - GmAdr + GmAdr structure for initialization. +**/ + uint32_t GmAdr; + +/** Offset 0x0105 - Enable ForceWake + Enable/disable ForceWake Models.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t ForceWake; + +/** Offset 0x0106 - Enable PavpLock + Enable/disable PavpLock.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PavpLock; + +/** Offset 0x0107 - Enable GraphicsFreqModify + Enable/disable GraphicsFreqModify.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t GraphicsFreqModify; + +/** Offset 0x0108 - Enable GraphicsFreqReq + Enable/disable GraphicsFreqReq.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t GraphicsFreqReq; + +/** Offset 0x0109 - Enable GraphicsVideoFreq + Enable/disable GraphicsVideoFreq.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t GraphicsVideoFreq; + +/** Offset 0x010A - Enable PmLock + Enable/disable PmLock.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PmLock; + +/** Offset 0x010B +**/ + uint8_t UnusedUpdSpace6[5]; + +/** Offset 0x0110 - Enable DopClockGating + Enable/disable DopClockGating.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t DopClockGating; + +/** Offset 0x0111 - Enable UnsolicitedAttackOverride + Enable/disable UnsolicitedAttackOverride.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t UnsolicitedAttackOverride; + +/** Offset 0x0112 - Enable WOPCMSupport + Enable/disable WOPCMSupport.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t WOPCMSupport; + +/** Offset 0x0113 - Enable WOPCMSize + Enable/disable WOPCMSize.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t WOPCMSize; + +/** Offset 0x0114 - Enable PowerGating + Enable/disable PowerGating.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t PowerGating; + +/** Offset 0x0115 - Enable UnitLevelClockGating + Enable/disable UnitLevelClockGating.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t UnitLevelClockGating; + +/** Offset 0x0116 - Enable FastBoot + Enable/disable FastBoot.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t FastBoot; + +/** Offset 0x0117 - Enable DynSR + Enable/disable DynSR.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t DynSR; + +/** Offset 0x0118 - Enable SaIpuEnable + Enable/disable SaIpuEnable.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t SaIpuEnable; + +/** Offset 0x0119 - Enable VtdEnable + Enable/disable VtdEnable.0:Disable;1:Enable + $EN_DIS +**/ + uint8_t VtdEnable; + +/** Offset 0x011A - BMP Logo Data Size + BMP logo data buffer size. +**/ + uint32_t LogoSize; + +/** Offset 0x011E - BMP Logo Data Pointer + BMP logo data pointer to a BMP format buffer. +**/ + uint32_t LogoPtr; + +/** Offset 0x0122 - Graphics Configuration Data Pointer + Graphics configuration data used for initialization. +**/ + uint32_t GraphicsConfigPtr; + +/** Offset 0x0126 - GT PM Support + Enable/Disable GT power management support. + $EN_DIS +**/ + uint8_t PmSupport; + +/** Offset 0x0127 - RC6(Render Standby) + Enable/Disable render standby support. + $EN_DIS +**/ + uint8_t EnableRenderStandby; + +/** Offset 0x0128 - PAVP Enable + Enable/Disable Protected Audio Visual Path (PAVP). + $EN_DIS +**/ + uint8_t PavpEnable; + +/** Offset 0x0129 - PAVP PR3 + Enable/Disable PAVP PR3 + $EN_DIS +**/ + uint8_t PavpPr3; + +/** Offset 0x012A - CdClock Frequency selection + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4(Default): 624 MHz + 0: 144 MHz, 1: 288 MHz, 2: 384 MHz, 3: 576 MHz, 4: 624 MHz +**/ + uint8_t CdClock; + +/** Offset 0x012B - Enable/Disable PeiGraphicsPeimInit + Enable(Default): Enable PeiGraphicsPeimInit, Disable: Disable PeiGraphicsPeimInit + $EN_DIS +**/ + uint8_t PeiGraphicsPeimInit; + +/** Offset 0x012C - Enable/Disable Timer 8254 Clock Setting + Enable/Disable Timer 8254 Clock + $EN_DIS +**/ + uint8_t Timer8254ClkSetting; + +/** Offset 0x012D +**/ + uint8_t ReservedFspsUpd[211]; +} __attribute__((packed)); + +/** Fsp S Test Configuration +**/ +struct FSP_S_TEST_CONFIG { + +/** Offset 0x0200 +**/ + uint32_t Signature; + +/** Offset 0x0204 +**/ + uint8_t ReservedFspsTestUpd[12]; +} __attribute__((packed)); + +/** Fsp S Restricted Configuration +**/ +struct FSP_S_RESTRICTED_CONFIG { + +/** Offset 0x0210 +**/ + uint32_t Signature; + +/** Offset 0x0214 +**/ + uint8_t ReservedFspsRestrictedUpd[12]; +} __attribute__((packed)); + +#define FSPS_UPD_SIGNATURE 0x4450555F53505346 /* 'FSPS_UPD' */ + +struct FSPS_UPD { + +/** Offset 0x0000 +**/ + struct FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + struct FSP_S_CONFIG FspsConfig; + +/** Offset 0x0200 +**/ + struct FSP_S_TEST_CONFIG FspsTestConfig; + +/** Offset 0x0210 +**/ + struct FSP_S_RESTRICTED_CONFIG FspsRestrictedConfig; + +/** Offset 0x0220 +**/ + uint16_t UpdTerminator; +} __attribute__((packed)); + +#endif diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h new file mode 100644 index 0000000..d12eb19 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_IOMAP_H_ +#define _SOC_APOLLOLAKE_IOMAP_H_ + +#define P2SB_BAR 0xd0000000 +#define MCH_BASE_ADDR 0xfed10000 +#define MCH_BASE_SIZE (32 * KiB) + +#define ACPI_PMIO_BASE 0x400 +#define R_ACPI_PM1_TMR 0x8 + +/* Accesses to these BARs are hardcoded in FSP */ +#define PMC_BAR0 0xfe042000 +#define PMC_BAR1 0xfe044000 + +#endif /* _SOC_APOLLOLAKE_IOMAP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/romstage.h b/src/soc/intel/apollolake/include/soc/romstage.h new file mode 100644 index 0000000..1ab9ffd --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/romstage.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _SOC_APOLLOLAKE_ROMSTAGE_H_ +#define _SOC_APOLLOLAKE_ROMSTAGE_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +asmlinkage void romstage_entry(void); +void mainboard_memory_init_params(struct FSPM_UPD *memupd); + +#endif /* _SOC_APOLLOLAKE_ROMSTAGE_H_ */ diff --git a/src/soc/intel/apollolake/romstage/entry.inc b/src/soc/intel/apollolake/romstage/entry.inc new file mode 100644 index 0000000..8855948 --- /dev/null +++ b/src/soc/intel/apollolake/romstage/entry.inc @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +apollolake_entry: + + /* reset stack pointer to CAR stack */ + mov $_car_stack_end, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + + call romstage_entry diff --git a/src/soc/intel/apollolake/romstage/romstage.c b/src/soc/intel/apollolake/romstage/romstage.c new file mode 100644 index 0000000..87b41fd --- /dev/null +++ b/src/soc/intel/apollolake/romstage/romstage.c @@ -0,0 +1,154 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/early_variables.h> +#include <arch/io.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <device/pci_def.h> +#include <fsp/FspmUpd.h> +#include <fsp/util.h> +#include <device/resource.h> +#include <string.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/northbridge.h> +#include <soc/romstage.h> +#include <soc/uart.h> + +/* + * Enables several BARs and devices which are needed for memory init + * - MCH_BASE_ADDR is needed in order to talk to the memory controller + * - PMC_BAR0 and PMC_BAR1 are used by FSP (with the base address hardcoded) + * Once raminit is done, we can safely let the allocator re-assign them + * - HPET is enabled because FSP wants to store a pointer to global data in the + * HPET comparator register + */ +static void soc_early_romstage_init(void) +{ + device_t pmc = PMC_DEV; + + /* Set MCH base address and enable bit */ + pci_write_config32(NB_DEV_ROOT, MCHBAR, MCH_BASE_ADDR | 1); + + /* Set PMC base address */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_0, PMC_BAR0); + pci_write_config32(pmc, PCI_BASE_ADDRESS_1, 0); /* 64-bit BAR */ + pci_write_config32(pmc, PCI_BASE_ADDRESS_2, PMC_BAR1); + pci_write_config32(pmc, PCI_BASE_ADDRESS_3, 0); /* 64-bit BAR */ + + /* PMIO BAR4 was already set earlier, hence the COMMAND_IO below */ + pci_write_config32(pmc, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER); + + /* Enable decoding for HPET. Needed for FSP global pointer storage */ + pci_write_config32(P2SB_DEV, 0x60, 1<<7); +} + +static void disable_watchdog(void) +{ + uint32_t reg; + device_t dev = PMC_DEV; + + /* Open up an IO window */ + pci_write_config16(dev, PCI_BASE_ADDRESS_4, ACPI_PMIO_BASE); + pci_write_config32(dev, PCI_COMMAND, + PCI_COMMAND_MASTER | PCI_COMMAND_IO); + + /* We don't have documentation for this bit, but it prevents reboots */ + reg = inl(ACPI_PMIO_BASE + 0x68); + reg |= 1 << 11; + outl(reg, ACPI_PMIO_BASE + 0x68); +} + + +asmlinkage void romstage_entry(void) +{ + void *hob_list_ptr; + struct resource fsp_mem; + struct range_entry reg_car; + + /* Be careful. Bootblock might already have initialized the console */ + if (!IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { + lpss_console_uart_init(); + console_init(); + } + + printk(BIOS_DEBUG, "Starting romstage...\n"); + + disable_watchdog(); + + soc_early_romstage_init(); + + /* We will load FSP blob into CAR, but only in the free region */ + reg_car.begin = (uint32_t) _car_data_end; + reg_car.end = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE ; + + if (fsp_memory_init(&hob_list_ptr, &reg_car) != FSP_SUCCESS) { + die("FSP memory init failed. Giving up."); + } + + fsp_find_reserved_memory(&fsp_mem, hob_list_ptr); + + /* initialize cbmem by adding FSP reserved memory first thing */ + cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY, + fsp_mem.size); + + /* make sure FSP memory is reserved in cbmem */ + if (fsp_mem.base != (uintptr_t)cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY)) + die("Failed to accommodate FSP reserved memory request"); + + /* Now that CBMEM is up, save the list so ramstage can use it */ + fsp_save_hob_list(hob_list_ptr); + + run_ramstage(); +} + +static void fill_console_params(struct FSPM_UPD *memupd) +{ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + memupd->FspmConfig.SerialDebugPortDevice = CONFIG_UART_FOR_CONSOLE; + memupd->FspmConfig.SerialDebugPortType = 2; + memupd->FspmConfig.SerialDebugPortStrideSize = 2; + memupd->FspmConfig.SerialDebugPortAddress = 0; + } else { + memupd->FspmConfig.SerialDebugPortType = 0; + } +} + +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *memupd) +{ + fill_console_params(memupd); + mainboard_memory_init_params(memupd); + + /* Do NOT let FSP do any GPIO pad configuration */ + memupd->FspmConfig.GpioPadInitTablePtr = NULL; + /* This is somewhere in SRAM */ + memupd->FspmConfig.FitTablePtr = read32(&fit_pointer); + /* Reserve enough memory under TOLUD to save CBMEM header */ + memupd->FspmArchUpd.BootLoaderTolumSize = cbmem_overhead_size(); + /* + /* It has nothing to with our stack size. We just ask FSP not to + /* tromp over our car data. + */ + memupd->FspmArchUpd.StackBase = (void *) CONFIG_DCACHE_RAM_BASE; + memupd->FspmArchUpd.StackSize = _car_data_end - _car_data_start; +} + +__attribute__ ((weak)) +void mainboard_memory_init_params(struct FSPM_UPD *memupd) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); +}

1 0

Patch set updated for coreboot: soc/intel/apollolake: Add support for memory-mapped boot media
by Andrey Petrov 26 Feb '16

26 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13706 -gerrit commit cc03867ed17291ad07ee88e7ca0fd35fbefc148a Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Feb 12 15:12:43 2016 -0800 soc/intel/apollolake: Add support for memory-mapped boot media On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 9 ++++ src/soc/intel/apollolake/Kconfig | 3 ++ src/soc/intel/apollolake/Makefile.inc | 3 ++ src/soc/intel/apollolake/mmap_boot.c | 74 ++++++++++++++++++++++++++++++ 4 files changed, 89 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 52d3777..9920b46 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -17,4 +17,13 @@ config MAINBOARD_VENDOR string default "Intel" +config IFD_BIOS_END + hex + default 0x6FF000 + +config IFD_BIOS_START + hex + default 0x1000 + + endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bb0cc20..401535f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -80,4 +80,7 @@ config C_ENV_BOOTBLOCK_SIZE hex default 0x8000 +config X86_TOP4G_BOOTMEDIA_MAP + bool + default n endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7f8beb0..17ddaec 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -11,17 +11,20 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c +bootblock-y += mmap_boot.c bootblock-y += placeholders.c bootblock-y += tsc_freq.c bootblock-y += uart_early.c romstage-y += placeholders.c romstage-y += gpio.c +romstage-y += mmap_boot.c romstage-y += uart_early.c smm-y += placeholders.c ramstage-y += placeholders.c ramstage-y += gpio.c +ramstage-y += mmap_boot.c ramstage-y += uart_early.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c new file mode 100644 index 0000000..ad7cfed --- /dev/null +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -0,0 +1,74 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> + +/* The 128 KiB right below 4G are decoded by readonly SRAM, not boot media */ +#define IFD_BIOS_MAX_MAPPED (CONFIG_IFD_BIOS_END - 128 * KiB) +#define IFD_MAPPED_SIZE (IFD_BIOS_MAX_MAPPED - CONFIG_IFD_BIOS_START) +#define IFD_BIOS_SIZE (CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START) + +/* + * If Apollo Lake is configured to boot from SPI flash "BIOS" region + * (as defined in descriptor) is mapped below 4GiB. Form a pointer for + * the base. + */ +#define VIRTUAL_ROM_BASE ((uintptr_t)(0x100000000ULL - IFD_BIOS_SIZE)) + +static const struct mem_region_device shadow_dev = MEM_REGION_DEV_INIT( + VIRTUAL_ROM_BASE, IFD_BIOS_MAX_MAPPED +); + +/* + * This is how we translate physical SPI flash address space into CPU memory-mapped space. In + * essence this means "BIOS" region (usually starts at flash physical 0x1000 is mapped to + * 4G - IFD_BIOS_SIZE. + */ +static const struct xlate_region_device real_dev = XLATE_REGION_INIT( + &shadow_dev.rdev, CONFIG_IFD_BIOS_START, + IFD_MAPPED_SIZE, CONFIG_ROM_SIZE +); + +const struct region_device *boot_device_ro(void) +{ + return &real_dev.rdev; +} + +static int iafw_boot_region_properties(struct cbfs_props *props) +{ + struct region regn; + + /* use fmap to locate CBFS area */ + if (fmap_locate_area("COREBOOT", &regn)) + return -1; + + props->offset = regn.offset; + props->size = regn.size; + + printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size); + + return 0; +} + +/* + * Named cbfs_master_header_locator so that it overrides the default, but + * incompatible locator in cbfs.c + */ +const struct cbfs_locator cbfs_master_header_locator = { + .name = "IAFW Locator", + .locate = iafw_boot_region_properties, +};

1 0

Patch set updated for coreboot: southbridge/amd/sb900: Add southbridge sb900 (hudson) non-AGESA
by Damien Zammit 26 Feb '16

26 Feb '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13711 -gerrit commit 664d3d3e4c493ebb9e9c64efec9206372fd42ef8 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Feb 10 14:03:52 2016 +1100 southbridge/amd/sb900: Add southbridge sb900 (hudson) non-AGESA Change-Id: I9bcb926d55a00993ba4d0a3c45541dbd883bbae1 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/southbridge/amd/sb900/Kconfig | 32 ++ src/southbridge/amd/sb900/Makefile.inc | 25 ++ src/southbridge/amd/sb900/acpi/audio.asl | 52 +++ src/southbridge/amd/sb900/acpi/fch.asl | 203 +++++++++++ src/southbridge/amd/sb900/acpi/lpc.asl | 104 ++++++ src/southbridge/amd/sb900/acpi/pci_int.asl | 469 +++++++++++++++++++++++++ src/southbridge/amd/sb900/acpi/pcie.asl | 91 +++++ src/southbridge/amd/sb900/acpi/sleepstates.asl | 36 ++ src/southbridge/amd/sb900/acpi/smbus.asl | 16 + src/southbridge/amd/sb900/acpi/usb.asl | 73 ++++ src/southbridge/amd/sb900/amd_pci_int_defs.h | 73 ++++ src/southbridge/amd/sb900/amd_pci_int_types.h | 30 ++ src/southbridge/amd/sb900/bootblock.c | 64 ++++ src/southbridge/amd/sb900/chip.h | 24 ++ src/southbridge/amd/sb900/early_setup.c | 122 +++++++ src/southbridge/amd/sb900/enable_usbdebug.c | 59 ++++ src/southbridge/amd/sb900/fadt.c | 209 +++++++++++ src/southbridge/amd/sb900/hda.c | 40 +++ src/southbridge/amd/sb900/ide.c | 38 ++ src/southbridge/amd/sb900/lpc.c | 346 ++++++++++++++++++ src/southbridge/amd/sb900/pci.c | 63 ++++ src/southbridge/amd/sb900/pci_devs.h | 114 ++++++ src/southbridge/amd/sb900/pcie.c | 56 +++ src/southbridge/amd/sb900/ramtop.c | 59 ++++ src/southbridge/amd/sb900/reset.c | 31 ++ src/southbridge/amd/sb900/sata.c | 41 +++ src/southbridge/amd/sb900/sb900.c | 181 ++++++++++ src/southbridge/amd/sb900/sb900.h | 87 +++++ src/southbridge/amd/sb900/sm.c | 114 ++++++ src/southbridge/amd/sb900/smbus.c | 246 +++++++++++++ src/southbridge/amd/sb900/smbus.h | 71 ++++ src/southbridge/amd/sb900/smi.c | 25 ++ src/southbridge/amd/sb900/smi.h | 65 ++++ src/southbridge/amd/sb900/smi_util.c | 79 +++++ src/southbridge/amd/sb900/smihandler.c | 134 +++++++ src/southbridge/amd/sb900/usb.c | 51 +++ 36 files changed, 3523 insertions(+) diff --git a/src/southbridge/amd/sb900/Kconfig b/src/southbridge/amd/sb900/Kconfig new file mode 100644 index 0000000..3899a22 --- /dev/null +++ b/src/southbridge/amd/sb900/Kconfig @@ -0,0 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +config SOUTHBRIDGE_AMD_SB900 + bool + select IOAPIC + select HAVE_USBDEBUG_OPTIONS + select HAVE_HARD_RESET + +if SOUTHBRIDGE_AMD_SB900 + +config BOOTBLOCK_SOUTHBRIDGE_INIT + string + default "southbridge/amd/sb900/bootblock.c" + +config EHCI_BAR + hex + default 0xfef00000 + +endif diff --git a/src/southbridge/amd/sb900/Makefile.inc b/src/southbridge/amd/sb900/Makefile.inc new file mode 100644 index 0000000..a9205a9 --- /dev/null +++ b/src/southbridge/amd/sb900/Makefile.inc @@ -0,0 +1,25 @@ +ifeq ($(CONFIG_SOUTHBRIDGE_AMD_SB900),y) + +ramstage-y += sb900.c +ramstage-y += usb.c +ramstage-y += lpc.c +ramstage-y += sm.c +ramstage-y += ide.c +ramstage-y += sata.c +ramstage-y += hda.c +#ramstage-y += pci.c +ramstage-y += pcie.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-y += reset.c +ramstage-y += ramtop.c +ramstage-$(CONFIG_USBDEBUG) += enable_usbdebug.c +ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c smi_util.c + +romstage-y += smbus.c +romstage-$(CONFIG_USBDEBUG_IN_ROMSTAGE) += enable_usbdebug.c +romstage-y += early_setup.c +romstage-y += ramtop.c + +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c smi_util.c + +endif diff --git a/src/southbridge/amd/sb900/acpi/audio.asl b/src/southbridge/amd/sb900/acpi/audio.asl new file mode 100644 index 0000000..e35ae85 --- /dev/null +++ b/src/southbridge/amd/sb900/acpi/audio.asl @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Device(AZHD) { /* 0:14.2 - HD Audio */ + Name(_ADR, 0x00140002) + OperationRegion(AZPD, PCI_Config, 0x00, 0x100) + Field(AZPD, AnyAcc, NoLock, Preserve) { + offset (0x42), + NSDI, 1, + NSDO, 1, + NSEN, 1, + offset (0x44), + IPCR, 4, + offset (0x54), + PWST, 2, + , 6, + PMEB, 1, + , 6, + PMST, 1, + offset (0x62), + MMCR, 1, + offset (0x64), + MMLA, 32, + offset (0x68), + MMHA, 32, + offset (0x6C), + MMDT, 16, + } + + Method (_INI, 0, NotSerialized) + { + If (LEqual (OSVR, 0x03)) + { + Store (Zero, NSEN) + Store (One, NSDO) + Store (One, NSDI) + } + } +} /* end AZHD */ diff --git a/src/southbridge/amd/sb900/acpi/fch.asl b/src/southbridge/amd/sb900/acpi/fch.asl new file mode 100644 index 0000000..d7cee4a --- /dev/null +++ b/src/southbridge/amd/sb900/acpi/fch.asl @@ -0,0 +1,203 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* South Bridge */ +/* _SB.PCI0 */ + +/* Operating System Capabilities Method */ +Method(_OSC,4) +{ + // Create DWord-addressable fields from the Capabilities Buffer + CreateDWordField(Arg3,0,CDW1) + CreateDWordField(Arg3,4,CDW2) + CreateDWordField(Arg3,8,CDW3) + + /* Check for proper PCI/PCIe UUID */ + If(LEqual(Arg0,ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + { + /* Let OS control everything */ + Return (Arg3) + } Else { + Or(CDW1,4,CDW1) // Unrecognized UUID + Return(Arg3) + } +} + +/* Describe the Southbridge devices */ + +/* 0:11.0 - SATA */ +Device(STCR) { + Name(_ADR, 0x00110000) + #include "acpi/sata.asl" +} /* end STCR */ + +/* 0:14.0 - SMBUS */ +Device(SBUS) { + Name(_ADR, 0x00140000) +} /* end SBUS */ + +#include "usb.asl" + +/* 0:14.2 - HD Audio */ +#include "audio.asl" + +/* 0:14.3 - LPC */ +#include "lpc.asl" + +/* 0:14.7 - SD Controller */ +Device(SDCN) { + Name(_ADR, 0x00140007) +} /* end SDCN */ + +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE + +/* 0:14.4 - PCI slot 1, 2, 3 */ +Device(PIBR) { + Name(_ADR, 0x00140004) + Name(_PRW, Package() {0x18, 4}) + + Method(_PRT, 0) { + Return (PCIB) + } +} + +/* 0:14.6 - GEC Controller */ +Device(ACMD) { + Name(_ADR, 0x00140006) +} /* end Ac97modem */ +#endif + +Name(CRES, ResourceTemplate() { + /* Set the Bus number and Secondary Bus number for the PCI0 device + * The Secondary bus range for PCI0 lets the system + * know what bus values are allowed on the downstream + * side of this PCI bus if there is a PCI-PCI bridge. + * PCI busses can have 256 secondary busses which + * range from [0-0xFF] but they do not need to be + * sequential. + */ + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x00FF, /* range maximum */ + 0x0000, /* translation */ + 0x0100, /* length */ + ,, PSB0) /* ResourceSourceIndex, ResourceSource, DescriptorName */ + + IO(Decode16, 0x0CF8, 0x0CF8, 1, 8) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0000, /* range minimum */ + 0x0CF7, /* range maximum */ + 0x0000, /* translation */ + 0x0CF8 /* length */ + ) + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x03B0, /* range minimum */ + 0x03DF, /* range maximum */ + 0x0000, /* translation */ + 0x0030 /* length */ + ) + + WORDIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, /* address granularity */ + 0x0D00, /* range minimum */ + 0xFFFF, /* range maximum */ + 0x0000, /* translation */ + 0xF300 /* length */ + ) + + Memory32Fixed(READONLY, 0x000A0000, 0x00020000, VGAM) /* VGA memory space */ + Memory32Fixed(READONLY, 0x000C0000, 0x00020000, EMM1) /* Assume C0000-E0000 empty */ + + /* memory space for PCI BARs below 4GB */ + Memory32Fixed(ReadOnly, 0x00000000, 0x00000000, MMIO) +}) /* End Name(_SB.PCI0.CRES) */ + +Method(_CRS, 0) { + /* DBGO("\\_SB\\PCI0\\_CRS\n") */ + CreateDWordField(CRES, ^MMIO._BAS, MM1B) + CreateDWordField(CRES, ^MMIO._LEN, MM1L) + + /* + * Declare memory between TOM1 and 4GB as available + * for PCI MMIO. + * Use ShiftLeft to avoid 64bit constant (for XP). + * This will work even if the OS does 32bit arithmetic, as + * 32bit (0x00000000 - TOM1) will wrap and give the same + * result as 64bit (0x100000000 - TOM1). + */ + Store(TOM1, MM1B) + ShiftLeft(0x10000000, 4, Local0) + Subtract(Local0, TOM1, Local0) + Store(Local0, MM1L) + + Return(CRES) /* note to change the Name buffer */ +} /* end of Method(_SB.PCI0._CRS) */ + +/* + * + * FIRST METHOD CALLED UPON BOOT + * + * 1. If debugging, print current OS and ACPI interpreter. + * 2. Get PCI Interrupt routing from ACPI VSM, this + * value is based on user choice in BIOS setup. + */ +Method(_INI, 0) { + /* DBGO("\\_SB\\_INI\n") */ + /* DBGO(" DSDT.ASL code from ") */ + /* DBGO(__DATE__) */ + /* DBGO(" ") */ + /* DBGO(__TIME__) */ + /* DBGO("\n Sleep states supported: ") */ + /* DBGO("\n") */ + /* DBGO(" \\_OS=") */ + /* DBGO(\_OS) */ + /* DBGO("\n \\_REV=") */ + /* DBGO(\_REV) */ + /* DBGO("\n") */ + + /* Determine the OS we're running on */ + OSFL() + +#if defined(CONFIG_HUDSON_IMC_FWM) && CONFIG_HUDSON_IMC_FWM + #include "acpi/AmdImc.asl" /* Hudson IMC function */ + ITZE() /* enable IMC Fan Control*/ +#endif +} /* End Method(_SB._INI) */ + +Method(OSFL, 0){ + + if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */ + + if(CondRefOf(\_OSI)) + { + Store(1, OSVR) /* Assume some form of XP */ + if (\_OSI("Windows 2006")) /* Vista */ + { + Store(2, OSVR) + } + } else { + If(WCMP(\_OS,"Linux")) { + Store(3, OSVR) /* Linux */ + } Else { + Store(4, OSVR) /* Gotta be WinCE */ + } + } + Return(OSVR) +} diff --git a/src/southbridge/amd/sb900/acpi/lpc.asl b/src/southbridge/amd/sb900/acpi/lpc.asl new file mode 100644 index 0000000..2044085 --- /dev/null +++ b/src/southbridge/amd/sb900/acpi/lpc.asl @@ -0,0 +1,104 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* 0:14.3 - LPC */ +Device(LIBR) { + Name(_ADR, 0x00140003) + /* Method(_INI) { + * DBGO("\\_SB\\PCI0\\LpcIsaBr\\_INI\n") + } */ /* End Method(_SB.SBRDG._INI) */ + + OperationRegion(CFG,PCI_Config,0x0,0x100) // Map PCI Configuration Space + Field(CFG,DWordAcc,NoLock,Preserve){ + Offset(0xA0), + BAR,32} // SPI Controller Base Address Register (Index 0xA0) + + Device(LDRC) // LPC device: Resource consumption + { + Name (_HID, EISAID("PNP0C02")) // ID for Motherboard resources + Name (CRS, ResourceTemplate () // Current Motherboard resources + { + Memory32Fixed(ReadWrite, // Setup for fixed resource location for SPI base address + 0x00000000, // Address Base + 0x00000000, // Address Length + BAR0 // Descriptor Name + ) + }) + + Method(_CRS,0,NotSerialized) + { + CreateDwordField(^CRS,^BAR0._BAS,SPIB) // Field to hold SPI base address + CreateDwordField(^CRS,^BAR0._LEN,SPIL) // Field to hold SPI address length + Store(BAR,SPIB) // SPI base address mapped + Store(0x1000,SPIL) // 4k space mapped + Return(CRS) + } + } + + /* Real Time Clock Device */ + Device(RTC0) { + Name(_HID, EISAID("PNP0B00")) /* AT Real Time Clock (not PIIX4 compatible) */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){8} + IO(Decode16,0x0070, 0x0070, 0, 2) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.RTC0) */ + + Device(TMR) { /* Timer */ + Name(_HID,EISAID("PNP0100")) /* System Timer */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){0} + IO(Decode16, 0x0040, 0x0040, 0, 4) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.TMR) */ + + Device(SPKR) { /* Speaker */ + Name(_HID,EISAID("PNP0800")) /* AT style speaker */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x0061, 0x0061, 0, 1) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.SPKR) */ + + Device(PIC) { + Name(_HID,EISAID("PNP0000")) /* AT Interrupt Controller */ + Name(_CRS, ResourceTemplate() { + IRQNoFlags(){2} + IO(Decode16,0x0020, 0x0020, 0, 2) + IO(Decode16,0x00A0, 0x00A0, 0, 2) + }) + } /* End Device(_SB.PCI0.LpcIsaBr.PIC) */ + + Device(MAD) { /* 8257 DMA */ + Name(_HID,EISAID("PNP0200")) /* Hardware Device ID */ + Name(_CRS, ResourceTemplate() { + DMA(Compatibility,BusMaster,Transfer8){4} + IO(Decode16, 0x0000, 0x0000, 0x10, 0x10) + IO(Decode16, 0x0081, 0x0081, 0x01, 0x03) + IO(Decode16, 0x0087, 0x0087, 0x01, 0x01) + IO(Decode16, 0x0089, 0x0089, 0x01, 0x03) + IO(Decode16, 0x008F, 0x008F, 0x01, 0x01) + IO(Decode16, 0x00C0, 0x00C0, 0x10, 0x20) + }) /* End Name(_SB.PCI0.LpcIsaBr.MAD._CRS) */ + } /* End Device(_SB.PCI0.LpcIsaBr.MAD) */ + + Device(COPR) { + Name(_HID,EISAID("PNP0C04")) /* Math Coprocessor */ + Name(_CRS, ResourceTemplate() { + IO(Decode16, 0x00F0, 0x00F0, 0, 0x10) + IRQNoFlags(){13} + }) + } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ + #include "acpi/superio.asl" +} /* end LIBR */ diff --git a/src/southbridge/amd/sb900/acpi/pci_int.asl b/src/southbridge/amd/sb900/acpi/pci_int.asl new file mode 100644 index 0000000..52e9e28 --- /dev/null +++ b/src/southbridge/amd/sb900/acpi/pci_int.asl @@ -0,0 +1,469 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */ + OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */ + Field(PCFG, ByteAcc, NoLock, Preserve) { + /* Byte offsets are computed using the following technique: + * ((bus number + 1) * ((device number * 8) * 4096)) + register offset + * The 8 comes from 8 functions per device, and 4096 bytes per function config space + */ + Offset(0x00088024), /* Byte offset to SATA register 24h - Bus 0, Device 17, Function 0 */ + STB5, 32, + Offset(0x00098042), /* Byte offset to OHCI0 register 42h - Bus 0, Device 19, Function 0 */ + PT0D, 1, + PT1D, 1, + PT2D, 1, + PT3D, 1, + PT4D, 1, + PT5D, 1, + PT6D, 1, + PT7D, 1, + PT8D, 1, + PT9D, 1, + Offset(0x000A0004), /* Byte offset to SMBUS register 4h - Bus 0, Device 20, Function 0 */ + SBIE, 1, + SBME, 1, + Offset(0x000A0008), /* Byte offset to SMBUS register 8h - Bus 0, Device 20, Function 0 */ + SBRI, 8, + Offset(0x000A0014), /* Byte offset to SMBUS register 14h - Bus 0, Device 20, Function 0 */ + SBB1, 32, + Offset(0x000A0078), /* Byte offset to SMBUS register 78h - Bus 0, Device 20, Function 0 */ + ,14, + P92E, 1, /* Port92 decode enable */ + } + + OperationRegion(SB5, SystemMemory, STB5, 0x1000) + Field(SB5, AnyAcc, NoLock, Preserve){ + /* Port 0 */ + Offset(0x120), /* Port 0 Task file status */ + P0ER, 1, + , 2, + P0DQ, 1, + , 3, + P0BY, 1, + Offset(0x128), /* Port 0 Serial ATA status */ + P0DD, 4, + , 4, + P0IS, 4, + Offset(0x12C), /* Port 0 Serial ATA control */ + P0DI, 4, + Offset(0x130), /* Port 0 Serial ATA error */ + , 16, + P0PR, 1, + + /* Port 1 */ + offset(0x1A0), /* Port 1 Task file status */ + P1ER, 1, + , 2, + P1DQ, 1, + , 3, + P1BY, 1, + Offset(0x1A8), /* Port 1 Serial ATA status */ + P1DD, 4, + , 4, + P1IS, 4, + Offset(0x1AC), /* Port 1 Serial ATA control */ + P1DI, 4, + Offset(0x1B0), /* Port 1 Serial ATA error */ + , 16, + P1PR, 1, + + /* Port 2 */ + Offset(0x220), /* Port 2 Task file status */ + P2ER, 1, + , 2, + P2DQ, 1, + , 3, + P2BY, 1, + Offset(0x228), /* Port 2 Serial ATA status */ + P2DD, 4, + , 4, + P2IS, 4, + Offset(0x22C), /* Port 2 Serial ATA control */ + P2DI, 4, + Offset(0x230), /* Port 2 Serial ATA error */ + , 16, + P2PR, 1, + + /* Port 3 */ + Offset(0x2A0), /* Port 3 Task file status */ + P3ER, 1, + , 2, + P3DQ, 1, + , 3, + P3BY, 1, + Offset(0x2A8), /* Port 3 Serial ATA status */ + P3DD, 4, + , 4, + P3IS, 4, + Offset(0x2AC), /* Port 3 Serial ATA control */ + P3DI, 4, + Offset(0x2B0), /* Port 3 Serial ATA error */ + , 16, + P3PR, 1, + } + + Method(_PIC, 0x01, NotSerialized) + { + If (Arg0) + { + \_SB.CIRQ() + } + Store(Arg0, PMOD) + } + + Method(CIRQ, 0x00, NotSerialized){ + } + + Name(IRQB, ResourceTemplate(){ + IRQ(Level,ActiveLow,Shared){15} + }) + + Name(IRQP, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){3, 4, 5, 7, 10, 11, 12, 15} + }) + + Name(PITF, ResourceTemplate(){ + IRQ(Level,ActiveLow,Exclusive){9} + }) + + Device(INTA) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + Method(_STA, 0) { + if (PIRA) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTA._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKA\\_DIS\n") */ + } /* End Method(_SB.INTA._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKA\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTA._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKA\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRA, IRQN) + Return(IRQB) + } /* Method(_SB.INTA._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKA\\_SRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRA) + } /* End Method(_SB.INTA._SRS) */ + } /* End Device(INTA) */ + + Device(INTB) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + Method(_STA, 0) { + if (PIRB) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTB._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKB\\_DIS\n") */ + } /* End Method(_SB.INTB._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKB\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTB._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRB, IRQN) + Return(IRQB) + } /* Method(_SB.INTB._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKB\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRB) + } /* End Method(_SB.INTB._SRS) */ + } /* End Device(INTB) */ + + Device(INTC) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + Method(_STA, 0) { + if (PIRC) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTC._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKC\\_DIS\n") */ + } /* End Method(_SB.INTC._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKC\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTC._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRC, IRQN) + Return(IRQB) + } /* Method(_SB.INTC._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKC\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRC) + } /* End Method(_SB.INTC._SRS) */ + } /* End Device(INTC) */ + + Device(INTD) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + Method(_STA, 0) { + if (PIRD) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTD._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKD\\_DIS\n") */ + } /* End Method(_SB.INTD._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKD\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTD._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRD, IRQN) + Return(IRQB) + } /* Method(_SB.INTD._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKD\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRD) + } /* End Method(_SB.INTD._SRS) */ + } /* End Device(INTD) */ + + Device(INTE) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + Method(_STA, 0) { + if (PIRE) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTE._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKE\\_DIS\n") */ + } /* End Method(_SB.INTE._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKE\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTE._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRE, IRQN) + Return(IRQB) + } /* Method(_SB.INTE._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKE\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRE) + } /* End Method(_SB.INTE._SRS) */ + } /* End Device(INTE) */ + + Device(INTF) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + Method(_STA, 0) { + if (PIRF) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTF._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKF\\_DIS\n") */ + } /* End Method(_SB.INTF._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKF\\_PRS\n") */ + Return(PITF) + } /* Method(_SB.INTF._PRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRF, IRQN) + Return(IRQB) + } /* Method(_SB.INTF._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKF\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRF) + } /* End Method(_SB.INTF._SRS) */ + } /* End Device(INTF) */ + + Device(INTG) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + Method(_STA, 0) { + if (PIRG) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTG._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKG\\_DIS\n") */ + } /* End Method(_SB.INTG._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKG\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTG._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRG, IRQN) + Return(IRQB) + } /* Method(_SB.INTG._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKG\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRG) + } /* End Method(_SB.INTG._SRS) */ + } /* End Device(INTG) */ + + Device(INTH) { + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + Method(_STA, 0) { + if (PIRH) { + Return(0x0B) /* sata is invisible */ + } else { + Return(0x09) /* sata is disabled */ + } + } /* End Method(_SB.INTH._STA) */ + + Method(_DIS ,0) { + /* DBGO("\\_SB\\LNKH\\_DIS\n") */ + } /* End Method(_SB.INTH._DIS) */ + + Method(_PRS ,0) { + /* DBGO("\\_SB\\LNKH\\_PRS\n") */ + Return(IRQP) + } /* Method(_SB.INTH._CRS) */ + + Method(_CRS ,0) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(IRQB, 0x1, IRQN) + ShiftLeft(1, PIRH, IRQN) + Return(IRQB) + } /* Method(_SB.INTH._CRS) */ + + Method(_SRS, 1) { + /* DBGO("\\_SB\\LNKH\\_CRS\n") */ + CreateWordField(ARG0, 1, IRQM) + + /* Use lowest available IRQ */ + FindSetRightBit(IRQM, Local0) + if (Local0) { + Decrement(Local0) + } + Store(Local0, PIRH) + } /* End Method(_SB.INTH._SRS) */ + } /* End Device(INTH) */ diff --git a/src/southbridge/amd/sb900/acpi/pcie.asl b/src/southbridge/amd/sb900/acpi/pcie.asl new file mode 100644 index 0000000..df299c1 --- /dev/null +++ b/src/southbridge/amd/sb900/acpi/pcie.asl @@ -0,0 +1,91 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* PCI IRQ mapping registers, C00h-C01h. */ + OperationRegion(PRQM, SystemIO, 0x00000C00, 0x00000002) + Field(PRQM, ByteAcc, NoLock, Preserve) { + PRQI, 0x00000008, + PRQD, 0x00000008, /* Offset: 1h */ + } + IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) { + PIRA, 0x00000008, /* Index 0 */ + PIRB, 0x00000008, /* Index 1 */ + PIRC, 0x00000008, /* Index 2 */ + PIRD, 0x00000008, /* Index 3 */ + PIRE, 0x00000008, /* Index 4 */ + PIRF, 0x00000008, /* Index 5 */ + PIRG, 0x00000008, /* Index 6 */ + PIRH, 0x00000008, /* Index 7 */ + } + + /* PCI Error control register */ + OperationRegion(PERC, SystemIO, 0x00000C14, 0x00000001) + Field(PERC, ByteAcc, NoLock, Preserve) { + SENS, 0x00000001, + PENS, 0x00000001, + SENE, 0x00000001, + PENE, 0x00000001, + } + + /* Client Management index/data registers */ + OperationRegion(CMT, SystemIO, 0x00000C50, 0x00000002) + Field(CMT, ByteAcc, NoLock, Preserve) { + CMTI, 8, + /* Client Management Data register */ + G64E, 1, + G64O, 1, + G32O, 2, + , 2, + GPSL, 2, + } + + /* GPM Port register */ + OperationRegion(GPT, SystemIO, 0x00000C52, 0x00000001) + Field(GPT, ByteAcc, NoLock, Preserve) { + GPB0,1, + GPB1,1, + GPB2,1, + GPB3,1, + GPB4,1, + GPB5,1, + GPB6,1, + GPB7,1, + } + + /* Flash ROM program enable register */ + OperationRegion(FRE, SystemIO, 0x00000C6F, 0x00000001) + Field(FRE, ByteAcc, NoLock, Preserve) { + , 0x00000006, + FLRE, 0x00000001, + } + + /* PM2 index/data registers */ + OperationRegion(PM2R, SystemIO, 0x00000CD0, 0x00000002) + Field(PM2R, ByteAcc, NoLock, Preserve) { + PM2I, 0x00000008, + PM2D, 0x00000008, + } + + /* Power Management I/O registers, TODO:PMIO is quite different in SB800. */ + OperationRegion(PIOR, SystemIO, 0x00000CD6, 0x00000002) + Field(PIOR, ByteAcc, NoLock, Preserve) { + PIOI, 0x00000008, + PIOD, 0x00000008, + } + + IndexField (PIOI, PIOD, ByteAcc, NoLock, Preserve) { + Offset(0xEE), + UPWS, 3, + } diff --git a/src/southbridge/amd/sb900/acpi/sleepstates.asl b/src/southbridge/amd/sb900/acpi/sleepstates.asl new file mode 100644 index 0000000..912c0df --- /dev/null +++ b/src/southbridge/amd/sb900/acpi/sleepstates.asl @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Supported sleep states: */ +Name(\_S0, Package () {0x00, 0x00, 0x00, 0x00} ) /* (S0) - working state */ + +If (LAnd(SSFG, 0x01)) { + Name(\_S1, Package () {0x01, 0x01, 0x00, 0x00} ) /* (S1) - sleeping w/CPU context */ +} +If (LAnd(SSFG, 0x02)) { + Name(\_S2, Package () {0x02, 0x02, 0x00, 0x00} ) /* (S2) - "light" Suspend to RAM */ +} +If (LAnd(SSFG, 0x04)) { + Name(\_S3, Package () {0x03, 0x03, 0x00, 0x00} ) /* (S3) - Suspend to RAM */ +} +If (LAnd(SSFG, 0x08)) { + Name(\_S4, Package () {0x04, 0x04, 0x00, 0x00} ) /* (S4) - Suspend to Disk */ +} + +Name(\_S5, Package () {0x05, 0x05, 0x00, 0x00} ) /* (S5) - Soft Off */ + +Name(\_SB.CSPS ,0) /* Current Sleep State (S0, S1, S2, S3, S4, S5) */ +Name(CSMS, 0) /* Current System State */ diff --git a/src/southbridge/amd/sb900/acpi/smbus.asl b/src/southbridge/amd/sb900/acpi/smbus.asl new file mode 100644 index 0000000..f0b8983 --- /dev/null +++ b/src/southbridge/amd/sb900/acpi/smbus.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* SMBus Support */ diff --git a/src/southbridge/amd/sb900/acpi/usb.asl b/src/southbridge/amd/sb900/acpi/usb.asl new file mode 100644 index 0000000..0794bf3 --- /dev/null +++ b/src/southbridge/amd/sb900/acpi/usb.asl @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* 0:12.0 - OHCI */ +Device(UOH1) { + Name(_ADR, 0x00120000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH1 */ + +/* 0:12.2 - EHCI */ +Device(UOH2) { + Name(_ADR, 0x00120002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH2 */ + +/* 0:13.0 - OHCI */ +Device(UOH3) { + Name(_ADR, 0x00130000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH3 */ + +/* 0:13.2 - EHCI */ +Device(UOH4) { + Name(_ADR, 0x00130002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH4 */ + +/* 0:16.0 - OHCI */ +Device(UOH5) { + Name(_ADR, 0x00160000) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH5 */ + +/* 0:16.2 - EHCI */ +Device(UOH6) { + Name(_ADR, 0x00160002) + Name(_PRW, Package() {0x0B, 3}) +} /* end UOH5 */ + +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +/* 0:14.5 - OHCI */ +Device(UEH1) { + Name(_ADR, 0x00140005) + Name(_PRW, Package() {0x0B, 3}) +} /* end UEH1 */ +#endif + +/* 0:10.0 - XHCI 0*/ +Device(XHC0) { + Name(_ADR, 0x00100000) + Name(_PRW, Package() {0x0B, 4}) +} /* end XHC0 */ + +#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE +/* 0:10.1 - XHCI 1*/ +Device(XHC1) { + Name(_ADR, 0x00100001) + Name(_PRW, Package() {0x0B, 4}) +} /* end XHC1 */ +#endif diff --git a/src/southbridge/amd/sb900/amd_pci_int_defs.h b/src/southbridge/amd/sb900/amd_pci_int_defs.h new file mode 100644 index 0000000..fd628c3 --- /dev/null +++ b/src/southbridge/amd/sb900/amd_pci_int_defs.h @@ -0,0 +1,73 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMD_PCI_INT_DEFS_H +#define AMD_PCI_INT_DEFS_H + +/* + * PIRQ and device routing - these define the index + * into the FCH PCI_INTR 0xC00/0xC01 interrupt + * routing table + */ +#define FCH_INT_TABLE_SIZE 0x54 + +#define PIRQ_NC 0x1F /* Not Used */ +#define PIRQ_A 0x00 /* INT A */ +#define PIRQ_B 0x01 /* INT B */ +#define PIRQ_C 0x02 /* INT C */ +#define PIRQ_D 0x03 /* INT D */ +#define PIRQ_E 0x04 /* INT E */ +#define PIRQ_F 0x05 /* INT F */ +#define PIRQ_G 0x06 /* INT G */ +#define PIRQ_H 0x07 /* INT H */ +#define PIRQ_MISC 0x08 /* Miscellaneous IRQ Settings - See FCH Spec */ +#define PIRQ_MISC0 0x09 /* Miscellaneous0 IRQ Settings */ +#define PIRQ_MISC1 0x0A /* Miscellaneous1 IRQ Settings */ +#define PIRQ_MISC2 0x0B /* Miscellaneous2 IRQ Settings */ +#define PIRQ_SIRQA 0x0C /* Serial IRQ INTA */ +#define PIRQ_SIRQB 0x0D /* Serial IRQ INTA */ +#define PIRQ_SIRQC 0x0E /* Serial IRQ INTA */ +#define PIRQ_SIRQD 0x0F /* Serial IRQ INTA */ +#define PIRQ_SCI 0x10 /* SCI IRQ */ +#define PIRQ_SMBUS 0x11 /* SMBUS 14h.0 */ +#define PIRQ_ASF 0x12 /* ASF */ +#define PIRQ_HDA 0x13 /* HDA 14h.2 */ +#define PIRQ_FC 0x14 /* FC */ +#define PIRQ_GEC 0x15 /* GEC */ +#define PIRQ_PMON 0x16 /* Performance Monitor */ +#define PIRQ_IMC0 0x20 /* IMC INT0 */ +#define PIRQ_IMC1 0x21 /* IMC INT1 */ +#define PIRQ_IMC2 0x22 /* IMC INT2 */ +#define PIRQ_IMC3 0x23 /* IMC INT3 */ +#define PIRQ_IMC4 0x24 /* IMC INT4 */ +#define PIRQ_IMC5 0x25 /* IMC INT5 */ +#define PIRQ_OHCI1 0x30 /* USB OHCI 12h.0 */ +#define PIRQ_EHCI1 0x31 /* USB EHCI 12h.2 */ +#define PIRQ_OHCI2 0x32 /* USB OHCI 13h.0 */ +#define PIRQ_EHCI2 0x33 /* USB EHCI 13h.2 */ +#define PIRQ_OHCI3 0x34 /* USB OHCI 16h.0 */ +#define PIRQ_EHCI3 0x35 /* USB EHCI 16h.2 */ +#define PIRQ_OHCI4 0x36 /* USB OHCI 14h.5 */ +#define PIRQ_IDE 0x40 /* IDE 14h.1 */ +#define PIRQ_SATA 0x41 /* SATA 11h.0 */ +#define PIRQ_SD 0x42 /* SD 14h.7 */ +#define PIRQ_GPP0 0x50 /* GPP INT 0 */ +#define PIRQ_GPP1 0x51 /* GPP INT 1 */ +#define PIRQ_GPP2 0x52 /* GPP INT 2 */ +#define PIRQ_GPP3 0x53 /* GPP INT 3 */ +#endif + +#endif /* AMD_PCI_INT_DEFS_H */ diff --git a/src/southbridge/amd/sb900/amd_pci_int_types.h b/src/southbridge/amd/sb900/amd_pci_int_types.h new file mode 100644 index 0000000..3d217fa --- /dev/null +++ b/src/southbridge/amd/sb900/amd_pci_int_types.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef AMD_PCI_INT_TYPES_H +#define AMD_PCI_INT_TYPES_H + +const char * intr_types[] = { + [0x00] = "INTA#\t", "INTB#\t", "INTC#\t", "INTD#\t", "INTE#\t", "INTF#\t", "INTG#\t", "INTH#\t", + [0x08] = "Misc\t", "Misc0\t", "Misc1\t", "Misc2\t", "Ser IRQ INTA", "Ser IRQ INTB", "Ser IRQ INTC", "Ser IRQ INTD", + [0x10] = "SCI\t", "SMBUS0\t", "ASF\t", "HDA\t", "SD\t\t", "GEC\t", "PerMon\t", + [0x20] = "IMC INT0\t", "IMC INT1\t", "IMC INT2\t", "IMC INT3\t", "IMC INT4\t", "IMC INT5\t", + [0x30] = "Dev18.0 INTA", "Dev18.2 INTB", "Dev19.0 INTA", "Dev19.2 INTB", "Dev22.0 INTA", "Dev22.2 INTB", "Dev20.5 INTC", + [0x40] = "IDE\t", "SATA\t", + [0x50] = "GPPInt0\t", "GPPInt1\t", "GPPInt2\t", "GPPInt3\t" +}; + +#endif /* AMD_PCI_INT_TYPES_H */ diff --git a/src/southbridge/amd/sb900/bootblock.c b/src/southbridge/amd/sb900/bootblock.c new file mode 100644 index 0000000..ee46443 --- /dev/null +++ b/src/southbridge/amd/sb900/bootblock.c @@ -0,0 +1,64 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_ids.h> + +/* + * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The SB900 power-on default is to map 512K ROM space. + * + */ +static void sb900_enable_rom(void) +{ + u8 reg8; + pci_devfn_t dev; + + dev = PCI_DEV(0, 0x14, 3); + + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 = pci_io_read_config8(dev, 0x48); + reg8 |= (1 << 3) | (1 << 4); + pci_io_write_config8(dev, 0x48, reg8); + + /* LPC ROM address range 1: */ + /* Enable LPC ROM range mirroring start at 0x000e(0000). */ + pci_io_write_config16(dev, 0x68, 0x000e); + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_io_write_config16(dev, 0x6a, 0x000f); + + /* LPC ROM address range 2: */ + /* + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + */ + pci_io_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_io_write_config16(dev, 0x6e, 0xffff); +} + +static void bootblock_southbridge_init(void) +{ + sb900_enable_rom(); +} diff --git a/src/southbridge/amd/sb900/chip.h b/src/southbridge/amd/sb900/chip.h new file mode 100644 index 0000000..fad0d13 --- /dev/null +++ b/src/southbridge/amd/sb900/chip.h @@ -0,0 +1,24 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SB900_CHIP_H +#define SB900_CHIP_H + +struct southbridge_amd_sb900_config +{ + u8 sd_mode; +}; + +#endif diff --git a/src/southbridge/amd/sb900/early_setup.c b/src/southbridge/amd/sb900/early_setup.c new file mode 100644 index 0000000..655b79e --- /dev/null +++ b/src/southbridge/amd/sb900/early_setup.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SB900_EARLY_SETUP_C_ +#define _SB900_EARLY_SETUP_C_ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <console/console.h> +#include <reset.h> +#include <arch/cpu.h> +#include <cbmem.h> +#include "sb900.h" + +void sb900_pci_port80(void) +{ + u8 byte; + device_t dev; + + /* P2P Bridge */ + dev = PCI_DEV(0, 0x14, 4); + + /* Chip Control: Enable subtractive decoding */ + byte = pci_read_config8(dev, 0x40); + byte |= 1 << 5; + pci_write_config8(dev, 0x40, byte); + + /* Misc Control: Enable subtractive decoding if 0x40 bit 5 is set */ + byte = pci_read_config8(dev, 0x4B); + byte |= 1 << 7; + pci_write_config8(dev, 0x4B, byte); + + /* The same IO Base and IO Limit here is meaningful because we set the + * bridge to be subtractive. During early setup stage, we have to make + * sure that data can go through port 0x80. + */ + /* IO Base: 0xf000 */ + byte = pci_read_config8(dev, 0x1C); + byte |= 0xF << 4; + pci_write_config8(dev, 0x1C, byte); + + /* IO Limit: 0xf000 */ + byte = pci_read_config8(dev, 0x1D); + byte |= 0xF << 4; + pci_write_config8(dev, 0x1D, byte); + + /* PCI Command: Enable IO response */ + byte = pci_read_config8(dev, 0x04); + byte |= 1 << 0; + pci_write_config8(dev, 0x04, byte); + + /* LPC controller */ + dev = PCI_DEV(0, 0x14, 3); + + byte = pci_read_config8(dev, 0x4A); + byte &= ~(1 << 5); /* disable lpc port 80 */ + pci_write_config8(dev, 0x4A, byte); +} + +void sb900_lpc_port80(void) +{ + u8 byte; + device_t dev; + + /* Enable LPC controller */ + outb(0xEC, 0xCD6); + byte = inb(0xCD7); + byte |= 1; + outb(0xEC, 0xCD6); + outb(byte, 0xCD7); + + /* Enable port 80 LPC decode in pci function 3 configuration space. */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x4a); + byte |= 1 << 5; /* enable port 80 */ + pci_write_config8(dev, 0x4a, byte); +} + +int s3_save_nvram_early(u32 dword, int size, int nvram_pos) +{ + int i; + printk(BIOS_DEBUG, "Writing %x of size %d to nvram pos: %d\n", dword, size, nvram_pos); + + for (i = 0; i<size; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } + + return nvram_pos; +} + +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos) +{ + u32 data = *old_dword; + int i; + for (i = 0; i<size; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + data &= ~(0xff << (i * 8)); + data |= inb(BIOSRAM_DATA) << (i *8); + nvram_pos++; + } + *old_dword = data; + printk(BIOS_DEBUG, "Loading %x of size %d to nvram pos:%d\n", *old_dword, size, + nvram_pos-size); + return nvram_pos; +} + +#endif diff --git a/src/southbridge/amd/sb900/enable_usbdebug.c b/src/southbridge/amd/sb900/enable_usbdebug.c new file mode 100644 index 0000000..ac66fcc --- /dev/null +++ b/src/southbridge/amd/sb900/enable_usbdebug.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <stdint.h> +#include <arch/io.h> +#include <device/pci_ehci.h> +#include <device/pci_def.h> +#include "sb900.h" + +#define DEBUGPORT_MISC_CONTROL 0x80 + +pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) +{ + if (hcd_idx==3) + return PCI_DEV(0, 0x16, 2); + else if (hcd_idx==2) + return PCI_DEV(0, 0x13, 2); + else + return PCI_DEV(0, 0x12, 2); +} + +void pci_ehci_dbg_set_port(pci_devfn_t dev, unsigned int port) +{ + u8 *base_regs = pci_ehci_base_regs(dev); + u32 reg32; + + /* Write the port number to DEBUGPORT_MISC_CONTROL[31:28]. */ + reg32 = read32(base_regs + DEBUGPORT_MISC_CONTROL); + reg32 &= ~(0xf << 28); + reg32 |= (port << 28); + reg32 |= (1 << 27); /* Enable Debug Port port number remapping. */ + write32(base_regs + DEBUGPORT_MISC_CONTROL, reg32); +} + + +void pci_ehci_dbg_enable(pci_devfn_t dev, unsigned long base) +{ + /* Enable all of the USB controllers */ + outb(0xEF, PM_INDEX); + outb(0x7F, PM_DATA); + + pci_write_config32(dev, EHCI_BAR_INDEX, base); + pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); +} diff --git a/src/southbridge/amd/sb900/fadt.c b/src/southbridge/amd/sb900/fadt.c new file mode 100644 index 0000000..2a37468 --- /dev/null +++ b/src/southbridge/amd/sb900/fadt.c @@ -0,0 +1,209 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * ACPI - create the Fixed ACPI Description Tables (FADT) + */ + +#include <string.h> +#include <console/console.h> +#include <arch/acpi.h> +#include <arch/io.h> +#include <device/device.h> +#include "sb900.h" +#include "smi.h" + +#define FADT_BOOT_ARCH (ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042) + +/* + * Reference section 5.2.9 Fixed ACPI Description Table (FADT) + * in the ACPI 3.0b specification. + */ +void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt) +{ + acpi_header_t *header = &(fadt->header); + + printk(BIOS_DEBUG, "pm_base: 0x%04x\n", SB900_ACPI_IO_BASE); + + /* Prepare the header */ + memset((void *)fadt, 0, sizeof(acpi_fadt_t)); + memcpy(header->signature, "FACP", 4); + header->length = sizeof(acpi_fadt_t); + header->revision = ACPI_FADT_REV_ACPI_3_0; + memcpy(header->oem_id, OEM_ID, 6); + memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); + memcpy(header->asl_compiler_id, ASLC, 4); + header->asl_compiler_revision = 0; + + if ((uintptr_t)facs > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: FACS lives above 4G\n"); + else + fadt->firmware_ctrl = (uintptr_t)facs; + + if ((uintptr_t)dsdt > 0xffffffff) + printk(BIOS_DEBUG, "ACPI: DSDT lives above 4G\n"); + else + fadt->dsdt = (uintptr_t)dsdt; + + fadt->model = 0; /* reserved, should be 0 ACPI 3.0 */ + fadt->preferred_pm_profile = PM_UNSPECIFIED; + fadt->sci_int = 9; /* SB900 - IRQ 09 – ACPI SCI */ + + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + fadt->smi_cmd = ACPI_SMI_CTL_PORT; + fadt->acpi_enable = ACPI_SMI_CMD_ENABLE; + fadt->acpi_disable = ACPI_SMI_CMD_DISABLE; + fadt->s4bios_req = 0; /* Not supported */ + fadt->pstate_cnt = 0; /* Not supported */ + fadt->cst_cnt = 0; /* Not supported */ + outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + } else { + fadt->smi_cmd = 0; /* disable system management mode */ + fadt->acpi_enable = 0; /* unused if SMI_CMD = 0 */ + fadt->acpi_disable = 0; /* unused if SMI_CMD = 0 */ + fadt->s4bios_req = 0; /* unused if SMI_CMD = 0 */ + fadt->pstate_cnt = 0; /* unused if SMI_CMD = 0 */ + fadt->cst_cnt = 0x00; /* unused if SMI_CMD = 0 */ + outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + } + + fadt->pm1a_evt_blk = ACPI_PM_EVT_BLK; + fadt->pm1b_evt_blk = 0x0000; + fadt->pm1a_cnt_blk = ACPI_PM1_CNT_BLK; + fadt->pm1b_cnt_blk = 0x0000; + fadt->pm2_cnt_blk = 0x0000; + fadt->pm_tmr_blk = ACPI_PM_TMR_BLK; + fadt->gpe0_blk = ACPI_GPE0_BLK; + fadt->gpe1_blk = 0x0000; /* No gpe1 block in sb900 */ + + fadt->pm1_evt_len = 4; /* 32 bits */ + fadt->pm1_cnt_len = 2; /* 16 bits */ + fadt->pm2_cnt_len = 0; + fadt->pm_tmr_len = 4; /* 32 bits */ + fadt->gpe0_blk_len = 8; /* 64 bits */ + fadt->gpe1_blk_len = 0; + fadt->gpe1_base = 0; + + fadt->p_lvl2_lat = ACPI_FADT_C2_NOT_SUPPORTED; + fadt->p_lvl3_lat = ACPI_FADT_C3_NOT_SUPPORTED; + fadt->flush_size = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->flush_stride = 0; /* set to 0 if WBINVD is 1 in flags */ + fadt->duty_offset = 1; /* CLK_VAL bits 3:1 */ + fadt->duty_width = 3; /* CLK_VAL bits 3:1 */ + fadt->day_alrm = 0; /* 0x7d these have to be */ + fadt->mon_alrm = 0; /* 0x7e added to cmos.layout */ + fadt->century = 0; /* 0x7f to make rtc alarm work */ + fadt->iapc_boot_arch = FADT_BOOT_ARCH; /* See table 5-10 */ + fadt->res2 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->flags = ACPI_FADT_WBINVD | /* See table 5-10 ACPI 3.0a spec */ + ACPI_FADT_C1_SUPPORTED | + ACPI_FADT_SLEEP_BUTTON | + ACPI_FADT_S4_RTC_WAKE | + ACPI_FADT_32BIT_TIMER | + ACPI_FADT_RESET_REGISTER | + ACPI_FADT_PCI_EXPRESS_WAKE | + ACPI_FADT_PLATFORM_CLOCK | + ACPI_FADT_S4_RTC_VALID | + ACPI_FADT_REMOTE_POWER_ON; + + /* Format is from 5.2.3.1: Generic Address Structure */ + /* reset_reg: see section 4.7.3.6 ACPI 3.0a spec */ + /* 8 bit write of value 0x06 to 0xCF9 in IO space */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0x0; + + fadt->reset_value = 6; + + fadt->res3 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res4 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + fadt->res5 = 0; /* reserved, MUST be 0 ACPI 3.0 */ + + + fadt->x_firmware_ctl_l = ((uintptr_t)facs) & 0xffffffff; + fadt->x_firmware_ctl_h = ((uint64_t)(uintptr_t)facs) >> 32; + fadt->x_dsdt_l = ((uintptr_t)dsdt) & 0xffffffff; + fadt->x_dsdt_h = ((uint64_t)(uintptr_t)dsdt) >> 32; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = 32; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->x_pm1a_evt_blk.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = ACPI_PM_EVT_BLK; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + fadt->x_pm1b_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_evt_blk.bit_width = 0; + fadt->x_pm1b_evt_blk.bit_offset = 0; + fadt->x_pm1b_evt_blk.access_size = 0; + fadt->x_pm1b_evt_blk.addrl = 0x0; + fadt->x_pm1b_evt_blk.addrh = 0x0; + + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = 16; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->x_pm1a_cnt_blk.access_size = 0; + fadt->x_pm1a_cnt_blk.addrl = ACPI_PM1_CNT_BLK; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + fadt->x_pm1b_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1b_cnt_blk.bit_width = 0; + fadt->x_pm1b_cnt_blk.bit_offset = 0; + fadt->x_pm1b_cnt_blk.access_size = 0; + fadt->x_pm1b_cnt_blk.addrl = 0x0; + fadt->x_pm1b_cnt_blk.addrh = 0x0; + + /* + * Note: Under this current AMD C state implementation, this is no longer + * used and should not be reported to OS. + */ + fadt->x_pm2_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm2_cnt_blk.bit_width = 0; + fadt->x_pm2_cnt_blk.bit_offset = 0; + fadt->x_pm2_cnt_blk.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->x_pm2_cnt_blk.addrl = 0; + fadt->x_pm2_cnt_blk.addrh = 0x0; + + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = 32; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->x_pm_tmr_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = ACPI_PM_TMR_BLK; + fadt->x_pm_tmr_blk.addrh = 0x0; + + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = 64; /* EventStatus + Event Enable */ + fadt->x_gpe0_blk.bit_offset = 0; + fadt->x_gpe0_blk.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = ACPI_GPE0_BLK; + fadt->x_gpe0_blk.addrh = 0x0; + + + fadt->x_gpe1_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe1_blk.bit_width = 0; + fadt->x_gpe1_blk.bit_offset = 0; + fadt->x_gpe1_blk.access_size = 0; + fadt->x_gpe1_blk.addrl = 0; + fadt->x_gpe1_blk.addrh = 0x0; + + header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t)); +} diff --git a/src/southbridge/amd/sb900/hda.c b/src/southbridge/amd/sb900/hda.c new file mode 100644 index 0000000..8b29580 --- /dev/null +++ b/src/southbridge/amd/sb900/hda.c @@ -0,0 +1,40 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include <delay.h> +#include "sb900.h" + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations hda_audio_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver hdaaudio_driver __pci_driver = { + .ops = &hda_audio_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_HDA, +}; diff --git a/src/southbridge/amd/sb900/ide.c b/src/southbridge/amd/sb900/ide.c new file mode 100644 index 0000000..144938c --- /dev/null +++ b/src/southbridge/amd/sb900/ide.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "sb900.h" + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations ide_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver ide_driver __pci_driver = { + .ops = &ide_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_IDE, +}; diff --git a/src/southbridge/amd/sb900/lpc.c b/src/southbridge/amd/sb900/lpc.c new file mode 100644 index 0000000..311b114 --- /dev/null +++ b/src/southbridge/amd/sb900/lpc.c @@ -0,0 +1,346 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pnp.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pci_def.h> +#include <pc80/mc146818rtc.h> +#include <pc80/isa-dma.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/acpi.h> +#include <pc80/i8254.h> +#include <pc80/i8259.h> +#include "sb900.h" + +static void lpc_init(device_t dev) +{ + u8 byte; + u32 dword; + device_t sm_dev; + + /* Enable the LPC Controller */ + sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); + dword = pci_read_config32(sm_dev, 0x64); + dword |= 1 << 20; + pci_write_config32(sm_dev, 0x64, dword); + + /* Initialize isa dma */ + isa_dma_init(); + + /* Enable DMA transaction on the LPC bus */ + byte = pci_read_config8(dev, 0x40); + byte |= (1 << 2); + pci_write_config8(dev, 0x40, byte); + + /* Disable the timeout mechanism on LPC */ + byte = pci_read_config8(dev, 0x48); + byte &= ~(1 << 7); + pci_write_config8(dev, 0x48, byte); + + /* Disable LPC MSI Capability */ + byte = pci_read_config8(dev, 0x78); + byte &= ~(1 << 1); + byte &= ~(1 << 0); /* Keep the old way. i.e., when bus master/DMA cycle is going + on on LPC, it holds PCI grant, so no LPC slave cycle can + interrupt and visit LPC. */ + pci_write_config8(dev, 0x78, byte); + + /* bit0: Enable prefetch a cacheline (64 bytes) when Host reads code from SPI rom */ + /* bit3: Fix SPI_CS# timing issue when running at 66M. TODO:A12. */ + byte = pci_read_config8(dev, 0xBB); + byte |= 1 << 0 | 1 << 3; + pci_write_config8(dev, 0xBB, byte); + + cmos_check_update_date(); + + /* Initialize the real time clock. + * The 0 argument tells cmos_init not to + * update CMOS unless it is invalid. + * 1 tells cmos_init to always initialize the CMOS. + */ + cmos_init(0); + + /* Initialize i8259 pic */ + setup_i8259 (); + + /* Initialize i8254 timers */ + setup_i8254 (); +} + +static void sb900_lpc_read_resources(device_t dev) +{ + struct resource *res; + + /* Get the normal pci resources of this device */ + pci_dev_read_resources(dev); /* We got one for APIC, or one more for TRAP */ + + /* Add an extra subtractive resource for both memory and I/O. */ + res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0)); + res->base = 0; + res->size = 0x1000; + res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + res = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0)); + res->base = 0xff800000; + res->size = 0x00800000; /* 8 MB for flash */ + res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | + IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + /* Add a memory resource for the SPI BAR. */ + fixed_mem_resource(dev, 2, SPI_BASE_ADDRESS / 1024, 1, IORESOURCE_SUBTRACTIVE); + + res = new_resource(dev, 3); /* IOAPIC */ + res->base = IO_APIC_ADDR; + res->size = 0x00001000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + + compact_resources(dev); +} + +static void sb900_lpc_set_resources(struct device *dev) +{ + struct resource *res; + + /* Special case. SPI Base Address. The SpiRomEnable should STAY set. */ + res = find_resource(dev, 2); + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, res->base | SPI_ROM_ENABLE); + + pci_dev_set_resources(dev); +} + +/** + * @brief Enable resources for children devices + * + * @param dev the device whose children's resources are to be enabled + * + */ +static void sb900_lpc_enable_childrens_resources(device_t dev) +{ + struct bus *link; + u32 reg, reg_x; + int var_num = 0; + u16 reg_var[3]; + u16 reg_size[1] = {512}; + u8 wiosize = pci_read_config8(dev, 0x74); + + /* Be bit relaxed, tolerate that LPC region might be bigger than resource we try to fit, + * do it like this for all regions < 16 bytes. If there is a resource > 16 bytes + * it must be 512 bytes to be able to allocate the fresh LPC window. + * + * AGESA likes to enable already one LPC region in wide port base 0x64-0x65, + * using DFLT_SIO_PME_BASE_ADDRESS, 512 bytes size + * The code tries to check if resource can fit into this region + */ + + reg = pci_read_config32(dev, 0x44); + reg_x = pci_read_config32(dev, 0x48); + + /* check if ranges are free and not use them if entry is just already taken */ + if (reg_x & (1 << 2)) + var_num = 1; + /* just in case check if someone did not manually set other ranges too */ + if (reg_x & (1 << 24)) + var_num = 2; + + if (reg_x & (1 << 25)) + var_num = 3; + + /* check AGESA region size */ + if (wiosize & (1 << 0)) + reg_size[0] = 16; + + reg_var[2] = pci_read_config16(dev, 0x90); + reg_var[1] = pci_read_config16(dev, 0x66); + reg_var[0] = pci_read_config16(dev, 0x64); + + for (link = dev->link_list; link; link = link->next) { + device_t child; + for (child = link->children; child; + child = child->sibling) { + if (child->enabled + && (child->path.type == DEVICE_PATH_PNP)) { + struct resource *res; + for (res = child->resource_list; res; res = res->next) { + u32 base, end; /* don't need long long */ + u32 rsize, set = 0, set_x = 0; + if (!(res->flags & IORESOURCE_IO)) + continue; + base = res->base; + end = resource_end(res); + /* find a resource size */ + printk(BIOS_DEBUG, "sb900 lpc decode:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); + switch (base) { + case 0x60: /* KB */ + case 0x64: /* MS */ + set |= (1 << 29); + rsize = 1; + break; + case 0x3f8: /* COM1 */ + set |= (1 << 6); + rsize = 8; + break; + case 0x2f8: /* COM2 */ + set |= (1 << 7); + rsize = 8; + break; + case 0x378: /* Parallel 1 */ + set |= (1 << 0); + set |= (1 << 1); /* + 0x778 for ECP */ + rsize = 8; + break; + case 0x3f0: /* FD0 */ + set |= (1 << 26); + rsize = 8; + break; + case 0x220: /* 0x220 - 0x227 */ + set |= (1 << 8); + rsize = 8; + break; + case 0x228: /* 0x228 - 0x22f */ + set |= (1 << 9); + rsize = 8; + break; + case 0x238: /* 0x238 - 0x23f */ + set |= (1 << 10); + rsize = 8; + break; + case 0x300: /* 0x300 -0x301 */ + set |= (1 << 18); + rsize = 2; + break; + case 0x400: + set_x |= (1 << 16); + rsize = 0x40; + break; + case 0x480: + set_x |= (1 << 17); + rsize = 0x40; + break; + case 0x500: + set_x |= (1 << 18); + rsize = 0x40; + break; + case 0x580: + set_x |= (1 << 19); + rsize = 0x40; + break; + case 0x4700: + set_x |= (1 << 22); + rsize = 0xc; + break; + case 0xfd60: + set_x |= (1 << 23); + rsize = 16; + break; + default: + rsize = 0; + /* try AGESA allocated region in region 0 */ + if ((var_num > 0) && ((base >=reg_var[0]) && + ((base + res->size) <= (reg_var[0] + reg_size[0])))) + rsize = reg_size[0]; + } + /* check if region found and matches the enable */ + if (res->size <= rsize) { + reg |= set; + reg_x |= set_x; + /* check if we can fit resource in variable range */ + } else if ((var_num < 3) && + ((res->size <= 16) || (res->size == 512))) { + /* use variable ranges if pre-defined do not match */ + switch (var_num) { + case 0: + reg_x |= (1 << 2); + if (res->size <= 16) { + wiosize |= (1 << 0); + } + break; + case 1: + reg_x |= (1 << 24); + if (res->size <= 16) + wiosize |= (1 << 2); + break; + case 2: + reg_x |= (1 << 25); + if (res->size <= 16) + wiosize |= (1 << 3); + break; + } + reg_var[var_num++] = + base & 0xffff; + } else { + printk(BIOS_ERR, "cannot fit LPC decode region:%s, base=0x%08x, end=0x%08x\n", + dev_path(child), base, end); + } + } + } + } + } + pci_write_config32(dev, 0x44, reg); + pci_write_config32(dev, 0x48, reg_x); + /* Set WideIO for as many IOs found (fall through is on purpose) */ + switch (var_num) { + case 3: + pci_write_config16(dev, 0x90, reg_var[2]); + /* fall through */ + case 2: + pci_write_config16(dev, 0x66, reg_var[1]); + /* fall through */ + case 1: + pci_write_config16(dev, 0x64, reg_var[0]); + break; + } + pci_write_config8(dev, 0x74, wiosize); +} + +static void sb900_lpc_enable_resources(device_t dev) +{ + pci_dev_enable_resources(dev); + sb900_lpc_enable_childrens_resources(dev); +} + +unsigned long acpi_fill_mcfg(unsigned long current) +{ + /* Just a dummy */ + return current; +} + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations lpc_ops = { + .read_resources = sb900_lpc_read_resources, + .set_resources = sb900_lpc_set_resources, + .enable_resources = sb900_lpc_enable_resources, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .write_acpi_tables = acpi_write_hpet, +#endif + .init = lpc_init, + .scan_bus = scan_lpc_bus, + .ops_pci = &lops_pci, +}; +static const struct pci_driver lpc_driver __pci_driver = { + .ops = &lpc_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_LPC, +}; diff --git a/src/southbridge/amd/sb900/pci.c b/src/southbridge/amd/sb900/pci.c new file mode 100644 index 0000000..aff0e26 --- /dev/null +++ b/src/southbridge/amd/sb900/pci.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "sb900.h" +#include "southbridge/amd/common/amd_pci_util.h" +#include <bootstate.h> + +/* + * Update the PCI devices with a valid IRQ number + * that is set in the mainboard PCI_IRQ structures. + */ +static void set_pci_irqs(void *unused) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* Write IRQs for all devicetree enabled devices */ + write_pci_cfg_irqs(); +} + +/* + * Hook this function into the PCI state machine + * on entry into BS_DEV_ENABLE. + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, set_pci_irqs, NULL); + +static struct pci_operations lops_pci = { + .set_subsystem = 0, +}; + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .init = DEVICE_NOOP, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pci_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCI, +}; diff --git a/src/southbridge/amd/sb900/pci_devs.h b/src/southbridge/amd/sb900/pci_devs.h new file mode 100644 index 0000000..88036c5 --- /dev/null +++ b/src/southbridge/amd/sb900/pci_devs.h @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SB900_PCI_DEVS_H_ +#define _SB900_PCI_DEVS_H_ + +#define BUS0 0 + +/* XHCI */ +#define XHCI_DEV 0x10 +#define XHCI_FUNC 0 +#define XHCI_DEVID 0x7814 +#define XHCI_DEVFN PCI_DEVFN(XHCI_DEV,XHCI_FUNC) + +/* SATA */ +#define SATA_DEV 0x11 +#define SATA_FUNC 0 +#define SATA_IDE_DEVID 0x7800 +#define AHCI_DEVID_MS 0x7801 +#define AHCI_DEVID_AMD 0x7804 +#define SATA_DEVFN PCI_DEVFN(SATA_DEV,SATA_FUNC) + +/* OHCI */ +#define OHCI1_DEV 0x12 +#define OHCI1_FUNC 0 +#define OHCI2_DEV 0x13 +#define OHCI2_FUNC 0 +#define OHCI3_DEV 0x16 +#define OHCI3_FUNC 0 +#define OHCI4_DEV 0x14 +#define OHCI4_FUNC 5 +#define OHCI_DEVID 0x7807 +#define OHCI1_DEVFN PCI_DEVFN(OHCI1_DEV,OHCI1_FUNC) +#define OHCI2_DEVFN PCI_DEVFN(OHCI2_DEV,OHCI2_FUNC) +#define OHCI3_DEVFN PCI_DEVFN(OHCI3_DEV,OHCI3_FUNC) +#define OHCI4_DEVFN PCI_DEVFN(OHCI4_DEV,OHCI4_FUNC) + +/* EHCI */ +#define EHCI1_DEV 0x12 +#define EHCI1_FUNC 2 +#define EHCI2_DEV 0x13 +#define EHCI2_FUNC 2 +#define EHCI3_DEV 0x16 +#define EHCI3_FUNC 2 +#define EHCI_DEVID 0x7808 +#define EHCI1_DEVFN PCI_DEVFN(EHCI1_DEV,EHCI1_FUNC) +#define EHCI2_DEVFN PCI_DEVFN(EHCI2_DEV,EHCI2_FUNC) +#define EHCI3_DEVFN PCI_DEVFN(EHCI3_DEV,EHCI3_FUNC) + +/* SMBUS */ +#define SMBUS_DEV 0x14 +#define SMBUS_FUNC 0 +#define SMBUS_DEVID 0x780B +#define SMBUS_DEVFN PCI_DEVFN(SMBUS_DEV,SMBUS_FUNC) + +/* IDE */ +#define IDE_DEV 0x14 +#define IDE_FUNC 1 +# define IDE_DEVID 0x780C +# define IDE_DEVFN PCI_DEVFN(IDE_DEV,IDE_FUNC) + +/* HD Audio */ +#define HDA_DEV 0x14 +#define HDA_FUNC 2 +#define HDA_DEVID 0x780D +#define HDA_DEVFN PCI_DEVFN(HDA_DEV,HDA_FUNC) + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_DEV PCU_DEV +#define LPC_FUNC 3 +#define LPC_DEVID 0x780E +#define LPC_DEVFN PCI_DEVFN(LPC_DEV,LPC_FUNC) + +/* PCI Ports */ +#define SB_PCI_PORT_DEV 0x14 +#define SB_PCI_PORT_FUNC 4 +# define SB_PCI_PORT_DEVID 0x780F +# define SB_PCI_PORT_DEVFN PCI_DEVFN(SB_PCI_PORT_DEV,SB_PCI_PORT_FUNC) + +/* SD Controller */ +#define SD_DEV 0x14 +#define SD_FUNC 7 +#define SD_DEVID 0x7806 +#define SD_DEVFN PCI_DEVFN(SD_DEV,SD_FUNC) + +/* PCIe Ports */ +#define SB_PCIE_DEV 0x15 +#define SB_PCIE_PORT1_FUNC 0 +#define SB_PCIE_PORT2_FUNC 1 +#define SB_PCIE_PORT3_FUNC 2 +#define SB_PCIE_PORT4_FUNC 3 +#define SB_PCIE_PORT1_DEVID 0x7820 +#define SB_PCIE_PORT2_DEVID 0x7821 +#define SB_PCIE_PORT3_DEVID 0x7822 +#define SB_PCIE_PORT4_DEVID 0x7823 +#define SB_PCIE_PORT1_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT1_FUNC) +#define SB_PCIE_PORT2_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT2_FUNC) +#define SB_PCIE_PORT3_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT3_FUNC) +#define SB_PCIE_PORT4_DEVFN PCI_DEVFN(SB_PCIE_DEV,SB_PCIE_PORT4_FUNC) + +#endif diff --git a/src/southbridge/amd/sb900/pcie.c b/src/southbridge/amd/sb900/pcie.c new file mode 100644 index 0000000..e090595 --- /dev/null +++ b/src/southbridge/amd/sb900/pcie.c @@ -0,0 +1,56 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include "sb900.h" + +static struct pci_operations lops_pci = { + .set_subsystem = 0, +}; + +static struct device_operations pci_ops = { + .read_resources = pci_bus_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_bus_enable_resources, + .scan_bus = pci_scan_bridge, + .reset_bus = pci_bus_reset, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver pciea_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEA, +}; + +static const struct pci_driver pcieb_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEB, +}; +static const struct pci_driver pciec_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIEC, +}; +static const struct pci_driver pcied_driver __pci_driver = { + .ops = &pci_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_PCIED, +}; diff --git a/src/southbridge/amd/sb900/ramtop.c b/src/southbridge/amd/sb900/ramtop.c new file mode 100644 index 0000000..01fd9d8 --- /dev/null +++ b/src/southbridge/amd/sb900/ramtop.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <arch/acpi.h> +#include <cbmem.h> +#include "sb900.h" + +int acpi_get_sleep_type(void) +{ + u16 tmp = inw(ACPI_PM1_CNT_BLK); + tmp = ((tmp & (7 << 10)) >> 10); + return (int)tmp; +} + +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) + +#ifndef __PRE_RAM__ +void backup_top_of_ram(uint64_t ramtop) +{ + u32 dword = (u32) ramtop; + int nvram_pos = 0xf8, i; /* temp */ + for (i = 0; i<4; i++) { + outb(nvram_pos, BIOSRAM_INDEX); + outb((dword >>(8 * i)) & 0xff , BIOSRAM_DATA); + nvram_pos++; + } +} +#endif + +unsigned long get_top_of_ram(void) +{ + uint32_t xdata = 0; + int xnvram_pos = 0xf8, xi; + if (acpi_get_sleep_type() != 3) + return 0; + for (xi = 0; xi<4; xi++) { + outb(xnvram_pos, BIOSRAM_INDEX); + xdata &= ~(0xff << (xi * 8)); + xdata |= inb(BIOSRAM_DATA) << (xi *8); + xnvram_pos++; + } + return (unsigned long) xdata; +} + +#endif diff --git a/src/southbridge/amd/sb900/reset.c b/src/southbridge/amd/sb900/reset.c new file mode 100644 index 0000000..200ec14 --- /dev/null +++ b/src/southbridge/amd/sb900/reset.c @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +// Use simple device model for this file even in ramstage +#define __SIMPLE_DEVICE__ + +#include <arch/io.h> +#include <reset.h> + +#include <northbridge/amd/amdk8/reset_test.c> + +void hard_reset(void) +{ + set_bios_reset(); + /* Try rebooting through port 0xcf9 */ + /* Actually it is not a real hard_reset --- it only reset coherent link table, but not reset link freq and width */ + outb((0 << 3) | (0 << 2) | (1 << 1), 0xcf9); + outb((0 << 3) | (1 << 2) | (1 << 1), 0xcf9); +} diff --git a/src/southbridge/amd/sb900/sata.c b/src/southbridge/amd/sb900/sata.c new file mode 100644 index 0000000..d65183b --- /dev/null +++ b/src/southbridge/amd/sb900/sata.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <delay.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <arch/io.h> +#include "sb900.h" + +static struct device_operations sata_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, +}; + +static const struct pci_driver sata0_driver __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_SATA, +}; + +static const struct pci_driver sata0_driver_ahci __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_SATA_AHCI, +}; diff --git a/src/southbridge/amd/sb900/sb900.c b/src/southbridge/amd/sb900/sb900.c new file mode 100644 index 0000000..5a214f8 --- /dev/null +++ b/src/southbridge/amd/sb900/sb900.c @@ -0,0 +1,181 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> + +#include <arch/io.h> +#include <arch/acpi.h> + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <cbmem.h> +#include "sb900.h" +#include "smbus.h" +#include "smi.h" + +#define PM_MMIO_BASE 0xfed80300 + +void pm_write8(u8 reg, u8 value) +{ + write8((void *)((uintptr_t)PM_MMIO_BASE + reg), value); +} + +u8 pm_read8(u8 reg) +{ + return read8((void *)((uintptr_t)PM_MMIO_BASE + reg)); +} + +void pm_write16(u8 reg, u16 value) +{ + write16((void *)((uintptr_t)PM_MMIO_BASE + reg), value); +} + +u16 pm_read16(u16 reg) +{ + return read16((void *)((uintptr_t)PM_MMIO_BASE + reg)); +} + +#define PM_REG_USB_ENABLE 0xef + +enum usb_enable { + USB_EN_DEVFN_12_0 = (1 << 0), + USB_EN_DEVFN_12_2 = (1 << 1), + USB_EN_DEVFN_13_0 = (1 << 2), + USB_EN_DEVFN_13_2 = (1 << 3), + USB_EN_DEVFN_16_0 = (1 << 4), + USB_EN_DEVFN_16_2 = (1 << 5), +}; + +static void sb900_disable_usb(u8 disable) +{ + u8 reg8; + + /* Bit 7 handles routing, 6 is reserved. we don't mess with those */ + disable &= 0x3f; + + reg8 = pm_read8(PM_REG_USB_ENABLE); + reg8 &= ~disable; + pm_write8(PM_REG_USB_ENABLE, reg8); +} + +void sb900_enable(device_t dev) +{ + printk(BIOS_DEBUG, "sb900_enable()\n"); + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0x14, 5): + if (dev->enabled == 0) { + // read the VENDEV ID + device_t usb_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 5)); + u32 usb_device_id = pci_read_config32(usb_dev, 0) >> 16; + u8 reg8; + if (usb_device_id == PCI_DEVICE_ID_ATI_SB900_USB_20_5) { + /* turn off and remove device 0:14.5 from PCI space */ + reg8 = pm_read8(0xef); + reg8 &= ~(1 << 6); + pm_write8(0xef, reg8); + } + } + break; + + case PCI_DEVFN(0x14, 7): + if (dev->enabled == 0) { + // read the VENDEV ID + device_t sd_dev = dev_find_slot( 0, PCI_DEVFN( 0x14, 7)); + u32 sd_device_id = pci_read_config32( sd_dev, 0) >> 16; + /* turn off the SDHC controller in the PM reg */ + u8 reg8; + if (sd_device_id == PCI_DEVICE_ID_AMD_HUDSON_SD) { + reg8 = pm_read8(0xe7); + reg8 &= ~(1 << 0); + pm_write8(0xe7, reg8); + } + else if (sd_device_id == PCI_DEVICE_ID_AMD_YANGTZE_SD) { + reg8 = pm_read8(0xe8); + reg8 &= ~(1 << 0); + pm_write8(0xe8, reg8); + } + /* remove device 0:14.7 from PCI space */ + reg8 = pm_read8(0xd3); + reg8 &= ~(1 << 6); + pm_write8(0xd3, reg8); + } + break; + + /* Make sure to disable other functions if function 0 is disabled */ + case PCI_DEVFN(0x12, 0): + if (dev->enabled == 0) + sb900_disable_usb(USB_EN_DEVFN_12_0); + case PCI_DEVFN(0x12, 2): /* Fall through */ + if (dev->enabled == 0) + sb900_disable_usb(USB_EN_DEVFN_12_2); + break; + case PCI_DEVFN(0x13, 0): + if (dev->enabled == 0) + sb900_disable_usb(USB_EN_DEVFN_13_0); + case PCI_DEVFN(0x13, 2): /* Fall through */ + if (dev->enabled == 0) + sb900_disable_usb(USB_EN_DEVFN_13_2); + break; + case PCI_DEVFN(0x16, 0): + if (dev->enabled == 0) + sb900_disable_usb(USB_EN_DEVFN_16_0); + case PCI_DEVFN(0x16, 2): /* Fall through */ + if (dev->enabled == 0) + sb900_disable_usb(USB_EN_DEVFN_16_2); + break; + default: + break; + } +} + +static void sb900_init_acpi_ports(void) +{ + /* We use some of these ports in SMM regardless of whether or not + * ACPI tables are generated. Enable these ports indiscriminately. + */ + + pm_write16(0x60, ACPI_PM_EVT_BLK); + pm_write16(0x62, ACPI_PM1_CNT_BLK); + pm_write16(0x64, ACPI_PM_TMR_BLK); + pm_write16(0x68, ACPI_GPE0_BLK); + /* CpuControl is in \_PR.CP00, 6 bytes */ + pm_write16(0x66, ACPI_CPU_CONTROL); + + if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) { + pm_write16(0x6a, ACPI_SMI_CTL_PORT); + sb900_enable_acpi_cmd_smi(); + } else { + pm_write16(0x6a, 0); + } + + /* AcpiDecodeEnable, When set, SB uses the contents of the PM registers + * at index 60-6B to decode ACPI I/O address. AcpiSmiEn & SmiCmdEn + */ + pm_write8(0x74, 1<<0 | 1<<1 | 1<<4 | 1<<2); +} + +static void sb900_init(void *chip_info) +{ + sb900_init_acpi_ports(); +} + +struct chip_operations southbridge_amd_sb900_ops = { + CHIP_NAME("AMD SB900") + .enable_dev = sb900_enable, + .init = sb900_init, +}; diff --git a/src/southbridge/amd/sb900/sb900.h b/src/southbridge/amd/sb900/sb900.h new file mode 100644 index 0000000..53c00f5 --- /dev/null +++ b/src/southbridge/amd/sb900/sb900.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2014 Sage Electronic Engineering, LLC + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SB900_H +#define SB900_H + +#include <device/pci_ids.h> +#include <device/device.h> +#include "chip.h" + +/* Power management index/data registers */ +#define BIOSRAM_INDEX 0xcd4 +#define BIOSRAM_DATA 0xcd5 +#define PM_INDEX 0xcd6 +#define PM_DATA 0xcd7 +#define PM2_INDEX 0xcd0 +#define PM2_DATA 0xcd1 + +#define SB900_ACPI_IO_BASE 0x800 + +#define ACPI_PM_EVT_BLK (SB900_ACPI_IO_BASE + 0x00) /* 4 bytes */ +#define ACPI_PM1_CNT_BLK (SB900_ACPI_IO_BASE + 0x04) /* 2 bytes */ +#define ACPI_PM_TMR_BLK (SB900_ACPI_IO_BASE + 0x18) /* 4 bytes */ +#define ACPI_GPE0_BLK (SB900_ACPI_IO_BASE + 0x10) /* 8 bytes */ +#define ACPI_CPU_CONTROL (SB900_ACPI_IO_BASE + 0x08) /* 6 bytes */ + +#define ACPI_SMI_CTL_PORT 0xb2 +#define ACPI_SMI_CMD_CST_CONTROL 0xde +#define ACPI_SMI_CMD_PST_CONTROL 0xad +#define ACPI_SMI_CMD_DISABLE 0xbe +#define ACPI_SMI_CMD_ENABLE 0xef +#define ACPI_SMI_CMD_S4_REQ 0xc0 + +#define REV_SB900_A11 0x11 +#define REV_SB900_A12 0x12 + +#define SPIROM_BASE_ADDRESS_REGISTER 0xA0 +#define SPI_ROM_ENABLE 0x02 +#define SPI_BASE_ADDRESS 0xFEC10000 + +static inline int sb900_sata_enable(void) +{ + return 1; +} + +static inline int sb900_ide_enable(void) +{ + return 0; +} + +#ifndef __SMM__ + +void pm_write8(u8 reg, u8 value); +u8 pm_read8(u8 reg); +void pm_write16(u8 reg, u16 value); +u16 pm_read16(u16 reg); + +#ifdef __PRE_RAM__ +void sb900_lpc_port80(void); +void sb900_pci_port80(void); +void sb900_clk_output_48Mhz(void); + +int s3_save_nvram_early(u32 dword, int size, int nvram_pos); +int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); + +#else +void sb900_enable(device_t dev); +void s3_resume_init_data(void *FchParams); + +#endif /* __PRE_RAM__ */ +#endif /* __SMM__ */ + +#endif /* SB900_H */ diff --git a/src/southbridge/amd/sb900/sm.c b/src/southbridge/amd/sb900/sm.c new file mode 100644 index 0000000..31cfd7b --- /dev/null +++ b/src/southbridge/amd/sb900/sm.c @@ -0,0 +1,114 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/smbus.h> +#include <pc80/mc146818rtc.h> +#include <arch/io.h> +#include <cpu/x86/lapic.h> +#include <arch/ioapic.h> +#include <stdlib.h> +#include "sb900.h" +#include "smbus.c" + +static void sm_init(device_t dev) +{ + setup_ioapic(VIO_APIC_VADDR, CONFIG_MAX_CPUS); +} + +static int lsmbus_recv_byte(device_t dev) +{ + u32 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x90); + + return do_smbus_recv_byte(res->base, device); +} + +static int lsmbus_send_byte(device_t dev, u8 val) +{ + u32 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x90); + + return do_smbus_send_byte(res->base, device, val); +} + +static int lsmbus_read_byte(device_t dev, u8 address) +{ + u32 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x90); + + return do_smbus_read_byte(res->base, device, address); +} + +static int lsmbus_write_byte(device_t dev, u8 address, u8 val) +{ + u32 device; + struct resource *res; + struct bus *pbus; + + device = dev->path.i2c.device; + pbus = get_pbus_smbus(dev); + + res = find_resource(pbus->dev, 0x90); + + return do_smbus_write_byte(res->base, device, address, val); +} +static struct smbus_bus_operations lops_smbus_bus = { + .recv_byte = lsmbus_recv_byte, + .send_byte = lsmbus_send_byte, + .read_byte = lsmbus_read_byte, + .write_byte = lsmbus_write_byte, +}; + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; +static struct device_operations smbus_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = pci_dev_enable_resources, + .init = sm_init, + .scan_bus = scan_smbus, + .ops_pci = &lops_pci, + .ops_smbus_bus = &lops_smbus_bus, +}; +static const struct pci_driver smbus_driver __pci_driver = { + .ops = &smbus_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_SM, +}; diff --git a/src/southbridge/amd/sb900/smbus.c b/src/southbridge/amd/sb900/smbus.c new file mode 100644 index 0000000..fed5272 --- /dev/null +++ b/src/southbridge/amd/sb900/smbus.c @@ -0,0 +1,246 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SB900_SMBUS_C_ +#define _SB900_SMBUS_C_ + +#include <io.h> +#include <stdint.h> +#include "smbus.h" + +static int smbus_wait_until_ready(u32 smbus_io_base) +{ + u32 loops; + loops = SMBUS_TIMEOUT; + do { + u8 val; + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; + if (val == 0) { /* ready now */ + return 0; + } + outb(val, smbus_io_base + SMBHSTSTAT); + } while (--loops); + return -2; /* time out */ +} + +static int smbus_wait_until_done(u32 smbus_io_base) +{ + u32 loops; + loops = SMBUS_TIMEOUT; + do { + u8 val; + + val = inb(smbus_io_base + SMBHSTSTAT); + val &= 0x1f; /* mask off reserved bits */ + if (val & 0x1c) { + return -5; /* error */ + } + if (val == 0x02) { + outb(val, smbus_io_base + SMBHSTSTAT); /* clear status */ + return 0; + } + } while (--loops); + return -3; /* timeout */ +} + +int do_smbus_recv_byte(u32 smbus_io_base, u32 device) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTCMD); + + return byte; +} + +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + /* set the command... */ + outb(val, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 2) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + return 0; +} + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, + u32 address) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 1, smbus_io_base + SMBHSTADDR); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + /* read results of transaction */ + byte = inb(smbus_io_base + SMBHSTDAT0); + + return byte; +} + +int do_smbus_write_byte(u32 smbus_io_base, u32 device, + u32 address, u8 val) +{ + u8 byte; + + if (smbus_wait_until_ready(smbus_io_base) < 0) { + return -2; /* not ready */ + } + + /* set the command/address... */ + outb(address & 0xff, smbus_io_base + SMBHSTCMD); + + /* set the device I'm talking too */ + outb(((device & 0x7f) << 1) | 0, smbus_io_base + SMBHSTADDR); + + /* output value */ + outb(val, smbus_io_base + SMBHSTDAT0); + + byte = inb(smbus_io_base + SMBHSTCTRL); + byte &= 0xe3; /* Clear [4:2] */ + byte |= (1 << 3) | (1 << 6); /* Byte data read/write command, start the command */ + outb(byte, smbus_io_base + SMBHSTCTRL); + + /* poll for transaction completion */ + if (smbus_wait_until_done(smbus_io_base) < 0) { + return -3; /* timeout or error */ + } + + return 0; +} + +void alink_ab_indx(u32 reg_space, u32 reg_addr, + u32 mask, u32 val) +{ + u32 tmp; + + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | reg_addr); */ + outl((reg_space & 0x7) << 29 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} + +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, + u32 mask, u32 val) +{ + u32 tmp; + + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); + tmp = inl(AB_DATA); + /* rpr 4.2 + * For certain revisions of the chip, the ABCFG registers, + * with an address of 0x100NN (where 'N' is any hexadecimal + * number), require an extra programming step.*/ + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + //printk(BIOS_DEBUG, "about write %x, index=%x", tmp, (reg_space&0x3)<<29 | (port&3) << 24 | reg_addr); + outl((reg_space & 0x7) << 29 | (port & 3) << 24 | reg_addr, AB_INDX); /* probably we dont have to do it again. */ + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} + +/* space = 0: AX_INDXC, AX_DATAC + * space = 1: AX_INDXP, AX_DATAP + */ +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, + u32 mask, u32 val) +{ + u32 tmp; + + /* read axindc to tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + tmp = inl(AB_DATA); + outl(0, AB_INDX); + + tmp &= ~mask; + tmp |= val; + + /* write tmp */ + outl(space << 29 | space << 3 | 0x30, AB_INDX); + outl(axindc, AB_DATA); + outl(0, AB_INDX); + outl(space << 29 | space << 3 | 0x34, AB_INDX); + outl(tmp, AB_DATA); + outl(0, AB_INDX); +} +#endif diff --git a/src/southbridge/amd/sb900/smbus.h b/src/southbridge/amd/sb900/smbus.h new file mode 100644 index 0000000..9d693cc --- /dev/null +++ b/src/southbridge/amd/sb900/smbus.h @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SB900_SMBUS_H +#define SB900_SMBUS_H + +#include <stdint.h> + +#define SMBHSTSTAT 0x0 +#define SMBSLVSTAT 0x1 +#define SMBHSTCTRL 0x2 +#define SMBHSTCMD 0x3 +#define SMBHSTADDR 0x4 +#define SMBHSTDAT0 0x5 +#define SMBHSTDAT1 0x6 +#define SMBHSTBLKDAT 0x7 + +#define SMBSLVCTRL 0x8 +#define SMBSLVCMD_SHADOW 0x9 +#define SMBSLVEVT 0xa +#define SMBSLVDAT 0xc + +#define AX_INDXC 0 +#define AX_INDXP 2 +#define AXCFG 4 +#define ABCFG 6 +#define RC_INDXC 1 +#define RC_INDXP 3 + +#define AB_INDX 0xCD8 +#define AB_DATA (AB_INDX+4) + +/* Between 1-10 seconds, We should never timeout normally + * Longer than this is just painful when a timeout condition occurs. + */ +#define SMBUS_TIMEOUT (100*1000*10) + +#define abcfg_reg(reg, mask, val) \ + alink_ab_indx((ABCFG), (reg), (mask), (val)) +#define axcfg_reg(reg, mask, val) \ + alink_ab_indx((AXCFG), (reg), (mask), (val)) +#define axindxc_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXC), (reg), (mask), (val)) +#define axindxp_reg(reg, mask, val) \ + alink_ax_indx((AX_INDXP), (reg), (mask), (val)) +#define rcindxc_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXC), (reg), (port), (mask), (val)) +#define rcindxp_reg(reg, port, mask, val) \ + alink_rc_indx((RC_INDXP), (reg), (port), (mask), (val)) + +int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address); +int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val); +int do_smbus_recv_byte(u32 smbus_io_base, u32 device); +int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val); +void alink_rc_indx(u32 reg_space, u32 reg_addr, u32 port, u32 mask, u32 val); +void alink_ab_indx(u32 reg_space, u32 reg_addr, u32 mask, u32 val); +void alink_ax_indx(u32 space /*c or p? */ , u32 axindc, u32 mask, u32 val); + +#endif diff --git a/src/southbridge/amd/sb900/smi.c b/src/southbridge/amd/sb900/smi.c new file mode 100644 index 0000000..c4ec41d --- /dev/null +++ b/src/southbridge/amd/sb900/smi.c @@ -0,0 +1,25 @@ +/* + * Utilities for SMM setup + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "smi.h" + +#include <console/console.h> +#include <cpu/cpu.h> + +void smm_setup_structures(void *gnvs, void *tcg, void *smi1) +{ + printk(BIOS_DEBUG, "smm_setup_structures STUB!!!\n"); +} + +/** Set the EOS bit and enable SMI generation from southbridge */ +void sb900_enable_smi_generation(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ + reg |= SMITRG0_EOS; /* Set EOS bit */ + smi_write32(SMI_REG_SMITRIG0, reg); +} diff --git a/src/southbridge/amd/sb900/smi.h b/src/southbridge/amd/sb900/smi.h new file mode 100644 index 0000000..8f20f8b --- /dev/null +++ b/src/southbridge/amd/sb900/smi.h @@ -0,0 +1,65 @@ +/* + * Utilities for SMI handlers and SMM setup + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#ifndef _SOUTHBRIDGE_AMD_SB900_SMI_H +#define _SOUTHBRIDGE_AMD_SB900_SMI_H + +#include <arch/io.h> + +/* ACPI_MMIO_BASE + 0x200 -- leave this string here so grep catches it. + * This is defined by AGESA, but we dpn't include AGESA headers to avoid + * polluting the namesace. + */ +#define SMI_BASE 0xfed80200 + +#define SMI_REG_SMITRIG0 0x98 +#define SMITRG0_EOS (1 << 28) +#define SMITRG0_SMIENB (1 << 31) + +#define SMI_REG_CONTROL0 0xa0 + +enum smi_mode { + SMI_MODE_DISABLE = 0, + SMI_MODE_SMI = 1, + SMI_MODE_NMI = 2, + SMI_MODE_IRQ13 = 3, +}; + +enum smi_lvl { + SMI_LVL_LOW = 0, + SMI_LVL_HIGH = 1, +}; + +static inline uint32_t smi_read32(uint8_t offset) +{ + return read32((void *)((uintptr_t)SMI_BASE + offset)); +} + +static inline void smi_write32(uint8_t offset, uint32_t value) +{ + write32((void *)((uintptr_t)SMI_BASE + offset), value); +} + +static inline uint16_t smi_read16(uint8_t offset) +{ + return read16((void *)((uintptr_t)SMI_BASE + offset)); +} + +static inline void smi_write16(uint8_t offset, uint16_t value) +{ + write16((void *)((uintptr_t)SMI_BASE + offset), value); +} + +void sb900_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level); +void sb900_disable_gevent_smi(uint8_t gevent); +void sb900_enable_acpi_cmd_smi(void); + +#ifndef __SMM__ +void sb900_enable_smi_generation(void); +#endif + +#endif /* _SOUTHBRIDGE_AMD_SB900_SMI_H */ diff --git a/src/southbridge/amd/sb900/smi_util.c b/src/southbridge/amd/sb900/smi_util.c new file mode 100644 index 0000000..3c2cd20 --- /dev/null +++ b/src/southbridge/amd/sb900/smi_util.c @@ -0,0 +1,79 @@ +/* + * SMM utilities used in both SMM and normal mode + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "smi.h" + +#include <console/console.h> + +#define SB900_SMI_ACPI_COMMAND 75 + +static void configure_smi(uint8_t smi_num, uint8_t mode) +{ + uint8_t reg32_offset, bit_offset; + uint32_t reg32; + + /* SMI sources range from [0:149] */ + if (smi_num > 149) { + printk(BIOS_WARNING, "BUG: Invalid SMI: %u\n", smi_num); + return; + } + + /* 16 sources per register, 2 bits per source; registers are 4 bytes */ + reg32_offset = (smi_num / 16) * 4; + bit_offset = (smi_num % 16) * 2; + + reg32 = smi_read32(SMI_REG_CONTROL0 + reg32_offset); + reg32 &= ~(0x3 << (bit_offset)); + reg32 |= (mode & 0x3) << bit_offset; + smi_write32(SMI_REG_CONTROL0 + reg32_offset, reg32); +} + +/** + * Configure generation of interrupts for given GEVENT pin + * + * @param gevent The GEVENT pin number. Valid values are 0 thru 23 + * @param mode The type of event this pin should generate. Note that only + * SMI_MODE_SMI generates an SMI. SMI_MODE_DISABLE disables events. + * @param level SMI_LVL_LOW or SMI_LVL_HIGH + */ +void sb900_configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level) +{ + uint32_t reg32; + /* GEVENT pins range from [0:23] */ + if (gevent > 23) { + printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); + return; + } + + /* SMI0 source is GEVENT0 and so on */ + configure_smi(gevent, mode); + + /* And set set the trigger level */ + reg32 = smi_read32(SMI_REG_SMITRIG0); + reg32 &= ~(1 << gevent); + reg32 |= (level & 0x1) << gevent; + smi_write32(SMI_REG_SMITRIG0, reg32); +} + +/** Disable events from given GEVENT pin */ +void sb900_disable_gevent_smi(uint8_t gevent) +{ + /* GEVENT pins range from [0:23] */ + if (gevent > 23) { + printk(BIOS_WARNING, "BUG: Invalid GEVENT: %u\n", gevent); + return; + } + + /* SMI0 source is GEVENT0 and so on */ + configure_smi(gevent, SMI_MODE_DISABLE); +} + +/** Enable SMIs on writes to ACPI SMI command port */ +void sb900_enable_acpi_cmd_smi(void) +{ + configure_smi(SB900_SMI_ACPI_COMMAND, SMI_MODE_SMI); +} diff --git a/src/southbridge/amd/sb900/smihandler.c b/src/southbridge/amd/sb900/smihandler.c new file mode 100644 index 0000000..1c9a2ec --- /dev/null +++ b/src/southbridge/amd/sb900/smihandler.c @@ -0,0 +1,134 @@ +/* + * SMI handler for SB900 southbridges + * + * Copyright (C) 2014 Alexandru Gagniuc <mr.nuke.me(a)gmail.com> + * Subject to the GNU GPL v2, or (at your option) any later version. + */ + +#include "sb900.h" +#include "smi.h" + +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <delay.h> + +#define SMI_0x88_ACPI_COMMAND (1 << 11) + +enum smi_source { + SMI_SOURCE_SCI = (1 << 0), + SMI_SOURCE_GPE = (1 << 1), + SMI_SOURCE_0x84 = (1 << 2), + SMI_SOURCE_0x88 = (1 << 3), + SMI_SOURCE_IRQ_TRAP = (1 << 4), + SMI_SOURCE_0x90 = (1 << 5) +}; + +static void sb900_apmc_smi_handler(void) +{ + u32 reg32; + const uint8_t cmd = inb(ACPI_SMI_CTL_PORT); + + switch (cmd) { + case ACPI_SMI_CMD_ENABLE: + reg32 = inl(ACPI_PM1_CNT_BLK); + reg32 |= (1 << 0); /* SCI_EN */ + outl(reg32, ACPI_PM1_CNT_BLK); + break; + case ACPI_SMI_CMD_DISABLE: + reg32 = inl(ACPI_PM1_CNT_BLK); + reg32 &= ~(1 << 0); /* clear SCI_EN */ + outl(ACPI_PM1_CNT_BLK, reg32); + break; + } + + mainboard_smi_apmc(cmd); +} + +int southbridge_io_trap_handler(int smif) +{ + return 0; +} + +static void process_smi_sci(void) +{ + const uint32_t status = smi_read32(0x10); + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x10, status); +} + +static void process_gpe_smi(void) +{ + const uint32_t status = smi_read32(0x80); + const uint32_t gevent_mask = (1 << 24) - 1; + + /* Only Bits [23:0] indicate GEVENT SMIs. */ + if (status & gevent_mask) { + /* A GEVENT SMI occurred */ + mainboard_smi_gpi(status & gevent_mask); + } + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x80, status); +} + +static void process_smi_0x84(void) +{ + const uint32_t status = smi_read32(0x84); + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x84, status); +} + +static void process_smi_0x88(void) +{ + const uint32_t status = smi_read32(0x88); + + if (status & SMI_0x88_ACPI_COMMAND) { + /* Command received via ACPI SMI command port */ + sb900_apmc_smi_handler(); + } + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x88, status); +} + +static void process_smi_0x8c(void) +{ + const uint32_t status = smi_read32(0x8c); + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x8c, status); +} + +static void process_smi_0x90(void) +{ + const uint32_t status = smi_read32(0x90); + + /* Clear events to prevent re-entering SMI if event isn't handled */ + smi_write32(0x90, status); +} + +void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save) +{ + const uint16_t smi_src = smi_read16(0x94); + + if (smi_src & SMI_SOURCE_SCI) + process_smi_sci(); + if (smi_src & SMI_SOURCE_GPE) + process_gpe_smi(); + if (smi_src & SMI_SOURCE_0x84) + process_smi_0x84(); + if (smi_src & SMI_SOURCE_0x88) + process_smi_0x88(); + if (smi_src & SMI_SOURCE_IRQ_TRAP) + process_smi_0x8c(); + if (smi_src & SMI_SOURCE_0x90) + process_smi_0x90(); +} + +void southbridge_smi_set_eos(void) +{ + uint32_t reg = smi_read32(SMI_REG_SMITRIG0); + reg |= SMITRG0_EOS; + smi_write32(SMI_REG_SMITRIG0, reg); +} diff --git a/src/southbridge/amd/sb900/usb.c b/src/southbridge/amd/sb900/usb.c new file mode 100644 index 0000000..5087ddb --- /dev/null +++ b/src/southbridge/amd/sb900/usb.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2010 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <device/pci_ops.h> +#include <device/pci_ehci.h> +#include <arch/io.h> +#include "sb900.h" + +static struct pci_operations lops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +static struct device_operations usb_ops = { + .read_resources = pci_ehci_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .ops_pci = &lops_pci, +}; + +static const struct pci_driver usb_0_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_18_0, +}; +static const struct pci_driver usb_1_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_18_2, +}; + +static const struct pci_driver usb_4_driver __pci_driver = { + .ops = &usb_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = PCI_DEVICE_ID_ATI_SB900_USB_20_5, +};

1 0

Patch set updated for coreboot: northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity)
by Damien Zammit 26 Feb '16

26 Feb '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13710 -gerrit commit 53c544e09b33424e5a211c71f6732e946666fc4f Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Feb 10 14:01:36 2016 +1100 northbridge/amd/amdfam10: Add family15h model10h-1fh (Trinity) Change-Id: I96d695ed10176276116fcf3a2b77605fb3f2d5db Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/amd/amdfam10/amdfam10_util.c | 1 + src/northbridge/amd/amdfam10/link_control.c | 7 +++++++ src/northbridge/amd/amdfam10/misc_control.c | 29 +++++++++++++++++++++++++-- src/northbridge/amd/amdfam10/nb_control.c | 10 +++++++-- src/northbridge/amd/amdfam10/northbridge.c | 10 ++++++--- src/northbridge/amd/amdfam10/raminit_amdmct.c | 3 +++ src/northbridge/amd/amdht/ht_wrapper.c | 5 +++++ src/northbridge/amd/amdmct/amddefs.h | 1 + src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 11 +++++++--- 9 files changed, 67 insertions(+), 10 deletions(-) diff --git a/src/northbridge/amd/amdfam10/amdfam10_util.c b/src/northbridge/amd/amdfam10/amdfam10_util.c index 0ef6c92..c9b30f8 100644 --- a/src/northbridge/amd/amdfam10/amdfam10_util.c +++ b/src/northbridge/amd/amdfam10/amdfam10_util.c @@ -101,6 +101,7 @@ uint64_t mctGetLogicalCPUID(u32 Node) ret = AMD_OR_B2; break; case 0x15020: + case 0x15101: ret = AMD_OR_C0; break; default: diff --git a/src/northbridge/amd/amdfam10/link_control.c b/src/northbridge/amd/amdfam10/link_control.c index d0d894c..468f184 100644 --- a/src/northbridge/amd/amdfam10/link_control.c +++ b/src/northbridge/amd/amdfam10/link_control.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -154,6 +155,12 @@ static const struct pci_driver mcf4_driver_fam10 __pci_driver = { .device = 0x1204, }; +static const struct pci_driver mcf4_driver_fam15_model10 __pci_driver = { + .ops = &mcf4_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1404, +}; + static const struct pci_driver mcf4_driver_fam15 __pci_driver = { .ops = &mcf4_ops, .vendor = PCI_VENDOR_ID_AMD, diff --git a/src/northbridge/amd/amdfam10/misc_control.c b/src/northbridge/amd/amdfam10/misc_control.c index 4c65bca..d6f9fd9 100644 --- a/src/northbridge/amd/amdfam10/misc_control.c +++ b/src/northbridge/amd/amdfam10/misc_control.c @@ -5,6 +5,7 @@ * Copyright (C) Stefan Reinauer * Copyright (C) 2007 Advanced Micro Devices, Inc. * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -117,16 +118,25 @@ static void set_agp_aperture(device_t dev, uint32_t pci_id) static void mcf3_set_resources_fam10h(device_t dev) { - /* Set the gart apeture */ + /* Set the gart aperture */ set_agp_aperture(dev, 0x1203); /* Set the generic PCI resources */ pci_dev_set_resources(dev); } +static void mcf3_set_resources_fam15h_model10(device_t dev) +{ + /* Set the gart aperture */ + set_agp_aperture(dev, 0x1403); + + /* Set the generic PCI resources */ + pci_dev_set_resources(dev); +} + static void mcf3_set_resources_fam15h(device_t dev) { - /* Set the gart apeture */ + /* Set the gart aperture */ set_agp_aperture(dev, 0x1603); /* Set the generic PCI resources */ @@ -175,6 +185,15 @@ static struct device_operations mcf3_ops_fam10h = { .ops_pci = 0, }; +static struct device_operations mcf3_ops_fam15h_model10 = { + .read_resources = mcf3_read_resources, + .set_resources = mcf3_set_resources_fam15h_model10, + .enable_resources = pci_dev_enable_resources, + .init = misc_control_init, + .scan_bus = 0, + .ops_pci = 0, +}; + static struct device_operations mcf3_ops_fam15h = { .read_resources = mcf3_read_resources, .set_resources = mcf3_set_resources_fam15h, @@ -190,6 +209,12 @@ static const struct pci_driver mcf3_driver __pci_driver = { .device = 0x1203, }; +static const struct pci_driver mcf3_driver_fam15_model10 __pci_driver = { + .ops = &mcf3_ops_fam15h_model10, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1403, +}; + static const struct pci_driver mcf3_driver_fam15 __pci_driver = { .ops = &mcf3_ops_fam15h, .vendor = PCI_VENDOR_ID_AMD, diff --git a/src/northbridge/amd/amdfam10/nb_control.c b/src/northbridge/amd/amdfam10/nb_control.c index 07f739d..1884799 100644 --- a/src/northbridge/amd/amdfam10/nb_control.c +++ b/src/northbridge/amd/amdfam10/nb_control.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -64,7 +65,6 @@ static void nb_control_init(struct device *dev) printk(BIOS_DEBUG, "done.\n"); } - static struct device_operations mcf5_ops = { .read_resources = pci_dev_read_resources, .set_resources = pci_dev_set_resources, @@ -74,8 +74,14 @@ static struct device_operations mcf5_ops = { .ops_pci = 0, }; +static const struct pci_driver mcf5_driver_fam15_model10 __pci_driver = { + .ops = &mcf5_ops, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1405, +}; + static const struct pci_driver mcf5_driver_fam15 __pci_driver = { .ops = &mcf5_ops, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1605, -}; \ No newline at end of file +}; diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 3b747bd..06079dd 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, Raptor Engineering * Copyright (C) 2007 Advanced Micro Devices, Inc. * @@ -673,26 +674,29 @@ static struct device_operations northbridge_operations = { .ops_pci = 0, }; - static const struct pci_driver mcf0_driver __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1200, }; - static void amdfam10_nb_init(void *chip_info) { relocate_sb_ht_chain(); } +static const struct pci_driver mcf0_driver_fam15_model10 __pci_driver = { + .ops = &northbridge_operations, + .vendor = PCI_VENDOR_ID_AMD, + .device = 0x1400, +}; + static const struct pci_driver mcf0_driver_fam15 __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, .device = 0x1600, }; - struct chip_operations northbridge_amd_amdfam10_ops = { CHIP_NAME("AMD Family 10h/15h Northbridge") .enable_dev = 0, diff --git a/src/northbridge/amd/amdfam10/raminit_amdmct.c b/src/northbridge/amd/amdfam10/raminit_amdmct.c index 1407631..6166169 100644 --- a/src/northbridge/amd/amdfam10/raminit_amdmct.c +++ b/src/northbridge/amd/amdfam10/raminit_amdmct.c @@ -579,6 +579,9 @@ static uint16_t mct_MaxLoadFreq(uint8_t count, uint8_t highest_rank_count, uint8 //G34 #elif CONFIG_CPU_SOCKET_TYPE == 0x15 #include "../amdmct/mct_ddr3/mctardk5.c" +//FM2 +#elif CONFIG_CPU_SOCKET_TYPE == 0x16 +#include "../amdmct/mct_ddr3/mctardk5.c" #endif #else /* DDR2 */ diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c index 32cf175..f31fcd2 100644 --- a/src/northbridge/amd/amdht/ht_wrapper.c +++ b/src/northbridge/amd/amdht/ht_wrapper.c @@ -258,6 +258,11 @@ static BOOL AMD_CB_IgnoreLink (u8 node, u8 link) static void amd_ht_init(struct sys_info *sysinfo) { + if (!sysinfo) { + printk(BIOS_DEBUG, "Skipping amd_ht_init()\n"); + return; + } + AMD_HTBLOCK ht_wrapper = { NULL, // u8 **topolist; 0, // u8 AutoBusStart; diff --git a/src/northbridge/amd/amdmct/amddefs.h b/src/northbridge/amd/amdmct/amddefs.h index 10a50d9..9193a04 100644 --- a/src/northbridge/amd/amdmct/amddefs.h +++ b/src/northbridge/amd/amdmct/amddefs.h @@ -162,3 +162,4 @@ #define AMD_PKGTYPE_G34 3 #define AMD_PKGTYPE_ASB2 4 #define AMD_PKGTYPE_C32 5 +#define AMD_PKGTYPE_FM2 6 diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 23c60b8..ba20456 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -6822,10 +6822,15 @@ static void mct_InitialMCT_D(struct MCTStatStruc *pMCTstat, struct DCTStatStruc static u32 mct_NodePresent_D(void) { u32 val; - if (is_fam15h()) - val = 0x16001022; - else + if (is_fam15h()) { + if (is_model10_1f()) { + val = 0x14001022; + } else { + val = 0x16001022; + } + } else { val = 0x12001022; + } return val; }

1 0

Patch set updated for coreboot: nb/amd/amdmct: Select max_lanes based on ECC presence or absence
by Damien Zammit 26 Feb '16

26 Feb '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13725 -gerrit commit a3d1837dd99ada2dbd7acc2e03801859e95d52f4 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Feb 17 14:14:47 2016 +1100 nb/amd/amdmct: Select max_lanes based on ECC presence or absence Change-Id: Ic5482dc13ab7b53ec4df408bbe32d20888ae2e12 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/northbridge/amd/amdmct/mct_ddr3/mct_d.c | 46 ++++---- src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c | 69 ++++++++---- src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c | 108 ++++++++++-------- src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c | 150 ++++++++++++++----------- 4 files changed, 221 insertions(+), 152 deletions(-) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index 4615dd2..23c60b8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -183,11 +183,13 @@ static void mct_ExtMCTConfig_Bx(struct DCTStatStruc *pDCTstat); static void mct_ExtMCTConfig_Cx(struct DCTStatStruc *pDCTstat); static void mct_ExtMCTConfig_Dx(struct DCTStatStruc *pDCTstat); +uint8_t is_ecc_enabled(struct MCTStatStruc *pMCTstat); + static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); + uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane); static void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); + uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane); /*See mctAutoInitMCT header for index relationships to CL and T*/ static const u16 Table_F_k[] = {00,200,266,333,400,533 }; @@ -329,6 +331,11 @@ static inline uint8_t is_model10_1f(void) return model101f; } +uint8_t is_ecc_enabled(struct MCTStatStruc *pMCTstat) +{ + return !!(pMCTstat->GStatus & (1 << GSB_ECCDIMMs)); +} + static uint16_t mhz_to_memclk_config(uint16_t freq) { if (is_fam15h()) @@ -2827,12 +2834,14 @@ restartinit: InterleaveNodes_D(pMCTstat, pDCTstatA); InterleaveChannels_D(pMCTstat, pDCTstatA); - printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n"); - if (!ECCInit_D(pMCTstat, pDCTstatA)) { /* Setup ECC control and ECC check-bits*/ - /* Memory was not cleared during ECC setup */ - /* mctDoWarmResetMemClr_D(); */ - printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n"); - MCTMemClr_D(pMCTstat,pDCTstatA); + if (is_ecc_enabled(pMCTstat)) { + printk(BIOS_DEBUG, "mctAutoInitMCT_D: ECCInit_D\n"); + if (!ECCInit_D(pMCTstat, pDCTstatA)) { /* Setup ECC control and ECC check-bits*/ + /* Memory was not cleared during ECC setup */ + /* mctDoWarmResetMemClr_D(); */ + printk(BIOS_DEBUG, "mctAutoInitMCT_D: MCTMemClr_D\n"); + MCTMemClr_D(pMCTstat,pDCTstatA); + } } if (is_fam15h()) { @@ -3031,7 +3040,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, uint16_t cdd_trwtto_we_delta; uint8_t receiver; uint8_t max_lane; - uint8_t ecc_enabled; uint8_t x4_present = 0; uint8_t x8_present = 0; uint8_t memclk_index; @@ -3056,8 +3064,6 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, uint8_t buffer_data_delay; int16_t latency_difference; uint16_t difference; - uint16_t current_total_delay_1[MAX_BYTE_LANES]; - uint16_t current_total_delay_2[MAX_BYTE_LANES]; uint8_t ddr_voltage_index; uint8_t max_dimms_installable; @@ -3074,12 +3080,14 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, ddr_voltage_index = dct_ddr_voltage_index(pDCTstat, dct); max_dimms_installable = mctGet_NVbits(NV_MAX_DIMMS_PER_CH); - ecc_enabled = !!(pMCTstat->GStatus & 1 << GSB_ECCDIMMs); - if (ecc_enabled) + if (is_ecc_enabled(pMCTstat)) max_lane = 9; else max_lane = 8; + uint16_t current_total_delay_1[max_lane]; + uint16_t current_total_delay_2[max_lane]; + if (pDCTstat->Dimmx4Present & ((dct)?0xaa:0x55)) x4_present = 1; if (pDCTstat->Dimmx8Present & ((dct)?0xaa:0x55)) @@ -3141,7 +3149,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) continue; - read_dqs_receiver_enable_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); + read_dqs_receiver_enable_control_registers(current_total_delay_2, dev, dct, dimm, index_reg, max_lane); if (first_dimm) { memcpy(current_total_delay_1, current_total_delay_2, sizeof(current_total_delay_1)); @@ -3187,7 +3195,7 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) continue; - read_dqs_write_timing_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); + read_dqs_write_timing_control_registers(current_total_delay_2, dev, dct, dimm, index_reg, max_lane); if (first_dimm) { memcpy(current_total_delay_1, current_total_delay_2, sizeof(current_total_delay_1)); @@ -3382,8 +3390,8 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) continue; - read_dqs_write_timing_control_registers(current_total_delay_1, dev, dct, dimm, index_reg); - read_dqs_receiver_enable_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); + read_dqs_write_timing_control_registers(current_total_delay_1, dev, dct, dimm, index_reg, max_lane); + read_dqs_receiver_enable_control_registers(current_total_delay_2, dev, dct, dimm, index_reg, max_lane); for (lane = 0; lane < max_lane; lane++) { if (current_total_delay_1[lane] > current_total_delay_2[lane]) @@ -3436,8 +3444,8 @@ static void fam15EnableTrainingMode(struct MCTStatStruc *pMCTstat, if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, receiver)) continue; - read_dqs_receiver_enable_control_registers(current_total_delay_1, dev, dct, dimm, index_reg); - read_dqs_write_timing_control_registers(current_total_delay_2, dev, dct, dimm, index_reg); + read_dqs_receiver_enable_control_registers(current_total_delay_1, dev, dct, dimm, index_reg, max_lane); + read_dqs_write_timing_control_registers(current_total_delay_2, dev, dct, dimm, index_reg, max_lane); for (lane = 0; lane < max_lane; lane++) { if (current_total_delay_1[lane] > current_total_delay_2[lane]) diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c index 19a7acb..9f9d95f 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctdqs_d.c @@ -15,10 +15,10 @@ */ static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); + uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane); static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, - uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg); + uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane); static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat); @@ -931,8 +931,6 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, uint32_t p = 0; uint32_t n = 0; uint32_t t = 0; - uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; - uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; uint32_t index_reg = 0x98; uint32_t dev = pDCTstat->dev_dct; @@ -942,6 +940,15 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "%s: Start\n", __func__); #endif + u8 max_lane; + if (is_ecc_enabled(pMCTstat)) + max_lane = 9; + else + max_lane = 8; + + uint16_t current_phy_phase_delay[max_lane]; + uint16_t current_read_dqs_delay[max_lane]; + mem_clk = Get_NB32_DCT(dev, dct, 0x94) & 0x1f; if (fam15h_freq_tab[mem_clk] == 0) { pDCTstat->CH_MaxRdLat[dct] = 0x55; @@ -981,9 +988,9 @@ static void Calc_SetMaxRdLatency_D_Fam15(struct MCTStatStruc *pMCTstat, if (!mct_RcvrRankEnabled_D(pMCTstat, pDCTstat, dct, dimm * 2)) continue; - read_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); - read_read_dqs_timing_control_registers(current_read_dqs_delay, dev, dct, dimm, index_reg); - for (lane = 0; lane < MAX_BYTE_LANES; lane++) + read_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg, max_lane); + read_read_dqs_timing_control_registers(current_read_dqs_delay, dev, dct, dimm, index_reg, max_lane); + for (lane = 0; lane < max_lane; lane++) if ((current_phy_phase_delay[lane] + current_read_dqs_delay[lane]) > max_delay) max_delay = (current_phy_phase_delay[lane] + current_read_dqs_delay[lane]); } @@ -1318,13 +1325,6 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, uint8_t write_iter; uint8_t read_iter; uint8_t check_antiphase; - uint16_t initial_write_dqs_delay[MAX_BYTE_LANES]; - uint16_t initial_read_dqs_delay[MAX_BYTE_LANES]; - uint16_t initial_write_data_timing[MAX_BYTE_LANES]; - uint16_t current_write_data_delay[MAX_BYTE_LANES]; - uint16_t current_read_dqs_delay[MAX_BYTE_LANES]; - uint16_t current_write_dqs_delay[MAX_BYTE_LANES]; - uint8_t passing_dqs_delay_found[MAX_BYTE_LANES]; uint8_t dqs_results_array[2][(lane_end - lane_start)][32][48]; /* [rank][lane][write step][read step + 16] */ uint8_t last_pos = 0; @@ -1335,6 +1335,20 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, uint32_t index_reg = 0x98; uint32_t dev = pDCTstat->dev_dct; + u8 max_lane; + if (is_ecc_enabled(pMCTstat)) + max_lane = 9; + else + max_lane = 8; + + uint16_t initial_write_dqs_delay[max_lane]; + uint16_t initial_read_dqs_delay[max_lane]; + uint16_t initial_write_data_timing[max_lane]; + uint16_t current_write_data_delay[max_lane]; + uint16_t current_read_dqs_delay[max_lane]; + uint16_t current_write_dqs_delay[max_lane]; + uint8_t passing_dqs_delay_found[max_lane]; + /* Calculate and program MaxRdLatency */ Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0); @@ -1374,7 +1388,7 @@ static uint8_t TrainDQSRdWrPos_D_Fam15(struct MCTStatStruc *pMCTstat, memset(dqs_results_array, 0, sizeof(dqs_results_array)); /* Read initial read / write DQS delays */ - read_dqs_write_timing_control_registers(initial_write_dqs_delay, dev, dct, dimm, index_reg); + read_dqs_write_timing_control_registers(initial_write_dqs_delay, dev, dct, dimm, index_reg, max_lane); read_dqs_read_data_timing_registers(initial_read_dqs_delay, dev, dct, dimm, index_reg); /* Read current settings of other (previously trained) lanes */ @@ -1665,15 +1679,22 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, uint32_t dword; uint32_t rx_en_offset; uint8_t dct_training_success; - uint16_t initial_phy_phase_delay[MAX_BYTE_LANES]; - uint16_t current_phy_phase_delay[MAX_BYTE_LANES]; - uint8_t lane_training_success[MAX_BYTE_LANES]; uint8_t dqs_results_array[1024]; uint16_t ren_step = 0x40; uint32_t index_reg = 0x98; uint32_t dev = pDCTstat->dev_dct; + u8 max_lane; + if (is_ecc_enabled(pMCTstat)) + max_lane = 9; + else + max_lane = 8; + + uint16_t initial_phy_phase_delay[max_lane]; + uint16_t current_phy_phase_delay[max_lane]; + uint8_t lane_training_success[max_lane]; + print_debug_dqs("\nTrainDQSReceiverEnCyc: Node_ID ", pDCTstat->Node_ID, 0); cr4 = read_cr4(); if (cr4 & (1<<9)) { @@ -1723,13 +1744,13 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, continue; } - for (lane = 0; lane < MAX_BYTE_LANES; lane++) + for (lane = 0; lane < max_lane; lane++) lane_training_success[lane] = 0; /* 2.10.5.8.3 (2) */ - read_dqs_receiver_enable_control_registers(initial_phy_phase_delay, dev, dct, dimm, index_reg); + read_dqs_receiver_enable_control_registers(initial_phy_phase_delay, dev, dct, dimm, index_reg, max_lane); - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { /* Initialize variables */ memset(dqs_results_array, 0, sizeof(dqs_results_array)); @@ -1751,7 +1772,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, #endif /* 2.10.5.8.3 (4 A) */ - write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg, max_lane); /* Calculate and program MaxRdLatency */ Calc_SetMaxRdLatency_D_Fam15(pMCTstat, pDCTstat, dct, 0); @@ -1796,7 +1817,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, current_phy_phase_delay[lane] -= 0x10; /* Update hardware registers with final values */ - write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_phy_phase_delay, dev, dct, dimm, index_reg, max_lane); break; } prev = dqs_results_array[current_phy_phase_delay[lane]]; @@ -1817,7 +1838,7 @@ static void TrainDQSReceiverEnCyc_D_Fam15(struct MCTStatStruc *pMCTstat, #if DQS_TRAIN_DEBUG > 0 printk(BIOS_DEBUG, "TrainDQSReceiverEnCyc_D_Fam15 DQS receiver enable timing: "); - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { printk(BIOS_DEBUG, " %03x", current_phy_phase_delay[lane]); } printk(BIOS_DEBUG, "\n"); diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index b8d89fe..9e3bed8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -236,12 +236,12 @@ static uint16_t fam15_receiver_enable_training_seed(struct DCTStatStruc *pDCTsta return seed; } -static void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void read_dqs_write_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane) { uint8_t lane; uint32_t dword; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { uint32_t wdt_reg; if ((lane == 0) || (lane == 1)) wdt_reg = 0x30; @@ -295,12 +295,12 @@ static void write_dqs_write_timing_control_registers(uint16_t* current_total_del } #endif -static void write_write_data_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void write_write_data_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane) { uint8_t lane; uint32_t dword; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { uint32_t wdt_reg; /* Calculate Write Data Timing register location */ @@ -334,7 +334,7 @@ static void write_write_data_timing_control_registers(uint16_t* current_total_de } } -static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane) { uint8_t lane; uint32_t mask; @@ -345,7 +345,7 @@ static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_d else mask = 0x1ff; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { uint32_t ret_reg; if ((lane == 0) || (lane == 1)) ret_reg = 0x10; @@ -368,7 +368,7 @@ static void read_dqs_receiver_enable_control_registers(uint16_t* current_total_d } } -static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane) { uint8_t lane; uint32_t mask; @@ -379,7 +379,7 @@ static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_ else mask = 0x1ff; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { uint32_t ret_reg; if ((lane == 0) || (lane == 1)) ret_reg = 0x10; @@ -405,12 +405,12 @@ static void write_dqs_receiver_enable_control_registers(uint16_t* current_total_ } } -static void read_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void read_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane) { uint8_t lane; uint32_t dword; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { uint32_t prc_reg; /* Calculate DRAM Phase Recovery Control register location */ @@ -437,12 +437,12 @@ static void read_dram_phase_recovery_control_registers(uint16_t* current_total_d } } -static void write_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void write_dram_phase_recovery_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane) { uint8_t lane; uint32_t dword; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { uint32_t prc_reg; /* Calculate DRAM Phase Recovery Control register location */ @@ -475,12 +475,12 @@ static void write_dram_phase_recovery_control_registers(uint16_t* current_total_ } } -static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg) +static void read_read_dqs_timing_control_registers(uint16_t* current_total_delay, uint32_t dev, uint8_t dct, uint8_t dimm, uint32_t index_reg, u8 max_lane) { uint8_t lane; uint32_t dword; - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { uint32_t rdt_reg; /* Calculate DRAM Read DQS Timing register location */ @@ -646,14 +646,14 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, /* 2.8.9.9.2 (1, 6) * Retrieve gross and fine timing fields from write DQS registers */ - read_dqs_write_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + read_dqs_write_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg, MAX_BYTE_LANES); /* 2.8.9.9.2 (1) * Program the Write Data Timing and Write ECC Timing register to * the values stored in the DQS Write Timing Control register * for each lane */ - write_write_data_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_write_data_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg, MAX_BYTE_LANES); /* 2.8.9.9.2 (2) * Program the Read DQS Timing Control and the Read DQS ECC Timing Control registers @@ -721,7 +721,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, /* 2.8.9.9.2 (6) * Write gross and fine timing fields to read DQS registers */ - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, MAX_BYTE_LANES); /* 2.8.9.9.2 (7) * Loop over all delay values up to 1 MEMCLK (0x40 delay steps) from the initial delay values @@ -765,17 +765,17 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, */ proc_IOCLFLUSH_D((rank == 0)?TestAddr0B:TestAddr1B); result_qword2 = read64_fs(convert_testaddr_and_channel_to_address(pDCTstat, (rank == 0)?TestAddr0B:TestAddr1B, Channel)); - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, MAX_BYTE_LANES); proc_IOCLFLUSH_D((rank == 0)?TestAddr0:TestAddr1); result_qword1 = read64_fs(convert_testaddr_and_channel_to_address(pDCTstat, (rank == 0)?TestAddr0:TestAddr1, Channel)); - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, MAX_BYTE_LANES); } else { proc_IOCLFLUSH_D((rank == 0)?TestAddr0:TestAddr1); result_qword1 = read64_fs(convert_testaddr_and_channel_to_address(pDCTstat, (rank == 0)?TestAddr0:TestAddr1, Channel)); - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, MAX_BYTE_LANES); proc_IOCLFLUSH_D((rank == 0)?TestAddr0B:TestAddr1B); result_qword2 = read64_fs(convert_testaddr_and_channel_to_address(pDCTstat, (rank == 0)?TestAddr0B:TestAddr1B, Channel)); - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, MAX_BYTE_LANES); } /* 2.8.9.9.2 (7 A e) * Compare both read patterns and flag passing ranks/lanes @@ -864,7 +864,7 @@ static void dqsTrainRcvrEn_SW_Fam10(struct MCTStatStruc *pMCTstat, } /* Update delays in hardware */ - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, MAX_BYTE_LANES); /* Save previous results for comparison in the next iteration */ for (lane = 0; lane < 8; lane++) @@ -1148,18 +1148,26 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, uint8_t mem_clk; uint16_t initial_seed; uint8_t train_both_nibbles; - uint16_t current_total_delay[MAX_BYTE_LANES]; - uint16_t dqs_ret_pass1_total_delay[MAX_BYTE_LANES]; - uint16_t rank0_current_total_delay[MAX_BYTE_LANES]; - uint16_t phase_recovery_delays[MAX_BYTE_LANES]; - uint16_t seed[MAX_BYTE_LANES]; - uint16_t seed_gross[MAX_BYTE_LANES]; - uint16_t seed_fine[MAX_BYTE_LANES]; - uint16_t seed_pre_gross[MAX_BYTE_LANES]; uint8_t package_type = mctGet_NVbits(NV_PACK_TYPE); uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; + u8 max_lane; + u8 ecc_enabled = !!(pMCTstat->GStatus & 1 << GSB_ECCDIMMs); + if (ecc_enabled) + max_lane = 9; + else + max_lane = 8; + + uint16_t current_total_delay[max_lane]; + uint16_t dqs_ret_pass1_total_delay[max_lane]; + uint16_t rank0_current_total_delay[max_lane]; + uint16_t phase_recovery_delays[max_lane]; + uint16_t seed[max_lane]; + uint16_t seed_gross[max_lane]; + uint16_t seed_fine[max_lane]; + uint16_t seed_pre_gross[max_lane]; + print_debug_dqs("\nTrainRcvEn: Node", pDCTstat->Node_ID, 0); print_debug_dqs("TrainRcvEn: Pass", Pass, 0); @@ -1239,7 +1247,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* Retrieve the total delay values from pass 1 of DQS receiver enable training */ if (Pass != FirstPass) { - read_dqs_receiver_enable_control_registers(dqs_ret_pass1_total_delay, dev, Channel, dimm, index_reg); + read_dqs_receiver_enable_control_registers(dqs_ret_pass1_total_delay, dev, Channel, dimm, index_reg, max_lane); } /* 2.10.5.8.2 @@ -1264,7 +1272,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.2 (2) * Retrieve gross and fine timing fields from write DQS registers */ - read_dqs_write_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + read_dqs_write_timing_control_registers(current_total_delay, dev, Channel, dimm, index_reg, max_lane); /* 2.10.5.8.2.1 * Generate the DQS Receiver Enable Training Seed Values @@ -1276,7 +1284,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, initial_seed = (uint16_t) (((((uint64_t) initial_seed) * fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100))); - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { uint16_t wl_pass1_delay; wl_pass1_delay = current_total_delay[lane]; @@ -1302,13 +1310,13 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, register_delay = 0x0; } - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { seed_prescaling = current_total_delay[lane] - register_delay - 0x20; seed[lane] = (uint16_t) (register_delay + ((((uint64_t) seed_prescaling) * fam15h_freq_tab[mem_clk] * 100) / (mctGet_NVbits(NV_MIN_MEMCLK) * 100))); } } - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { seed_gross[lane] = (seed[lane] >> 5) & 0x1f; seed_fine[lane] = seed[lane] & 0x1f; @@ -1332,12 +1340,12 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.2 (2) / 2.10.5.8.2.1 (5 6) * Program PhRecFineDly and PhRecGrossDly */ - write_dram_phase_recovery_control_registers(phase_recovery_delays, dev, Channel, dimm, index_reg); + write_dram_phase_recovery_control_registers(phase_recovery_delays, dev, Channel, dimm, index_reg, max_lane); /* 2.10.5.8.2 (2) / 2.10.5.8.2.1 (7) * Program the DQS Receiver Enable delay values for each lane */ - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, max_lane); /* 2.10.5.8.2 (3) * Program DqsRcvTrEn = 1 @@ -1361,12 +1369,12 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, /* 2.10.5.8.2 (6) * Read PhRecGrossDly, PhRecFineDly */ - read_dram_phase_recovery_control_registers(phase_recovery_delays, dev, Channel, dimm, index_reg); + read_dram_phase_recovery_control_registers(phase_recovery_delays, dev, Channel, dimm, index_reg, max_lane); /* 2.10.5.8.2 (7) * Calculate and program the DQS Receiver Enable delay values */ - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { current_total_delay[lane] = (phase_recovery_delays[lane] & 0x1f); current_total_delay[lane] |= ((seed_gross[lane] + ((phase_recovery_delays[lane] >> 5) & 0x1f) - seed_pre_gross[lane] + 1) << 5); if (nibble == 0) { @@ -1390,7 +1398,7 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, printk(BIOS_DEBUG, "\t\tTrainRcvEn55: Channel: %d dimm: %d nibble: %d lane %d current_total_delay: %04x CH_D_B_RCVRDLY: %04x\n", Channel, dimm, nibble, lane, current_total_delay[lane], pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane]); #endif - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, max_lane); } if (rank == 0) { @@ -1403,14 +1411,14 @@ static void dqsTrainRcvrEn_SW_Fam15(struct MCTStatStruc *pMCTstat, * Compute the average delay across both ranks and program the result into * the DQS Receiver Enable delay registers */ - for (lane = 0; lane < MAX_BYTE_LANES; lane++) { + for (lane = 0; lane < max_lane; lane++) { current_total_delay[lane] = (rank0_current_total_delay[lane] + current_total_delay[lane]) / 2; if (lane == 8) pDCTstat->CH_D_BC_RCVRDLY[Channel][dimm] = current_total_delay[lane]; else pDCTstat->CH_D_B_RCVRDLY[Channel][dimm][lane] = current_total_delay[lane]; } - write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); + write_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, max_lane); } } @@ -1526,11 +1534,19 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, uint8_t mem_clk; uint32_t nb_clk; uint8_t nb_pstate; - uint16_t current_total_delay[MAX_BYTE_LANES]; - uint16_t current_rdqs_total_delay[MAX_BYTE_LANES]; uint8_t current_worst_case_total_delay_dimm; uint16_t current_worst_case_total_delay_value; + u8 max_lane; + u8 ecc_enabled = !!(pMCTstat->GStatus & 1 << GSB_ECCDIMMs); + if (ecc_enabled) + max_lane = 9; + else + max_lane = 8; + + uint16_t current_total_delay[max_lane]; + uint16_t current_rdqs_total_delay[max_lane]; + uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; print_debug_dqs("\nTrainMaxRdLatency: Node", pDCTstat->Node_ID, 0); @@ -1592,8 +1608,8 @@ static void dqsTrainMaxRdLatency_SW_Fam15(struct MCTStatStruc *pMCTstat, } /* Retrieve the total delay values from pass 1 of DQS receiver enable training */ - read_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg); - read_read_dqs_timing_control_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg); + read_dqs_receiver_enable_control_registers(current_total_delay, dev, Channel, dimm, index_reg, max_lane); + read_read_dqs_timing_control_registers(current_rdqs_total_delay, dev, Channel, dimm, index_reg, max_lane); for (lane = 0; lane < 8; lane++) { current_total_delay[lane] += current_rdqs_total_delay[lane]; diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c index 2b8a997..258da21 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mhwlc_d.c @@ -32,8 +32,8 @@ void prepareDimms(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, u8 dct, u8 dimm, BOOL wl); void programODT(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, u8 dimm); void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, uint8_t dct, uint8_t dimm, uint8_t pass, uint8_t nibble); -void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, u8 targetAddr, uint8_t pass); -void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, uint8_t pass, uint8_t nibble); +void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, u8 targetAddr, uint8_t pass, u8 max_lane); +void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, uint8_t pass, uint8_t nibble, u8 max_lane); static int32_t abs(int32_t val) { if (val < 0) @@ -77,6 +77,12 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT u16 Addl_Data_Offset, Addl_Data_Port; sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; + uint8_t max_lane; + + if (is_ecc_enabled(pMCTstat)) + max_lane = 9; + else + max_lane = 8; pDCTData->WLPass = pass; /* 1. Specify the target DIMM that is to be trained by programming @@ -176,8 +182,8 @@ uint8_t AgesaHwWlPhase1(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT /* Read from registers F2x[1, 0]9C_x[51:50] and F2x[1, 0]9C_x52 * to get the gross and fine delay settings * for the target DIMM and save these values. */ - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { - getWLByteDelay(pDCTstat, dct, ByteLane, dimm, pass, nibble); + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { + getWLByteDelay(pDCTstat, dct, ByteLane, dimm, pass, nibble, max_lane); } pDCTData->WLCriticalGrossDelayPrevPass = 0x0; @@ -192,11 +198,17 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT u8 ByteLane; uint8_t status = 0; sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; + uint8_t max_lane; + + if (is_ecc_enabled(pMCTstat)) + max_lane = 9; + else + max_lane = 8; if (is_fam15h()) { - int32_t gross_diff[MAX_BYTE_LANES]; + int32_t gross_diff[max_lane]; int32_t cgd = pDCTData->WLCriticalGrossDelayPrevPass; - uint8_t index = (uint8_t)(MAX_BYTE_LANES * dimm); + uint8_t index = (uint8_t)(max_lane * dimm); printk(BIOS_SPEW, "\toriginal critical gross delay: %d\n", cgd); @@ -205,7 +217,7 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT */ /* Calculate the Critical Gross Delay */ - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { /* Calculate the gross delay differential for this lane */ gross_diff[ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane] + pDCTData->WLGrossDelay[index+ByteLane]; gross_diff[ByteLane] -= pDCTData->WLSeedPreGrossDelay[index+ByteLane]; @@ -231,7 +243,7 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT * Figure out why this is and fix it, then remove the bypass code below... */ if (pass == FirstPass) { - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { pDCTData->WLGrossDelay[index+ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane]; pDCTData->WLFineDelay[index+ByteLane] = pDCTData->WLSeedFineDelay[index+ByteLane]; } @@ -240,7 +252,7 @@ uint8_t AgesaHwWlPhase2(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT } /* Compensate for occasional noise/instability causing sporadic training failure */ - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { uint8_t faulty_value_detected = 0; uint16_t total_delay_seed = ((pDCTData->WLSeedGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLSeedFineDelay[index+ByteLane] & 0x1f); uint16_t total_delay_phy = ((pDCTData->WLGrossDelay[index+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[index+ByteLane] & 0x1f); @@ -278,12 +290,18 @@ uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT u8 ByteLane; sMCTStruct *pMCTData = pDCTstat->C_MCTPtr; sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; + u8 max_lane; + + if (is_ecc_enabled(pMCTstat)) + max_lane = 9; + else + max_lane = 8; if (is_fam15h()) { uint32_t dword; - int32_t gross_diff[MAX_BYTE_LANES]; + int32_t gross_diff[max_lane]; int32_t cgd = pDCTData->WLCriticalGrossDelayPrevPass; - uint8_t index = (uint8_t)(MAX_BYTE_LANES * dimm); + uint8_t index = (uint8_t)(max_lane * dimm); /* Apply offset(s) if needed */ if (cgd < 0) { @@ -292,7 +310,7 @@ uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT dword |= ((abs(cgd) & 0x3) << 24); Set_NB32_DCT(pDCTstat->dev_dct, dct, 0xa8, dword); - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { /* Calculate the gross delay differential for this lane */ gross_diff[ByteLane] = pDCTData->WLSeedGrossDelay[index+ByteLane] + pDCTData->WLGrossDelay[index+ByteLane]; gross_diff[ByteLane] -= pDCTData->WLSeedPreGrossDelay[index+ByteLane]; @@ -313,8 +331,8 @@ uint8_t AgesaHwWlPhase3(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCT /* Write the adjusted gross and fine delay settings * to the target DIMM. */ - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { - setWLByteDelay(pDCTstat, dct, ByteLane, dimm, 1, pass); + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { + setWLByteDelay(pDCTstat, dct, ByteLane, dimm, 1, pass, max_lane); } /* 6. Configure DRAM Phy Control Register so that the phy stops driving @@ -1006,6 +1024,12 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; uint16_t fam10h_freq_tab[] = {0, 0, 0, 400, 533, 667, 800}; uint16_t fam15h_freq_tab[] = {0, 0, 0, 0, 333, 0, 400, 0, 0, 0, 533, 0, 0, 0, 667, 0, 0, 0, 800, 0, 0, 0, 933}; + uint8_t max_lane; + + if (is_ecc_enabled(pMCTstat)) + max_lane = 9; + else + max_lane = 8; if (is_fam15h()) { /* MemClkFreq: 0x4: 333MHz; 0x6: 400MHz; 0xa: 533MHz; 0xe: 667MHz; 0x12: 800MHz; 0x16: 933MHz */ @@ -1113,9 +1137,9 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui Seed_Fine = Seed_Total & 0x1f; /* Save seed values for later use */ - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { - pDCTData->WLSeedGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross; - pDCTData->WLSeedFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { + pDCTData->WLSeedGrossDelay[max_lane*dimm+ByteLane] = Seed_Gross; + pDCTData->WLSeedFineDelay[max_lane*dimm+ByteLane] = Seed_Fine; if (Seed_Gross == 0) Seed_PreGross = 0; @@ -1124,7 +1148,7 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui else Seed_PreGross = 2; - pDCTData->WLSeedPreGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_PreGross; + pDCTData->WLSeedPreGrossDelay[max_lane*dimm+ByteLane] = Seed_PreGross; } } else { if (pDCTData->Status[DCT_STATUS_REGISTERED]) { @@ -1150,7 +1174,7 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui } } } - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { /* Program an initialization value to registers F2x[1, 0]9C_x[51:50] and * F2x[1, 0]9C_x52 to set the gross and fine delay for all the byte lane fields @@ -1160,8 +1184,8 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui * of 01Fh. This represents a 1UI (UI=.5MEMCLK) delay and is determined * by design. */ - pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross; - pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; + pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] = Seed_Gross; + pDCTData->WLFineDelay[max_lane*dimm+ByteLane] = Seed_Fine; printk(BIOS_SPEW, "\tLane %02x initial seed: %04x\n", ByteLane, ((Seed_Gross & 0x1f) << 5) | (Seed_Fine & 0x1f)); } } else { @@ -1170,8 +1194,8 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui /* From BKDG, Write Leveling Seed Value. */ if (is_fam15h()) { uint32_t RegisterDelay; - int32_t SeedTotal[MAX_BYTE_LANES]; - int32_t SeedTotalPreScaling[MAX_BYTE_LANES]; + int32_t SeedTotal[max_lane]; + int32_t SeedTotalPreScaling[max_lane]; uint32_t WrDqDqsEarly; uint8_t AddrCmdPrelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */ @@ -1194,17 +1218,17 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui WrDqDqsEarly = 0; /* Generate new seed values */ - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { /* Calculate adjusted seed values */ - SeedTotal[ByteLane] = (pDCTData->WLFineDelayPrevPass[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) | - ((pDCTData->WLGrossDelayPrevPass[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) << 5); + SeedTotal[ByteLane] = (pDCTData->WLFineDelayPrevPass[max_lane*dimm+ByteLane] & 0x1f) | + ((pDCTData->WLGrossDelayPrevPass[max_lane*dimm+ByteLane] & 0x1f) << 5); SeedTotalPreScaling[ByteLane] = (SeedTotal[ByteLane] - RegisterDelay - (0x20 * WrDqDqsEarly)); SeedTotal[ByteLane] = (int32_t) (RegisterDelay + ((((int64_t) SeedTotalPreScaling[ByteLane]) * fam15h_freq_tab[MemClkFreq] * 100) / (fam15h_freq_tab[pDCTData->WLPrevMemclkFreq] * 100))); } /* Generate register values from seeds */ - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { printk(BIOS_SPEW, "\tLane %02x scaled delay: %04x\n", ByteLane, SeedTotal[ByteLane]); if (SeedTotal[ByteLane] >= 0) { @@ -1229,21 +1253,21 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui Seed_PreGross = Seed_Gross; /* Save seed values for later use */ - pDCTData->WLSeedGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross; - pDCTData->WLSeedFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; - pDCTData->WLSeedPreGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_PreGross; + pDCTData->WLSeedGrossDelay[max_lane*dimm+ByteLane] = Seed_Gross; + pDCTData->WLSeedFineDelay[max_lane*dimm+ByteLane] = Seed_Fine; + pDCTData->WLSeedPreGrossDelay[max_lane*dimm+ByteLane] = Seed_PreGross; - pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_PreGross; - pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; + pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] = Seed_PreGross; + pDCTData->WLFineDelay[max_lane*dimm+ByteLane] = Seed_Fine; - printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[max_lane*dimm+ByteLane] & 0x1f)); } } else { uint32_t RegisterDelay; uint32_t SeedTotalPreScaling; uint32_t SeedTotal; uint8_t AddrCmdPrelaunch = 0; /* TODO: Fetch the correct value from RC2[0] */ - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { if (pDCTData->Status[DCT_STATUS_REGISTERED]) { if (AddrCmdPrelaunch == 0) @@ -1253,8 +1277,8 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui } else { RegisterDelay = 0; } - SeedTotalPreScaling = ((pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) | - (pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] << 5)) - RegisterDelay; + SeedTotalPreScaling = ((pDCTData->WLFineDelay[max_lane*dimm+ByteLane] & 0x1f) | + (pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] << 5)) - RegisterDelay; /* SeedTotalPreScaling = (the total delay value in F2x[1, 0]9C_x[4A:30] from pass 1 of write levelization training) - RegisterDelay. */ SeedTotal = (uint16_t) ((((uint64_t) SeedTotalPreScaling) * @@ -1277,49 +1301,49 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui Seed_Gross = SeedTotal / 32; Seed_Fine = SeedTotal & 0x1f; - pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Gross; - pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = Seed_Fine; + pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] = Seed_Gross; + pDCTData->WLFineDelay[max_lane*dimm+ByteLane] = Seed_Fine; - printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[max_lane*dimm+ByteLane] & 0x1f)); } } /* Save initial seeds for upper nibble pass */ - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { - pDCTData->WLSeedPreGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedPreGrossDelay[MAX_BYTE_LANES*dimm+ByteLane]; - pDCTData->WLSeedGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane]; - pDCTData->WLSeedFinePrevNibble[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane]; + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { + pDCTData->WLSeedPreGrossPrevNibble[max_lane*dimm+ByteLane] = pDCTData->WLSeedPreGrossDelay[max_lane*dimm+ByteLane]; + pDCTData->WLSeedGrossPrevNibble[max_lane*dimm+ByteLane] = pDCTData->WLGrossDelay[max_lane*dimm+ByteLane]; + pDCTData->WLSeedFinePrevNibble[max_lane*dimm+ByteLane] = pDCTData->WLFineDelay[max_lane*dimm+ByteLane]; } } else { /* Restore seed values from lower nibble pass */ if (is_fam15h()) { - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { - pDCTData->WLSeedGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane]; - pDCTData->WLSeedFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[MAX_BYTE_LANES*dimm+ByteLane]; - pDCTData->WLSeedPreGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedPreGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane]; + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { + pDCTData->WLSeedGrossDelay[max_lane*dimm+ByteLane] = pDCTData->WLSeedGrossPrevNibble[max_lane*dimm+ByteLane]; + pDCTData->WLSeedFineDelay[max_lane*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[max_lane*dimm+ByteLane]; + pDCTData->WLSeedPreGrossDelay[max_lane*dimm+ByteLane] = pDCTData->WLSeedPreGrossPrevNibble[max_lane*dimm+ByteLane]; - pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedPreGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane]; - pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[MAX_BYTE_LANES*dimm+ByteLane]; + pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] = pDCTData->WLSeedPreGrossPrevNibble[max_lane*dimm+ByteLane]; + pDCTData->WLFineDelay[max_lane*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[max_lane*dimm+ByteLane]; - printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[max_lane*dimm+ByteLane] & 0x1f)); } } else { - for (ByteLane = 0; ByteLane < MAX_BYTE_LANES; ByteLane++) { - pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedGrossPrevNibble[MAX_BYTE_LANES*dimm+ByteLane]; - pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[MAX_BYTE_LANES*dimm+ByteLane]; + for (ByteLane = 0; ByteLane < max_lane; ByteLane++) { + pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] = pDCTData->WLSeedGrossPrevNibble[max_lane*dimm+ByteLane]; + pDCTData->WLFineDelay[max_lane*dimm+ByteLane] = pDCTData->WLSeedFinePrevNibble[max_lane*dimm+ByteLane]; - printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[MAX_BYTE_LANES*dimm+ByteLane] & 0x1f)); + printk(BIOS_SPEW, "\tLane %02x new seed: %04x\n", ByteLane, ((pDCTData->WLGrossDelay[max_lane*dimm+ByteLane] & 0x1f) << 5) | (pDCTData->WLFineDelay[max_lane*dimm+ByteLane] & 0x1f)); } } } } pDCTData->WLPrevMemclkFreq = MemClkFreq; - setWLByteDelay(pDCTstat, dct, ByteLane, dimm, 0, pass); + setWLByteDelay(pDCTstat, dct, ByteLane, dimm, 0, pass, max_lane); } /*----------------------------------------------------------------------------- - * void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 Dimm){ + * void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 Dimm, u8 max_lane){ * * Description: * This function writes the write levelization byte delay for the Phase @@ -1339,7 +1363,7 @@ void procConfig(struct MCTStatStruc *pMCTstat, struct DCTStatStruc *pDCTstat, ui * *----------------------------------------------------------------------------- */ -void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, u8 targetAddr, uint8_t pass) +void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, u8 targetAddr, uint8_t pass, u8 max_lane) { sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; u8 fineStartLoc, fineEndLoc, grossStartLoc, grossEndLoc, tempB, index, offsetAddr; @@ -1347,12 +1371,12 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 if (targetAddr == 0) { - index = (u8)(MAX_BYTE_LANES * dimm); + index = (u8)(max_lane * dimm); ValueLow = 0; ValueHigh = 0; ByteLane = 0; EccValue = 0; - while (ByteLane < MAX_BYTE_LANES) + while (ByteLane < max_lane) { if (is_fam15h()) { grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; @@ -1394,7 +1418,7 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 else { /* Fam10h BKDG Rev. 3.62 2.8.9.9.1 (6) */ - index = (u8)(MAX_BYTE_LANES * dimm); + index = (u8)(max_lane * dimm); grossDelayValue = pDCTData->WLGrossDelay[index+ByteLane]; fineDelayValue = pDCTData->WLFineDelay[index+ByteLane]; @@ -1440,7 +1464,7 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 } /*----------------------------------------------------------------------------- - * void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 Dimm, u8 Nibble) + * void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 Dimm, u8 Nibble, u8 max_lane) * * Description: * This function reads the write levelization byte delay from the Phase @@ -1458,13 +1482,13 @@ void setWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 * *----------------------------------------------------------------------------- */ -void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, uint8_t pass, uint8_t nibble) +void getWLByteDelay(struct DCTStatStruc *pDCTstat, uint8_t dct, u8 ByteLane, u8 dimm, uint8_t pass, uint8_t nibble, u8 max_lane) { sDCTStruct *pDCTData = pDCTstat->C_DCTPtr[dct]; u8 fineStartLoc, fineEndLoc, grossStartLoc, grossEndLoc, tempB, tempB1, index; u32 addr, fine, gross; tempB = 0; - index = (u8)(MAX_BYTE_LANES*dimm); + index = (u8)(max_lane*dimm); if (ByteLane < 4) { tempB = (u8)(8 * ByteLane); addr = DRAM_CONT_ADD_PHASE_REC_CTRL_LOW;

1 0

Patch set updated for coreboot: mb/asus/f2a85-m_fam10: Add ASUS F2A85-M (using non-AGESA)
by Damien Zammit 26 Feb '16

26 Feb '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13712 -gerrit commit 3ff119e9dd63186577d622a806c539ffd939ad86 Author: Damien Zammit <damien(a)zamaudio.com> Date: Wed Feb 10 14:06:30 2016 +1100 mb/asus/f2a85-m_fam10: Add ASUS F2A85-M (using non-AGESA) Change-Id: I28717d9e78336e6097fd91f270cac2bfed9534d8 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/mainboard/asus/f2a85-m_fam10/Kconfig | 99 ++++++ src/mainboard/asus/f2a85-m_fam10/Kconfig.name | 2 + src/mainboard/asus/f2a85-m_fam10/acpi/cpstate.asl | 111 +++++++ src/mainboard/asus/f2a85-m_fam10/acpi/gpe.asl | 72 +++++ .../asus/f2a85-m_fam10/acpi/mainboard.asl | 32 ++ src/mainboard/asus/f2a85-m_fam10/acpi/routing.asl | 258 +++++++++++++++ src/mainboard/asus/f2a85-m_fam10/acpi/sata.asl | 16 + src/mainboard/asus/f2a85-m_fam10/acpi/si.asl | 22 ++ src/mainboard/asus/f2a85-m_fam10/acpi/sleep.asl | 96 ++++++ src/mainboard/asus/f2a85-m_fam10/acpi/superio.asl | 16 + src/mainboard/asus/f2a85-m_fam10/acpi/thermal.asl | 16 + src/mainboard/asus/f2a85-m_fam10/acpi/usb_oc.asl | 27 ++ src/mainboard/asus/f2a85-m_fam10/acpi_tables.c | 48 +++ src/mainboard/asus/f2a85-m_fam10/board_info.txt | 7 + src/mainboard/asus/f2a85-m_fam10/bootblock.c | 23 ++ src/mainboard/asus/f2a85-m_fam10/cmos.layout | 74 +++++ src/mainboard/asus/f2a85-m_fam10/devicetree.cb | 125 ++++++++ src/mainboard/asus/f2a85-m_fam10/dsdt.asl | 48 +++ src/mainboard/asus/f2a85-m_fam10/get_bus_conf.c | 5 + src/mainboard/asus/f2a85-m_fam10/hdaverb | 24 ++ src/mainboard/asus/f2a85-m_fam10/irq_tables.c | 103 ++++++ src/mainboard/asus/f2a85-m_fam10/mainboard.c | 47 +++ src/mainboard/asus/f2a85-m_fam10/mptable.c | 182 +++++++++++ src/mainboard/asus/f2a85-m_fam10/romstage.c | 353 +++++++++++++++++++++ 24 files changed, 1806 insertions(+) diff --git a/src/mainboard/asus/f2a85-m_fam10/Kconfig b/src/mainboard/asus/f2a85-m_fam10/Kconfig new file mode 100644 index 0000000..ee0a997 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/Kconfig @@ -0,0 +1,99 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> +# Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +if BOARD_ASUS_F2A85_M_FAM10 + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + select CPU_AMD_SOCKET_FM2_NON_AGESA + select DIMM_DDR3 + select DIMM_REGISTERED + select DIMM_VOLTAGE_SET_SUPPORT + select NORTHBRIDGE_AMD_AMDFAM10 + select SOUTHBRIDGE_AMD_SB900 + select SUPERIO_ITE_IT8728F + select HAVE_OPTION_TABLE + select HAVE_PIRQ_TABLE + select HAVE_MP_TABLE + select HAVE_ACPI_TABLES + select BOARD_ROMSIZE_KB_8192 + select ENABLE_APIC_EXT_ID + select PCI + select PCIEXP_PLUGIN_SUPPORT + select SB_HT_CHAIN_UNITID_OFFSET_ONLY + +config HT_CHAIN_END_UNITID_BASE + hex + default 0x1 + +config HT_CHAIN_UNITID_BASE + hex + default 0x0 + +config MAINBOARD_DIR + string + default "asus/f2a85-m_fam10" + +config MAINBOARD_PART_NUMBER + string + default "F2A85-M" + +config BOOTBLOCK_MAINBOARD_INIT + string + default "mainboard/asus/f2a85-m_fam10/bootblock.c" + +config DCACHE_RAM_BASE + hex + default 0xc2000 + +config DCACHE_RAM_SIZE + hex + default 0x1e000 + +config APIC_ID_OFFSET + hex + default 0 + +config HW_MEM_HOLE_SIZEK + hex + default 0x200000 + +config MAX_CPUS + int + default 32 + +config MAX_PHYSICAL_CPUS + int + default 1 + +config MAINBOARD_POWER_ON_AFTER_POWER_FAIL + bool + default y + +config IRQ_SLOT_COUNT + int + default 13 + +config ONBOARD_VGA_IS_PRIMARY + bool + default y + +config VGA_BIOS_ID + string + default "1002,9993" + +endif # BOARD_ASUS_F2A85_M_FAM10 diff --git a/src/mainboard/asus/f2a85-m_fam10/Kconfig.name b/src/mainboard/asus/f2a85-m_fam10/Kconfig.name new file mode 100644 index 0000000..c3cfb1d --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_ASUS_F2A85_M_FAM10 + bool "F2A85-M(NONAGESA)" diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/cpstate.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/cpstate.asl new file mode 100644 index 0000000..0951006 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/cpstate.asl @@ -0,0 +1,111 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* This file defines the processor and performance state capability + * for each core in the system. It is included into the DSDT for each + * core. It assumes that each core of the system has the same performance + * characteristics. +*/ +/* +DefinitionBlock ("DSDT.AML","DSDT",0x01,"XXXXXX","XXXXXXXX",0x00010001) + { + Scope (\_PR) { + Processor(CPU0,0,0x808,0x06) { + #include "cpstate.asl" + } + Processor(CPU1,1,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU2,2,0x0,0x0) { + #include "cpstate.asl" + } + Processor(CPU3,3,0x0,0x0) { + #include "cpstate.asl" + } + } +*/ + /* P-state support: The maximum number of P-states supported by the */ + /* CPUs we'll use is 6. */ + /* Get from AMI BIOS. */ + Name(_PSS, Package(){ + Package() + { + 0x00000D48, + 0x00011170, + 0x00000004, + 0x00000004, + 0x00000000, + 0x00000000 + }, + + Package() + { + 0x00000AF0, + 0x0000C544, + 0x00000004, + 0x00000004, + 0x00000001, + 0x00000001 + }, + + Package() + { + 0x000009C4, + 0x0000B3B0, + 0x00000004, + 0x00000004, + 0x00000002, + 0x00000002 + }, + + Package() + { + 0x00000898, + 0x0000ABE0, + 0x00000004, + 0x00000004, + 0x00000003, + 0x00000003 + }, + + Package() + { + 0x00000708, + 0x0000A410, + 0x00000004, + 0x00000004, + 0x00000004, + 0x00000004 + }, + + Package() + { + 0x00000578, + 0x00006F54, + 0x00000004, + 0x00000004, + 0x00000005, + 0x00000005 + } + }) + + Name(_PCT, Package(){ + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)}, + ResourceTemplate(){Register(FFixedHW, 0, 0, 0)} + }) + + Method(_PPC, 0){ + Return(0) + } diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/gpe.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/gpe.asl new file mode 100644 index 0000000..c34faaf --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/gpe.asl @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope(\_GPE) { /* Start Scope GPE */ + + /* General event 3 */ + Method(_L03) { + /* DBGO("\\_GPE\\_L00\n") */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Legacy PM event */ + Method(_L08) { + /* DBGO("\\_GPE\\_L08\n") */ + } + + /* Temp warning (TWarn) event */ + Method(_L09) { + /* DBGO("\\_GPE\\_L09\n") */ + /* Notify (\_TZ.TZ00, 0x80) */ + } + + /* USB controller PME# */ + Method(_L0B) { + /* DBGO("\\_GPE\\_L0B\n") */ + Notify(\_SB.PCI0.UOH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH2, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH3, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH5, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UOH6, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PCI0.UEH1, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* ExtEvent0 SCI event */ + Method(_L10) { + /* DBGO("\\_GPE\\_L10\n") */ + } + + + /* ExtEvent1 SCI event */ + Method(_L11) { + /* DBGO("\\_GPE\\_L11\n") */ + } + + /* GPIO0 or GEvent8 event */ + Method(_L18) { + /* DBGO("\\_GPE\\_L18\n") */ + Notify(\_SB.PCI0.PBR4, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } + + /* Azalia SCI event */ + Method(_L1B) { + /* DBGO("\\_GPE\\_L1B\n") */ + Notify(\_SB.PCI0.AZHD, 0x02) /* NOTIFY_DEVICE_WAKE */ + Notify(\_SB.PWRB, 0x02) /* NOTIFY_DEVICE_WAKE */ + } +} /* End Scope GPE */ diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/mainboard.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/mainboard.asl new file mode 100644 index 0000000..f88ad68 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/mainboard.asl @@ -0,0 +1,32 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* Data to be patched by the BIOS during POST */ + /* FIXME the patching is not done yet! */ + /* Memory related values */ + Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */ + Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */ + Name(PBLN, 0x0) /* Length of BIOS area */ + + Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ + Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ + Name(HPBA, 0xFED00000) /* Base address of HPET table */ + + Name(SSFG, 0x0D) /* S1 support: bit 0, S2 Support: bit 1, etc. S0 & S5 assumed */ + + /* Some global data */ + Name(OSVR, 3) /* Assume nothing. WinXp = 1, Vista = 2, Linux = 3, WinCE = 4 */ + Name(OSV, Ones) /* Assume nothing */ + Name(PMOD, One) /* Assume APIC */ diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/routing.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/routing.asl new file mode 100644 index 0000000..0af6b42 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/routing.asl @@ -0,0 +1,258 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + /* Routing is in System Bus scope */ + Name(PR0, Package(){ + /* NB devices */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, INTB, 0 }, + Package(){0x0001FFFF, 1, INTC, 0 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 slot */ + Package(){0x0002FFFF, 0, INTC, 0 }, + Package(){0x0002FFFF, 1, INTD, 0 }, + Package(){0x0002FFFF, 2, INTA, 0 }, + Package(){0x0002FFFF, 3, INTB, 0 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for 4x slot */ + Package(){0x0004FFFF, 0, INTA, 0 }, + Package(){0x0004FFFF, 1, INTB, 0 }, + Package(){0x0004FFFF, 2, INTC, 0 }, + Package(){0x0004FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ + /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ + Package(){0x0014FFFF, 0, INTA, 0 }, + Package(){0x0014FFFF, 1, INTB, 0 }, + Package(){0x0014FFFF, 2, INTC, 0 }, + Package(){0x0014FFFF, 3, INTD, 0 }, + + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, INTC, 0 }, + Package(){0x0012FFFF, 1, INTB, 0 }, + + Package(){0x0013FFFF, 0, INTC, 0 }, + Package(){0x0013FFFF, 1, INTB, 0 }, + + Package(){0x0016FFFF, 0, INTC, 0 }, + Package(){0x0016FFFF, 1, INTB, 0 }, + + /* SB devices */ + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, INTC, 0 }, + Package(){0x0010FFFF, 1, INTB, 0 }, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, INTD, 0 }, + + /* Bus 0, Dev 21 Pcie Bridge */ + Package(){0x0015FFFF, 0, INTA, 0 }, + Package(){0x0015FFFF, 1, INTB, 0 }, + Package(){0x0015FFFF, 2, INTC, 0 }, + Package(){0x0015FFFF, 3, INTD, 0 }, + }) + + Name(APR0, Package(){ + /* NB devices in APIC mode */ + /* Bus 0, Dev 0 - F15 Host Controller */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 1 - PCI Bridge for Internal Graphics(IGP) */ + Package(){0x0001FFFF, 0, 0, 17 }, + Package(){0x0001FFFF, 1, 0, 18 }, + + /* Bus 0, Dev 2 - PCIe Bridge for x16 PCIe Slot */ + Package(){0x0002FFFF, 0, 0, 18 }, + Package(){0x0002FFFF, 1, 0, 19 }, + Package(){0x0002FFFF, 2, 0, 16 }, + Package(){0x0002FFFF, 3, 0, 17 }, + + /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ + + /* Bus 0, Dev 4 - PCIe Bridge for x4 PCIe Slot black */ + Package(){0x0004FFFF, 0, 0, 16 }, + Package(){0x0004FFFF, 1, 0, 17 }, + Package(){0x0004FFFF, 2, 0, 18 }, + Package(){0x0004FFFF, 3, 0, 19 }, + + /* Bus 0, Dev 5 - General purpose PCIe bridge 5 */ + /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ + /* Bus 0, Dev 7 - PCIe Bridge for network card */ + /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ + + /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ + Package(){0x0014FFFF, 0, 0, 16 }, + Package(){0x0014FFFF, 1, 0, 17 }, + Package(){0x0014FFFF, 2, 0, 18 }, + Package(){0x0014FFFF, 3, 0, 19 }, + + /* SB devices in APIC mode */ + /* Bus 0, Dev 18,19,22 - USB: OHCI @ func 0 + * EHCI @ func 2 */ + Package(){0x0012FFFF, 0, 0, 18 }, + Package(){0x0012FFFF, 1, 0, 17 }, + + Package(){0x0013FFFF, 0, 0, 18 }, + Package(){0x0013FFFF, 1, 0, 17 }, + + Package(){0x0016FFFF, 0, 0, 18 }, + Package(){0x0016FFFF, 1, 0, 17 }, + + /* Bus 0, Dev 16 - USB: XHCI func 0, 1 */ + Package(){0x0010FFFF, 0, 0, 0x12}, + Package(){0x0010FFFF, 1, 0, 0x11}, + + /* Bus 0, Dev 17 - SATA controller */ + Package(){0x0011FFFF, 0, 0, 19 }, + + /* Bus 0, Dev 21 PCIE Bridge */ + Package(){0x0015FFFF, 0, 0, 17 }, + Package(){0x0015FFFF, 1, 0, 18 }, + Package(){0x0015FFFF, 2, 0, 19 }, + Package(){0x0015FFFF, 3, 0, 16 }, + }) + + Name(PS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + Name(APS2, Package(){ + /* The external GFX - Hooked to PCIe slot 2 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + /* black slot */ + Name(PS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(APS4, Package(){ + /* PCIe slot - Hooked to PCIe slot 4 */ + Package(){0x0000FFFF, 0, 0, 16 }, + Package(){0x0000FFFF, 1, 0, 17 }, + Package(){0x0000FFFF, 2, 0, 18 }, + Package(){0x0000FFFF, 3, 0, 19 }, + }) + + Name(PS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(APS5, Package(){ + /* PCIe slot - Hooked to PCIe slot 5 */ + Package(){0x0000FFFF, 0, 0, 17 }, + Package(){0x0000FFFF, 1, 0, 18 }, + Package(){0x0000FFFF, 2, 0, 19 }, + Package(){0x0000FFFF, 3, 0, 16 }, + }) + + Name(PS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, INTC, 0 }, + Package(){0x0000FFFF, 1, INTD, 0 }, + Package(){0x0000FFFF, 2, INTA, 0 }, + Package(){0x0000FFFF, 3, INTB, 0 }, + }) + Name(APS6, Package(){ + /* PCIe slot - Hooked to PCIe slot 6 */ + Package(){0x0000FFFF, 0, 0, 18 }, + Package(){0x0000FFFF, 1, 0, 19 }, + Package(){0x0000FFFF, 2, 0, 16 }, + Package(){0x0000FFFF, 3, 0, 17 }, + }) + + Name(PS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, INTD, 0 }, + Package(){0x0000FFFF, 1, INTA, 0 }, + Package(){0x0000FFFF, 2, INTB, 0 }, + Package(){0x0000FFFF, 3, INTC, 0 }, + }) + + Name(APS7, Package(){ + /* The onboard Ethernet chip - Hooked to PCIe slot 7 */ + Package(){0x0000FFFF, 0, 0, 19 }, + Package(){0x0000FFFF, 1, 0, 16 }, + Package(){0x0000FFFF, 2, 0, 17 }, + Package(){0x0000FFFF, 3, 0, 18 }, + }) + + Name(PBR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, INTA, 0 }, + Package(){0x0000FFFF, 1, INTB, 0 }, + Package(){0x0000FFFF, 2, INTC, 0 }, + Package(){0x0000FFFF, 3, INTD, 0 }, + }) + Name(ABR0, Package(){ + /* PCIx1 on SB */ + Package(){0x0000FFFF, 0, 0, 0x10 }, + Package(){0x0000FFFF, 1, 0, 0x11 }, + Package(){0x0000FFFF, 2, 0, 0x12 }, + Package(){0x0000FFFF, 3, 0, 0x13 }, + }) + + Name(PBR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, INTB, 0 }, + Package(){0x0000FFFF, 1, INTC, 0 }, + Package(){0x0000FFFF, 2, INTD, 0 }, + Package(){0x0000FFFF, 3, INTA, 0 }, + }) + Name(ABR1, Package(){ + /* Onboard network */ + Package(){0x0000FFFF, 0, 0, 0x11 }, + Package(){0x0000FFFF, 1, 0, 0x12 }, + Package(){0x0000FFFF, 2, 0, 0x13 }, + Package(){0x0000FFFF, 3, 0, 0x10 }, + }) + + /* SB PCI Bridge */ + Name(PCIB, Package(){ + /* PCI slots: slot 0 behind Dev14, Fun4. */ + Package(){0x0005FFFF, 0, 0, 0x14 }, + Package(){0x0005FFFF, 1, 0, 0x15 }, + Package(){0x0005FFFF, 2, 0, 0x16 }, + Package(){0x0005FFFF, 3, 0, 0x17 }, + }) diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/sata.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/sata.asl new file mode 100644 index 0000000..46daa0e --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/sata.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* No SATA functionality */ diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/si.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/si.asl new file mode 100644 index 0000000..ff0c3cf --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/si.asl @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + Scope(\_SI) { + Method(_SST, 1) { + /* DBGO("\\_SI\\_SST\n") */ + /* DBGO(" New Indicator state: ") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + } + } /* End Scope SI */ diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/sleep.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/sleep.asl new file mode 100644 index 0000000..1d553bd --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/sleep.asl @@ -0,0 +1,96 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* Wake status package */ +Name(WKST,Package(){Zero, Zero}) + +/* +* \_PTS - Prepare to Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2, etc +* +* Exit: +* -none- +* +* The _PTS control method is executed at the beginning of the sleep process +* for S1-S5. The sleeping value is passed to the _PTS control method. This +* control method may be executed a relatively long time before entering the +* sleep state and the OS may abort the operation without notification to +* the ACPI driver. This method cannot modify the configuration or power +* state of any device in the system. +*/ +Method(\_PTS, 1) { + /* DBGO("\\_PTS\n") */ + /* DBGO("From S0 to S") */ + /* DBGO(Arg0) */ + /* DBGO("\n") */ + + /* Clear sleep SMI status flag and enable sleep SMI trap. */ + /*Store(One, CSSM) + Store(One, SSEN)*/ + + /* On older chips, clear PciExpWakeDisEn */ + /*if (LLessEqual(\_SB.SBRI, 0x13)) { + * Store(0,\_SB.PWDE) + *} + */ + + /* Clear wake status structure. */ + Store(0, Index(WKST,0)) + Store(0, Index(WKST,1)) + + Store (0x07, UPWS) +} /* End Method(\_PTS) */ + +/* +* \_BFS OEM Back From Sleep method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* -none- +*/ +Method(\_BFS, 1) { + /* DBGO("\\_BFS\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ +} + +/* +* \_WAK System Wake method +* +* Entry: +* Arg0=The value of the sleeping state S1=1, S2=2 +* +* Exit: +* Return package of 2 DWords +* Dword 1 - Status +* 0x00000000 wake succeeded +* 0x00000001 Wake was signaled but failed due to lack of power +* 0x00000002 Wake was signaled but failed due to thermal condition +* Dword 2 - Power Supply state +* if non-zero the effective S-state the power supply entered +*/ +Method(\_WAK, 1) { + /* DBGO("\\_WAK\n") */ + /* DBGO("From S") */ + /* DBGO(Arg0) */ + /* DBGO(" to S0\n") */ + + Return(WKST) +} /* End Method(\_WAK) */ diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/superio.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/superio.asl new file mode 100644 index 0000000..6f95a8a --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/superio.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* No Super I/O device or functionality yet */ diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/thermal.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/thermal.asl new file mode 100644 index 0000000..d769f9a --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/thermal.asl @@ -0,0 +1,16 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* No thermal zone functionality */ diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi/usb_oc.asl b/src/mainboard/asus/f2a85-m_fam10/acpi/usb_oc.asl new file mode 100644 index 0000000..f5d6980 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi/usb_oc.asl @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* USB overcurrent mapping pins. */ +Name(UOM0, 0) +Name(UOM1, 2) +Name(UOM2, 0) +Name(UOM3, 7) +Name(UOM4, 2) +Name(UOM5, 2) +Name(UOM6, 6) +Name(UOM7, 2) +Name(UOM8, 6) +Name(UOM9, 6) diff --git a/src/mainboard/asus/f2a85-m_fam10/acpi_tables.c b/src/mainboard/asus/f2a85-m_fam10/acpi_tables.c new file mode 100644 index 0000000..3433bfc --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/acpi_tables.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpigen.h> +#include <arch/ioapic.h> +#include <console/console.h> +#include <cpu/amd/amdfam15.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <string.h> + +unsigned long acpi_fill_madt(unsigned long current) +{ + /* create all subtables for processors */ + current = acpi_create_madt_lapics(current); + + /* Write Hudson IOAPIC, only one */ + current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, CONFIG_MAX_CPUS, + IO_APIC_ADDR, 0); + + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 0, 2, 0); + current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) + current, 0, 9, 9, 0xF); + /* 0: mean bus 0--->ISA */ + /* 0: PIC 0 */ + /* 2: APIC 2 */ + /* 5 mean: 0101 --> Edge-triggered, Active high */ + + /* create all subtables for processors */ + current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, 0xff, 5, 1); + /* 1: LINT1 connect to NMI */ + + return current; +} diff --git a/src/mainboard/asus/f2a85-m_fam10/board_info.txt b/src/mainboard/asus/f2a85-m_fam10/board_info.txt new file mode 100644 index 0000000..091def6 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: http://www.asus.com/Motherboards/AMD_Socket_FM2/F2A85M/ +ROM package: DIP8 +ROM protocol: [http://www.winbond-usa.com/hq/enu/ProductAndSales/ProductLines/FlashMemory/… SPI] +ROM socketed: y +Flashrom support: y +Release year: 2013 diff --git a/src/mainboard/asus/f2a85-m_fam10/bootblock.c b/src/mainboard/asus/f2a85-m_fam10/bootblock.c new file mode 100644 index 0000000..77a9e41 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/bootblock.c @@ -0,0 +1,23 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> + +void bootblock_mainboard_init(void) +{ + bootblock_northbridge_init(); + bootblock_southbridge_init(); +} diff --git a/src/mainboard/asus/f2a85-m_fam10/cmos.layout b/src/mainboard/asus/f2a85-m_fam10/cmos.layout new file mode 100644 index 0000000..d83bb14 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/cmos.layout @@ -0,0 +1,74 @@ +#***************************************************************************** +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +#***************************************************************************** + +entries + +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +392 3 e 5 baud_rate +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum +# Reserve the extended AMD configuration registers +1000 24 r 0 amd_reserved + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +5 0 115200 +5 1 57600 +5 2 38400 +5 3 19200 +5 4 9600 +5 5 4800 +5 6 2400 +5 7 1200 +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/asus/f2a85-m_fam10/devicetree.cb b/src/mainboard/asus/f2a85-m_fam10/devicetree.cb new file mode 100644 index 0000000..0d826cc --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/devicetree.cb @@ -0,0 +1,125 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +chip northbridge/amd/amdfam10/root_complex + + device cpu_cluster 0 on + chip cpu/amd/socket_FM2 + device lapic 10 on end + end + end + + device domain 0 on + subsystemid 0x1022 0x1410 inherit + chip northbridge/amd/amdfam10 # NB RAM Controller + + device pci 0.0 on end # Root Complex + device pci 0.2 on end # IOMMU + device pci 1.0 on end # Internal Graphics P2P bridge 0x99XX + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIE SLOT0 x16 blue + device pci 3.0 off end # unused? + device pci 4.0 on end # PCIE 4x black + device pci 5.0 off end # unused? + device pci 6.0 off end # unused? + device pci 7.0 off end # LAN + device pci 8.0 off end # NB/SB Link P2P bridge + + device pci 18.0 on + chip southbridge/amd/sb900 # it is under NB/SB Link, but on the same pci bus + device pci 10.0 on end # XHCI HC0 + device pci 10.1 on end # XHCI HC1 + device pci 11.0 on end # SATA + device pci 12.0 on end # USB + device pci 12.2 on end # USB + device pci 13.0 on end # USB + device pci 13.2 on end # USB + device pci 14.0 on # SMBUS + chip drivers/generic/generic #dimm 0 + device i2c 50 on end # 7-bit SPD address + end + chip drivers/generic/generic #dimm 1 + device i2c 51 on end # 7-bit SPD address + end + end # SM + device pci 14.1 off end # IDE 0x439c + device pci 14.2 on end # HDA 0x4383 + device pci 14.3 on # LPC 0x439d + chip superio/ite/it8728f + register hwm_ctl_register = "0xc0" + register hwm_main_ctl_register = "0x33" + register hwm_adc_temp_chan_en_reg = "0x38" + register hwm_fan1_ctl_pwm = "0x00" + register hwm_fan2_ctl_pwm = "0x00" + register hwm_fan3_ctl_pwm = "0x00" + + device pnp 2e.0 off # Floppy + io 0x60 = 0x3f0 + irq 0x70 = 6 + drq 0x74 = 2 + end + device pnp 2e.1 on # Com1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.2 off # Com2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.3 off # Parallel Port + io 0x60 = 0x378 + irq 0x70 = 7 + end + device pnp 2e.4 on # Env Controller + io 0x60 = 0x290 + io 0x62 = 0x220 + irq 0x70 = 0 + end + device pnp 2e.5 on # Keyboard + io 0x60 = 0x60 + io 0x62 = 0x64 + irq 0x70 = 1 + end + device pnp 2e.6 off # Mouse + irq 0x70 = 12 + end + device pnp 2e.7 on # GPIO + io 0x60 = 0x228 #SMI + io 0x62 = 0x300 #Simple I/O + io 0x64 = 0x238 #Phony resource IT8603E does not have it + irq 0x70 = 0 + end + device pnp 2e.a off end # CIR + end #superio/ite/it8728f + end #device pci 14.3 # LPC + device pci 14.4 on end # PCI 0x4384 + device pci 14.5 on end # USB 2 + device pci 14.6 off end # Gec + device pci 14.7 off end # SD + device pci 15.0 on end # PCIe 0 - onboard PCIe 1x + device pci 15.1 on end # PCIe 1 onboard gigabit + device pci 15.2 off end # unused + device pci 15.3 off end # unused + + end #chip southbridge/amd/sb900 + end #18.0 + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end + end #chip northbridge/amd/amdfam10 + end #domain +end #chip northbridge/amd/amdfam10/root_complex diff --git a/src/mainboard/asus/f2a85-m_fam10/dsdt.asl b/src/mainboard/asus/f2a85-m_fam10/dsdt.asl new file mode 100644 index 0000000..a58ab7e --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/dsdt.asl @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2013 Sage Electronic Engineering, LLC + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* DefinitionBlock Statement */ +DefinitionBlock ( + "DSDT.AML", /* Output filename */ + "DSDT", /* Signature */ + 0x02, /* DSDT Revision, needs to be 2 for 64bit */ + "ASUS ", /* OEMID */ + "COREBOOT", /* TABLE ID */ + 0x00010001 /* OEM Revision */ + ) +{ /* Start of ASL file */ + /* #include <arch/x86/acpi/debug.asl> */ /* Include global debug methods if needed */ + + //#include "acpi/usb_oc.asl" + + //#include "northbridge/amd/amdfam10/amdfam10_util.asl" + + /* Globals for the platform */ + //#include "acpi/mainboard.asl" + + /* Describe the Sleep Methods (WAK, PTS, GTS, etc.) for this platform */ + //#include "acpi/sleep.asl" + + Scope(\_SB) { + /* global utility methods expected within the \_SB scope */ + //#include <arch/x86/acpi/globutil.asl> + + /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ + //#include "acpi/routing.asl" + + } /* End Scope(_SB) */ +} +/* End of ASL file */ diff --git a/src/mainboard/asus/f2a85-m_fam10/get_bus_conf.c b/src/mainboard/asus/f2a85-m_fam10/get_bus_conf.c new file mode 100644 index 0000000..f627bd6 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/get_bus_conf.c @@ -0,0 +1,5 @@ +#include <cpu/amd/amdfam10_sysconf.h> + +void get_bus_conf(void) +{ +} diff --git a/src/mainboard/asus/f2a85-m_fam10/hdaverb b/src/mainboard/asus/f2a85-m_fam10/hdaverb new file mode 100644 index 0000000..a544e2a --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/hdaverb @@ -0,0 +1,24 @@ +const CODEC_ENTRY f2a85_m_alc887_VerbTbl[] = { +> {0x11, 0x99430140}, +> {0x12, 0x411111f0}, +> {0x14, 0x01014010}, +> {0x15, 0x01011012}, +> {0x16, 0x01016011}, +> {0x17, 0x01012014}, +> {0x18, 0x01a19850}, +> {0x19, 0x02a19c60}, +> {0x1a, 0x0181305f}, +> {0x1b, 0x02214c20}, +> {0x1c, 0x411111f0}, +> {0x1d, 0x4005e601}, +> {0x1e, 0x01456130}, +> {0x1f, 0x411111f0}, +> {0xff, 0xffffffff} +}; + +static const CODEC_TBL_LIST CodecTableList[] = +{ +> {0x10ec0887, (CODEC_ENTRY*)&f2a85_m_alc887_VerbTbl[0]}, +> {(UINT32)0x0FFFFFFFF, (CODEC_ENTRY*)0x0FFFFFFFFUL} +}; + diff --git a/src/mainboard/asus/f2a85-m_fam10/irq_tables.c b/src/mainboard/asus/f2a85-m_fam10/irq_tables.c new file mode 100644 index 0000000..eeaf8d3 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/irq_tables.c @@ -0,0 +1,103 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/pirq_routing.h> +#include <console/console.h> +#include <cpu/amd/amdfam15.h> +#include <device/pci_def.h> +#include <stdint.h> +#include <string.h> + +static void write_pirq_info(struct irq_info *pirq_info, u8 bus, u8 devfn, + u8 link0, u16 bitmap0, u8 link1, u16 bitmap1, + u8 link2, u16 bitmap2, u8 link3, u16 bitmap3, + u8 slot, u8 rfu) +{ + pirq_info->bus = bus; + pirq_info->devfn = devfn; + pirq_info->irq[0].link = link0; + pirq_info->irq[0].bitmap = bitmap0; + pirq_info->irq[1].link = link1; + pirq_info->irq[1].bitmap = bitmap1; + pirq_info->irq[2].link = link2; + pirq_info->irq[2].bitmap = bitmap2; + pirq_info->irq[3].link = link3; + pirq_info->irq[3].bitmap = bitmap3; + pirq_info->slot = slot; + pirq_info->rfu = rfu; +} + + +unsigned long write_pirq_routing_table(unsigned long addr) +{ + struct irq_routing_table *pirq; + struct irq_info *pirq_info; + u32 slot_num; + u8 *v; + + u8 sum = 0; + int i; + + /* Align the table to be 16 byte aligned. */ + addr += 15; + addr &= ~15; + + /* This table must be between 0xf0000 & 0x100000 */ + printk(BIOS_INFO, "Writing IRQ routing tables to 0x%lx...", addr); + + pirq = (void *)(addr); + v = (u8 *) (addr); + + pirq->signature = PIRQ_SIGNATURE; + pirq->version = PIRQ_VERSION; + + pirq->rtr_bus = 0; + pirq->rtr_devfn = PCI_DEVFN(0x14, 4); + + pirq->exclusive_irqs = 0; + + pirq->rtr_vendor = 0x1002; + pirq->rtr_device = 0x4384; + + pirq->miniport_data = 0; + + memset(pirq->rfu, 0, sizeof(pirq->rfu)); + + pirq_info = (void *)(&pirq->checksum + 1); + slot_num = 0; + + /* pci bridge */ + write_pirq_info(pirq_info, 0, PCI_DEVFN(0x14, 4), + 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, + 0); + pirq_info++; + + slot_num++; + + pirq->size = 32 + 16 * slot_num; + + for (i = 0; i < pirq->size; i++) + sum += v[i]; + + sum = pirq->checksum - sum; + + if (sum != pirq->checksum) { + pirq->checksum = sum; + } + + printk(BIOS_INFO, "write_pirq_routing_table done.\n"); + + return (unsigned long)pirq_info; +} diff --git a/src/mainboard/asus/f2a85-m_fam10/mainboard.c b/src/mainboard/asus/f2a85-m_fam10/mainboard.c new file mode 100644 index 0000000..e1a1712 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/mainboard.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/msr.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> + +static void mainboard_enable(device_t dev) +{ + msr_t msr; + + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + msr = rdmsr(0xC0011020); + msr.lo &= ~(1 << 28); + wrmsr(0xC0011020, msr); + + msr = rdmsr(0xC0011022); + msr.lo &= ~(1 << 4); + msr.lo &= ~(1 << 13); + wrmsr(0xC0011022, msr); + + msr = rdmsr(0xC0011023); + msr.lo &= ~(1 << 23); + wrmsr(0xC0011023, msr); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, +}; diff --git a/src/mainboard/asus/f2a85-m_fam10/mptable.c b/src/mainboard/asus/f2a85-m_fam10/mptable.c new file mode 100644 index 0000000..267c824 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/mptable.c @@ -0,0 +1,182 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/ioapic.h> +#include <arch/smp/mpspec.h> +#include <cpu/amd/amdfam15.h> +#include <cpu/x86/lapic.h> +#include <device/pci.h> +#include <stdint.h> +#include <string.h> + +u8 picr_data[] = { + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x0A,0xF1,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x1F,0x1F,0x1F,0x1F +}; +u8 intr_data[0x54] = { + 0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x00,0x00,0x00,0x00,0x1F,0x1F,0x1F,0x1F, + 0x09,0x1F,0x1F,0x10,0x1F,0x10,0x1F,0x10,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x05,0x1F,0x1F,0x1F,0x1F,0x1F,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x12,0x11,0x12,0x11,0x12,0x11,0x12,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x11,0x13,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00, + 0x10,0x11,0x12,0x13 +}; + +static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) +{ + mc->mpc_length += length; + mc->mpc_entry_count++; +} + +static void my_smp_write_bus(struct mp_config_table *mc, + unsigned char id, const char *bustype) +{ + struct mpc_config_bus *mpc; + mpc = smp_next_mpc_entry(mc); + memset(mpc, '\0', sizeof(*mpc)); + mpc->mpc_type = MP_BUS; + mpc->mpc_busid = id; + memcpy(mpc->mpc_bustype, bustype, sizeof(mpc->mpc_bustype)); + smp_add_mpc_entry(mc, sizeof(*mpc)); +} + +static void *smp_write_config_table(void *v) +{ + struct mp_config_table *mc; + int bus_isa; + u8 byte; + + /* + * By the time this function gets called, the IOAPIC registers + * have been written so they can be read to get the correct + * APIC ID and Version + */ + u8 ioapic_id = (io_apic_read(VIO_APIC_VADDR, 0x00) >> 24); + u8 ioapic_ver = (io_apic_read(VIO_APIC_VADDR, 0x01) & 0xFF); + + mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); + + mptable_init(mc, LOCAL_APIC_ADDR); + memcpy(mc->mpc_oem, "AMD ", 8); + + smp_write_processors(mc); + + //mptable_write_buses(mc, NULL, &bus_isa); + my_smp_write_bus(mc, 0, "PCI "); + my_smp_write_bus(mc, 1, "PCI "); + bus_isa = 0x02; + my_smp_write_bus(mc, bus_isa, "ISA "); + + /* I/O APICs: APIC ID Version State Address */ + smp_write_ioapic(mc, ioapic_id, ioapic_ver, VIO_APIC_VADDR); + + /* PIC IRQ routine */ + for (byte = 0x0; byte < sizeof(picr_data); byte ++) { + outb(byte, 0xC00); + outb(picr_data[byte], 0xC01); + } + + /* APIC IRQ routine */ + for (byte = 0x0; byte < sizeof(intr_data); byte ++) { + outb(byte | 0x80, 0xC00); + outb(intr_data[byte], 0xC01); + } + + /* I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ +#define IO_LOCAL_INT(type, intr, apicid, pin) \ + smp_write_lintsrc(mc, (type), MP_IRQ_TRIGGER_EDGE | MP_IRQ_POLARITY_HIGH, bus_isa, (intr), (apicid), (pin)); + mptable_add_isa_interrupts(mc, bus_isa, ioapic_id, 0); + + /* PCI interrupts are level triggered, and are + * associated with a specific bus/device/function tuple. + */ +#define PCI_INT(bus, dev, int_sign, pin) \ + smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), ioapic_id, (pin)) + + /* IOMMU */ + PCI_INT(0x0, 0x0, 0x0, 0x10); + PCI_INT(0x0, 0x0, 0x1, 0x11); + PCI_INT(0x0, 0x0, 0x2, 0x12); + PCI_INT(0x0, 0x0, 0x3, 0x13); + + /* Internal VGA */ + PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]); + PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]); + + /* SMBUS */ + PCI_INT(0x0, 0x14, 0x0, 0x10); + + /* HD Audio */ + PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]); + + /* USB */ + PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); + PCI_INT(0x0, 0x12, 0x1, intr_data[0x31]); + PCI_INT(0x0, 0x13, 0x0, intr_data[0x32]); + PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]); + PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]); + PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]); + PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]); + + /* sata */ + PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); + PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); + + /* on board NIC & Slot PCIE. */ + + /* PCI slots */ + device_t dev = dev_find_slot(0, PCI_DEVFN(0x14, 4)); + if (dev && dev->enabled) { + u8 bus_pci = dev->link_list->secondary; + /* PCI_SLOT 0. */ + PCI_INT(bus_pci, 0x5, 0x0, 0x14); + PCI_INT(bus_pci, 0x5, 0x1, 0x15); + PCI_INT(bus_pci, 0x5, 0x2, 0x16); + PCI_INT(bus_pci, 0x5, 0x3, 0x17); + } + + /* PCIe Lan*/ + PCI_INT(0x0, 0x06, 0x0, 0x13); + + /* FCH PCIe PortA */ + PCI_INT(0x0, 0x15, 0x0, 0x10); + /* FCH PCIe PortB */ + PCI_INT(0x0, 0x15, 0x1, 0x11); + /* FCH PCIe PortC */ + PCI_INT(0x0, 0x15, 0x2, 0x12); + /* FCH PCIe PortD */ + PCI_INT(0x0, 0x15, 0x3, 0x13); + + /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ + IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); + IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); + /* There is no extension information... */ + + /* Compute the checksums */ + return mptable_finalize(mc); +} + +unsigned long write_smp_table(unsigned long addr) +{ + void *v; + v = smp_write_floating_table(addr, 0); + return (unsigned long)smp_write_config_table(v); +} diff --git a/src/mainboard/asus/f2a85-m_fam10/romstage.c b/src/mainboard/asus/f2a85-m_fam10/romstage.c new file mode 100644 index 0000000..b756b49 --- /dev/null +++ b/src/mainboard/asus/f2a85-m_fam10/romstage.c @@ -0,0 +1,353 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Advanced Micro Devices, Inc. + * Copyright (C) 2012 Rudolf Marek <r.marek(a)assembler.cz> + * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +unsigned int get_sbdn(unsigned bus); + +#include <arch/acpi.h> +#include <arch/cpu.h> +#include <arch/io.h> +#include <arch/stages.h> +#include <cbmem.h> +#include <console/console.h> +#include <cpu/amd/car.h> +#include <cpu/x86/bist.h> +#include <cpu/x86/lapic.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <device/pnp_def.h> +#include <spd.h> +#include <cpu/amd/model_10xxx_rev.h> +#include <northbridge/amd/amdfam10/raminit.h> +#include <northbridge/amd/amdfam10/amdfam10.h> +#include <delay.h> +#include "northbridge/amd/amdfam10/reset_test.c" +#include <stdint.h> +#include <string.h> +#include <superio/ite/common/ite.h> +#include <superio/ite/it8728f/it8728f.h> +#include <southbridge/amd/sb900/sb900.h> +#include <southbridge/amd/sb900/smbus.h> +#include "northbridge/amd/amdfam10/debug.c" +//#include "northbridge/amd/amdfam10/setup_resource_map.c" + +#define MMIO_NON_POSTED_START 0xfed00000 +#define MMIO_NON_POSTED_END 0xfedfffff +#define SB_MMIO 0xFED80000 +#define SB_MMIO_MISC32(x) *(volatile u32 *)(SB_MMIO + 0xE00 + (x)) + +#define SMBUS_IO_BASE 0xb00 +#define SMBUS_AUX_IO_BASE 0xb20 + +#define SERIAL_DEV PNP_DEV(0x2e, IT8728F_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8728F_GPIO) + +static void writepmreg (int reg, int data) +{ + outb(reg, 0xCD6); + outb(data, 0xCD7); +} + +static void activate_spd_rom(const struct mem_controller *ctrl) +{ + u32 iobase = SMBUS_IO_BASE; + + writepmreg (0x2D, iobase >> 8); + writepmreg (0x2C, iobase | 1); + /* Set SMBUS clock to 400KHz */ + outb(66000000 / 400000 / 4, iobase + 0x0E); +} + +inline int spd_read_byte(unsigned device, unsigned address) +{ + return do_smbus_read_byte(SMBUS_IO_BASE, device, address); +} + +static const uint8_t spd_addr_fam15[] = { + // Socket 0 Node 0 ("Node 0") + RC00, DIMM0, DIMM1, 0, 0, DIMM2, DIMM3, 0, 0, +}; + +#include <northbridge/amd/amdfam10/amdfam10.h> +#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" +#include "northbridge/amd/amdfam10/pci.c" +//#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" + +#include <cpu/amd/microcode.h> + +#include "cpu/amd/family_10h-family_15h/init_cpus.c" +//#include "northbridge/amd/amdfam10/early_ht.c" + +static void sbxxx_enable_48mhzout(void) +{ + /* most likely programming to 48MHz out signal */ + u32 reg32; + reg32 = SB_MMIO_MISC32(0x28); + reg32 &= 0xffc7ffff; + reg32 |= 0x00100000; + SB_MMIO_MISC32(0x28) = reg32; + + reg32 = SB_MMIO_MISC32(0x40); + reg32 &= ~0x80u; + SB_MMIO_MISC32(0x40) = reg32; +} + +static void set_ddr3_voltage(uint8_t node, uint8_t index) { + uint8_t byte; + uint8_t value = 0; + + if (index == 0) + value = 0x0; + else if (index == 1) + value = 0x1; + else if (index == 2) + value = 0x4; + else if (index == 3) + value = 0x5; + if (node == 1) + value <<= 1; + + /* Set GPIOs */ + byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd1); + if (node == 0) + byte &= ~0x5; + if (node == 1) + byte &= ~0xa; + byte |= value; + pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd1, byte); + + /* Enable GPIO output drivers */ + byte = pci_read_config8(PCI_DEV(0, 0x14, 3), 0xd0); + byte &= 0x0f; + pci_write_config8(PCI_DEV(0, 0x14, 3), 0xd0, byte); +} + +void DIMMSetVoltages(struct MCTStatStruc *pMCTstat, + struct DCTStatStruc *pDCTstatA) { + u8 dimm; + u8 socket = 0; + u8 set_voltage = 0x1; + + set_ddr3_voltage(socket, set_voltage); + + /* Save 1.5V DIMM voltages for MCT and SMBIOS use */ + for (dimm = 0; dimm < MAX_DIMMS_SUPPORTED; dimm++) { + pDCTstatA->DimmConfiguredVoltage[dimm] = set_voltage; + } + /* Allow the DDR supply voltages to settle */ + udelay(100000); + printk(BIOS_DEBUG, "DIMM voltage set to index %02x\n", set_voltage); +} + +unsigned int get_sbdn(unsigned int bus) +{ + device_t dev; + + dev = PCI_DEV(0, 0x14, 0); + return (dev >> 15) & 0x1f; +} + +void soft_reset(void) +{ +} + +static void execute_memory_test(void) +{ + /* Test DRAM functionality */ + uint32_t i; + uint32_t* dataptr; + printk(BIOS_DEBUG, "Writing test patterns to memory...\n"); + for (i=0; i < 0x1000000; i = i + 8) { + dataptr = (void *)(0x300000 + i); + *dataptr = 0x55555555; + dataptr = (void *)(0x300000 + i + 4); + *dataptr = 0xaaaaaaaa; + } + printk(BIOS_DEBUG, "Done!\n"); + printk(BIOS_DEBUG, "Testing memory...\n"); + uint32_t readback; + for (i=0; i < 0x1000000; i = i + 8) { + dataptr = (void *)(0x300000 + i); + readback = *dataptr; + if (readback != 0x55555555) + printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0x55555555); + dataptr = (void *)(0x300000 + i + 4); + readback = *dataptr; + if (readback != 0xaaaaaaaa) + printk(BIOS_DEBUG, "%p: INCORRECT VALUE %08x (should have been %08x)\n", dataptr, readback, 0xaaaaaaaa); + } + printk(BIOS_DEBUG, "Done!\n"); +} + +void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) +{ + u32 val; + u8 byte; + device_t dev; + uint32_t bsp_apicid = 0; + msr_t msr; + + struct sys_info *sysinfo = &sysinfo_car; + + /* Limit the maximum HT speed to 2.6GHz to prevent lockups + * due to HT CPU <--> CPU wiring not being validated to 3.2GHz + */ + sysinfo->ht_link_cfg.ht_speed_limit = 2600; + + if (!cpu_init_detectedx && boot_cpu()) { + + //set_bsp_node_CHtExtNodeCfgEn(); + //enumerate_ht_chain(); + + /* enable SIO LPC decode */ + dev = PCI_DEV(0, 0x14, 3); + byte = pci_read_config8(dev, 0x48); + byte |= 3; /* 2e, 2f */ + pci_write_config8(dev, 0x48, byte); + + /* enable serial decode */ + byte = pci_read_config8(dev, 0x44); + byte |= (1 << 6); /* 0x3f8 */ + pci_write_config8(dev, 0x44, byte); + + sb900_pci_port80(); + + post_code(0x30); + + /* enable SB MMIO space */ + outb(0x24, 0xcd6); + outb(0x1, 0xcd7); + + /* enable SIO clock */ + sbxxx_enable_48mhzout(); + ite_kill_watchdog(GPIO_DEV); + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + ite_enable_3vsbsw(GPIO_DEV); + console_init(); + + printk(BIOS_SPEW, "CONSOLE: Hello\n"); + + /* turn on secondary smbus at b20 */ + outb(0x28, 0xcd6); + byte = inb(0xcd7); + byte |= 1; + outb(byte, 0xcd7); + } + + if (bist == 0) + bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); + + post_code(0x34); + + /* Halt if there was a built in self test failure */ + report_bist_failure(bist); + + /* Load MPB */ + val = cpuid_eax(1); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); + + set_sysinfo_in_ram(0); + + //update_microcode(val); + + cpuSetAMDMSR(0); + + /* Pass NULL to this function to skip */ + amd_ht_init(NULL); + //amd_ht_fixup(sysinfo); + + post_code(0x35); + + finalize_node_setup(sysinfo); + //setup_mb_resource_map(); + post_code(0x36); + + /* Wait for all the APs core0 started by finalize_node_setup. */ + wait_all_core0_started(); + + if (IS_ENABLED(CONFIG_LOGICAL_CPUS)) { + /* Core0 on each node is configured. Now setup any additional cores. */ + printk(BIOS_DEBUG, "start_other_cores()\n"); + start_other_cores(bsp_apicid); + post_code(0x37); + wait_all_other_cores_started(bsp_apicid); + } + + if (IS_ENABLED(CONFIG_SET_FIDVID)) { + msr = rdmsr(0xc0010071); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + + /* FIXME: The sb fid change may survive the warm reset and only need to be done once */ + //enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); + + post_code(0x38); + + if (!warm_reset_detect(0)) { // BSP is node 0 + init_fidvid_bsp(bsp_apicid, sysinfo->nodes); + } else { + init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 + } + + post_code(0x39); + + /* show final fid and vid */ + msr=rdmsr(0xc0010071); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); + } + + post_code(0x3a); + + set_ddr3_voltage(0, 1); + + post_code(0x3b); + + ///* Set up peripheral control lines */ + //set_peripheral_control_lines(); + fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr_fam15); + + post_code(0x40); + printk(BIOS_DEBUG, "do raminit..."); + raminit_amdmct(sysinfo); + printk(BIOS_DEBUG, "done\n"); + post_code(0x41); + + execute_memory_test(); + + post_code(0x42); + + cbmem_initialize_empty(); + + amdmct_cbmem_store_info(sysinfo); + + post_cache_as_ram(); + + post_code(0xee); /* Should never see this post code. */ +} + +BOOL AMD_CB_ManualBUIDSwapList (u8 node, u8 link, const u8 **List) +{ + /* Force BUID to 0 */ + static const u8 swaplist[] = { 0xFF, CONFIG_HT_CHAIN_UNITID_BASE, + CONFIG_HT_CHAIN_END_UNITID_BASE, 0xFF }; + if ((node == 0) && (link == 0)) { /* BSP SB link */ + *List = swaplist; + return 1; + } + + return 0; +}

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coreboot-gerrit February 2016