coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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1305 discussions

New patch to review for coreboot: lib: Implement framework for retrieving WiFi regulatory domain
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13836 -gerrit commit 6685f94a52b54e35579627852b96bc613b0fddec Author: Felix Durairaj <felixx.durairaj(a)intel.com> Date: Fri Nov 20 15:51:35 2015 -0800 lib: Implement framework for retrieving WiFi regulatory domain Platforms that need to initialize WRDD package with the regulatory domain information should implement function wifi_regulatory_domain. A weak implementation is provided here. Signed-off-by: fdurairx <felixx.durairaj(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/314384 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Commit-Queue: Hannah Williams <hannah.williams(a)intel.com> Tested-by: Hannah Williams <hannah.williams(a)intel.com> (cherry picked from commit c25d7221679d1fab830d614eeabfa3436bce6ac1) BUG=chrome-os-partner:50516 BRANCH=glados TEST=build and boot on chell Change-Id: I1cbdf4e940b009c74ee8ed8f4fca85f4f5c943b2 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 27bba336e620a2d3d331e350d4f46164e337fabc Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Change-Id: I84e2acd748856437b40bbf997bf23f158c711712 Original-Reviewed-on: https://chromium-review.googlesource.com/329291 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/lib/Makefile.inc | 1 + src/lib/wrdd.c | 22 ++++++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 7d1d146..646fefa 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -114,6 +114,7 @@ ramstage-y += cbfs.c ramstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ramstage-y += lzma.c lzmadecode.c ramstage-y += stack.c +ramstage-y += wrdd.c ramstage-$(CONFIG_CONSOLE_CBMEM) += cbmem_console.c ramstage-$(CONFIG_BOOTSPLASH) += jpeg.c ramstage-$(CONFIG_TRACE) += trace.c diff --git a/src/lib/wrdd.c b/src/lib/wrdd.c new file mode 100644 index 0000000..da082f8 --- /dev/null +++ b/src/lib/wrdd.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <wrdd.h> + +uint16_t __attribute__((weak)) wifi_regulatory_domain(void) +{ + return WRDD_DEFAULT_REGULATORY_DOMAIN; +}

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New patch to review for coreboot: Skylake: Support Intel Speed Shift Technology based on config
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13835 -gerrit commit 8ff7fbd2289c08e08ca81f64f77d01ad4f1936d6 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Mon Feb 8 17:15:29 2016 +0530 Skylake: Support Intel Speed Shift Technology based on config Intel Speed Shift Technology is a new mechanism that replaces Legacy P-state. ISST allows OS hints about energy/performance preference. H/W performs the actual P-state control (autonomous) 1. Optimization frequency seclection for low residency workloads, no longer a static knee point. 2. Optimized frequency selection for best energy to performance trade offs. 3. Kick down frequency (from idle) fpr best responsiveness while taking energy consumption init account. Coreboot's responsiblity is to configure MSR 0x1AA ISST_EN bits which will reflect in CPUID.06h:EAX[Bit 7] that driver checkes and enable HWP accordingly. BUG=chrome-os-partner:47517 BRANCH=None TEST=Booted kunimitsu and verify HWP getting enabled/disabled using Intel P-state driver. Change-Id: I91722aa1077f4ef6c8620b103be3e29cfcd974e5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: aa7d004cb2e19047e4434e3e2544cf69393ce28f Original-Change-Id: Ie617da337babde7f196a7af712263e37f7eed56f Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/313107 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Wenkai Du <wenkai.du(a)intel.com> --- src/soc/intel/skylake/chip.h | 2 ++ src/soc/intel/skylake/cpu.c | 29 +++++++++++++++++++++++++++++ src/soc/intel/skylake/include/soc/msr.h | 3 +++ 3 files changed, 34 insertions(+) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 0b87f2d..6203916 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -326,6 +326,8 @@ struct soc_intel_skylake_config { /* PL2 Override value in Watts */ u32 tdp_pl2_override; u8 PmTimerDisabled; + /* Intel Speed Shift Technology */ + u8 speed_shift_enable; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 2fa8582..327bee9 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -207,6 +207,32 @@ static void configure_thermal_target(void) } } +static void configure_isst(void) +{ + device_t dev = SA_DEV_ROOT; + config_t *conf = dev->chip_info; + msr_t msr; + + if (conf->speed_shift_enable) { + /* + * Kernel driver checks CPUID.06h:EAX[Bit 7] to determine if HWP + is supported or not. Coreboot needs to configure MSR 0x1AA + which is then reflected in the CPUID register. + */ + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo |= MISC_PWR_MGMT_ISST_EN; /* Enable Speed Shift */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_INT; /* Enable Interrupt */ + msr.lo |= MISC_PWR_MGMT_ISST_EN_EPP; /* Enable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } else { + msr = rdmsr(MSR_MISC_PWR_MGMT); + msr.lo &= ~MISC_PWR_MGMT_ISST_EN; /* Disable Speed Shift */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_INT; /* Disable Interrupt */ + msr.lo &= ~MISC_PWR_MGMT_ISST_EN_EPP; /* Disable EPP */ + wrmsr(MSR_MISC_PWR_MGMT, msr); + } +} + static void configure_misc(void) { msr_t msr; @@ -335,6 +361,9 @@ static void cpu_core_init(device_t cpu) /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); + /* Configure Intel Speed Shift */ + configure_isst(); + /* Thermal throttle activation offset */ configure_thermal_target(); diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index db154b7..4d295e1 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -36,6 +36,9 @@ #define IA32_MISC_ENABLE 0x1a0 #define MSR_MISC_PWR_MGMT 0x1aa #define MISC_PWR_MGMT_EIST_HW_DIS (1 << 0) +#define MISC_PWR_MGMT_ISST_EN (1 << 6) +#define MISC_PWR_MGMT_ISST_EN_INT (1 << 7) +#define MISC_PWR_MGMT_ISST_EN_EPP (1 << 12) #define MSR_TURBO_RATIO_LIMIT 0x1ad #define MSR_TEMPERATURE_TARGET 0x1a2 #define IA32_PERF_CTL 0x199

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New patch to review for coreboot: vboot: Set S3_RESUME flag for vboot context if necessary
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13834 -gerrit commit 87d3eba01c62d302d68e42041cb9b9d53f00b39f Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Feb 19 20:26:07 2016 -0800 vboot: Set S3_RESUME flag for vboot context if necessary If a platform does verification of the memory init step, and it must resume with the same slot that it booted from then it needs to set the vboot context flag when resuming instead of booting. This will affect the slot that is selected to verify and resume from. BUG=chromium:577269 BRANCH=glados TEST=manually tested on chell: 1) ensure that booting from slot A resumes from slot A. 2) ensure that booting from slot B resumes from slot B. 3) do RW update while booted from slot A (so the flags are set to try slot B) and ensure that suspend/resume still functions properly using current slot A. 4) do RW update while booted from slot B (so the flags are set to try slot A) and ensure that suspend/resume still functions properly using current slot B. Change-Id: I77e6320e36b4d2cbc308cfb39f0d4999e3497be3 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 4c84af7eae7b2a52a28cc3ef8a80649301215a68 Original-Change-Id: I395e5abaccd6f578111f242d1e85e28dced469ea Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328775 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/vendorcode/google/chromeos/vboot2/vboot_logic.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c index a4829c0..d43fb27 100644 --- a/src/vendorcode/google/chromeos/vboot2/vboot_logic.c +++ b/src/vendorcode/google/chromeos/vboot2/vboot_logic.c @@ -311,6 +311,15 @@ void verstage_main(void) antirollback_read_space_firmware(&ctx); timestamp_add_now(TS_END_TPMINIT); + /* Set S3 resume flag if vboot should behave differently when selecting + * which slot to boot. This is only relevant to vboot if the platform + * does verification of memory init and thus must ensure it resumes with + * the same slot that it booted from. */ + if (IS_ENABLED(CONFIG_RESUME_PATH_SAME_AS_BOOT) && + IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK) && + vboot_platform_is_resuming()) + ctx.flags |= VB2_CONTEXT_S3_RESUME; + if (!IS_ENABLED(CONFIG_VIRTUAL_DEV_SWITCH) && get_developer_mode_switch()) ctx.flags |= VB2_CONTEXT_FORCE_DEVELOPER_MODE;

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New patch to review for coreboot: skylake: Increase IGD stolen size to 64MB
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13833 -gerrit commit 738d489a5a24dd6a37f5477ce0b05c59d8a8fcd9 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Sat Feb 20 09:10:53 2016 -0800 skylake: Increase IGD stolen size to 64MB The FBC hardware for skylake does not have access to the bios_reserved range so it always assumes 8MB is used and so the kernel will therefore need to avoid using the last 8MB of the stolen window. With the default stolen size of 32MB(-8MB) there is not enough space for FBC to work with a high resolution panel. Kernel reference: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/commit/?id=a… BUG=chrome-os-partner:50396 BRANCH=glados TEST=build and boot on chell DVT Change-Id: I3049d7d9e7c551aad5b8fd1630d5fbd88ccb2692 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: fff1f4b35e23e77cdc72c5bcc290f199494cdbbb Original-Change-Id: If468cca5759a320f3cd2d7eb09f4bcc0117b24cb Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328813 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/romstage/romstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 9b95f72..9c61095 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -85,6 +85,15 @@ void soc_memory_init_params(struct romstage_params *params, dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; + /* + * Set IGD stolen size to 64MB. The FBC hardware for skylake does not + * have access to the bios_reserved range so it always assumes 8MB is + * used and so the kernel will avoid the last 8MB of the stolen window. + * With the default stolen size of 32MB(-8MB) there is not enough space + * for FBC to work with a high resolution panel. + */ + upd->IgdDvmt50PreAlloc = 2; + upd->MmioSize = 0x800; /* 2GB in MB */ upd->TsegSize = CONFIG_SMM_TSEG_SIZE; upd->IedSize = CONFIG_IED_REGION_SIZE;

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New patch to review for coreboot: nyan: Fix timestamps and CBFS SPI integration
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13832 -gerrit commit cd6b484b6ba8371f1e94708672e988630eb21338 Author: Julius Werner <jwerner(a)chromium.org> Date: Wed Feb 17 16:12:46 2016 -0800 nyan: Fix timestamps and CBFS SPI integration Nyan is an old board that was committed before several core code modernizations to timestamp and CBFS code. Not all of those later patches were correctly integrated with old boards like this, and the core code has evolved to a point where it doesn't actually boot anymore. This patch fixes that issue and brings the Nyan boards more in line with how later ARM platforms look. BRANCH=None BUG=None TEST=My Blaze boots again. Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717 Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/328543 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> --- src/mainboard/google/nyan/Kconfig | 3 + src/mainboard/google/nyan_big/Kconfig | 3 + src/mainboard/google/nyan_blaze/Kconfig | 3 + src/soc/nvidia/tegra124/bootblock.c | 3 + src/soc/nvidia/tegra124/include/soc/memlayout.ld | 3 +- src/soc/nvidia/tegra124/spi.c | 92 ------------------------ 6 files changed, 14 insertions(+), 93 deletions(-) diff --git a/src/mainboard/google/nyan/Kconfig b/src/mainboard/google/nyan/Kconfig index 8f0c9de..d03f4d7 100644 --- a/src/mainboard/google/nyan/Kconfig +++ b/src/mainboard/google/nyan/Kconfig @@ -26,12 +26,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config CHROMEOS select CHROMEOS_VBNV_EC select EC_SOFTWARE_SYNC select VIRTUAL_DEV_SWITCH + select COMMON_CBFS_SPI_WRAPPER config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_big/Kconfig b/src/mainboard/google/nyan_big/Kconfig index b6f84f6..3ba61d5 100644 --- a/src/mainboard/google/nyan_big/Kconfig +++ b/src/mainboard/google/nyan_big/Kconfig @@ -27,12 +27,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config CHROMEOS select EC_SOFTWARE_SYNC select CHROMEOS_VBNV_EC select VIRTUAL_DEV_SWITCH + select COMMON_CBFS_SPI_WRAPPER config MAINBOARD_DIR string diff --git a/src/mainboard/google/nyan_blaze/Kconfig b/src/mainboard/google/nyan_blaze/Kconfig index 0fd763d..07d3374 100644 --- a/src/mainboard/google/nyan_blaze/Kconfig +++ b/src/mainboard/google/nyan_blaze/Kconfig @@ -28,12 +28,15 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT select BOARD_ROMSIZE_KB_4096 select SPI_FLASH + select SPI_FLASH_GIGADEVICE + select SPI_FLASH_WINBOND select SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B config CHROMEOS select EC_SOFTWARE_SYNC select CHROMEOS_VBNV_EC select VIRTUAL_DEV_SWITCH + select COMMON_CBFS_SPI_WRAPPER config MAINBOARD_DIR string diff --git a/src/soc/nvidia/tegra124/bootblock.c b/src/soc/nvidia/tegra124/bootblock.c index cebe405..2a526a7 100644 --- a/src/soc/nvidia/tegra124/bootblock.c +++ b/src/soc/nvidia/tegra124/bootblock.c @@ -24,6 +24,7 @@ #include <soc/nvidia/tegra/apbmisc.h> #include <soc/pinmux.h> #include <soc/power.h> +#include <timestamp.h> #include <vendorcode/google/chromeos/chromeos.h> static void run_next_stage(void *entry) @@ -81,6 +82,8 @@ void main(void) PINMUX_PWR_INT_N_FUNC_PMICINTR | PINMUX_INPUT_ENABLE); + timestamp_init(0); + run_romstage(); } diff --git a/src/soc/nvidia/tegra124/include/soc/memlayout.ld b/src/soc/nvidia/tegra124/include/soc/memlayout.ld index c3f5f4e..5bab362 100644 --- a/src/soc/nvidia/tegra124/include/soc/memlayout.ld +++ b/src/soc/nvidia/tegra124/include/soc/memlayout.ld @@ -33,7 +33,8 @@ SECTIONS STACK(0x4000E000, 8K) BOOTBLOCK(0x40010000, 24K) VERSTAGE(0x40016000, 72K) - ROMSTAGE(0x40028000, 96K) + ROMSTAGE(0x40028000, 95K) + TIMESTAMP(0x4003FC00, 1K) SRAM_END(0x40040000) DRAM_START(0x80000000) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index d5f7861..d5be4a6 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -798,69 +798,6 @@ int spi_xfer(struct spi_slave *slave, const void *dout, return ret; } -#define JEDEC_READ 0x03 -#define JEDEC_READ_OUTSIZE 0x04 -#define JEDEC_FAST_READ_DUAL 0x3b -#define JEDEC_FAST_READ_DUAL_OUTSIZE 0x05 - -static struct spi_slave *boot_slave; - -static ssize_t tegra_spi_readat(const struct region_device *rdev, void *dest, - size_t offset, size_t count) -{ - u8 spi_read_cmd[JEDEC_FAST_READ_DUAL_OUTSIZE]; - unsigned int read_cmd_bytes; - int ret = count; - struct tegra_spi_channel *channel; - - channel = to_tegra_spi(boot_slave->bus); - - if (channel->dual_mode) { - /* - * Command 0x3b will interleave data only, command 0xbb will - * interleave the address as well. It's nice to see the address - * plainly when debugging, and we're mostly concerned with - * large transfers so the optimization of using 0xbb isn't - * really worthwhile. - */ - spi_read_cmd[0] = JEDEC_FAST_READ_DUAL; - spi_read_cmd[4] = 0x00; /* dummy byte */ - read_cmd_bytes = JEDEC_FAST_READ_DUAL_OUTSIZE; - } else { - spi_read_cmd[0] = JEDEC_READ; - read_cmd_bytes = JEDEC_READ_OUTSIZE; - } - spi_read_cmd[1] = (offset >> 16) & 0xff; - spi_read_cmd[2] = (offset >> 8) & 0xff; - spi_read_cmd[3] = offset & 0xff; - - spi_claim_bus(boot_slave); - - if (spi_xfer(boot_slave, spi_read_cmd, - read_cmd_bytes, NULL, 0) < 0) { - ret = -1; - printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", - __func__, sizeof(spi_read_cmd)); - goto tegra_spi_cbfs_read_exit; - } - - if (channel->dual_mode) { - setbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); - } - if (spi_xfer(boot_slave, NULL, 0, dest, count)) { - ret = -1; - printk(BIOS_ERR, "%s: Failed to transfer %u bytes\n", - __func__, count); - } - if (channel->dual_mode) - clrbits_le32(&channel->regs->command1, SPI_CMD1_BOTH_EN_BIT); - -tegra_spi_cbfs_read_exit: - /* de-assert /CS */ - spi_release_bus(boot_slave); - return ret; -} - struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) { struct tegra_spi_channel *channel = to_tegra_spi(bus); @@ -869,32 +806,3 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) return &channel->slave; } - -static const struct region_device_ops tegra_spi_ops = { - .mmap = mmap_helper_rdev_mmap, - .munmap = mmap_helper_rdev_munmap, - .readat = tegra_spi_readat, -}; - -static struct mmap_helper_region_device mdev = - MMAP_HELPER_REGION_INIT(&tegra_spi_ops, 0, CONFIG_ROM_SIZE); - -const struct region_device *boot_device_ro(void) -{ - return &mdev.rdev; -} - -void boot_device_init(void) -{ - struct tegra_spi_channel *boot_chan; - - boot_chan = &tegra_spi_channels[CONFIG_BOOT_MEDIA_SPI_BUS - 1]; - boot_chan->slave.cs = CONFIG_BOOT_MEDIA_SPI_CHIP_SELECT; - -#if CONFIG_SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B == 1 - boot_chan->dual_mode = 1; -#endif - boot_slave = &boot_chan->slave; - - mmap_helper_device_init(&mdev, _cbfs_cache, _cbfs_cache_size); -}

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New patch to review for coreboot: mainboard/google/chell: provide configuration for all pads
by Patrick Georgi 26 Feb '16

26 Feb '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13831 -gerrit commit 06e746b85b0715be660181bd0f8cadab3bcbe25a Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 17 13:24:42 2016 -0600 mainboard/google/chell: provide configuration for all pads Instead of relying on power-on-reset values provide configuration for all pads. PAD_CFG_NC() was used for all pads which had no nets routed on the board. PAD_CFG_GPO(0) was used for pads which had nets routed on the board in order to terminate them. BUG=chrome-os-partner:50301 BRANCH=glados TEST=Built and booted chell. Suspended and resumed on EVT. Change-Id: I7960442d5c06f58a1b671cdefac71ef0bc3b0cd5 Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> Original-Commit-Id: 6a167cd0a747402bfc3cc9b6fbaaceceda766ee9 Original-Change-Id: I519011b049235dc2a960939c0bed274252dbffa8 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/327835 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/mainboard/google/chell/gpio.h | 162 +++++++++++++++++++------------------- 1 file changed, 81 insertions(+), 81 deletions(-) diff --git a/src/mainboard/google/chell/gpio.h b/src/mainboard/google/chell/gpio.h index f9374d1..01b4e31 100644 --- a/src/mainboard/google/chell/gpio.h +++ b/src/mainboard/google/chell/gpio.h @@ -66,58 +66,58 @@ static const struct pad_config gpio_table[] = { /* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* PIRQA# */ /* GPP_A7 */ +/* PIRQA# */ PAD_CFG_NC(GPP_A7), /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), -/* CLKOUT_LPC1 */ /* GPP_A10 */ -/* PME# */ /* GPP_A11 */ -/* BM_BUSY# */ /* GPP_A12 */ +/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10), +/* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP), +/* BM_BUSY# */ PAD_CFG_NC(GPP_A12), /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), -/* SUS_STAT# */ /* GPP_A14 */ +/* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP), /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), -/* SD_1P8_SEL */ /* GPP_A16 */ -/* SD_PWR_EN# */ /* GPP_A17 */ -/* ISH_GP0 */ /* GPP_A18 */ -/* ISH_GP1 */ /* GPP_A19 */ -/* ISH_GP2 */ /* GPP_A20 */ -/* ISH_GP3 */ /* GPP_A21 */ -/* ISH_GP4 */ /* GPP_A22 */ -/* ISH_GP5 */ /* GPP_A23 */ -/* CORE_VID0 */ /* GPP_B0 */ -/* CORE_VID1 */ /* GPP_B1 */ -/* VRALERT# */ /* GPP_B2 */ +/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16), +/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), +/* ISH_GP1 */ PAD_CFG_NC(GPP_A19), +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), +/* ISH_GP5 */ PAD_CFG_NC(GPP_A23), +/* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP), +/* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP), +/* VRALERT# */ PAD_CFG_NC(GPP_B2), /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD_INT_L */ -/* CPU_GP3 */ /* GPP_B4 */ +/* CPU_GP3 */ PAD_CFG_NC(GPP_B4), /* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TRACKPAD WAKE */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */ /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */ -/* SRCCLKREQ3# */ /* GPP_B8 */ -/* SRCCLKREQ4# */ /* GPP_B9 */ -/* SRCCLKREQ5# */ /* GPP_B10 */ -/* EXT_PWR_GATE# */ /* GPP_B11 */ +/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8), +/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9), +/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), +/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11), /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* SPKR */ /* GPP_B14 */ -/* GSPI0_CS# */ /* GPP_B15 */ +/* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP), +/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), /* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), /* WLAN WAKE */ -/* GSPI0_MISO */ /* GPP_B17 */ -/* GSPI0_MOSI */ /* GPP_B18 */ -/* GSPI1_CS# */ /* GPP_B19 */ -/* GSPI1_CLK */ /* GPP_B20 */ -/* GSPI1_MISO */ /* GPP_B21 */ -/* GSPI1_MOSI */ /* GPP_B22 */ +/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17), +/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP), +/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19), +/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20), +/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21), +/* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP), /* SM1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */ /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */ -/* SMBALERT# */ /* GPP_C2 */ +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), /* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */ /* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */ /* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */ /* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */ /* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */ -/* UART0_RXD */ /* GPP_C8 */ -/* UART0_TXD */ /* GPP_C9 */ -/* UART0_RTS# */ /* GPP_C10 */ +/* UART0_RXD */ PAD_CFG_NC(GPP_C8), +/* UART0_TXD */ PAD_CFG_NC(GPP_C9), +/* UART0_RTS# */ PAD_CFG_NC(GPP_C10), /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ /* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */ /* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */ @@ -131,39 +131,39 @@ static const struct pad_config gpio_table[] = { /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */ /* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */ -/* SPI1_CS# */ /* GPP_D0 */ -/* SPI1_CLK */ /* GPP_D1 */ -/* SPI1_MISO */ /* GPP_D2 */ -/* SPI1_MOSI */ /* GPP_D3 */ -/* FASHTRIG */ /* GPP_D4 */ +/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP), +/* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP), +/* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP), +/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP), +/* FASHTRIG */ PAD_CFG_NC(GPP_D4), /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */ /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */ -/* ISH_I2C1_SDA */ /* GPP_D7 */ -/* ISH_I2C1_SCL */ /* GPP_D8 */ -/* ISH_SPI_CS# */ /* GPP_D9 */ +/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), +/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), +/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9), /* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */ -/* ISH_SPI_MISO */ /* GPP_D11 */ +/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11), /* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */ -/* ISH_UART0_RXD */ /* GPP_D13 */ -/* ISH_UART0_TXD */ /* GPP_D14 */ -/* ISH_UART0_RTS# */ /* GPP_D15 */ -/* ISH_UART0_CTS# */ /* GPP_D16 */ -/* DMIC_CLK1 */ /* GPP_D17 */ -/* DMIC_DATA1 */ /* GPP_D18 */ +/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13), +/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), +/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15), +/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16), +/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17), +/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18), /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* SPI1_IO2 */ /* GPP_D21 */ +/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP), /* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */ /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */ -/* SATAXPCIE1 */ /* GPP_E1 */ -/* SATAXPCIE2 */ /* GPP_E2 */ -/* CPU_GP0 */ /* GPP_E3 */ -/* SATA_DEVSLP0 */ /* GPP_E4 */ -/* SATA_DEVSLP1 */ /* GPP_E5 */ -/* SATA_DEVSLP2 */ /* GPP_E6 */ +/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), +/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2), +/* CPU_GP0 */ PAD_CFG_NC(GPP_E3), +/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4), +/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), +/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), /* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN_INT_L */ -/* SATALED# */ /* GPP_E8 */ +/* SATALED# */ PAD_CFG_NC(GPP_E8), /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */ /* USB2_OC1# */ /* GPP_E10 */ /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */ @@ -173,12 +173,12 @@ static const struct pad_config gpio_table[] = { /* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SMI_L */ /* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EC_SCI_L */ /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ /* GPP_E18 */ -/* DDPB_CTRLDATA */ /* GPP_E19 */ -/* DDPC_CTRLCLK */ /* GPP_E20 */ -/* DDPC_CTRLDATA */ /* GPP_E21 */ -/* DDPD_CTRLCLK */ /* GPP_E22 */ -/* DDPD_CTRLDATA */ /* GPP_E23 */ +/* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP), +/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */ +/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), +/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */ +/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23), /* * The next 4 pads are for bit banging the amplifiers. They are connected * together with i2s0 signals. For default behavior of i2s make these @@ -188,14 +188,14 @@ static const struct pad_config gpio_table[] = { /* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP), /* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP), /* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP), -/* I2C2_SDA */ /* GPP_F4 */ -/* I2C2_SCL */ /* GPP_F5 */ -/* I2C3_SDA */ /* GPP_F6 */ -/* I2C3_SCL */ /* GPP_F7 */ +/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), +/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), +/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), +/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* AUDIO1V8_SDA */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* AUDIO1V8_SCL */ /* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */ -/* I2C5_SCL */ /* GPP_F11 */ +/* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -207,27 +207,27 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* RSVD */ /* GPP_F23 */ -/* SD_CMD */ /* GPP_G0 */ -/* SD_DATA0 */ /* GPP_G1 */ -/* SD_DATA1 */ /* GPP_G2 */ -/* SD_DATA2 */ /* GPP_G3 */ -/* SD_DATA3 */ /* GPP_G4 */ -/* SD_CD# */ /* GPP_G5 */ -/* SD_CLK */ /* GPP_G6 */ -/* SD_WP */ /* GPP_G7 */ +/* RSVD */ PAD_CFG_NC(GPP_F23), +/* SD_CMD */ PAD_CFG_NC(GPP_G0), +/* SD_DATA0 */ PAD_CFG_NC(GPP_G1), +/* SD_DATA1 */ PAD_CFG_NC(GPP_G2), +/* SD_DATA2 */ PAD_CFG_NC(GPP_G3), +/* SD_DATA3 */ PAD_CFG_NC(GPP_G4), +/* SD_CD# */ PAD_CFG_NC(GPP_G5), +/* SD_CLK */ PAD_CFG_NC(GPP_G6), +/* SD_WP */ PAD_CFG_NC(GPP_G7), /* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */ /* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), -/* SLP_A# */ /* GPD6 */ -/* RSVD */ /* GPD7 */ +/* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP), +/* RSVD */ PAD_CFG_NC(GPD7), /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* SLP_WLAN# */ /* GPD9 */ -/* SLP_S5# */ /* GPD10 */ -/* LANPHYC */ /* GPD11 */ +/* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP), +/* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP), +/* LANPHYC */ PAD_CFG_NC(GPD11), }; /* Early pad configuration in romstage. */

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Patch merged into coreboot/master: payloads: Load coreinfo as a secondary payload
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit 4351ace145c4069f9c93ca7541d6dfaf8300b53b Author: Martin Roth <martinroth(a)google.com> Date: Tue Feb 16 19:40:47 2016 -0700 payloads: Load coreinfo as a secondary payload This allows coreinfo to be added to CBFS as a 'secondary' payload on x86 systems, to be loaded by the main payload if desired. Selecting this option, which defaults to no, builds the coreinfo payload and adds it to CBFS as `img/coreinfo` which can then be loaded by for example SeaBIOS or GRUB. Change-Id: I52661d486823bc4bb215ce92dca118c9d2c2a309 Signed-off-by: Martin Roth <martinroth(a)google.com> Reviewed-on: https://review.coreboot.org/13728 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13728 for details. -gerrit

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Patch merged into coreboot/master: nvramcui: Add Makefile
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit 7d82499634cf8aa1a3b3fa363d2e774a8e357a52 Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Date: Mon Jan 25 09:20:24 2016 +0100 nvramcui: Add Makefile Users had to build nvramcui manually because payload.sh was only meant for abuild. Now the user can build it with: cd payloads/libpayload/ && make menuconfig && make && make install cd ../nvramcui && make Change-Id: I409a3c39a1e1738e8071febb1a3f169e1aee959a Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org> Reviewed-on: https://review.coreboot.org/13778 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13778 for details. -gerrit

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Patch merged into coreboot/master: During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width.
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit ba894be382c1a0365c435d5be2b54422731d66c8 Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Thu Feb 25 23:20:14 2016 -0600 During DRAM initialization on certain ASpeed devices, an incorrect bit (bit 10) was checked in the "SDRAM Bus Width Status" register to determine DRAM width. Query bit 6 instead in accordance with the Aspeed AST2050 datasheet v1.05. Change-Id: I05c3c7877015d95eb8d512f7410604b9af043b26 Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Reviewed-on: https://review.coreboot.org/13807 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13807 for details. -gerrit

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Patch merged into coreboot/master: nb/intel/sandybridge/raminit: Adjust timB to prevent overflow
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit d912f1d4f973f415a431932b71e9cee0b1c82549 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Mon Feb 15 20:07:42 2016 +0100 nb/intel/sandybridge/raminit: Adjust timB to prevent overflow Improved version of I1a115a45d5febf351d89721ece79eaf43f7ee8a0 The first version wasn't well tested due to the lack of hardware and it was to aggressive. With timC being direct function of timB's 6 LSBs it's critical to match timC and timB. Some tests increments the value of timB by a small value, which might cause the 6bit value to overflow, if it's close to 0x3F. Increment the value by a small offset if it's likely to overflow, to make sure it won't overflow while running tests and bricks the system due to a non matching timC. In comparission to the first attempt, only 4 out of 128 timB values are considered bad. Needs test on real hardware ! Fixes a "edge write discovery failed" on my test system. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: If9abfc5f92e20a8f39c6f50cc709ca1cedf6827d Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> Reviewed-on: https://review.coreboot.org/13714 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/13714 for details. -gerrit

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coreboot-gerrit February 2016