coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Add support for memory-mapped boot media
by Andrey Petrov 26 Feb '16

26 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13706 -gerrit commit 3ab81f5bb7bbce0ff4bdf6878f273bea464d86ba Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Fri Feb 12 15:12:43 2016 -0800 soc/intel/apollolake: Add support for memory-mapped boot media On Apollo Lake SPI flash is memory mapped. The mapping is different to previous platforms. Only "BIOS" region is mapped in contrast to whole flash. Also, the 128 KiB right below 4 GiB are being decoded by readonly SRAM. Fail accesses to those regions, rather than returning false data. Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/mainboard/intel/apollolake_rvp/Kconfig | 9 ++++ src/soc/intel/apollolake/Kconfig | 3 ++ src/soc/intel/apollolake/Makefile.inc | 3 ++ src/soc/intel/apollolake/mmap_boot.c | 69 ++++++++++++++++++++++++++++++ 4 files changed, 84 insertions(+) diff --git a/src/mainboard/intel/apollolake_rvp/Kconfig b/src/mainboard/intel/apollolake_rvp/Kconfig index 52d3777..9920b46 100644 --- a/src/mainboard/intel/apollolake_rvp/Kconfig +++ b/src/mainboard/intel/apollolake_rvp/Kconfig @@ -17,4 +17,13 @@ config MAINBOARD_VENDOR string default "Intel" +config IFD_BIOS_END + hex + default 0x6FF000 + +config IFD_BIOS_START + hex + default 0x1000 + + endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index bb0cc20..401535f 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -80,4 +80,7 @@ config C_ENV_BOOTBLOCK_SIZE hex default 0x8000 +config X86_TOP4G_BOOTMEDIA_MAP + bool + default n endif diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 7f8beb0..17ddaec 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -11,17 +11,20 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += gpio.c +bootblock-y += mmap_boot.c bootblock-y += placeholders.c bootblock-y += tsc_freq.c bootblock-y += uart_early.c romstage-y += placeholders.c romstage-y += gpio.c +romstage-y += mmap_boot.c romstage-y += uart_early.c smm-y += placeholders.c ramstage-y += placeholders.c ramstage-y += gpio.c +ramstage-y += mmap_boot.c ramstage-y += uart_early.c CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c new file mode 100644 index 0000000..703b887 --- /dev/null +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -0,0 +1,69 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> + +/* The 128 KiB right below 4G are decoded by readonly SRAM, not boot media */ +#define IFD_BIOS_MAX_MAPPED (CONFIG_IFD_BIOS_END - 128 * KiB) +#define IFD_MAPPED_SIZE (IFD_BIOS_MAX_MAPPED - CONFIG_IFD_BIOS_START) +#define IFD_BIOS_SIZE (CONFIG_IFD_BIOS_END - CONFIG_IFD_BIOS_START) + +/* + * If Apollo Lake is configured to boot from SPI flash "BIOS" region + * (as defined in descriptor) is mapped below 4GiB. Form a pointer for + * the base. + */ +#define VIRTUAL_ROM_BASE ((uintptr_t)(0x100000000ULL - IFD_BIOS_SIZE)) + +static const struct mem_region_device shadow_dev = MEM_REGION_DEV_INIT( + VIRTUAL_ROM_BASE, IFD_BIOS_MAX_MAPPED +); + +static const struct xlate_region_device real_dev = XLATE_REGION_INIT( + &shadow_dev.rdev, CONFIG_IFD_BIOS_START, + IFD_MAPPED_SIZE, CONFIG_ROM_SIZE +); + +const struct region_device *boot_device_ro(void) +{ + return &real_dev.rdev; +}; + +static int iafw_boot_region_properties(struct cbfs_props *props) +{ + struct region regn; + + /* use fmap to locate CBFS area */ + if (fmap_locate_area("COREBOOT", &regn)) + return 1; + + props->offset = regn.offset; + props->size = regn.size; + + printk(BIOS_DEBUG, "CBFS @ %zx size %zx\n", props->offset, props->size); + + return 0; +} + +/* + * Named cbfs_master_header_locator so that it overrides the default, but + * incompatible locator in cbfs.c + */ +const struct cbfs_locator cbfs_master_header_locator = { + .name = "IAFW Locator", + .locate = iafw_boot_region_properties, +};

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Patch merged into coreboot/master: mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init()
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit 951f7c7e7892728cc5a472c2359b692e0e710d24 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:05:04 2016 -0600 mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init() Now that the SoC is configuring the UART pads there's no need to implement bootblock_mainboard_early_init(). Remove it and bootblock.c. Change-Id: I2ae7ea38351733e1c9757cde20b79e1d19d0c1e5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13794 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/13794 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: implement bootblock_soc_early_init()
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit 672be9a02862c659d9d2f53963dee8d09d09dcea Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:02:58 2016 -0600 soc/intel/apollolake: implement bootblock_soc_early_init() Provide a bootblock_soc_early_init() to that takes care of initializing the UART on behalf of the mainboard when serial console is enabled. Change-Id: I2d3875110b6f58a9e0b4c113084b85817aa05a87 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13793 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/13793 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: provide function to set up uart pads and controller
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit a513519df0084cb1f22339e5c156e95e435f1c0e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:00:03 2016 -0600 soc/intel/apollolake: provide function to set up uart pads and controller Instead of pushing the same code into each mainboard for configuring the the UART pads and initializing the host contoller provide a function to perform all the actions on behalf of the mainboard. The set of pads configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option. Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13792 Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/13792 for details. -gerrit

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Patch merged into coreboot/master: lib/bootblock: provide SoC callback parity with mainboard
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit be7cbdcc9df8028b129dd155400ae0fe8f236351 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 18:56:00 2016 -0600 lib/bootblock: provide SoC callback parity with mainboard There was no 'early' call into the SoC code prior to console getting initialized. Not having this enforces the mainboard to drive the setup of the console which typically just ends up calling into the SoC code. Provide a SoC early init call to handle this without having to duplicate the same code in mainboards utilizing the same SoC. Change-Id: Ia233dc3ae89a77df284d6d5cf5b2b051ad3be089 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13791 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/13791 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/appollolake: fix comment in gpio_defs.h
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit 0aa7d247ae2ca3ac8f9ae2a8dced478fa340c120 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 12:59:20 2016 -0600 soc/intel/appollolake: fix comment in gpio_defs.h GPIO_187 is the beginning of the Northwest community pads. Change-Id: I5565ecf534530144e80c65d886db11b53f38f935 Signed-off-by Aaron Durbin <adurbin(a)chormium.org> Reviewed-on: https://review.coreboot.org/13789 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/13789 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: group serial console options into one Kconfig
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit 6181030ba62e952fbbd4995ecdff4cea33f0df32 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 18:49:07 2016 -0600 soc/intel/apollolake: group serial console options into one Kconfig Add SOC_UART_DEBUG which does all the appropriate selection of the dependent Kconfig options for seral console. Also provide a default option of it being turned off instead of always selected. Change-Id: I1a6dba9c0072a17859c8f389709afe6fe3b04fac Signed-off-by: Aaron Durbin <adurbin(a)chormium.org> Reviewed-on: https://review.coreboot.org/13790 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) Reviewed-by: Andrey Petrov <andrey.petrov(a)intel.com> See https://review.coreboot.org/13790 for details. -gerrit

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Patch merged into coreboot/master: lib/memrange: avoid shadow object declarations
by gerrit＠coreboot.org 26 Feb '16

26 Feb '16

the following patch was just integrated into master: commit a7141c518a94b42923712de0d83a3e45fe1ee3ca Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 18:49:25 2016 -0600 lib/memrange: avoid shadow object declarations Fix an error where a variable named 'free' was shadowing the function 'free'. src/lib/memrange.c:293:73: error: declaration of 'free' shadows a global declaration [-Werror=shadow] Change-Id: Ie57194b392f8f00ed4fd5c76dab27299b00ae293 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/13788 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/13788 for details. -gerrit

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Patch set updated for coreboot: FSP2.0: Add framebuffer graphics support
by Andrey Petrov 25 Feb '16

25 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13802 -gerrit commit f49741d73f2da5721764c93ffb85020ecb4d9291 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:22:03 2016 -0800 FSP2.0: Add framebuffer graphics support This adds a few helper functions that are intended to assist setting up framebuffer. Change-Id: Id8ed4de1f9de32e9222b0120c15a6d33676346e7 Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/graphics.c | 105 ++++++++++++++++++++++++++++++++++++ 1 file changed, 105 insertions(+) diff --git a/src/drivers/intel/fsp2_0/graphics.c b/src/drivers/intel/fsp2_0/graphics.c new file mode 100644 index 0000000..1480179 --- /dev/null +++ b/src/drivers/intel/fsp2_0/graphics.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <cbfs.h> +#include <console/console.h> +#include <fsp/util.h> + +enum pixel_format { + pixel_rgbx_8bpc = 0, + pixel_bgrx_8bpc = 1, + pixel_bitmask = 2, /* defined by <rgb>_mask values */ +}; + +static const uint8_t uuid_graphics_info[16] = { + 0xce, 0x2c, 0xf6, 0x39, 0x25, 0x68, 0x69, 0x46, + 0xbb, 0x56, 0x54, 0x1a, 0xba, 0x75, 0x3a, 0x07 +}; + +struct hob_graphics_info { + uint64_t framebuffer_base; + uint32_t framebuffer_size; + uint32_t version; + uint32_t horizontal_resolution; + uint32_t vertical_resolution; + uint32_t pixel_format; /* See enum pixel_format */ + uint32_t red_mask; + uint32_t green_mask; + uint32_t blue_mask; + uint32_t reserved_mask; + uint32_t pixels_per_scanline; +} __attribute__((packed)); + +struct pixel { + uint8_t pos; + uint8_t size; +}; + +static const struct fsp_framebuffer { + struct pixel red; + struct pixel green; + struct pixel blue; + struct pixel rsvd; +} fsp_framebuffer_format_map[] = { + [pixel_rgbx_8bpc] = { {0, 8}, {8, 8}, {16, 8}, {24, 8} }, + [pixel_bgrx_8bpc] = { {16, 8}, {8, 8}, {0, 8}, {24, 8} }, +}; + +enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer) +{ + size_t size; + const struct hob_graphics_info *ginfo; + const struct fsp_framebuffer *fbinfo; + + ginfo = fsp_find_extension_hob_by_uuid(uuid_graphics_info, &size); + + if (!ginfo) { + printk(BIOS_ALERT, "Graphics hand-off block not found\n"); + return CB_ERR; + } + + if (ginfo->pixel_format > ARRAY_SIZE(fsp_framebuffer_format_map)) { + printk(BIOS_ALERT, "FSP set unknown framebuffer format: %d\n", + ginfo->pixel_format); + return CB_ERR; + } + + fbinfo = fsp_framebuffer_format_map + ginfo->pixel_format; + + framebuffer->physical_address = ginfo->framebuffer_base; + framebuffer->x_resolution = ginfo->horizontal_resolution; + framebuffer->y_resolution = ginfo->vertical_resolution; + framebuffer->bytes_per_line = ginfo->pixels_per_scanline * 4; + framebuffer->bits_per_pixel = 32; + framebuffer->red_mask_pos = fbinfo->red.pos; + framebuffer->red_mask_size = fbinfo->red.size; + framebuffer->green_mask_pos = fbinfo->green.pos; + framebuffer->green_mask_size = fbinfo->green.size; + framebuffer->blue_mask_pos = fbinfo->blue.pos; + framebuffer->blue_mask_size = fbinfo->blue.size; + framebuffer->reserved_mask_pos = fbinfo->rsvd.pos; + framebuffer->reserved_mask_size = fbinfo->rsvd.pos; + framebuffer->tag = LB_TAG_FRAMEBUFFER; + framebuffer->size = sizeof(*framebuffer); + return CB_SUCCESS; +} + +uintptr_t fsp_load_vbt(void) +{ + void *vbt; + + vbt = cbfs_boot_map_with_leak("vbt.bin", CBFS_TYPE_RAW, NULL); + if (!vbt) + printk(BIOS_NOTICE, "Could not locate a VBT file in CBFS\n"); + + return (uintptr_t)vbt; +}

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Patch set updated for coreboot: FSP2.0: Add hand-off-block parsers
by Andrey Petrov 25 Feb '16

25 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13801 -gerrit commit 0fd92e2aafd5dea929b9b3fccb5a887ba1a86470 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:20:38 2016 -0800 FSP2.0: Add hand-off-block parsers FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 297 ++++++++++++++++++++++++++++++ 1 file changed, 297 insertions(+) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c new file mode 100644 index 0000000..df68e61 --- /dev/null +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -0,0 +1,297 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <fsp/util.h> +#include <inttypes.h> +#include <lib.h> +#include <string.h> + +#define HOB_HEADER_LEN 8 + +struct hob_header { + uint16_t type; + uint16_t length; +} __attribute__((packed)); + +struct hob_resource { + uint8_t owner_guid[16]; + uint32_t type; + uint32_t attribute_type; + uint64_t addr; + uint64_t length; +} __attribute__((packed)); + +enum resource_type { + EFI_RESOURCE_SYSTEM_MEMORY = 0, + EFI_RESOURCE_MEMORY_MAPPED_IO = 1, + EFI_RESOURCE_IO = 2, + EFI_RESOURCE_FIRMWARE_DEVICE = 3, + EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4, + EFI_RESOURCE_MEMORY_RESERVED = 5, + EFI_RESOURCE_IO_RESERVED = 6, + EFI_RESOURCE_MAX_MEMORY_TYPE = 7, +}; + +static const char *resource_names[] = { + [EFI_RESOURCE_SYSTEM_MEMORY] = "SYSTEM_MEMORY", + [EFI_RESOURCE_MEMORY_MAPPED_IO] = "MMIO", + [EFI_RESOURCE_IO] = "IO", + [EFI_RESOURCE_FIRMWARE_DEVICE] = "FIRMWARE_DEVICE", + [EFI_RESOURCE_MEMORY_MAPPED_IO_PORT] = "MMIO_PORT", + [EFI_RESOURCE_MEMORY_RESERVED] = "MEMORY_RESERVED", + [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED", +}; + +enum hob_type { + HOB_TYPE_HANDOFF = 0x0001, + HOB_TYPE_MEMORY_ALLOCATION = 0x0002, + HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, + HOB_TYPE_GUID_EXTENSION = 0x0004, + HOB_TYPE_FV = 0x0005, + HOB_TYPE_CPU = 0x0006, + HOB_TYPE_MEMORY_POOL = 0x0007, + HOB_TYPE_FV2 = 0x0009, + HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, + HOB_TYPE_UCAPSULE = 0x000B, + HOB_TYPE_UNUSED = 0xFFFE, + HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, +}; + +/* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ +static const uint8_t uuid_owner_bootloader_tolum[16] = { + 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, + 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44, +}; + +static const uint8_t uuid_owner_fsp[16] = { + 0x59, 0x97, 0xa7, 0x69, 0x73, 0x13, 0x67, 0x43, + 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e, +}; + +static const uint8_t uuid_owner_tseg[16] = { + 0x7c, 0x74, 0x38, 0xd0, 0x0c, 0xd0, 0x80, 0x49, + 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 +}; + +static const uint8_t empty_uuid[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static const struct uuid_name_map { + const void *uuid; + const char *name; +} uuid_names[] = { + { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, + { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, + { uuid_owner_tseg, "TSEG" }, +}; + +static const char *resource_name(enum resource_type type) +{ + if (type >= ARRAY_SIZE(resource_names)) + return "UNKNOWN"; + return resource_names[type]; +} + +/* + * Utilities for walking HOBs + */ + +static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) +{ + return !memcmp(uuid1, uuid2, 16); +} + +static const char *uuid_name(const uint8_t uuid[16]) +{ + size_t i; + const struct uuid_name_map *owner_entry; + + for (i = 0; i < ARRAY_SIZE(uuid_names); i++) { + owner_entry = uuid_names + i; + if (uuid_compare(uuid, owner_entry->uuid)) + return owner_entry->name; + } + return "UNKNOWN"; +} + +static const struct hob_header *next_hob(const struct hob_header *parent) +{ + union { + const struct hob_header *hob; + uintptr_t addr; + } hob_walker; + + hob_walker.hob = parent; + hob_walker.addr += parent->length; + return hob_walker.hob; +} + +static const void *hob_header_to_struct(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN; + return hob_walker.hob_descr; +} + +static const void *hob_header_to_extension_hob(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN + 16; /* header and 16-byte UUID */ + return hob_walker.hob_descr; +} + +static const +struct hob_resource *hob_header_to_resource(const struct hob_header *hob) +{ + return hob_header_to_struct(hob); +} + +/* + * Utilities for locating and identifying HOBs + */ + +void fsp_save_hob_list(void *hob_list_ptr) +{ + void **cbmem_loc; + cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*hob_list_ptr)); + *cbmem_loc = hob_list_ptr; +} + +const void *fsp_get_hob_list(void) +{ + void **list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); + + return (list_loc) ? (*list_loc) : NULL; +} + +static const +struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, + const uint8_t uuid[16]) +{ + const struct hob_resource *res; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) + continue; + + res = hob_header_to_resource(hob); + if (uuid_compare(res->owner_guid, uuid)) + return res; + } + return NULL; +} + +void fsp_find_reserved_memory(struct resource *res, const void *hob_list) +{ + const struct hob_resource *fsp_mem; + + res->size = 0; + res->align = 0; + res->gran = 0; + res->next = NULL; + + fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp); + + if (!fsp_mem) { + return; + } + + res->base = fsp_mem->addr; + res->size = fsp_mem->length; +} + +/* + * Utilities for printing HOB information + */ + +static void print_guid(const void *base) +{ + uint32_t big; + uint16_t mid[2]; + + const uint8_t *id = base; + big = read32(id + 0); + mid[0] = read16(id + 4); + mid[1] = read16(id + 6); + + printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", + big, mid[0], mid[1], + id[8], id[9], id[10], id[11], id[12], id[13],id[14], id[15]); +} + +static void print_resource_descriptor(const void *base) +{ + const struct hob_resource *res; + + res = hob_header_to_resource(base); + + printk(BIOS_DEBUG, "Resource %s, attribute %x\n", + resource_name(res->type), res->attribute_type); + printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); + if (!uuid_compare(res->owner_guid, empty_uuid)) { + printk(BIOS_DEBUG, "\tOwner GUID: "); + print_guid(res->owner_guid); + printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); + } +} + + +void fsp_print_memory_resource_hobs(const void *hob_list) +{ + const struct hob_header *hob = hob_list; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR) + print_resource_descriptor(hob); + } +} + +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) +{ + const uint8_t *hob_uuid; + const struct hob_header *hob = fsp_get_hob_list(); + + if (!hob) + return NULL; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_GUID_EXTENSION) + continue; + + hob_uuid = hob_header_to_struct(hob); + if (uuid_compare(hob_uuid, uuid)) { + *size = hob->length - (HOB_HEADER_LEN + 16); + return hob_header_to_extension_hob(hob); + } + } + + return NULL; +}

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coreboot-gerrit February 2016