coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: FSP2.0: Add coreboot<->FSP header files
by Andrey Petrov 25 Feb '16

25 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13796 -gerrit commit 5e4255ca7f72f1ea0282546c662787fc1a2a9f10 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:13:12 2016 -0800 FSP2.0: Add coreboot<->FSP header files This adds important header files that specify calling interface between coreboot and FSP. Change-Id: I393601c91e3c3f630e0fc899f1140ecefed8ecba Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/Kconfig | 1 + src/drivers/intel/Makefile.inc | 1 + src/drivers/intel/fsp2_0/Kconfig | 42 +++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 11 +++ src/drivers/intel/fsp2_0/include/fsp/api.h | 101 +++++++++++++++++++++ src/drivers/intel/fsp2_0/include/fsp/info_header.h | 45 +++++++++ src/drivers/intel/fsp2_0/include/fsp/util.h | 42 +++++++++ 7 files changed, 243 insertions(+) diff --git a/src/drivers/intel/Kconfig b/src/drivers/intel/Kconfig index 19986f4..e5525d8 100644 --- a/src/drivers/intel/Kconfig +++ b/src/drivers/intel/Kconfig @@ -14,5 +14,6 @@ ## source src/drivers/intel/fsp1_1/Kconfig +source src/drivers/intel/fsp2_0/Kconfig source src/drivers/intel/gma/Kconfig source src/drivers/intel/i210/Kconfig diff --git a/src/drivers/intel/Makefile.inc b/src/drivers/intel/Makefile.inc index e54f07b..67c1163 100644 --- a/src/drivers/intel/Makefile.inc +++ b/src/drivers/intel/Makefile.inc @@ -2,4 +2,5 @@ subdirs-y += gma subdirs-$(CONFIG_GENERATE_SMBIOS_TABLES) += wifi subdirs-$(CONFIG_PLATFORM_USES_FSP1_0) += fsp1_0 subdirs-$(CONFIG_PLATFORM_USES_FSP1_1) += fsp1_1 +subdirs-$(CONFIG_PLATFORM_USES_FSP2_0) += fsp2_0 subdirs-$(CONFIG_DRIVER_INTEL_I210) += i210 diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig new file mode 100644 index 0000000..a05d8de --- /dev/null +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -0,0 +1,42 @@ +config PLATFORM_USES_FSP2_0 + bool + help + Include FSP 2.0 wrappers and functionality + +if PLATFORM_USES_FSP2_0 + +comment "Intel FSP 2.0" + +config ADD_FSP_BINARIES + bool "Add Intel FSP 2.0 binaries to CBFS" + help + Add the FSP-M and FSP-S binaries to CBFS. Note that coreboot does not + use the FSP-T binary, so that will not be included. + +config FSP_M_FILE + string "Intel FSP-M (memory init) binary path and filename" + depends on ADD_FSP_BINARIES + help + The path and filename of the Intel FSP-M binary for this platform. + +config FSP_S_FILE + string "Intel FSP-S (silicon init) binary path and filename" + depends on ADD_FSP_BINARIES + help + The path and filename of the Intel FSP-S binary for this platform. + + +config ADD_VBT_DATA_FILE + bool "Add a Video Bios Table (VBT) binary to CBFS" + help + Add a VBT file data file to CBFS. The VBT describes the integrated + GPU and connections, and is needed by FSP in order to initialize the + display. + +config VBT_FILE + string "VBT binary path and filename" + depends on ADD_VBT_DATA_FILE + help + The path and filename of the VBT binary for this platform. + +endif # PLATFORM_USES_FSP2_0 diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc new file mode 100644 index 0000000..61faefa --- /dev/null +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -0,0 +1,11 @@ +romstage-y += hand_off_block.c +romstage-y += util.c +romstage-y += memory_init.c + +ramstage-y += graphics.c +ramstage-y += hand_off_block.c +ramstage-y += notify.c +ramstage-y += silicon_init.c +ramstage-y += util.c + +CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h new file mode 100644 index 0000000..aae17e8 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -0,0 +1,101 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_API_H_ +#define _FSP2_0_API_H_ + +#include <stddef.h> +#include <memrange.h> + +enum fsp_status { + FSP_SUCCESS = 0x00000000, + FSP_INVALID_PARAMETER = 0x80000002, + FSP_UNSUPPORTED = 0x80000003, + FSP_NOT_READY = 0x80000006, + FSP_DEVICE_ERROR = 0x80000007, + FSP_OUT_OF_RESOURCES = 0x80000009, + FSP_VOLUME_CORRUPTED = 0x8000000a, + FSP_NOT_FOUND = 0x8000000a, + FSP_TIMEOUT = 0x80000012, + FSP_ABORTED = 0x80000015, + FSP_INCOMPATIBLE_VERSION = 0x80000010, + FSP_SECURITY_VIOLATION = 0x8000001a, + FSP_CRC_ERROR = 0x8000001b, +}; + +enum fsp_notify_phase { + AFTER_PCI_ENUM = 0x20, + READY_TO_BOOT = 0x40 +}; + + +/* Opaque structures. These are platform-specific. */ +struct FSPM_UPD; +struct FSPS_UPD; + +/* Main FSP stages */ +enum fsp_status fsp_memory_init(void **hob_list, struct range_entry *r); +enum fsp_status fsp_silicon_init(struct range_entry *r); +enum fsp_status fsp_notify(enum fsp_notify_phase phase); + +/* Callbacks for updating stage-specific parameters */ +void platform_fsp_memory_init_params_cb(struct FSPM_UPD *memupd); +void platform_fsp_silicon_init_params_cb(struct FSPS_UPD *silupd); + +/* + * # DOCUMENTATION: + * + * This file defines the interface between coreboot and the FSP 2.0 wrapper + * fsp_memory_init(), fsp_silicon_init(), and fsp_notify() are the main entry + * points and map 1:1 to the FSP entry points of the same name. + * + * ### fsp_memory_init(): + * - hob_list: retuns a pointer to the HOB storage area created by FSP + * - r: memory range that the binary is allowed to be loaded into + * + * This function is responsible for loading and executing the memory + * initialization code from the FSP-M binary. It expects this binary to reside + * in cbfs as FSP_M_FILE. + * + * The function takes one parameter, which is described below, but does not + * take in memory parameters as an argument. The memory parameters can be filled + * in with platform_fsp_memory_init_params_cb(). This is a callback symbol + * that fsp_memory_init() will call. The platform must provide this symbol. + * + * FSP returns information about the memory layout in a series of structures + * called hand-off-blocks (HOB). The "hob_list" output parameter will point to + * the start of the HOB list. The fsp reserved region will also be described by + * one of the HOBs. For more information on parsing these structures, see + * fsp/util.h + * + * + * ### fsp_silicon_init(): + * - r: memory range that the binary is allowed to be loaded into + * + * This function is responsible for loading and executing the silicon + * initialization code from the FSP-S binary. It expects this binary to reside + * in cbfs as FSP_S_FILE. + * + * Like fsp_memory_init(), it provides a callback to fill in FSP-specific + * parameters, via platform_fsp_silicon_init_params_cb(). The platform must + * also provide this symbol. + * + * + * ### fsp_notify(): + * - phase: Which FSP notification phase + * + * This function is responsible for loading and executing the notify code from + * the FSP-S binary. It expects that fsp_silicon_init() has already been called + * succesfully, and that the FSP-S binary is still loaded into memory. + */ + +#endif /* _FSP2_0_API_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h new file mode 100644 index 0000000..a59780f --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_INFO_HEADER_H_ +#define _FSP2_0_INFO_HEADER_H_ + +#include <stdint.h> +#include <stdlib.h> +#include <types.h> + +#define FSP_HDR_OFFSET 0x94 +#define FSP_HDR_LEN 0x48 +#define FSP_HDR_SIGNATURE "FSPH" +#define FSP_HDR_ATTRIB_FSPT (0b0001 << 27) +#define FSP_HDR_ATTRIB_FSPM (0b0010 << 27) +#define FSP_HDR_ATTRIB_FSPS (0b0011 << 27) + +struct fsp_header { + uint32_t fsp_revision; + size_t image_size; + uintptr_t image_base; + uint32_t image_attribute; + size_t cfg_region_offset; + size_t cfg_region_size; + size_t notify_phase_entry_offset; + size_t memory_init_entry_offset; + size_t silicon_init_entry_offset; + char image_id[sizeof(uint64_t) + 1]; + uint8_t revision; +}; + +enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob); +void fsp_print_header_info(const struct fsp_header *hdr); +void fsp_print_upd_info(const struct fsp_header *hdr, void *cfg_blob); + +#endif /* _FSP2_0_INFO_HEADER_H_ */ diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h new file mode 100644 index 0000000..69e545e --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#ifndef _FSP2_0_UTIL_H_ +#define _FSP2_0_UTIL_H_ + +#include <boot/coreboot_tables.h> +#include <fsp/info_header.h> +#include <device/resource.h> +#include <memrange.h> + +/* + * Hand-off-block handling functions that depend on CBMEM, and thus can only + * be used after cbmem_initialize(). + */ +void fsp_save_hob_list(void *hob_list_ptr); +const void *fsp_get_hob_list(void); +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size); +enum cb_err fsp_fill_lb_framebuffer(struct lb_framebuffer *framebuffer); +/* + * Hand-off-block utilities which do not depend on CBMEM, but need to be passed + * the HOB list explicitly. + */ +void fsp_find_reserved_memory(struct resource *res, const void *hob_list); +void fsp_print_memory_resource_hobs(const void *hob_list); + +/* Load an FSP binary into CBFS, and fill the associated fsp_header struct */ +enum cb_err fsp_load_binary(struct fsp_header *hdr, const char *name, + struct range_entry *r); +/* Load a vbt.bin file for graphics. Returns 0 if a valid VBT is not found. */ +uintptr_t fsp_load_vbt(void); + +#endif /* _FSP2_0_UTIL_H_ */

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Patch set updated for coreboot: abuild: Use 12 lines of context for errors
by Stefan Reinauer 25 Feb '16

25 Feb '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12720 -gerrit commit 1d078bf6431246f2e06ca6bc4edca50ac9b88304 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Mon Dec 14 16:36:45 2015 -0800 abuild: Use 12 lines of context for errors The current default of 6 lines leaves us with no context about the actual error: *** ERROR: 3 warnings encountered, and warnings are errors. coreboot-gerrit/util/kconfig/Makefile:38: recipe for target 'oldconfig' failed make[1]: *** [oldconfig] Error 1 make[1]: Leaving directory 'coreboot-gerrit' Change-Id: I67e7d740e7b3b1c66005dc1bf50557a20bc15428 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/abuild/abuild | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/abuild/abuild b/util/abuild/abuild index cddcb57..ffa16b5 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -40,7 +40,7 @@ if [ -d "$XGCCPATH" ] && [[ ":$PATH:" != *":$XGCCPATH:"* ]]; then fi # Lines of error context to be printed in FAILURE case -CONTEXT=6 +CONTEXT=12 # Configure-only mode configureonly=0

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New patch to review for coreboot: emulation/qemu-power8: move the image to start at 0x100
by Ronald G. Minnich 25 Feb '16

25 Feb '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13795 -gerrit commit 426fceeda979dc615f93c92d9d3c180edf1065e8 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Thu Feb 25 17:58:42 2016 +0000 emulation/qemu-power8: move the image to start at 0x100 This seems to be the standard. Change-Id: I6484f3ff0d188ce4b270af4777f368696bfc75e6 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/mainboard/emulation/qemu-power8/memlayout.ld | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/emulation/qemu-power8/memlayout.ld b/src/mainboard/emulation/qemu-power8/memlayout.ld index 2daad30..2e3984c 100644 --- a/src/mainboard/emulation/qemu-power8/memlayout.ld +++ b/src/mainboard/emulation/qemu-power8/memlayout.ld @@ -20,8 +20,8 @@ // TODO: fill in these blanks for Power8. SECTIONS { - DRAM_START(0x0) - BOOTBLOCK(0x0, 64K) + DRAM_START(0x100) + BOOTBLOCK(0x100, 64K-0x100) ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K)

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Patch set updated for coreboot: soc/intel/apollolake: implement bootblock_soc_early_init()
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13793 -gerrit commit 200c1836bcca8bb1681dc6788dd63e3f118f31b0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:02:58 2016 -0600 soc/intel/apollolake: implement bootblock_soc_early_init() Provide a bootblock_soc_early_init() to that takes care of initializing the UART on behalf of the mainboard when serial console is enabled. Change-Id: I2d3875110b6f58a9e0b4c113084b85817aa05a87 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/bootblock/bootblock.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 5007613..4ea3f70 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -17,6 +17,7 @@ #include <soc/cpu.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> +#include <soc/uart.h> void asmlinkage bootblock_c_entry(void) { @@ -42,3 +43,10 @@ void platform_prog_run(struct prog *prog) msr.lo |= (1 << 8); wrmsr(MSR_POWER_MISC, msr); } + +void bootblock_soc_early_init(void) +{ + /* Prepare UART for serial console. */ + if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) + soc_console_uart_init(); +}

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Patch set updated for coreboot: soc/intel/apollolake: provide function to set up uart pads and controller
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13792 -gerrit commit d9edcd04dec47f5bfd8361121a89a2248375a41e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:00:03 2016 -0600 soc/intel/apollolake: provide function to set up uart pads and controller Instead of pushing the same code into each mainboard for configuring the the UART pads and initializing the host contoller provide a function to perform all the actions on behalf of the mainboard. The set of pads configured is dictated by the CONFIG_UART_FOR_CONSOLE Kconfig option. Change-Id: I06c499c7ee056b970468e0386d4bb1bc26537247 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/apollolake/include/soc/uart.h | 3 +++ src/soc/intel/apollolake/uart_early.c | 32 ++++++++++++++++++++++++++++- 2 files changed, 34 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h index fd535fb..16f09b1 100644 --- a/src/soc/intel/apollolake/include/soc/uart.h +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -25,4 +25,7 @@ void lpss_console_uart_init(void); +/* Initialize the console UART including the pads for the configured UART. */ +void soc_console_uart_init(void); + #endif /* _SOC_APOLLOLAKE_UART_H_ */ diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index d3b1d80..4ee4a38 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -22,12 +22,21 @@ static void lpss_uart_write(uint16_t reg, uint32_t val) write32((void *)base, val); } +static inline int invalid_uart_for_console(void) +{ + /* There are actually only 2 UARTS, and they are named UART1 and + * UART2. They live at pci functions 1 and 2 respectively. */ + if (CONFIG_UART_FOR_CONSOLE > 2 || CONFIG_UART_FOR_CONSOLE < 1) + return 1; + return 0; +} + void lpss_console_uart_init(void) { uint32_t clk_sel; device_t uart = _LPSS_PCI_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); - if (CONFIG_UART_FOR_CONSOLE > 2) + if (invalid_uart_for_console()) return; /* Enable BAR0 for the UART -- this is where the 8250 registers hide */ @@ -59,3 +68,24 @@ unsigned int uart_platform_refclk(void) /* That's within 0.5% of the actual value we've set earlier */ return 115200 * 16; } + +static const struct pad_config uart_gpios[] = { + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), /* UART1 RX */ + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), /* UART1 TX */ + PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX */ + PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ +}; + +void soc_console_uart_init(void) +{ + /* Get a 0-based pad index. See invalid_uart_for_console() above. */ + const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; + + if (invalid_uart_for_console()) + return; + + /* Configure the 2 pads per UART. */ + gpio_configure_pads(&uart_gpios[pad_index * 2], 2); + + lpss_console_uart_init(); +}

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Patch set updated for coreboot: mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init()
by Aaron Durbin 25 Feb '16

25 Feb '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13794 -gerrit commit d3a9da29f3d5ecbf0293b598b103ec03a2ba37ff Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Feb 24 19:05:04 2016 -0600 mainboard/intel/apollolake_rvp: remove bootblock_mainboard_early_init() Now that the SoC is configuring the UART pads there's no need to implement bootblock_mainboard_early_init(). Remove it and bootblock.c. Change-Id: I2ae7ea38351733e1c9757cde20b79e1d19d0c1e5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/intel/apollolake_rvp/Makefile.inc | 1 - src/mainboard/intel/apollolake_rvp/bootblock.c | 30 ------------------------- 2 files changed, 31 deletions(-) diff --git a/src/mainboard/intel/apollolake_rvp/Makefile.inc b/src/mainboard/intel/apollolake_rvp/Makefile.inc index 8501868..e69de29 100644 --- a/src/mainboard/intel/apollolake_rvp/Makefile.inc +++ b/src/mainboard/intel/apollolake_rvp/Makefile.inc @@ -1 +0,0 @@ -bootblock-y += bootblock.c diff --git a/src/mainboard/intel/apollolake_rvp/bootblock.c b/src/mainboard/intel/apollolake_rvp/bootblock.c deleted file mode 100644 index c1b7d41..0000000 --- a/src/mainboard/intel/apollolake_rvp/bootblock.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - */ - -#include <bootblock_common.h> -#include <console/console.h> -#include <soc/gpio.h> -#include <soc/gpio_defs.h> -#include <soc/uart.h> - -static struct pad_config aplk_rvp_gpios[] = { - PAD_CFG_NF(GPIO_46, NATIVE, DEEP, NF1), /* UART2 RX*/ - PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1) /* UART2 TX*/ -}; - -void bootblock_mainboard_early_init(void) -{ - if (IS_ENABLED(CONFIG_BOOTBLOCK_CONSOLE)) { - gpio_configure_pads(aplk_rvp_gpios, ARRAY_SIZE(aplk_rvp_gpios)); - lpss_console_uart_init(); - } -}

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Patch merged into coreboot/master: mc_tcu3: Enable graphic init code
by gerrit＠coreboot.org 25 Feb '16

25 Feb '16

the following patch was just integrated into master: commit e0b3c7bef1ab5ed6721b7ea6411862ae6e177ef6 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Wed Feb 24 07:35:17 2016 +0100 mc_tcu3: Enable graphic init code The used Baytrail-M SoC on TCU3 tend to have issues with DisplayPort if the graphic power gate is not set up in coreboot. To avoid this error, use the graphic init code on this board. Change-Id: I973bbaa7d86c1ede1f2884b3a08ccb31f7d85087 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/13774 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/13774 for details. -gerrit

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Patch merged into coreboot/master: fsp_baytrail: Fix a possible hanging DisplayPort
by gerrit＠coreboot.org 25 Feb '16

25 Feb '16

the following patch was just integrated into master: commit 1c3b1112fa2dbdd66b0470224715dc6da254ce62 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Fri Feb 19 10:50:38 2016 +0100 fsp_baytrail: Fix a possible hanging DisplayPort On some devices it can happen that DisplayPort TX lanes do not work properly if the power gate setup is omitted. If that happens, DisplayPort training will fail and therefore DisplayPort channel will not work. Both ports are affected. It seems that not every CPU shows this effect and those that are affected tend to fail more often in a cold environment. With this fix a board that originally shows this failure was running for over 1000 power cycles without issues. Change-Id: Ia266674490a1bee63a85b38d1dc949dcdf683cbc Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> Reviewed-on: https://review.coreboot.org/13743 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/13743 for details. -gerrit

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Patch set updated for coreboot: pcengines/apu1: Supply TPM modules on the LPC connector
by Tobias Diedrich 25 Feb '16

25 Feb '16

Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12796 -gerrit commit 8de6e3167b70f6c84b54dc9c1b81d33235fc92cf Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Date: Wed Dec 23 23:27:06 2015 +0100 pcengines/apu1: Supply TPM modules on the LPC connector Since the APU1 has an LPC connector it is possible to connect a TPM. I'm using mine mostly for the HWRNG which the APU1 lacks. This takes care of setting up the TPM interrupt. Interrupt 5 was chosen since it is not otherwise used on the APU1, Alternatively 1, 7, 10-11 and 14-15 should be available as well. It may also be possible to share the ACPI interrupt (9). Previously I was getting frequent "genirq: Flags mismatch irq 4. 00000000 (serial) vs. 00000080 (tpm0)" errors. With this I also no longer need to use "tpm_tis.force=1" on the kernel commandline since the TPM is now declared in the ACPI DSDT. See also https://plus.google.com/+TobiasDiedrich/posts/cRv9MwrCdEa and https://plus.google.com/+TobiasDiedrich/posts/BDnJLGFMW8o Change-Id: Ie732228471f6c40d77e17cbed34726961b1fcddd Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- src/mainboard/pcengines/apu1/Kconfig | 1 + src/mainboard/pcengines/apu1/devicetree.cb | 5 +++++ src/southbridge/amd/cimx/sb800/acpi/lpc.asl | 4 ++++ 3 files changed, 10 insertions(+) diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 2328776..5eb9e1c 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -30,6 +30,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 select SPD_CACHE + select MAINBOARD_HAS_LPC_TPM config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb index 72e89c0..1a263a2 100644 --- a/src/mainboard/pcengines/apu1/devicetree.cb +++ b/src/mainboard/pcengines/apu1/devicetree.cb @@ -43,6 +43,11 @@ chip northbridge/amd/agesa/family14/root_complex device pci 14.1 off end # IDE 0x439c device pci 14.2 off end # HDA 0x4383 device pci 14.3 on # LPC 0x439d + chip drivers/pc80/tpm # Support TPM on the LPC header. + device pnp 0c31.0 on + irq 0x70 = 5 + end + end chip superio/nuvoton/nct5104d register "irq_trigger_type" = "0" device pnp 2e.0 off end diff --git a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl index 98d5aa5..c2d1ebd 100644 --- a/src/southbridge/amd/cimx/sb800/acpi/lpc.asl +++ b/src/southbridge/amd/cimx/sb800/acpi/lpc.asl @@ -77,4 +77,8 @@ Device(LIBR) { }) } /* End Device(_SB.PCI0.LpcIsaBr.COPR) */ #include "acpi/superio.asl" + +#if CONFIG_MAINBOARD_HAS_LPC_TPM + #include <drivers/pc80/tpm/acpi/tpm.asl> +#endif } /* end LIBR */

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Patch merged into coreboot/master: x86/Makefile.inc: Fix redundant addition of memlayout.ld in bootblock
by gerrit＠coreboot.org 25 Feb '16

25 Feb '16

the following patch was just integrated into master: commit 01554574492a4965668e0d9423d3ae4da079cfde Author: Furquan Shaikh <furquan(a)google.com> Date: Wed Feb 24 09:42:16 2016 -0800 x86/Makefile.inc: Fix redundant addition of memlayout.ld in bootblock For C_ENVIRONMENT_BOOTBLOCK, memlayout.ld is added by call to early_x86_stage. Remove redundant addition of memlayout.ld in this case. Change-Id: Ibb5ce690ac4e63f7ff5063d5bd04daeeb731e4d7 Signed-off-by: Furquan Shaikh <furquan(a)google.com> Reviewed-on: https://review.coreboot.org/13777 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/13777 for details. -gerrit

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coreboot-gerrit February 2016