coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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1305 discussions

New patch to review for coreboot: buildgcc: revert: enable multilib for gcc
by Stefan Reinauer 27 Feb '16

27 Feb '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13850 -gerrit commit fc57ad46c74b9ab9cbf16a5333da065467767450 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Feb 27 12:48:31 2016 -0800 buildgcc: revert: enable multilib for gcc Commit 8e68aff caused the cross toolchain to fail building on Ubuntu 15.10 Change-Id: I965e5cb208056ae5648eacf054ba14d49d6f9dbe Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/buildgcc | 1 - 1 file changed, 1 deletion(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index e4a6d47..adc5fc2 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -439,7 +439,6 @@ build_GCC() { --disable-libssp --disable-bootstrap --disable-nls \ --disable-libquadmath --without-headers \ --disable-threads \ - --enable-interwork --enable-multilib \ --disable-libatomic --disable-libcc1 --disable-decimal-float \ ${GCC_OPTIONS} --enable-languages="${LANGUAGES}" \ --with-system-zlib \

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New patch to review for coreboot: buildgcc: Fix building GDB for mipsel-elf
by Stefan Reinauer 27 Feb '16

27 Feb '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13849 -gerrit commit 7d07324c79e02ab81f71ae4669a7761e31e6f23a Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Feb 27 12:35:54 2016 -0800 buildgcc: Fix building GDB for mipsel-elf Change-Id: I31ed159b13c0da60383068832615c6e4a9608efe Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/patches/gdb-7.9.1_sim-arange.patch | 61 ++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/util/crossgcc/patches/gdb-7.9.1_sim-arange.patch b/util/crossgcc/patches/gdb-7.9.1_sim-arange.patch new file mode 100644 index 0000000..bf56c2d --- /dev/null +++ b/util/crossgcc/patches/gdb-7.9.1_sim-arange.patch @@ -0,0 +1,61 @@ +From: Mike Frysinger <vapier at gentoo dot org> + +With newer versions of gcc (5.x), the extern inline we're using with the +sim-arange module no longer works. Since this code really wants the gnu +inline semantics, use that attribute explicitly. + +Reported-by: DJ Delorie <dj(a)redhat.com> +Reported-by: Joel Sherrill <joel.sherrill(a)oarcorp.com> + +diff -urN gdb-7.9.1.orig/sim/common/sim-arange.h gdb-7.9.1/sim/common/sim-arange.h +--- gdb-7.9.1.orig/sim/common/sim-arange.h 2015-05-13 10:36:05.000000000 -0700 ++++ gdb-7.9.1/sim/common/sim-arange.h 2016-02-27 12:22:58.090512073 -0800 +@@ -60,22 +60,26 @@ + address_word /*start*/, + address_word /*end*/); + ++/* TODO: This should get moved into sim-inline.h. */ ++#ifdef HAVE_INLINE ++#ifdef SIM_ARANGE_C ++#define SIM_ARANGE_INLINE INLINE ++#else ++#define SIM_ARANGE_INLINE EXTERN_INLINE ++#endif ++#else ++#define SIM_ARANGE_INLINE EXTERN ++#endif ++ + /* Return non-zero if ADDR is in range AR, traversing the entire tree. + If no range is specified, that is defined to mean "everything". */ +-extern INLINE int ++SIM_ARANGE_INLINE int + sim_addr_range_hit_p (ADDR_RANGE * /*ar*/, address_word /*addr*/); + #define ADDR_RANGE_HIT_P(ar, addr) \ + ((ar)->range_tree == NULL || sim_addr_range_hit_p ((ar), (addr))) + + #ifdef HAVE_INLINE +-#ifdef SIM_ARANGE_C +-#define SIM_ARANGE_INLINE INLINE +-#else +-#define SIM_ARANGE_INLINE EXTERN_INLINE +-#endif + #include "sim-arange.c" +-#else +-#define SIM_ARANGE_INLINE + #endif + #define SIM_ARANGE_C_INCLUDED + +diff -urN gdb-7.9.1.orig/sim/common/sim-inline.h gdb-7.9.1/sim/common/sim-inline.h +--- gdb-7.9.1.orig/sim/common/sim-inline.h 2015-05-13 10:36:05.000000000 -0700 ++++ gdb-7.9.1/sim/common/sim-inline.h 2016-02-27 12:23:58.169085087 -0800 +@@ -303,7 +303,9 @@ + /* ??? Temporary, pending decision to always use extern inline and do a vast + cleanup of inline support. */ + #ifndef INLINE2 +-#if defined (__GNUC__) ++#if defined (__GNUC_GNU_INLINE__) || defined (__GNUC_STDC_INLINE__) ++#define INLINE2 __inline__ __attribute__ ((__gnu_inline__)) ++#elif defined (__GNUC__) + #define INLINE2 __inline__ + #else + #define INLINE2 /*inline*/

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New patch to review for coreboot: buildgcc: Add support for gdb on x86_64-elf
by Stefan Reinauer 27 Feb '16

27 Feb '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13848 -gerrit commit 58488f38890eddde661f35e7c52752f56029a3a9 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Feb 27 12:33:39 2016 -0800 buildgcc: Add support for gdb on x86_64-elf Change-Id: I99f5842d1dc03b3f2d747c5abae7170214313284 Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/patches/gdb-7.9.1_amd64.patch | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/util/crossgcc/patches/gdb-7.9.1_amd64.patch b/util/crossgcc/patches/gdb-7.9.1_amd64.patch new file mode 100644 index 0000000..c3ee93d --- /dev/null +++ b/util/crossgcc/patches/gdb-7.9.1_amd64.patch @@ -0,0 +1,15 @@ +diff -urN gdb-7.9.1.orig/gdb/configure.tgt gdb-7.9.1/gdb/configure.tgt +--- gdb-7.9.1.orig/gdb/configure.tgt 2015-05-13 10:36:05.000000000 -0700 ++++ gdb-7.9.1/gdb/configure.tgt 2016-02-27 11:26:26.386113921 -0800 +@@ -683,6 +683,11 @@ + i387-tdep.o i386bsd-tdep.o i386obsd-tdep.o \ + obsd-tdep.o bsd-uthread.o solib-svr4.o" + ;; ++x86_64-*-*) ++ # Target: amd64 ++ gdb_target_obs="amd64-tdep.o i386-tdep.o i387-tdep.o" ++ ;; ++ + xtensa*-*-linux*) gdb_target=linux + # Target: GNU/Linux Xtensa + gdb_target_obs="xtensa-tdep.o xtensa-config.o xtensa-linux-tdep.o \

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New patch to review for coreboot: buildgcc: Allow specifying destination directory
by Stefan Reinauer 27 Feb '16

27 Feb '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13847 -gerrit commit 340e644b781e3241ed9400e36d6b71f8b8ee2d80 Author: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Date: Sat Feb 27 12:29:58 2016 -0800 buildgcc: Allow specifying destination directory With this change you can say $ make DEST=/opt/cross-1.35 to get all of the cross toolchain built and installed to /opt/cross-1.35 Change-Id: Icc3e605c4824bfa2831d030e4ed9dd0331ff722f Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> --- util/crossgcc/Makefile | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/util/crossgcc/Makefile b/util/crossgcc/Makefile index 11cc5fc..aadf316 100644 --- a/util/crossgcc/Makefile +++ b/util/crossgcc/Makefile @@ -1,5 +1,6 @@ # if no architecture is specified, set a default BUILD_PLATFORM ?= i386-elf +DEST ?= $(PWD)/xgcc # For the toolchain builds, use CPUS=x to use multiple processors to build # use KEEP_SOURCES=1 to keep temporary files after the build @@ -23,19 +24,20 @@ build_tools: build_gcc build_gdb build_gcc: bash ./buildgcc -p $(BUILD_PLATFORM) $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) \ - $(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES)) + $(if $(BUILD_LANGUAGES),-l $(BUILD_LANGUAGES)) -d $(DEST) build_gdb: ifeq ($(SKIP_GDB),) - bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) + bash ./buildgcc -p $(BUILD_PLATFORM) -P gdb $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) \ + $(BUILDGCC_OPTIONS) -d $(DEST) endif build_iasl: - bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) + bash ./buildgcc -P iasl $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) build_clang: ifeq ($(SKIP_CLANG),) - bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) + bash ./buildgcc -P clang $(if $(CPUS),-j $(CPUS)) $(if $(KEEP_SOURCES),-t) $(BUILDGCC_OPTIONS) -d $(DEST) endif ###########################################################

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Patch set updated for coreboot: crosstool: add EXPAT as a dependency on the gdb build.
by Stefan Reinauer 27 Feb '16

27 Feb '16

Stefan Reinauer (stefan.reinauer(a)coreboot.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13846 -gerrit commit 9ab82b0ba19051abb6bc38e6e4e2d18495e2cc44 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sat Feb 27 04:06:42 2016 +0000 crosstool: add EXPAT as a dependency on the gdb build. qemu-power8 wants to tell about itself with XML, and so we need to build gdb with EXPAT so it can understand XML. Change-Id: I460e27f883956ed5d54e6070916e2682ee0f7a1b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- util/crossgcc/buildgcc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index dc6540d..e4a6d47 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -627,9 +627,10 @@ case "$PACKAGE" in ;; GDB|gdb) NAME="${TARGETARCH} cross GDB" - PACKAGES="GDB" if [ $SKIPPYTHON -eq 0 ]; then - PACKAGES="EXPAT PYTHON $PACKAGES" + PACKAGES="EXPAT PYTHON GDB" + else + PACKAGES="EXPAT GDB" fi ;; CLANG|clang)

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Patch set updated for coreboot: coreinfo: quote $(AS) and $(CC) in $(LPAS) and $(LPCC)
by Iru Cai 27 Feb '16

27 Feb '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13845 -gerrit commit 61280481d90ea8a45f6c4e9363058940c6fa1383 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Sat Feb 27 11:47:06 2016 +0800 coreinfo: quote $(AS) and $(CC) in $(LPAS) and $(LPCC) Without this change it'll get a build error with crossgcc-x64 because $(AS) is "util/crossgcc/xgcc/bin/x86_64-elf-as --32", and running $(LPAS) (i.e. AS=$(AS) lpas) will run "--32" instead of "x86_64-elf-as". Change-Id: I95e5630cb1d4f1ce81a8ca8a7bf338450b325f02 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- payloads/coreinfo/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index a3a02c2..c9f5c10 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -78,8 +78,8 @@ CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) OBJCOPY := $(OBJCOPY_$(ARCH-y)) -LPCC := CC=$(CC) $(LIBPAYLOAD_DIR)/libpayload/bin/lpgcc -LPAS := AS=$(AS) $(LIBPAYLOAD_DIR)/libpayload/bin/lpas +LPCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/libpayload/bin/lpgcc +LPAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/libpayload/bin/lpas CFLAGS += -Wall -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES)

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Patch set updated for coreboot: FSP2.0: Add hand-off-block parsers
by Andrey Petrov 27 Feb '16

27 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13801 -gerrit commit 7eba8774bf60515407c9725f26639d1d25108a3d Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:20:38 2016 -0800 FSP2.0: Add hand-off-block parsers FSP creates hand-off-blocks (HOBs) to exchange information with coreboot. This adds a set of utilities to parse HOBs and extract some useful information from them. Change-Id: If55dbfaa021cd68c312813a5532a36c68806dbbc Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/hand_off_block.c | 294 ++++++++++++++++++++++++++++++ 1 file changed, 294 insertions(+) diff --git a/src/drivers/intel/fsp2_0/hand_off_block.c b/src/drivers/intel/fsp2_0/hand_off_block.c new file mode 100644 index 0000000..3bc33af --- /dev/null +++ b/src/drivers/intel/fsp2_0/hand_off_block.c @@ -0,0 +1,294 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbmem.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <fsp/util.h> +#include <inttypes.h> +#include <lib.h> +#include <string.h> + +#define HOB_HEADER_LEN 8 + +struct hob_header { + uint16_t type; + uint16_t length; +} __attribute__((packed)); + +struct hob_resource { + uint8_t owner_guid[16]; + uint32_t type; + uint32_t attribute_type; + uint64_t addr; + uint64_t length; +} __attribute__((packed)); + +enum resource_type { + EFI_RESOURCE_SYSTEM_MEMORY = 0, + EFI_RESOURCE_MEMORY_MAPPED_IO = 1, + EFI_RESOURCE_IO = 2, + EFI_RESOURCE_FIRMWARE_DEVICE = 3, + EFI_RESOURCE_MEMORY_MAPPED_IO_PORT = 4, + EFI_RESOURCE_MEMORY_RESERVED = 5, + EFI_RESOURCE_IO_RESERVED = 6, + EFI_RESOURCE_MAX_MEMORY_TYPE = 7, +}; + +static const char *resource_names[] = { + [EFI_RESOURCE_SYSTEM_MEMORY] = "SYSTEM_MEMORY", + [EFI_RESOURCE_MEMORY_MAPPED_IO] = "MMIO", + [EFI_RESOURCE_IO] = "IO", + [EFI_RESOURCE_FIRMWARE_DEVICE] = "FIRMWARE_DEVICE", + [EFI_RESOURCE_MEMORY_MAPPED_IO_PORT] = "MMIO_PORT", + [EFI_RESOURCE_MEMORY_RESERVED] = "MEMORY_RESERVED", + [EFI_RESOURCE_IO_RESERVED] = "IO_RESERVED", +}; + +enum hob_type { + HOB_TYPE_HANDOFF = 0x0001, + HOB_TYPE_MEMORY_ALLOCATION = 0x0002, + HOB_TYPE_RESOURCE_DESCRIPTOR = 0x0003, + HOB_TYPE_GUID_EXTENSION = 0x0004, + HOB_TYPE_FV = 0x0005, + HOB_TYPE_CPU = 0x0006, + HOB_TYPE_MEMORY_POOL = 0x0007, + HOB_TYPE_FV2 = 0x0009, + HOB_TYPE_LOAD_PEIM_UNUSED = 0x000A, + HOB_TYPE_UCAPSULE = 0x000B, + HOB_TYPE_UNUSED = 0xFFFE, + HOB_TYPE_END_OF_HOB_LIST = 0xFFFF, +}; + +/* UUIDs (GUIDs) in little-endian, so they can be used with memcmp() */ +static const uint8_t uuid_owner_bootloader_tolum[16] = { + 0x56, 0x4f, 0xff, 0x73, 0x8e, 0xaa, 0x51, 0x44, + 0xb3, 0x16, 0x36, 0x35, 0x36, 0x67, 0xad, 0x44, +}; + +static const uint8_t uuid_owner_fsp[16] = { + 0x59, 0x97, 0xa7, 0x69, 0x73, 0x13, 0x67, 0x43, + 0xa6, 0xc4, 0xc7, 0xf5, 0x9e, 0xfd, 0x98, 0x6e, +}; + +static const uint8_t uuid_owner_tseg[16] = { + 0x7c, 0x74, 0x38, 0xd0, 0x0c, 0xd0, 0x80, 0x49, + 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55 +}; + +static const uint8_t empty_uuid[16] = { + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 +}; + +static const struct uuid_name_map { + const void *uuid; + const char *name; +} uuid_names[] = { + { uuid_owner_bootloader_tolum, "BOOTLOADER_TOLUM" }, + { uuid_owner_fsp, "FSP_RESERVED_MEMORY" }, + { uuid_owner_tseg, "TSEG" }, +}; + +static const char *resource_name(enum resource_type type) +{ + if (type >= ARRAY_SIZE(resource_names)) + return "UNKNOWN"; + return resource_names[type]; +} + +/* + * Utilities for walking HOBs + */ + +static bool uuid_compare(const uint8_t uuid1[16], const uint8_t uuid2[16]) +{ + return !memcmp(uuid1, uuid2, 16); +} + +static const char *uuid_name(const uint8_t uuid[16]) +{ + size_t i; + const struct uuid_name_map *owner_entry; + + for (i = 0; i < ARRAY_SIZE(uuid_names); i++) { + owner_entry = uuid_names + i; + if (uuid_compare(uuid, owner_entry->uuid)) + return owner_entry->name; + } + return "UNKNOWN"; +} + +static const struct hob_header *next_hob(const struct hob_header *parent) +{ + union { + const struct hob_header *hob; + uintptr_t addr; + } hob_walker; + + hob_walker.hob = parent; + hob_walker.addr += parent->length; + return hob_walker.hob; +} + +static const void *hob_header_to_struct(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN; + return hob_walker.hob_descr; +} + +static const void *hob_header_to_extension_hob(const struct hob_header *hob) +{ + union { + const struct hob_header *hob_hdr; + const void *hob_descr; + uintptr_t addr; + } hob_walker; + + hob_walker.hob_hdr = hob; + hob_walker.addr += HOB_HEADER_LEN + 16; /* header and 16-byte UUID */ + return hob_walker.hob_descr; +} + +static const +struct hob_resource *hob_header_to_resource(const struct hob_header *hob) +{ + return hob_header_to_struct(hob); +} + +/* + * Utilities for locating and identifying HOBs + */ + +void fsp_save_hob_list(void *hob_list_ptr) +{ + void **cbmem_loc; + cbmem_loc = cbmem_add(CBMEM_ID_FSP_RUNTIME, sizeof(*hob_list_ptr)); + *cbmem_loc = hob_list_ptr; +} + +const void *fsp_get_hob_list(void) +{ + void **list_loc = cbmem_find(CBMEM_ID_FSP_RUNTIME); + + return (list_loc) ? (*list_loc) : NULL; +} + +static const +struct hob_resource *find_resource_hob_by_uuid(const struct hob_header *hob, + const uint8_t uuid[16]) +{ + const struct hob_resource *res; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_RESOURCE_DESCRIPTOR) + continue; + + res = hob_header_to_resource(hob); + if (uuid_compare(res->owner_guid, uuid)) + return res; + } + return NULL; +} + +void fsp_find_reserved_memory(struct resource *res, const void *hob_list) +{ + const struct hob_resource *fsp_mem; + + memset(res, 0, sizeof(*res)); + + fsp_mem = find_resource_hob_by_uuid(hob_list, uuid_owner_fsp); + + if (!fsp_mem) { + return; + } + + res->base = fsp_mem->addr; + res->size = fsp_mem->length; +} + +/* + * Utilities for printing HOB information + */ + +static void print_guid(const void *base) +{ + uint32_t big; + uint16_t mid[2]; + + const uint8_t *id = base; + big = read32(id + 0); + mid[0] = read16(id + 4); + mid[1] = read16(id + 6); + + printk(BIOS_DEBUG, "%08x-%04x-%04x-%02x%02x%02x%02x%02x%02x%02x%02x", + big, mid[0], mid[1], + id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); +} + +static void print_resource_descriptor(const void *base) +{ + const struct hob_resource *res; + + res = hob_header_to_resource(base); + + printk(BIOS_DEBUG, "Resource %s, attribute %x\n", + resource_name(res->type), res->attribute_type); + printk(BIOS_DEBUG, "\t0x%08llx + 0x%08llx\n", res->addr, res->length); + if (!uuid_compare(res->owner_guid, empty_uuid)) { + printk(BIOS_DEBUG, "\tOwner GUID: "); + print_guid(res->owner_guid); + printk(BIOS_DEBUG, " (%s)\n", uuid_name(res->owner_guid)); + } +} + + +void fsp_print_memory_resource_hobs(const void *hob_list) +{ + const struct hob_header *hob = hob_list; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + if (hob->type == HOB_TYPE_RESOURCE_DESCRIPTOR) + print_resource_descriptor(hob); + } +} + +const void *fsp_find_extension_hob_by_uuid(const uint8_t *uuid, size_t *size) +{ + const uint8_t *hob_uuid; + const struct hob_header *hob = fsp_get_hob_list(); + + if (!hob) + return NULL; + + for ( ; hob->type != HOB_TYPE_END_OF_HOB_LIST; hob = next_hob(hob)) { + + if (hob->type != HOB_TYPE_GUID_EXTENSION) + continue; + + hob_uuid = hob_header_to_struct(hob); + if (uuid_compare(hob_uuid, uuid)) { + *size = hob->length - (HOB_HEADER_LEN + 16); + return hob_header_to_extension_hob(hob); + } + } + + return NULL; +}

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Patch set updated for coreboot: FSP2.0: Add utility functions
by Andrey Petrov 27 Feb '16

27 Feb '16

Andrey Petrov (andrey.petrov(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13797 -gerrit commit 8c1ee503d55a83f76123203a526b9d6bd6465124 Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Thu Feb 25 14:15:37 2016 -0800 FSP2.0: Add utility functions This adds a set of utility functions that help load and identify FSP blobs. Change-Id: I1d23f60fd1dc8de7966142bcd793289220a1fa5e Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/drivers/intel/fsp2_0/util.c | 122 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 122 insertions(+) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c new file mode 100644 index 0000000..34d8ad9 --- /dev/null +++ b/src/drivers/intel/fsp2_0/util.c @@ -0,0 +1,122 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <cbfs.h> +#include <console/console.h> +#include <fsp/util.h> +#include <lib.h> +#include <memrange.h> +#include <string.h> + +static bool looks_like_fsp_header(const uint8_t *raw_hdr) +{ + if (memcmp(raw_hdr, FSP_HDR_SIGNATURE, 4)) { + printk(BIOS_ALERT, "Did not find a valid FSP signature\n"); + return false; + } + + if (read32(raw_hdr + 4) != FSP_HDR_LEN) { + printk(BIOS_ALERT, "FSP header has invalid length\n"); + return false; + } + + return true; +} + +enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) +{ + const uint8_t *raw_hdr = fsp_blob; + + if (!looks_like_fsp_header(raw_hdr)) + return CB_ERR; + + hdr->revision = read8(raw_hdr + 11); + hdr->fsp_revision = read32(raw_hdr + 12); + memcpy(hdr->image_id, raw_hdr + 16, ARRAY_SIZE(hdr->image_id)); + hdr->image_id[ARRAY_SIZE(hdr->image_id) - 1] = '\0'; + hdr->image_size = read32(raw_hdr + 24); + hdr->image_base = read32(raw_hdr + 28); + hdr->image_attribute = read32(raw_hdr + 32); + hdr->cfg_region_offset = read32(raw_hdr + 36); + hdr->cfg_region_size = read32(raw_hdr + 40); + hdr->notify_phase_entry_offset = read32(raw_hdr + 56); + hdr->memory_init_entry_offset = read32(raw_hdr + 60); + hdr->silicon_init_entry_offset = read32(raw_hdr + 68); + + return CB_SUCCESS; +} + +void fsp_print_header_info(const struct fsp_header *hdr) +{ + printk(BIOS_DEBUG, "Revision %u, image ID: %s, base 0x%lx + 0x%zx\n", + hdr->revision, hdr->image_id, hdr->image_base, hdr->image_size); + printk(BIOS_DEBUG, "\tConfig region 0x%zx + 0x%zx\n", + hdr->cfg_region_offset, hdr->cfg_region_size); + + if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPM) { + printk(BIOS_DEBUG, "\tMemory init offset 0x%zx\n", + hdr->memory_init_entry_offset); + } + + if (hdr->image_attribute & FSP_HDR_ATTRIB_FSPS) { + printk(BIOS_DEBUG, "\tSilicon init offset 0x%zx\n", + hdr->silicon_init_entry_offset); + printk(BIOS_DEBUG, "\tNotify phase offset 0x%zx\n", + hdr->notify_phase_entry_offset); + } + +} + +enum cb_err fsp_load_binary(struct fsp_header *hdr, + const char *name, + struct range_entry *range) +{ + struct cbfsf file_desc; + struct region_device file_data; + void *membase; + + if (cbfs_boot_locate(&file_desc, name, NULL)) { + printk(BIOS_ERR, "Could not locate %s in CBFS\n", name); + return CB_ERR; + } + + cbfs_file_data(&file_data, &file_desc); + + /* Map just enough of the file to be able to parse the header. */ + membase = rdev_mmap(&file_data, FSP_HDR_OFFSET, FSP_HDR_LEN); + if (fsp_identify(hdr, membase) != CB_SUCCESS) { + printk(BIOS_ERR, "%s did not have a valid FSP header\n", name); + return CB_ERR; + } + + fsp_print_header_info(hdr); + + /* Check if size specified in the header matches the cbfs file size */ + if (region_device_sz(&file_data) < hdr->image_size) { + printk(BIOS_ERR, "%s size bigger than cbfs file.\n", name); + return CB_ERR; + } + + /* Check if the binary load address is within expected range */ + if (range_entry_base(range) > hdr->image_base || range_entry_end(range) <= hdr->image_base + + hdr->image_size) { + printk(BIOS_ERR, "%s is outside of allowed range\n", name); + return CB_ERR; + } + + /* Load binary into memory. */ + rdev_readat(&file_data, (void *)hdr->image_base, 0, hdr->image_size); + + return CB_SUCCESS; +}

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New patch to review for coreboot: crosstool: add EXPAT as a dependency on the gdb build.
by Ronald G. Minnich 27 Feb '16

27 Feb '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13846 -gerrit commit b5e4788a4067e01fb0fb1a7ace8069309b94dff2 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sat Feb 27 04:06:42 2016 +0000 crosstool: add EXPAT as a dependency on the gdb build. qemu-power8 wants to tell about itself with XML, and so we need to build gdb with EXPAT so it can understand XML. Change-Id: I460e27f883956ed5d54e6070916e2682ee0f7a1b Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- util/crossgcc/buildgcc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index dc6540d..e4a6d47 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -627,9 +627,10 @@ case "$PACKAGE" in ;; GDB|gdb) NAME="${TARGETARCH} cross GDB" - PACKAGES="GDB" if [ $SKIPPYTHON -eq 0 ]; then - PACKAGES="EXPAT PYTHON $PACKAGES" + PACKAGES="EXPAT PYTHON GDB" + else + PACKAGES="EXPAT GDB" fi ;; CLANG|clang)

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New patch to review for coreboot: coreinfo: quote $(AS) and $(CC) in $(LPAS) and $(LPCC)
by Iru Cai 27 Feb '16

27 Feb '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13845 -gerrit commit 91d0f64c105a7a39aa82a7f3eb33ce20570909fe Author: Iru Cai <mytbk920423(a)gmail.com> Date: Sat Feb 27 11:47:06 2016 +0800 coreinfo: quote $(AS) and $(CC) in $(LPAS) and $(LPCC) without this change it'll get a build error with crossgcc-x64 because $(AS) is "util/crossgcc/xgcc/bin/x86_64-elf-as --32", and running $(LPAS) (i.e. AS=$(AS) lpas) will run "--32" instead of "x86_64-elf-as". Change-Id: I95e5630cb1d4f1ce81a8ca8a7bf338450b325f02 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- payloads/coreinfo/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/coreinfo/Makefile b/payloads/coreinfo/Makefile index a3a02c2..c9f5c10 100644 --- a/payloads/coreinfo/Makefile +++ b/payloads/coreinfo/Makefile @@ -78,8 +78,8 @@ CC := $(CC_$(ARCH-y)) AS := $(AS_$(ARCH-y)) OBJCOPY := $(OBJCOPY_$(ARCH-y)) -LPCC := CC=$(CC) $(LIBPAYLOAD_DIR)/libpayload/bin/lpgcc -LPAS := AS=$(AS) $(LIBPAYLOAD_DIR)/libpayload/bin/lpas +LPCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/libpayload/bin/lpgcc +LPAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/libpayload/bin/lpas CFLAGS += -Wall -Werror -Os -fno-builtin $(CFLAGS_$(ARCH-y)) $(INCLUDES)

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coreboot-gerrit February 2016