coreboot-gerrit February 2016

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Patch set updated for coreboot: drivers/lenovo: Add hybrid graphics driver
by Patrick Rudolph 28 Feb '16

28 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12896 -gerrit commit 097d24e949a14040e1ce5a3ad6f3753fdb4dc9c5 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:35:08 2015 +0100 drivers/lenovo: Add hybrid graphics driver Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T530 using Nvidia NVS 5400m. Depends on change id: I97418f421fb1e525752c32ba886c7c78e8d3aa24 Ie37ec4aeae8ab49fe8e26438c430911d1815551c Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/lenovo/Kconfig | 13 +++++ src/drivers/lenovo/Makefile.inc | 1 + src/drivers/lenovo/hybrid_graphics.c | 100 +++++++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/Kconfig | 1 + src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t530/Kconfig | 1 + src/southbridge/intel/i82801ix/Kconfig | 1 + 9 files changed, 120 insertions(+) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index f20f3b2..f8eddf2 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -27,3 +27,16 @@ config DIGITIZER_ABSENT endchoice endif + +config DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n + +config HYBRID_GRAPHICS_GPIO_NUM + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + int + default 52 + help + Set a default GPIO that sets the panel LVDS signal routing to + integrated or discrete GPU. + diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc index c50db5b..66f8594 100644 --- a/src/drivers/lenovo/Makefile.inc +++ b/src/drivers/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c new file mode 100644 index 0000000..863029f --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <device/pci.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h> + +/* Hybrid graphics allows to connect LVDS interface to either iGPU + * or dGPU depending on GPIO level. + * As it is only linked on lenovo and only executed if the GPU exists + * we know for sure that the dGPU is there and connected to first PEG slot. + * + * Note: Once native gfx init is done for AMD or Nvida graphic + * cards, merge this code. + */ + +static void hybrid_graphics_enable_peg(struct device *dev) +{ + /* connect LVDS interface to dGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + printk(BIOS_DEBUG, "Switching panel to discrete GPU\n"); + dev->enabled = 1; +} + +static void hybrid_graphics_disable_peg(struct device *dev) +{ + struct device *peg_dev; + + /* connect LVDS interface to iGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + printk(BIOS_DEBUG, "Switching panel to integrated GPU\n"); + printk(BIOS_DEBUG, "Disabling device 0x%04x:0x%04x on bus %s\n", + dev->vendor, dev->device, bus_path(dev->bus)); + dev->enabled = 0; + + /* Disable PEG10 */ + peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (peg_dev) + peg_dev->enabled = 0; +} + +static struct pci_operations pci_dev_ops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations hybrid_graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .scan_bus = 0, + .enable = hybrid_graphics_enable_peg, + .disable = hybrid_graphics_disable_peg, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids_nvidia[] = { + 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ + 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ + 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ + 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ + 0 }; + +static const struct pci_driver hybrid_peg_nvidia __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .devices = pci_device_ids_nvidia, +}; + +static const unsigned short pci_device_ids_amd[] = { + 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ + 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ + 0 }; + +static const struct pci_driver hybrid_peg_amd __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_ATI, + .devices = pci_device_ids_amd, +}; + diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 0eac311..59938bd 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index ce81af7..14a6707 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index cec1b14..660b63d 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select IVYBRIDGE_LVDS select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 66a5c64..b2151c8 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index f3b378a..4d9b45f 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 2822774..b3e5069 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -23,6 +23,7 @@ config SOUTHBRIDGE_INTEL_I82801IX select USE_WATCHDOG_ON_BOOT select HAVE_SMI_HANDLER select HAVE_USBDEBUG_OPTIONS + select SOUTHBRIDGE_INTEL_COMMON_GPIO if SOUTHBRIDGE_INTEL_I82801IX

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Patch set updated for coreboot: drivers/lenovo: Add hybrid graphics driver
by Patrick Rudolph 28 Feb '16

28 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12896 -gerrit commit 8c78f00f4a792c7a1f1df42ec6f711ed3bcd199d Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sat Dec 26 08:35:08 2015 +0100 drivers/lenovo: Add hybrid graphics driver Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Tested on Lenovo T530 using Nvidia NVS 5400m. Depends on change id: I97418f421fb1e525752c32ba886c7c78e8d3aa24 Ie37ec4aeae8ab49fe8e26438c430911d1815551c Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/drivers/lenovo/Kconfig | 13 +++++ src/drivers/lenovo/Makefile.inc | 1 + src/drivers/lenovo/hybrid_graphics.c | 100 +++++++++++++++++++++++++++++++++++ src/mainboard/lenovo/t400/Kconfig | 1 + src/mainboard/lenovo/t420s/Kconfig | 1 + src/mainboard/lenovo/t430s/Kconfig | 1 + src/mainboard/lenovo/t520/Kconfig | 1 + src/mainboard/lenovo/t530/Kconfig | 1 + 8 files changed, 119 insertions(+) diff --git a/src/drivers/lenovo/Kconfig b/src/drivers/lenovo/Kconfig index f20f3b2..f8eddf2 100644 --- a/src/drivers/lenovo/Kconfig +++ b/src/drivers/lenovo/Kconfig @@ -27,3 +27,16 @@ config DIGITIZER_ABSENT endchoice endif + +config DRIVERS_LENOVO_HYBRID_GRAPHICS + bool + default n + +config HYBRID_GRAPHICS_GPIO_NUM + depends on DRIVERS_LENOVO_HYBRID_GRAPHICS + int + default 52 + help + Set a default GPIO that sets the panel LVDS signal routing to + integrated or discrete GPU. + diff --git a/src/drivers/lenovo/Makefile.inc b/src/drivers/lenovo/Makefile.inc index c50db5b..66f8594 100644 --- a/src/drivers/lenovo/Makefile.inc +++ b/src/drivers/lenovo/Makefile.inc @@ -1 +1,2 @@ ramstage-$(CONFIG_DRIVERS_LENOVO_WACOM) += wacom.c +ramstage-$(CONFIG_DRIVERS_LENOVO_HYBRID_GRAPHICS) += hybrid_graphics.c diff --git a/src/drivers/lenovo/hybrid_graphics.c b/src/drivers/lenovo/hybrid_graphics.c new file mode 100644 index 0000000..863029f --- /dev/null +++ b/src/drivers/lenovo/hybrid_graphics.c @@ -0,0 +1,100 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Patrick Rudolph + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <types.h> +#include <string.h> +#include <device/device.h> +#include <device/pci_def.h> +#include <device/pci_ops.h> +#include <device/pci_ids.h> +#include <device/pci.h> +#include <console/console.h> +#include <southbridge/intel/common/gpio.h> + +/* Hybrid graphics allows to connect LVDS interface to either iGPU + * or dGPU depending on GPIO level. + * As it is only linked on lenovo and only executed if the GPU exists + * we know for sure that the dGPU is there and connected to first PEG slot. + * + * Note: Once native gfx init is done for AMD or Nvida graphic + * cards, merge this code. + */ + +static void hybrid_graphics_enable_peg(struct device *dev) +{ + /* connect LVDS interface to dGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_LOW); + printk(BIOS_DEBUG, "Switching panel to discrete GPU\n"); + dev->enabled = 1; +} + +static void hybrid_graphics_disable_peg(struct device *dev) +{ + struct device *peg_dev; + + /* connect LVDS interface to iGPU */ + set_gpio(CONFIG_HYBRID_GRAPHICS_GPIO_NUM, GPIO_LEVEL_HIGH); + printk(BIOS_DEBUG, "Switching panel to integrated GPU\n"); + printk(BIOS_DEBUG, "Disabling device 0x%04x:0x%04x on bus %s\n", + dev->vendor, dev->device, bus_path(dev->bus)); + dev->enabled = 0; + + /* Disable PEG10 */ + peg_dev = dev_find_slot(0, PCI_DEVFN(1, 0)); + if (peg_dev) + peg_dev->enabled = 0; +} + +static struct pci_operations pci_dev_ops_pci = { + .set_subsystem = pci_dev_set_subsystem, +}; + +struct device_operations hybrid_graphics_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = pci_dev_init, + .scan_bus = 0, + .enable = hybrid_graphics_enable_peg, + .disable = hybrid_graphics_disable_peg, + .ops_pci = &pci_dev_ops_pci, +}; + +static const unsigned short pci_device_ids_nvidia[] = { + 0x0ffc, /* Nvidia NVS Quadro K1000m Lenovo W530 */ + 0x0def, /* NVidia NVS 5400m Lenovo T430/T530 */ + 0x0dfc, /* NVidia NVS 5200m Lenovo T430s */ + 0x1056, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x1057, /* NVidia NVS 4200m Lenovo T420/T520 */ + 0x0a6c, /* NVidia NVS 3100m Lenovo T410/T510 */ + 0 }; + +static const struct pci_driver hybrid_peg_nvidia __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_NVIDIA, + .devices = pci_device_ids_nvidia, +}; + +static const unsigned short pci_device_ids_amd[] = { + 0x9591, /* ATI Mobility Radeon HD 3650 Lenovo T500/W500 */ + 0x95c4, /* ATI Mobility Radeon HD 3470 Lenovo T400/R400 */ + 0 }; + +static const struct pci_driver hybrid_peg_amd __pci_driver = { + .ops = &hybrid_graphics_ops, + .vendor = PCI_VENDOR_ID_ATI, + .devices = pci_device_ids_amd, +}; + diff --git a/src/mainboard/lenovo/t400/Kconfig b/src/mainboard/lenovo/t400/Kconfig index 0eac311..59938bd 100644 --- a/src/mainboard/lenovo/t400/Kconfig +++ b/src/mainboard/lenovo/t400/Kconfig @@ -22,6 +22,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG select INTEL_INT15 select SUPERIO_NSC_PC87382 + select DRIVERS_LENOVO_HYBRID_GRAPHICS config MAINBOARD_DIR string diff --git a/src/mainboard/lenovo/t420s/Kconfig b/src/mainboard/lenovo/t420s/Kconfig index ce81af7..14a6707 100644 --- a/src/mainboard/lenovo/t420s/Kconfig +++ b/src/mainboard/lenovo/t420s/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t430s/Kconfig b/src/mainboard/lenovo/t430s/Kconfig index cec1b14..660b63d 100644 --- a/src/mainboard/lenovo/t430s/Kconfig +++ b/src/mainboard/lenovo/t430s/Kconfig @@ -19,6 +19,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select IVYBRIDGE_LVDS select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t520/Kconfig b/src/mainboard/lenovo/t520/Kconfig index 66a5c64..b2151c8 100644 --- a/src/mainboard/lenovo/t520/Kconfig +++ b/src/mainboard/lenovo/t520/Kconfig @@ -18,6 +18,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select INTEL_INT15 select SANDYBRIDGE_LVDS select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE diff --git a/src/mainboard/lenovo/t530/Kconfig b/src/mainboard/lenovo/t530/Kconfig index f3b378a..4d9b45f 100644 --- a/src/mainboard/lenovo/t530/Kconfig +++ b/src/mainboard/lenovo/t530/Kconfig @@ -20,6 +20,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MAINBOARD_DO_NATIVE_VGA_INIT # default to native vga init select ENABLE_VMX select MAINBOARD_HAS_LPC_TPM + select DRIVERS_LENOVO_HYBRID_GRAPHICS # Workaround for EC/KBC IRQ1. select SERIRQ_CONTINUOUS_MODE

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Patch set updated for coreboot: nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk
by Patrick Rudolph 28 Feb '16

28 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13487 -gerrit commit 7386bc889590756ce8b0bf37046e173f9b36820b Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jan 26 20:02:14 2016 +0100 nb/intel/sandybridge/romstage: Read fuse bits for max MEM Clk Instead of hardcoding the maximum supported DDR frequency to 800Mhz (DDR3-1600), read the fuse bits that encode this information. Test system: * Intel IvyBridge * Gigabyte GA-B75M-D3H Change-Id: I515a2695a490f16aeb946bfaf3a1e860c607cba9 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/include/device/dram/ddr3.h | 4 +- src/northbridge/intel/sandybridge/raminit.c | 63 +++++++++++++++++++------ src/northbridge/intel/sandybridge/sandybridge.h | 3 ++ 3 files changed, 55 insertions(+), 15 deletions(-) diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 0520ead..89907ae 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -33,8 +33,10 @@ * These values are in 1/256 ns units. * @{ */ +#define TCK_1333MHZ 192 +#define TCK_1200MHZ 212 #define TCK_1066MHZ 240 -#define TCK_933MHZ 275 +#define TCK_933MHZ 275 #define TCK_800MHZ 320 #define TCK_666MHZ 384 #define TCK_533MHZ 480 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 40089e2..5b7ae8d 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -4072,26 +4072,61 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, static unsigned int get_mem_min_tck(void) { + u32 reg32; + u8 rev; const struct device *dev; - const struct northbridge_intel_sandybridge_config *cfg; + const struct northbridge_intel_sandybridge_config *cfg = NULL; dev = dev_find_slot(0, HOST_BRIDGE); - if (!(dev && dev->chip_info)) - return DEFAULT_TCK; - - cfg = dev->chip_info; + if (dev) + cfg = dev->chip_info; /* If this is zero, it just means devicetree.cb didn't set it */ - if (cfg->max_mem_clock_mhz == 0) + if (!cfg || cfg->max_mem_clock_mhz == 0) { + rev = pci_read_config8(PCI_DEV(0, 0, 0), PCI_DEVICE_ID); + + if ((rev & BASE_REV_MASK) == BASE_REV_SNB) { + /* read Capabilities A Register DMFC bits */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_A); + reg32 &= 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + /* reserved: */ + default: + break; + } + } else { + /* read Capabilities B Register DMFC bits */ + reg32 = pci_read_config32(PCI_DEV(0, 0, 0), CAPID0_B); + reg32 = (reg32 >> 4) & 0x7; + + switch (reg32) { + case 7: return TCK_533MHZ; + case 6: return TCK_666MHZ; + case 5: return TCK_800MHZ; + case 4: return TCK_933MHZ; + case 3: return TCK_1066MHZ; + case 2: return TCK_1200MHZ; + case 1: return TCK_1333MHZ; + /* reserved: */ + default: + break; + } + } return DEFAULT_TCK; - - if (cfg->max_mem_clock_mhz >= 800) - return TCK_800MHZ; - else if (cfg->max_mem_clock_mhz >= 666) - return TCK_666MHZ; - else if (cfg->max_mem_clock_mhz >= 533) - return TCK_533MHZ; - return TCK_400MHZ; + } else { + if (cfg->max_mem_clock_mhz >= 800) + return TCK_800MHZ; + else if (cfg->max_mem_clock_mhz >= 666) + return TCK_666MHZ; + else if (cfg->max_mem_clock_mhz >= 533) + return TCK_533MHZ; + else + return TCK_400MHZ; + } } void perform_raminit(int s3resume) diff --git a/src/northbridge/intel/sandybridge/sandybridge.h b/src/northbridge/intel/sandybridge/sandybridge.h index 570e1f7..ba8f8d9 100644 --- a/src/northbridge/intel/sandybridge/sandybridge.h +++ b/src/northbridge/intel/sandybridge/sandybridge.h @@ -99,6 +99,9 @@ #define TSEG 0xb8 /* TSEG base */ #define TOLUD 0xbc /* Top of Low Used Memory */ +#define CAPID0_A 0xe4 /* Capabilities Register A */ +#define CAPID0_B 0xe8 /* Capabilities Register B */ + #define SKPAD 0xdc /* Scratchpad Data */ /* Device 0:1.0 PCI configuration space (PCI Express) */

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Patch set updated for coreboot: northbridge/intel: add missing #include guards
by Iru Cai 28 Feb '16

28 Feb '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13775 -gerrit commit e52512b34d32ac2d13468d70e07184e5f64959ac Author: Iru Cai <mytbk920423(a)gmail.com> Date: Wed Feb 24 15:03:58 2016 +0800 northbridge/intel: add missing #include guards I first found the missing of #include guards when I tried to include both sandybridge/gma.h and sandybridge/sandybridge.h, but sandybridge.h includes gma.h in it and gives a compile error. Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/northbridge/intel/e7501/e7501.h | 5 +++++ src/northbridge/intel/e7505/e7505.h | 5 +++++ src/northbridge/intel/fsp_sandybridge/chip.h | 5 +++++ src/northbridge/intel/fsp_sandybridge/gma.h | 5 +++++ src/northbridge/intel/haswell/chip.h | 5 +++++ src/northbridge/intel/haswell/gma.h | 5 +++++ src/northbridge/intel/i3100/chip.h | 5 +++++ src/northbridge/intel/i440bx/i440bx.h | 5 +++++ src/northbridge/intel/i82830/i82830.h | 5 +++++ src/northbridge/intel/i855/i855.h | 5 +++++ src/northbridge/intel/i945/chip.h | 5 +++++ src/northbridge/intel/nehalem/chip.h | 5 +++++ src/northbridge/intel/pineview/chip.h | 5 +++++ src/northbridge/intel/sandybridge/chip.h | 5 +++++ src/northbridge/intel/sandybridge/gma.h | 5 +++++ src/northbridge/intel/sch/nvs.h | 5 +++++ 16 files changed, 80 insertions(+) diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h index a9690d8..a2800fc 100644 --- a/src/northbridge/intel/e7501/e7501.h +++ b/src/northbridge/intel/e7501/e7501.h @@ -18,6 +18,9 @@ * e7501.h: PCI configuration space for the Intel E7501 memory controller */ +#ifndef NORTHBRIDGE_INTEL_E7501_E7501_H +#define NORTHBRIDGE_INTEL_E7501_E7501_H + /************ D0:F0 ************/ // Register offsets #define MAYBE_SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */ @@ -73,3 +76,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* NORTHBRIDGE_INTEL_E7501_E7501_H */ diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 525dce8..9c9171d 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -18,6 +18,9 @@ * e7505.h: PCI configuration space for the Intel E7501 memory controller */ +#ifndef NORTHBRIDGE_INTEL_E7505_E7505_H +#define NORTHBRIDGE_INTEL_E7505_E7505_H + /************ D0:F0 ************/ // Register offsets #define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */ @@ -78,3 +81,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* NORTHBRIDGE_INTEL_E7505_E7505_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h index e6f3a54..eb86b83 100644 --- a/src/northbridge/intel/fsp_sandybridge/chip.h +++ b/src/northbridge/intel/fsp_sandybridge/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_CHIP_H +#define NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -39,3 +42,5 @@ struct northbridge_intel_fsp_sandybridge_config { struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/gma.h b/src/northbridge/intel/fsp_sandybridge/gma.h index baab695..5693e0c 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.h +++ b/src/northbridge/intel/fsp_sandybridge/gma.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H +#define NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H + /* mailbox 0: header */ typedef struct { u8 signature[16]; @@ -161,3 +164,5 @@ typedef struct { } __attribute__((packed)) optionrom_vbt_t; #define VBT_SIGNATURE 0x54425624 + +#endif /* NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 67ba074..098bc33 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H +#define NORTHBRIDGE_INTEL_HASWELL_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -41,3 +44,5 @@ struct northbridge_intel_haswell_config { }; extern struct chip_operations northbridge_intel_haswell_ops; + +#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */ diff --git a/src/northbridge/intel/haswell/gma.h b/src/northbridge/intel/haswell/gma.h index baab695..5adab57 100644 --- a/src/northbridge/intel/haswell/gma.h +++ b/src/northbridge/intel/haswell/gma.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_HASWELL_GMA_H +#define NORTHBRIDGE_INTEL_HASWELL_GMA_H + /* mailbox 0: header */ typedef struct { u8 signature[16]; @@ -161,3 +164,5 @@ typedef struct { } __attribute__((packed)) optionrom_vbt_t; #define VBT_SIGNATURE 0x54425624 + +#endif /* NORTHBRIDGE_INTEL_HASWELL_GMA_H */ diff --git a/src/northbridge/intel/i3100/chip.h b/src/northbridge/intel/i3100/chip.h index aa7407a..5da7431 100644 --- a/src/northbridge/intel/i3100/chip.h +++ b/src/northbridge/intel/i3100/chip.h @@ -13,8 +13,13 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_I3100_CHIP_H +#define NORTHBRIDGE_INTEL_I3100_CHIP_H + struct northbridge_intel_i3100_config { /* Interrupt line connect */ u16 intrline; }; + +#endif /* NORTHBRIDGE_INTEL_I3100_CHIP_H */ diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 44dca2f..4724719 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_I440BX_I440BX_H +#define NORTHBRIDGE_INTEL_I440BX_I440BX_H + /* * Datasheet: * - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller @@ -82,3 +85,5 @@ #define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */ #define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */ #define BUFFC 0xf0 /* Buffer Control Register (0x0000). */ + +#endif /* NORTHBRIDGE_INTEL_I440BX_I440BX_H */ diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h index e1e2862..74520b1 100644 --- a/src/northbridge/intel/i82830/i82830.h +++ b/src/northbridge/intel/i82830/i82830.h @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H +#define NORTHBRIDGE_INTEL_I82830_I82830_H + #define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ #define GCC0 0x50 /* GMCH Control #0 (0xa072) */ #define GCC1 0x52 /* GMCH Control #1 (0x0000) */ @@ -45,3 +48,5 @@ #define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ #define APSIZE 0xb4 /* Apterture Size (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ + +#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */ diff --git a/src/northbridge/intel/i855/i855.h b/src/northbridge/intel/i855/i855.h index 10c7873..467875f 100644 --- a/src/northbridge/intel/i855/i855.h +++ b/src/northbridge/intel/i855/i855.h @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_I855_I855_H +#define NORTHBRIDGE_INTEL_I855_I855_H + /* Host-Hub Interface Bridge */ #define GMC 0x50 /* GMCH Misc. Control (0x0000) */ #define GGC 0x52 /* GMCH Graphics Control (0x0030) */ @@ -70,3 +73,5 @@ #define DRT_TRAS_MIN_7 (1 << 9) #define DRT_TRAS_MIN_6 (2 << 9) #define DRT_TRAS_MIN_5 (3 << 9) + +#endif /* NORTHBRIDGE_INTEL_I855_I855_H */ diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 52925ff..446af72 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -1,3 +1,6 @@ +#ifndef NORTHBRIDGE_INTEL_I945_CHIP_H +#define NORTHBRIDGE_INTEL_I945_CHIP_H + #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { @@ -6,3 +9,5 @@ struct northbridge_intel_i945_config { int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index 5598022..caf9819 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H +#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -39,3 +42,5 @@ struct northbridge_intel_nehalem_config { struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */ diff --git a/src/northbridge/intel/pineview/chip.h b/src/northbridge/intel/pineview/chip.h index aabb05e..a63db78 100644 --- a/src/northbridge/intel/pineview/chip.h +++ b/src/northbridge/intel/pineview/chip.h @@ -1,3 +1,6 @@ +#ifndef NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H +#define NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H + #include <drivers/intel/gma/i915.h> struct northbridge_intel_pineview_config { @@ -7,3 +10,5 @@ struct northbridge_intel_pineview_config { int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index b04f95e..5effc0d 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H +#define NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -45,3 +48,5 @@ struct northbridge_intel_sandybridge_config { struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 8381863..0832468 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H +#define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H + /* mailbox 0: header */ typedef struct { u8 signature[16]; @@ -114,3 +117,5 @@ struct i915_gpu_controller_info; int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u8 *mmio, u32 lfb); + +#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/sch/nvs.h b/src/northbridge/intel/sch/nvs.h index d147b9c..b167f26 100644 --- a/src/northbridge/intel/sch/nvs.h +++ b/src/northbridge/intel/sch/nvs.h @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_SCH_NVS_H +#define NORTHBRIDGE_INTEL_SCH_NVS_H + typedef struct { u16 osys; u8 smif; @@ -100,3 +103,5 @@ typedef struct { u8 idet; u8 dock; } global_nvs_t; + +#endif /* NORTHBRIDGE_INTEL_SCH_NVS_H */

1 0

New patch to review for coreboot: nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic
by Patrick Rudolph 28 Feb '16

28 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13853 -gerrit commit a17f30e3264bc9b2b5a75bf94ce11250bd32e0d3 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Feb 28 16:14:45 2016 +0100 nb/intel/sandybridge/raminit: Make discover_timC_write non cyclic The code can't handle cyclic zero runs. Make sure it will never wrap around by setting the top-most bit to constant one. Fixes "Mini channel test failed (2)". Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 Change-Id: I55e610d984d564bd4675f9318dead6d6c1e288a3 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 40089e2..603122c 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -3422,9 +3422,12 @@ static void discover_timC_write(ramctr_timing * ctrl) u32 raw_statistics[MAX_TIMC + 1]; int statistics[MAX_TIMC + 1]; + /* Make sure rn.start < rn.end */ + statistics[MAX_TIMC] = 1; + fill_pattern5(ctrl, channel, pat); write32(DEFAULT_MCHBAR + 0x4288 + 0x400 * channel, 0x1f); - for (timC = 0; timC < MAX_TIMC + 1; timC++) { + for (timC = 0; timC < MAX_TIMC; timC++) { FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].timC = timC; program_timings(ctrl, channel); @@ -3436,10 +3439,11 @@ static void discover_timC_write(ramctr_timing * ctrl) } FOR_ALL_LANES { struct run rn; - for (timC = 0; timC <= MAX_TIMC; timC++) + for (timC = 0; timC < MAX_TIMC; timC++) statistics[timC] = !!(raw_statistics[timC] & (1 << lane)); + rn = get_longest_zero_run(statistics, MAX_TIMC + 1); if (rn.all)

1 0

New patch to review for coreboot: nb/intel/sandybridge/raminit: Fill SMBIOS type17 info
by Patrick Rudolph 28 Feb '16

28 Feb '16

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13852 -gerrit commit 1b23f80902ae38ae9b597d582750b5a927bffbfc Author: Patrick Rudolph <siro(a)das-labor.org> Date: Sun Feb 28 15:24:04 2016 +0100 nb/intel/sandybridge/raminit: Fill SMBIOS type17 info Fill minimal info required for SMBIOS type 17. Report DIMM size, channel, rank and DDR speed. Allows dmidecode to print the current RAM configuration. Move report_memory_config() to make sure cbmem is initialized to prevent system hang. Test system: * Gigabyte GA-B75M-D3H * Intel Pentium CPU G2130 * Linux 4.3 * dmidecode 3.0 Change-Id: I4e5f772d68484b9cb178ca8a1d63ad99839f3993 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/northbridge/intel/sandybridge/raminit.c | 60 ++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 9 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 40089e2..eb21933 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -27,6 +27,8 @@ #include <timestamp.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> +#include <memory_info.h> +#include <smbios.h> #include "raminit_native.h" #include "sandybridge.h" #include <delay.h> @@ -239,22 +241,36 @@ static void toggle_io_reset(void) { static void report_memory_config(void) { u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; - int i; + struct memory_info *mem_info; + int channel; + uint16_t ddr_freq; + struct dimm_info *dimm; addr_decoder_common = MCHBAR32(0x5000); addr_decode_ch[0] = MCHBAR32(0x5004); addr_decode_ch[1] = MCHBAR32(0x5008); - printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(0x5e04) * 13333 * 2 + 50) / 100); + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (mem_info) + memset(mem_info, 0, sizeof(*mem_info)); + + ddr_freq = (MCHBAR32(0x5e04) * 13333 * 2 + 50) / 100; + + printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", ddr_freq); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); - for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { - u32 ch_conf = addr_decode_ch[i]; - printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", i, - ch_conf); + for (channel = 0; channel < ARRAY_SIZE(addr_decode_ch); channel++) { + u32 ch_conf = addr_decode_ch[channel]; + + printk(BIOS_DEBUG, "memcfg channel[%d] config (%8.8x):\n", + channel, ch_conf); printk(BIOS_DEBUG, " ECC %s\n", ecc_decoder[(ch_conf >> 24) & 3]); printk(BIOS_DEBUG, " enhanced interleave mode %s\n", @@ -271,6 +287,32 @@ static void report_memory_config(void) ((ch_conf >> 20) & 1) ? 16 : 8, ((ch_conf >> 18) & 1) ? "dual" : "single", ((ch_conf >> 16) & 1) ? ", selected" : ""); + + if (!mem_info) + continue; + + if ((ch_conf >> 0) & 0xff) { + dimm = &mem_info->dimm[mem_info->dimm_cnt]; + dimm->ddr_type = MEMORY_TYPE_DDR3; + dimm->ddr_frequency = ddr_freq; + dimm->dimm_size = ((ch_conf >> 0) & 0xff) * 256; + dimm->channel_num = channel; + dimm->rank_per_dimm = ((ch_conf >> 17) & 1) + 1; + dimm->dimm_num = 0; + dimm->bus_width = ((ch_conf >> 19) & 1) ? 16 : 8; + mem_info->dimm_cnt++; + } + if ((ch_conf >> 8) & 0xff) { + dimm = &mem_info->dimm[mem_info->dimm_cnt]; + dimm->ddr_type = MEMORY_TYPE_DDR3; + dimm->ddr_frequency = ddr_freq; + dimm->dimm_size = ((ch_conf >> 8) & 0xff) * 256; + dimm->channel_num = channel; + dimm->rank_per_dimm = ((ch_conf >> 18) & 1) + 1; + dimm->dimm_num = 1; + dimm->bus_width = ((ch_conf >> 20) & 1) ? 16 : 8; + mem_info->dimm_cnt++; + } } } @@ -4055,8 +4097,6 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, intel_early_me_init_done(ME_INIT_STATUS_SUCCESS); intel_early_me_status(); - report_memory_config(); - cbmem_was_inited = !cbmem_recovery(s3resume); if (!s3resume) save_timings(&ctrl); @@ -4065,6 +4105,8 @@ void init_dram_ddr3(spd_raw_data * spds, int mobile, int min_tck, outb(0x6, 0xcf9); halt(); } + + report_memory_config(); } #define HOST_BRIDGE PCI_DEVFN(0, 0)

1 0

New patch to review for coreboot: Documentation/Intel: More CorebootPayloadPkg documentation
by Leroy P Leahy 28 Feb '16

28 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13851 -gerrit commit 9f88c7b5dbb86958f68179afe29cd5a1de00ef78 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 28 06:22:47 2016 -0800 Documentation/Intel: More CorebootPayloadPkg documentation Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/quark.html | 4 +-- Documentation/Intel/SoC/soc.html | 54 +++++++++++++++++++++++++++++++++++- Documentation/Intel/development.html | 13 ++++++++- Documentation/Intel/index.html | 16 ++++++++++- 4 files changed, 82 insertions(+), 5 deletions(-) diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index ea704a9..5fe3f5c 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -47,7 +47,7 @@ <hr> -<h1>Quark™ EDK2 CorebootPayloadPkg</h1> +<h1><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h1> <p> Build Instructions: </p> @@ -214,6 +214,6 @@ Documentation: <hr> -<p>Modified: 20 February 2016</p> +<p>Modified: 24 February 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 5a0a442..2380cdf 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -33,6 +33,7 @@ </ol> </li> <li><a href="#AcpiTables">ACPI Tables</a></li> + <li><a href="#LegacyHardware">Legacy Hardware</a></li> </ol> @@ -560,7 +561,7 @@ Use the following steps to debug the call to TempRamInit: <hr> <h1><a name="AcpiTables">ACPI Tables</a></h1> <p> - One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg. + One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. </p> <h2>FADT</h2> @@ -664,6 +665,57 @@ Use the following steps to debug the call to TempRamInit: </ol> + +<hr> +<h1><a name="LegacyHardware">Legacy Hardware</a></h1> +<p> + One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. +</p> + +<table border="1"> + <tr bgcolor="c0ffc0"> + <th>Peripheral</th> + <th>Use</th> + <th>8259 Interrupt Vector</th> + <th>IDT Base Offset</th> + <th>Interrupt Handler</th> + </tr> + <tr> + <td> + <a target="_blank" href="http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf">8254</a> + Programmable Interval Timer + </td> + <td> + EDK2: PcAtChipsetPkg/8254TimerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/T…">Timer.c</a> + </td> + <td>0</td> + <td>0x340</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/T…">TimerInterruptHandler</a> + </td> + </tr> + <tr> + <td> + <a target="_blank" href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uac…">8259</a> + Programmable Interrupt Controller + </td> + <td> + EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptC…">8259.c</a> + </td> + <td> + Master interrupts: 0, 2 - 7<br> + Slave interrupts: 8 - 15<br> + Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15 + </td> + <td> + Master: 0x340, 0x350 - 0x378<br> + Slave: 0x380 - 0x3b8<br> + Interrupt descriptors are 8 bytes each + </td> + <td> </td> + </tr> +</table> + <hr> <p>Modified: 28 February 2016</p> </body> diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 74a476f..7b82321 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -125,6 +125,7 @@ <li>Payload and OS Features: <ul> <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li> + <li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li> </ul> </li> </ul> @@ -142,6 +143,16 @@ <th>Testing</th> </tr> <tr> + <td>8254 Programmable Interval Timer</td> + <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> + <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> + </tr> + <tr> + <td>8259 Programmable Interrupt Controller</td> + <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> + <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> + </tr> + <tr> <td>Cache-as-RAM</td> <td> <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a> @@ -335,6 +346,6 @@ <hr> -<p>Modified: 20 February 2016</p> +<p>Modified: 24 February 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index 61d14c8..4d508bf 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -21,6 +21,7 @@ <h1>x86 coreboot Development</h1> <ul> + <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> <li><a target="_blank" href="development.html">Overall</a> development</li> <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration </li> @@ -28,10 +29,23 @@ <li><a target="_blank" href="Board/board.html">Board</a> support</li> </ul> +<h1>Payload Development</h1> +<ul> + <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> + <ul> + <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Pr…">EDK II Development Process</a></li> + <li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20pa…">White Papers</a></li> + <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github…">SourceForge to Github Quick Start</a></li> + <li>UEFI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_…">2.5 Errata A</a></li> + </ul> + </li> +</ul> + + + <h1>Documentation</h1> <ul> <li><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI 6.0 Specification</a></li> - <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3…">Software Developer Manual</a></li> <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-speci…">V1.1</a></li> </ul>

1 0

Patch set updated for coreboot: Documentation/Intel: Add ACPI link and more FADT documentation
by Leroy P Leahy 28 Feb '16

28 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13765 -gerrit commit 4b8f320b4dab0eb3d7b5c13050c23bfbfaf53668 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 21 16:13:16 2016 -0800 Documentation/Intel: Add ACPI link and more FADT documentation Add a link to the ACPI specification. Update the FADT table to better describe the use and ACPI specification reference for the various fields. TEST=None Change-Id: I77cd925800d71398be6d677de48874099ea26479 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/soc.html | 84 ++++++++++++++++++++++++++++++++++------ Documentation/Intel/index.html | 3 +- 2 files changed, 75 insertions(+), 12 deletions(-) diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 3e72da3..5a0a442 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -566,21 +566,83 @@ Use the following steps to debug the call to TempRamInit: <h2>FADT</h2> <p> The EDK2 module - CorebootModulePkg/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPe…">CbSupportPei.c</a> - requires that the FADT contains the following values: + CorebootModulePkg/Library/CbParseLib/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbP…">CbParseLib.c</a> + requires that the FADT contains the values in the table below. + These values are placed into a HOB identified by + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CorebootMod…">gUefiAcpiBoardInfoGuid</a> + by routine + CorebootModulePkg/CbSupportPei/CbSupportPei/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/CbSupportPe…">CbPeiEntryPoint</a>. </p> <table border="1"> <tr bgcolor="#c0ffc0"> - <td>EDK2 Field</td> <td>Coreboot Field</td> + <td>EDK2 Field</td> + <td>gUefiAcpiBoardInfoGuid</td> + <td>Use</li> + <td> + <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI Spec.</a> + Section + </td> + </tr> + <tr> + <td>gpe0_blk<br>gpe0_blk_len</td> + <td>Gpe0Blk<br>Gpe0BlkLen</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootModulePkg/Library/CbP…">PmGpeEnBase</a> + </td> + <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Shutdown</a></td> + <td>4.8.4.1</td> + </tr> + <tr> + <td>pm1a_cnt_blk</td> + <td>Pm1aCntBlk</td> + <td>PmCtrlRegBase</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Shutdown</a><br> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Suspend</a> + </td> + <td>4.8.3.2.1</td> + </tr> + <tr> + <td>pm1a_evt_blk</td> + <td>Pm1aEvtBlk</td> + <td>PmEvtBase</td> + <td><a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Shutdown</a></td> + <td>4.8.3.1.1</td> + </tr> + <tr> + <td>pm_tmr_blk</td> + <td>PmTmrBlk</td> + <td>PmTimerRegBase</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Ac…">Timer</a> + </td> + <td>4.8.3.3</td> + </tr> + <tr> + <td>reset_reg.</td> + <td>ResetReg.Address</td> + <td>ResetRegAddress</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Cold</a> + and + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Warm</a> + resets + </td> + <td>4.3.3.6</td> + </tr> + <tr> + <td>reset_value</td> + <td>ResetValue</td> + <td>ResetValue</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Cold</a> + and + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/CorebootPayloadPkg/Library/Re…">Warm</a> + resets + </td> + <td>4.8.3.6</td> </tr> - <tr><td>Pm1aCntBlk</td><td>pm1a_cnt_blk</td></tr> - <tr><td>PmTmrBlk</td><td>pm_tmr_blk</td></tr> - <tr><td>ResetReg.Address</td><td>reset_reg.</td></tr> - <tr><td>ResetValue</td><td>reset_value</td></tr> - <tr><td>Pm1aEvtBlk</td><td>pm1a_evt_blk</td></tr> - <tr><td>Gpe0Blk</td><td>gpe0_blk</td></tr> - <tr><td>Gpe0BlkLen</td><td>gpe0_blk_len</td></tr> </table> <p> The EDK2 data structure is defined in @@ -603,6 +665,6 @@ Use the following steps to debug the call to TempRamInit: <hr> -<p>Modified: 20 February 2016</p> +<p>Modified: 28 February 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index 5a622a9..61d14c8 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -30,6 +30,7 @@ <h1>Documentation</h1> <ul> + <li><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI 6.0 Specification</a></li> <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3…">Software Developer Manual</a></li> <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-speci…">V1.1</a></li> @@ -37,6 +38,6 @@ <hr> -<p>Modified: 31 January 2016</p> +<p>Modified: 28 February 2016</p> </body> </html> \ No newline at end of file

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Patch set updated for coreboot: soc/intel/quark: Initialize some of the FADT base registers
by Leroy P Leahy 28 Feb '16

28 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13764 -gerrit commit b22e4235747efaaf3be566b056fc8e2b4b8e5e42 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 21 16:04:53 2016 -0800 soc/intel/quark: Initialize some of the FADT base registers Initialize the base addresses for: * Power management control * Power management status * Reset * Power management timer * General-Purpose Event 0 Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when: * Register address are properly displayed by the payload * "reset -c" performs a reset and reboots the system * "reset -w" performs a reset and reboots the system * "reset -s" performs a reset and turns off the power Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/Makefile.inc | 1 + src/soc/intel/quark/acpi.c | 72 +++++++++++++++++++++++++++++++++ src/soc/intel/quark/include/soc/iomap.h | 6 +++ src/soc/intel/quark/pmc.c | 51 +++++++++++++++++++++++ 4 files changed, 130 insertions(+) diff --git a/src/soc/intel/quark/Makefile.inc b/src/soc/intel/quark/Makefile.inc index c89a97e..d8650fa 100644 --- a/src/soc/intel/quark/Makefile.inc +++ b/src/soc/intel/quark/Makefile.inc @@ -26,6 +26,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += chip.c ramstage-y += memmap.c ramstage-y += northcluster.c +ramstage-y += pmc.c ramstage-y += tsc_freq.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart_common.c ramstage-$(CONFIG_ENABLE_BUILTIN_HSUART1) += uart.c diff --git a/src/soc/intel/quark/acpi.c b/src/soc/intel/quark/acpi.c index f43a74c..90adc34 100644 --- a/src/soc/intel/quark/acpi.c +++ b/src/soc/intel/quark/acpi.c @@ -16,6 +16,7 @@ */ #include <soc/acpi.h> +#include <soc/ramstage.h> unsigned long acpi_fill_madt(unsigned long current) { @@ -30,4 +31,75 @@ unsigned long acpi_fill_mcfg(unsigned long current) void acpi_fill_in_fadt(acpi_fadt_t *fadt) { + struct device *dev = dev_find_slot(0, + PCI_DEVFN(PCI_DEVICE_NUMBER_QNC_LPC, + PCI_FUNCTION_NUMBER_QNC_LPC)); + uint32_t gpe0_base = pci_read_config32(dev, R_QNC_LPC_GPE0BLK) + & B_QNC_LPC_GPE0BLK_MASK; + uint32_t pmbase = pci_read_config32(dev, R_QNC_LPC_PM1BLK) + & B_QNC_LPC_PM1BLK_MASK; + + fadt->flags = ACPI_FADT_RESET_REGISTER | ACPI_FADT_PLATFORM_CLOCK; + + /* PM1 Status: ACPI 4.8.3.1.1 */ + fadt->pm1a_evt_blk = pmbase + R_QNC_PM1BLK_PM1S; + fadt->pm1_evt_len = 2; + + fadt->x_pm1a_evt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_evt_blk.bit_width = fadt->pm1_evt_len * 8; + fadt->x_pm1a_evt_blk.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_evt_blk.addrl = pmbase + R_QNC_PM1BLK_PM1S; + fadt->x_pm1a_evt_blk.addrh = 0x0; + + /* PM1 Control: ACPI 4.8.3.2.1 */ + fadt->pm1a_cnt_blk = pmbase + R_QNC_PM1BLK_PM1C; + fadt->pm1_cnt_len = 2; + + fadt->x_pm1a_cnt_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm1a_cnt_blk.bit_width = fadt->pm1_cnt_len * 8; + fadt->x_pm1a_cnt_blk.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_WORD_ACCESS; + fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk; + fadt->x_pm1a_cnt_blk.addrh = 0x0; + + /* PM Timer: ACPI 4.8.3.3 */ + fadt->pm_tmr_blk = pmbase + R_QNC_PM1BLK_PM1T; + fadt->pm_tmr_len = 4; + + fadt->x_pm_tmr_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_pm_tmr_blk.bit_width = fadt->pm_tmr_len * 8; + fadt->x_pm_tmr_blk.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_pm_tmr_blk.addrl = fadt->pm_tmr_blk; + fadt->x_pm_tmr_blk.addrh = 0x0; + + /* Reset Register: ACPI 4.8.3.6, 5.2.3.2 */ + fadt->reset_reg.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->reset_reg.bit_width = 8; + fadt->reset_reg.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_BYTE_ACCESS; + fadt->reset_reg.addrl = 0xcf9; + fadt->reset_reg.addrh = 0; + + /* Soft/Warm Reset */ + fadt->reset_value = 6; + + /* General-Purpose Event 0 Registers: ACPI 4.8.4.1 */ + fadt->gpe0_blk = gpe0_base; + fadt->gpe0_blk_len = 4 * 2; + + fadt->x_gpe0_blk.space_id = ACPI_ADDRESS_SPACE_IO; + fadt->x_gpe0_blk.bit_width = fadt->gpe0_blk_len * 8; + fadt->x_gpe0_blk.bit_offset = 0; + fadt->reset_reg.access_size = ACPI_ACCESS_SIZE_DWORD_ACCESS; + fadt->x_gpe0_blk.addrl = fadt->gpe0_blk; + fadt->x_gpe0_blk.addrh = 0; + + /* Display the base registers */ + printk(BIOS_DEBUG, "FADT:\n"); + printk(BIOS_DEBUG, " 0x%08x: GPE0_BASE\n", gpe0_base); + printk(BIOS_DEBUG, " 0x%08x: PMBASE\n", pmbase); + printk(BIOS_DEBUG, " 0x%08x: RESET\n", fadt->reset_reg.addrl); + } diff --git a/src/soc/intel/quark/include/soc/iomap.h b/src/soc/intel/quark/include/soc/iomap.h index f033dcb..31cf604 100644 --- a/src/soc/intel/quark/include/soc/iomap.h +++ b/src/soc/intel/quark/include/soc/iomap.h @@ -24,4 +24,10 @@ /* UART MMIO */ #define UART_BASE_ADDRESS CONFIG_TTYS0_BASE +/* + * I/O port address space + */ +#define ACPI_BASE_ADDRESS 0x1000 +#define ACPI_BASE_SIZE 0x100 + #endif /* _QUARK_IOMAP_H_ */ diff --git a/src/soc/intel/quark/pmc.c b/src/soc/intel/quark/pmc.c new file mode 100644 index 0000000..fbed935 --- /dev/null +++ b/src/soc/intel/quark/pmc.c @@ -0,0 +1,51 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015-2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/iomap.h> +#include <soc/pci_devs.h> +#include <soc/pm.h> +#include <soc/ramstage.h> + +static void pmc_read_resources(device_t dev) +{ + unsigned index = 0; + struct resource *res; + + /* Get the normal PCI resources of this device. */ + pci_dev_read_resources(dev); + + /* PMBASE */ + res = new_resource(dev, index++); + res->base = ACPI_BASE_ADDRESS; + res->size = ACPI_BASE_SIZE; + res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; +} + +static struct device_operations device_ops = { + .read_resources = &pmc_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .scan_bus = &scan_lpc_bus, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = QUARK_V_LPC_DEVICE_ID_0, +};

1 0

Patch set updated for coreboot: northbridge/intel: add missing #include guards
by Iru Cai 28 Feb '16

28 Feb '16

Iru Cai (mytbk920423(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13775 -gerrit commit 8dd7d82ad68311988b303bdfc8f861008cde14a6 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Wed Feb 24 15:03:58 2016 +0800 northbridge/intel: add missing #include guards I first found the missing of #include guards when I tried to include both sandybridge/gma.h and sandybridge/sandybridge.h, but sandybridge.h includes gma.h in it and gives a compile error. Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> --- src/northbridge/intel/e7501/e7501.h | 5 +++++ src/northbridge/intel/e7505/e7505.h | 5 +++++ src/northbridge/intel/fsp_sandybridge/chip.h | 5 +++++ src/northbridge/intel/fsp_sandybridge/gma.h | 5 +++++ src/northbridge/intel/haswell/chip.h | 5 +++++ src/northbridge/intel/haswell/gma.h | 5 +++++ src/northbridge/intel/i3100/chip.h | 5 +++++ src/northbridge/intel/i440bx/i440bx.h | 5 +++++ src/northbridge/intel/i82830/i82830.h | 5 +++++ src/northbridge/intel/i855/i855.h | 5 +++++ src/northbridge/intel/i945/chip.h | 5 +++++ src/northbridge/intel/nehalem/chip.h | 5 +++++ src/northbridge/intel/pineview/chip.h | 5 +++++ src/northbridge/intel/sandybridge/chip.h | 5 +++++ src/northbridge/intel/sandybridge/gma.h | 5 +++++ src/northbridge/intel/sch/nvs.h | 5 +++++ 16 files changed, 80 insertions(+) diff --git a/src/northbridge/intel/e7501/e7501.h b/src/northbridge/intel/e7501/e7501.h index a9690d8..dca4194 100644 --- a/src/northbridge/intel/e7501/e7501.h +++ b/src/northbridge/intel/e7501/e7501.h @@ -18,6 +18,9 @@ * e7501.h: PCI configuration space for the Intel E7501 memory controller */ +#ifndef E7501_H +#define E7501_H + /************ D0:F0 ************/ // Register offsets #define MAYBE_SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? (if similar to 855PM) */ @@ -73,3 +76,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* E7501_H */ diff --git a/src/northbridge/intel/e7505/e7505.h b/src/northbridge/intel/e7505/e7505.h index 525dce8..d0be736 100644 --- a/src/northbridge/intel/e7505/e7505.h +++ b/src/northbridge/intel/e7505/e7505.h @@ -18,6 +18,9 @@ * e7505.h: PCI configuration space for the Intel E7501 memory controller */ +#ifndef E7505_H +#define E7505_H + /************ D0:F0 ************/ // Register offsets #define SMRBASE 0x14 /* System Memory RCOMP Base Address Register, 32 bit? */ @@ -78,3 +81,5 @@ #define NERR_GLOBAL 0x44 /* Next global error register, 32 bits */ #define DRAM_FERR 0x80 /* DRAM first error register, 8 bits */ #define DRAM_NERR 0x82 /* DRAM next error register, 8 bits */ + +#endif /* E7505_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/chip.h b/src/northbridge/intel/fsp_sandybridge/chip.h index e6f3a54..eb86b83 100644 --- a/src/northbridge/intel/fsp_sandybridge/chip.h +++ b/src/northbridge/intel/fsp_sandybridge/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_CHIP_H +#define NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -39,3 +42,5 @@ struct northbridge_intel_fsp_sandybridge_config { struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/fsp_sandybridge/gma.h b/src/northbridge/intel/fsp_sandybridge/gma.h index baab695..5693e0c 100644 --- a/src/northbridge/intel/fsp_sandybridge/gma.h +++ b/src/northbridge/intel/fsp_sandybridge/gma.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H +#define NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H + /* mailbox 0: header */ typedef struct { u8 signature[16]; @@ -161,3 +164,5 @@ typedef struct { } __attribute__((packed)) optionrom_vbt_t; #define VBT_SIGNATURE 0x54425624 + +#endif /* NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/haswell/chip.h b/src/northbridge/intel/haswell/chip.h index 67ba074..098bc33 100644 --- a/src/northbridge/intel/haswell/chip.h +++ b/src/northbridge/intel/haswell/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_HASWELL_CHIP_H +#define NORTHBRIDGE_INTEL_HASWELL_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -41,3 +44,5 @@ struct northbridge_intel_haswell_config { }; extern struct chip_operations northbridge_intel_haswell_ops; + +#endif /* NORTHBRIDGE_INTEL_HASWELL_CHIP_H */ diff --git a/src/northbridge/intel/haswell/gma.h b/src/northbridge/intel/haswell/gma.h index baab695..5adab57 100644 --- a/src/northbridge/intel/haswell/gma.h +++ b/src/northbridge/intel/haswell/gma.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_HASWELL_GMA_H +#define NORTHBRIDGE_INTEL_HASWELL_GMA_H + /* mailbox 0: header */ typedef struct { u8 signature[16]; @@ -161,3 +164,5 @@ typedef struct { } __attribute__((packed)) optionrom_vbt_t; #define VBT_SIGNATURE 0x54425624 + +#endif /* NORTHBRIDGE_INTEL_HASWELL_GMA_H */ diff --git a/src/northbridge/intel/i3100/chip.h b/src/northbridge/intel/i3100/chip.h index aa7407a..5da7431 100644 --- a/src/northbridge/intel/i3100/chip.h +++ b/src/northbridge/intel/i3100/chip.h @@ -13,8 +13,13 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_I3100_CHIP_H +#define NORTHBRIDGE_INTEL_I3100_CHIP_H + struct northbridge_intel_i3100_config { /* Interrupt line connect */ u16 intrline; }; + +#endif /* NORTHBRIDGE_INTEL_I3100_CHIP_H */ diff --git a/src/northbridge/intel/i440bx/i440bx.h b/src/northbridge/intel/i440bx/i440bx.h index 44dca2f..4724719 100644 --- a/src/northbridge/intel/i440bx/i440bx.h +++ b/src/northbridge/intel/i440bx/i440bx.h @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_I440BX_I440BX_H +#define NORTHBRIDGE_INTEL_I440BX_I440BX_H + /* * Datasheet: * - Name: Intel 440BX AGPset: 82443BX Host Bridge/Controller @@ -82,3 +85,5 @@ #define DWTC 0xe0 /* DRAM Write Thermal Throttling Control (0x000..000). */ #define DRTC 0xe8 /* DRAM Read Thermal Throttling Control (0x000..000). */ #define BUFFC 0xf0 /* Buffer Control Register (0x0000). */ + +#endif /* NORTHBRIDGE_INTEL_I440BX_I440BX_H */ diff --git a/src/northbridge/intel/i82830/i82830.h b/src/northbridge/intel/i82830/i82830.h index e1e2862..74520b1 100644 --- a/src/northbridge/intel/i82830/i82830.h +++ b/src/northbridge/intel/i82830/i82830.h @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_I82830_I82830_H +#define NORTHBRIDGE_INTEL_I82830_I82830_H + #define RRBAR 0x48 /* Register Range Base Address (0x00000000) */ #define GCC0 0x50 /* GMCH Control #0 (0xa072) */ #define GCC1 0x52 /* GMCH Control #1 (0x0000) */ @@ -45,3 +48,5 @@ #define APBASE 0x10 /* Aperture Base Configuration (0x00000008) */ #define APSIZE 0xb4 /* Apterture Size (0x00) */ #define ATTBASE 0xb8 /* Aperture Translation Table Base (0x00000000) */ + +#endif /* NORTHBRIDGE_INTEL_I82830_I82830_H */ diff --git a/src/northbridge/intel/i855/i855.h b/src/northbridge/intel/i855/i855.h index 10c7873..467875f 100644 --- a/src/northbridge/intel/i855/i855.h +++ b/src/northbridge/intel/i855/i855.h @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_I855_I855_H +#define NORTHBRIDGE_INTEL_I855_I855_H + /* Host-Hub Interface Bridge */ #define GMC 0x50 /* GMCH Misc. Control (0x0000) */ #define GGC 0x52 /* GMCH Graphics Control (0x0030) */ @@ -70,3 +73,5 @@ #define DRT_TRAS_MIN_7 (1 << 9) #define DRT_TRAS_MIN_6 (2 << 9) #define DRT_TRAS_MIN_5 (3 << 9) + +#endif /* NORTHBRIDGE_INTEL_I855_I855_H */ diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 52925ff..446af72 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -1,3 +1,6 @@ +#ifndef NORTHBRIDGE_INTEL_I945_CHIP_H +#define NORTHBRIDGE_INTEL_I945_CHIP_H + #include <drivers/intel/gma/i915.h> struct northbridge_intel_i945_config { @@ -6,3 +9,5 @@ struct northbridge_intel_i945_config { int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/nehalem/chip.h b/src/northbridge/intel/nehalem/chip.h index 5598022..caf9819 100644 --- a/src/northbridge/intel/nehalem/chip.h +++ b/src/northbridge/intel/nehalem/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_NEHALEM_CHIP_H +#define NORTHBRIDGE_INTEL_NEHALEM_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -39,3 +42,5 @@ struct northbridge_intel_nehalem_config { struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_NEHALEM_CHIP_H */ diff --git a/src/northbridge/intel/pineview/chip.h b/src/northbridge/intel/pineview/chip.h index aabb05e..a63db78 100644 --- a/src/northbridge/intel/pineview/chip.h +++ b/src/northbridge/intel/pineview/chip.h @@ -1,3 +1,6 @@ +#ifndef NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H +#define NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H + #include <drivers/intel/gma/i915.h> struct northbridge_intel_pineview_config { @@ -7,3 +10,5 @@ struct northbridge_intel_pineview_config { int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_PINEVIEW_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/chip.h b/src/northbridge/intel/sandybridge/chip.h index b04f95e..5effc0d 100644 --- a/src/northbridge/intel/sandybridge/chip.h +++ b/src/northbridge/intel/sandybridge/chip.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H +#define NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H + #include <drivers/intel/gma/i915.h> /* @@ -45,3 +48,5 @@ struct northbridge_intel_sandybridge_config { struct i915_gpu_controller_info gfx; }; + +#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_CHIP_H */ diff --git a/src/northbridge/intel/sandybridge/gma.h b/src/northbridge/intel/sandybridge/gma.h index 8381863..0832468 100644 --- a/src/northbridge/intel/sandybridge/gma.h +++ b/src/northbridge/intel/sandybridge/gma.h @@ -13,6 +13,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H +#define NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H + /* mailbox 0: header */ typedef struct { u8 signature[16]; @@ -114,3 +117,5 @@ struct i915_gpu_controller_info; int i915lightup_sandy(const struct i915_gpu_controller_info *info, u32 physbase, u16 pio, u8 *mmio, u32 lfb); + +#endif /* NORTHBRIDGE_INTEL_SANDYBRIDGE_GMA_H */ diff --git a/src/northbridge/intel/sch/nvs.h b/src/northbridge/intel/sch/nvs.h index d147b9c..b167f26 100644 --- a/src/northbridge/intel/sch/nvs.h +++ b/src/northbridge/intel/sch/nvs.h @@ -14,6 +14,9 @@ * GNU General Public License for more details. */ +#ifndef NORTHBRIDGE_INTEL_SCH_NVS_H +#define NORTHBRIDGE_INTEL_SCH_NVS_H + typedef struct { u16 osys; u8 smif; @@ -100,3 +103,5 @@ typedef struct { u8 idet; u8 dock; } global_nvs_t; + +#endif /* NORTHBRIDGE_INTEL_SCH_NVS_H */

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coreboot-gerrit February 2016