coreboot-gerrit February 2016

coreboot-gerrit@coreboot.org

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1305 discussions

Patch merged into coreboot/master: soc/intel/quark: Reserve non-MMIO space
by gerrit＠coreboot.org 29 Feb '16

29 Feb '16

the following patch was just integrated into master: commit 79f065a79d4dd7dbfd2844eab5e5ccc68f3ba523 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 28 11:30:17 2016 -0800 soc/intel/quark: Reserve non-MMIO space Adjust the memory map to allocate MMIO from non-memory addresses. TEST=None Change-Id: Icb6863665c466e8609af73eb9338165c7d6f46bf Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13856 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13856 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/quark: Initialize some of the FADT base registers
by gerrit＠coreboot.org 29 Feb '16

29 Feb '16

the following patch was just integrated into master: commit a6de5470fa757f7e9c40d417e7f40551ccdba99c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 21 16:04:53 2016 -0800 soc/intel/quark: Initialize some of the FADT base registers Initialize the base addresses for: * Power management control * Power management status * Reset * Power management timer * General-Purpose Event 0 Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when: * Register address are properly displayed by the payload * "reset -c" performs a reset and reboots the system * "reset -w" performs a reset and reboots the system * "reset -s" performs a reset and turns off the power Change-Id: I9d043f4906a067b2477650140210cfae4a7f8b79 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13764 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13764 for details. -gerrit

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Patch merged into coreboot/master: Documentation/Intel: More CorebootPayloadPkg documentation
by gerrit＠coreboot.org 29 Feb '16

29 Feb '16

the following patch was just integrated into master: commit 4ee073d4769a966e1da0e61575e1b1f9c6ad820a Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 28 06:22:47 2016 -0800 Documentation/Intel: More CorebootPayloadPkg documentation Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13851 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13851 for details. -gerrit

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Patch set updated for coreboot: Documentation/Intel: More CorebootPayloadPkg documentation
by Leroy P Leahy 29 Feb '16

29 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13851 -gerrit commit 60a4ecf8e16129bb5ef7d8609ddf59eda7359446 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 28 06:22:47 2016 -0800 Documentation/Intel: More CorebootPayloadPkg documentation Add more documentation on the features that the EDK-II CorebootPayloadPkg is using. Add 8254 and 8259 documentation links. Add EDK-II documentation links. TEST=Boot CorebootPayloadPkg to shell prompt Change-Id: I66df1be0ba908b51b5ddb44a8671b2d7bdb46493 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- Documentation/Intel/SoC/quark.html | 4 +-- Documentation/Intel/SoC/soc.html | 54 +++++++++++++++++++++++++++++++++++- Documentation/Intel/development.html | 13 ++++++++- Documentation/Intel/index.html | 16 ++++++++++- 4 files changed, 82 insertions(+), 5 deletions(-) diff --git a/Documentation/Intel/SoC/quark.html b/Documentation/Intel/SoC/quark.html index ea704a9..5fe3f5c 100644 --- a/Documentation/Intel/SoC/quark.html +++ b/Documentation/Intel/SoC/quark.html @@ -47,7 +47,7 @@ <hr> -<h1>Quark™ EDK2 CorebootPayloadPkg</h1> +<h1><a name="CorebootPayloadPkg">Quark™ EDK2 CorebootPayloadPkg</a></h1> <p> Build Instructions: </p> @@ -214,6 +214,6 @@ Documentation: <hr> -<p>Modified: 20 February 2016</p> +<p>Modified: 24 February 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/SoC/soc.html b/Documentation/Intel/SoC/soc.html index 5a0a442..2380cdf 100644 --- a/Documentation/Intel/SoC/soc.html +++ b/Documentation/Intel/SoC/soc.html @@ -33,6 +33,7 @@ </ol> </li> <li><a href="#AcpiTables">ACPI Tables</a></li> + <li><a href="#LegacyHardware">Legacy Hardware</a></li> </ol> @@ -560,7 +561,7 @@ Use the following steps to debug the call to TempRamInit: <hr> <h1><a name="AcpiTables">ACPI Tables</a></h1> <p> - One of the payloads that needs ACPI tables is the EDK2 CorebootPayloadPkg. + One of the payloads that needs ACPI tables is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. </p> <h2>FADT</h2> @@ -664,6 +665,57 @@ Use the following steps to debug the call to TempRamInit: </ol> + +<hr> +<h1><a name="LegacyHardware">Legacy Hardware</a></h1> +<p> + One of the payloads that needs legacy hardare is the EDK2 <a target="_blank" href="quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a>. +</p> + +<table border="1"> + <tr bgcolor="c0ffc0"> + <th>Peripheral</th> + <th>Use</th> + <th>8259 Interrupt Vector</th> + <th>IDT Base Offset</th> + <th>Interrupt Handler</th> + </tr> + <tr> + <td> + <a target="_blank" href="http://www.scs.stanford.edu/10wi-cs140/pintos/specs/8254.pdf">8254</a> + Programmable Interval Timer + </td> + <td> + EDK2: PcAtChipsetPkg/8254TimerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/T…">Timer.c</a> + </td> + <td>0</td> + <td>0x340</td> + <td> + <a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8254TimerDxe/T…">TimerInterruptHandler</a> + </td> + </tr> + <tr> + <td> + <a target="_blank" href="https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&cad=rja&uac…">8259</a> + Programmable Interrupt Controller + </td> + <td> + EDK2: PcAtChipsetPkg/8259InterruptControllerDxe/<a target="_blank" href="https://github.com/tianocore/edk2/blob/master/PcAtChipsetPkg/8259InterruptC…">8259.c</a> + </td> + <td> + Master interrupts: 0, 2 - 7<br> + Slave interrupts: 8 - 15<br> + Interrupt vector 1 is never generated, the cascaded input generates interrupts 8 - 15 + </td> + <td> + Master: 0x340, 0x350 - 0x378<br> + Slave: 0x380 - 0x3b8<br> + Interrupt descriptors are 8 bytes each + </td> + <td> </td> + </tr> +</table> + <hr> <p>Modified: 28 February 2016</p> </body> diff --git a/Documentation/Intel/development.html b/Documentation/Intel/development.html index 74a476f..7b82321 100644 --- a/Documentation/Intel/development.html +++ b/Documentation/Intel/development.html @@ -125,6 +125,7 @@ <li>Payload and OS Features: <ul> <li><a target="_blank" href="SoC/soc.html#AcpiTables">ACPI Tables</a></li> + <li><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</li> </ul> </li> </ul> @@ -142,6 +143,16 @@ <th>Testing</th> </tr> <tr> + <td>8254 Programmable Interval Timer</td> + <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> + <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> + </tr> + <tr> + <td>8259 Programmable Interrupt Controller</td> + <td><a target="_blank" href="SoC/soc.html#LegacyHardware">Legacy hardware</a> support</td> + <td><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> gets to shell prompt</td> + </tr> + <tr> <td>Cache-as-RAM</td> <td> <a target="_blank" href="SoC/soc.html#TempRamInit">Find</a> @@ -335,6 +346,6 @@ <hr> -<p>Modified: 20 February 2016</p> +<p>Modified: 24 February 2016</p> </body> </html> \ No newline at end of file diff --git a/Documentation/Intel/index.html b/Documentation/Intel/index.html index 61d14c8..4d508bf 100644 --- a/Documentation/Intel/index.html +++ b/Documentation/Intel/index.html @@ -21,6 +21,7 @@ <h1>x86 coreboot Development</h1> <ul> + <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> <li><a target="_blank" href="development.html">Overall</a> development</li> <li><a target="_blank" href="fsp1_1.html">FSP 1.1</a> integration </li> @@ -28,10 +29,23 @@ <li><a target="_blank" href="Board/board.html">Board</a> support</li> </ul> +<h1>Payload Development</h1> +<ul> + <li><a target="_blank" href="SoC/quark.html#CorebootPayloadPkg">CorebootPayloadPkg</a> + <ul> + <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK-II-Development-Pr…">EDK II Development Process</a></li> + <li>EDK II <a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/EDK%20II%20White%20pa…">White Papers</a></li> + <li><a target="_blank" href="https://github.com/tianocore/tianocore.github.io/wiki/SourceForge-to-Github…">SourceForge to Github Quick Start</a></li> + <li>UEFI <a target="_blank" href="http://www.uefi.org/sites/default/files/resources/UEFI%20Spec%202_5_Errata_…">2.5 Errata A</a></li> + </ul> + </li> +</ul> + + + <h1>Documentation</h1> <ul> <li><a target="_blank" href="http://www.uefi.org/sites/default/files/resources/ACPI_6.0.pdf">ACPI 6.0 Specification</a></li> - <li>Get the <a target="_blank" href="https://www.coreboot.org/Git">coreboot source</li> <li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-3…">Software Developer Manual</a></li> <li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-speci…">V1.1</a></li> </ul>

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Patch merged into coreboot/master: Documentation/Intel: Add ACPI link and more FADT documentation
by gerrit＠coreboot.org 29 Feb '16

29 Feb '16

the following patch was just integrated into master: commit ca20b5fa6fbb81180da961f2ac0cb27a3bad583d Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 21 16:13:16 2016 -0800 Documentation/Intel: Add ACPI link and more FADT documentation Add a link to the ACPI specification. Update the FADT table to better describe the use and ACPI specification reference for the various fields. TEST=None Change-Id: I77cd925800d71398be6d677de48874099ea26479 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> Reviewed-on: https://review.coreboot.org/13765 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/13765 for details. -gerrit

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Patch set updated for coreboot: mainboard/intel/galileo: Enable USB
by Leroy P Leahy 29 Feb '16

29 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13857 -gerrit commit 06d96421b6c8cdb8bd3653003c044020d4726b78 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 28 11:35:29 2016 -0800 mainboard/intel/galileo: Enable USB Enable the EHCI and OHCI controllers. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when at the UEFI shell prompt: * After issuing: * "connect -r" * "map -r" * The "dir" command displays the contents of the USB flash drive * A USB keyboard can issue shell commands * The "drivers" command shows an EHCI and OHCI connection Change-Id: Iad9abced98d9b645e8b12fa0845c97260cf62a72 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/devicetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 1b72ff0..6b27758 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -22,8 +22,8 @@ chip soc/intel/quark device pci 14.0 off end # 8086 08A7 - SD/SDIO/eMMC controller device pci 14.1 off end # 8086 0936 - HSUART 0 device pci 14.2 off end # 8086 0939 - USB 2.0 Device port - device pci 14.3 off end # 8086 0939 - USB EHCI Host controller - device pci 14.4 off end # 8086 093A - USB OHCI Host controller + device pci 14.3 on end # 8086 0939 - USB EHCI Host controller + device pci 14.4 on end # 8086 093A - USB OHCI Host controller device pci 14.5 on end # 8086 0936 - HSUART 1 device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0 device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1

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New patch to review for coreboot: mainboard/intel/galileo: Enable USB
by Leroy P Leahy 28 Feb '16

28 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13857 -gerrit commit fa3facd23b5d2ebf699f1fcc4eebf1f08db3b370 Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 28 11:35:29 2016 -0800 mainboard/intel/galileo: Enable USB Enable the EHCI and OHCI controllers. Testing on Galileo: * Edit the src/mainboard/intel/galileo/Makefile.inc file: * Add "select ADD_FSP_PDAT_FILE" * Add "select ADD_FSP_RAW_BIN" * Add "select ADD_RMU_FILE" * Place the FSP.bin file in the location specified by CONFIG_FSP_FILE * Place the pdat.bin files in the location specified by CONFIG_FSP_PDAT_FILE * Place the rmu.bin file in the location specified by CONFIG_RMU_FILE * Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate UEFIPAYLOAD.fd * Edit .config file and add the following lines: * CONFIG_PAYLOAD_ELF=y * CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd" * Testing successful when: * At shell, directory of USB flash drive is successful * Shell commands can be issued using a USB keyboard * "drivers" command shows an EHCI and OHCI connection Change-Id: Iad9abced98d9b645e8b12fa0845c97260cf62a72 Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/mainboard/intel/galileo/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/intel/galileo/devicetree.cb b/src/mainboard/intel/galileo/devicetree.cb index 1b72ff0..93abdf3 100644 --- a/src/mainboard/intel/galileo/devicetree.cb +++ b/src/mainboard/intel/galileo/devicetree.cb @@ -24,6 +24,8 @@ chip soc/intel/quark device pci 14.2 off end # 8086 0939 - USB 2.0 Device port device pci 14.3 off end # 8086 0939 - USB EHCI Host controller device pci 14.4 off end # 8086 093A - USB OHCI Host controller + device pci 14.3 on end # 8086 0939 - USB EHCI Host controller + device pci 14.4 on end # 8086 093A - USB OHCI Host controller device pci 14.5 on end # 8086 0936 - HSUART 1 device pci 14.6 off end # 8086 0937 - 10/100 Ethernet MAC 0 device pci 14.7 off end # 8086 0937 - 10/100 Ethernet MAC 1

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New patch to review for coreboot: soc/intel/quark: Reserve non-MMIO space
by Leroy P Leahy 28 Feb '16

28 Feb '16

Leroy P Leahy (leroy.p.leahy(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/13856 -gerrit commit b059850f22028961ffb529a35210c49b67ad996c Author: Lee Leahy <leroy.p.leahy(a)intel.com> Date: Sun Feb 28 11:30:17 2016 -0800 soc/intel/quark: Reserve non-MMIO space Adjust the memory map to allocate MMIO from non-memory addresses. TEST=None Change-Id: Icb6863665c466e8609af73eb9338165c7d6f46bf Signed-off-by: Lee Leahy <leroy.p.leahy(a)intel.com> --- src/soc/intel/quark/northcluster.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/quark/northcluster.c b/src/soc/intel/quark/northcluster.c index 90ea256..b52c3b7 100644 --- a/src/soc/intel/quark/northcluster.c +++ b/src/soc/intel/quark/northcluster.c @@ -59,7 +59,13 @@ static void nc_read_resources(device_t dev) size_k = (unsigned long)cbmem_top() - base_k; ram_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k)); - /* cbmem_top -> 4GiB is mmio. */ + /* cbmem_top -> 0xc0000000 - reserved */ + base_k += size_k; + size_k = 0xc0000000 - base_k; + reserved_ram_resource(dev, index++, RES_IN_KIB(base_k), + RES_IN_KIB(size_k)); + + /* 0xc0000000 -> 4GiB is mmio. */ base_k += size_k; size_k = 0x100000000ull - base_k; mmio_resource(dev, index++, RES_IN_KIB(base_k), RES_IN_KIB(size_k));

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Patch merged into coreboot/master: coreinfo: quote $(AS) and $(CC) in $(LPAS) and $(LPCC)
by gerrit＠coreboot.org 28 Feb '16

28 Feb '16

the following patch was just integrated into master: commit 283fd8e653a8ef8631403fd27a52115041385804 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Sat Feb 27 11:47:06 2016 +0800 coreinfo: quote $(AS) and $(CC) in $(LPAS) and $(LPCC) Without this change it'll get a build error with crossgcc-x64 because $(AS) is "util/crossgcc/xgcc/bin/x86_64-elf-as --32", and running $(LPAS) (i.e. AS=$(AS) lpas) will run "--32" instead of "x86_64-elf-as". Change-Id: I95e5630cb1d4f1ce81a8ca8a7bf338450b325f02 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/13845 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/13845 for details. -gerrit

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Patch merged into coreboot/master: northbridge/intel: add missing #include guards
by gerrit＠coreboot.org 28 Feb '16

28 Feb '16

the following patch was just integrated into master: commit d7ee9dda708321f80161695714737b0f974509d3 Author: Iru Cai <mytbk920423(a)gmail.com> Date: Wed Feb 24 15:03:58 2016 +0800 northbridge/intel: add missing #include guards I first found the missing of #include guards when I tried to include both sandybridge/gma.h and sandybridge/sandybridge.h, but sandybridge.h includes gma.h in it and gives a compile error. Change-Id: I13fdb8014b82e6065be2064137b7ea10062deaca Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/13775 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro(a)das-labor.org> See https://review.coreboot.org/13775 for details. -gerrit

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coreboot-gerrit February 2016