coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: util/cbfstool: Fix to build with latest llvm
by Patrick Georgi 01 Dec '16

01 Dec '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17568 -gerrit commit 415a5167efde1881c93f543bc7e6f564a11bf606 Author: Manoj Gupta <manojgupta(a)google.com> Date: Mon Nov 14 11:19:30 2016 -0800 util/cbfstool: Fix to build with latest llvm cbfs-payload-linux.c:255:43: note: add parentheses around left hand side expression to silence this warning if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags & 1)) { BUG=chromium:665657 TEST=coreboot-utils builds Change-Id: I025c784330885cce8ae43c44f9d938394af30ed5 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 35c4935f2a89c3d3b45213372bcf0474a60eda43 Original-Change-Id: I8758e7d158ca32e87107797f2a33b9d9a0e4676f Original-Reviewed-on: https://chromium-review.googlesource.com/411335 Original-Commit-Ready: Manoj Gupta <manojgupta(a)chromium.org> Original-Tested-by: Manoj Gupta <manojgupta(a)chromium.org> Original-Reviewed-by: Mike Frysinger <vapier(a)chromium.org> --- util/cbfstool/cbfs-payload-linux.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/cbfstool/cbfs-payload-linux.c b/util/cbfstool/cbfs-payload-linux.c index afb0f3a..ac7e729 100644 --- a/util/cbfstool/cbfs-payload-linux.c +++ b/util/cbfstool/cbfs-payload-linux.c @@ -252,7 +252,7 @@ int parse_bzImage_to_payload(const struct buffer *input, } unsigned long kernel_base = 0x100000; - if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags & 1)) { + if ((hdr->protocol_version >= 0x200) && (!hdr->loadflags)) { kernel_base = 0x1000; /* zImage kernel */ } /* kernel prefers an address, so listen */

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New patch to review for coreboot: intel/nehalem: Use romstage_handoff for S3
by Kyösti Mälkki 01 Dec '16

01 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17676 -gerrit commit 3911eb3dafdb87cf9e5f1d8d4ab8b35fb3ba4228 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 25 11:40:00 2016 +0300 intel/nehalem: Use romstage_handoff for S3 Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/x201/mainboard.c | 5 ++--- src/mainboard/lenovo/x201/romstage.c | 15 +++------------ src/mainboard/packardbell/ms2290/romstage.c | 15 ++------------- src/northbridge/intel/nehalem/nehalem.h | 4 ---- src/northbridge/intel/nehalem/northbridge.c | 21 --------------------- 5 files changed, 7 insertions(+), 53 deletions(-) diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index 2f35c81..6c5f9c9 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -18,6 +18,7 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> @@ -90,7 +91,6 @@ static void fill_ssdt(device_t device) static void mainboard_enable(device_t dev) { - device_t dev0; u16 pmbase; dev->ops->init = mainboard_init; @@ -110,8 +110,7 @@ static void mainboard_enable(device_t dev) 0x10); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0, 0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_LFP, 2); diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 7b8d7f9..6856f5b 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -26,6 +26,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> @@ -277,19 +278,9 @@ void mainboard_romstage_entry(unsigned long bist) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume) { + quick_ram_check(); - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - quick_ram_check(); - } -#endif + romstage_handoff_init(s3resume); #if CONFIG_LPC_TPM init_tpm(s3resume); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 04c9513..1f28ea6 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -26,6 +26,7 @@ #include <cpu/x86/lapic.h> #include <lib.h> #include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> #include <console/console.h> #include <cpu/x86/bist.h> #include <cpu/intel/romstage.h> @@ -267,17 +268,5 @@ void mainboard_romstage_entry(unsigned long bist) outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04); } -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume) { - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); - } else { - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafebabe); - quick_ram_check(); - } -#endif + romstage_handoff_init(s3resume); } diff --git a/src/northbridge/intel/nehalem/nehalem.h b/src/northbridge/intel/nehalem/nehalem.h index f20ef2d..ee8dd00 100644 --- a/src/northbridge/intel/nehalem/nehalem.h +++ b/src/northbridge/intel/nehalem/nehalem.h @@ -222,10 +222,6 @@ enum { #define D0F0_TOLUD 0xb0 #define D0F0_SKPD 0xdc /* Scratchpad Data */ -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe - - #define D0F0_CAPID0 0xe0 #define TSEG 0xac /* TSEG base */ diff --git a/src/northbridge/intel/nehalem/northbridge.c b/src/northbridge/intel/nehalem/northbridge.c index 06c0a96..3a24b71 100644 --- a/src/northbridge/intel/nehalem/northbridge.c +++ b/src/northbridge/intel/nehalem/northbridge.c @@ -287,26 +287,6 @@ static void northbridge_init(struct device *dev) MCHBAR32(0x5500) = 0x00100001; } -static void northbridge_enable(device_t dev) -{ -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev, SKPAD)) { - case 0xcafebabe: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; - case 0xcafed00d: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; - } -#endif -} - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -316,7 +296,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .init = northbridge_init, - .enable = northbridge_enable, .acpi_fill_ssdt_generator = generate_cpu_entries, .scan_bus = 0, .ops_pci = &intel_pci_ops,

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New patch to review for coreboot: intel/i945: Use romstage_handoff for S3
by Kyösti Mälkki 01 Dec '16

01 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17675 -gerrit commit 4b1ac2da0a93aca27451628076c1f48814b43ceb Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 25 11:40:00 2016 +0300 intel/i945: Use romstage_handoff for S3 Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/t60/mainboard.c | 7 +++---- src/mainboard/lenovo/x60/mainboard.c | 7 +++---- src/northbridge/intel/i945/early_init.c | 12 ++---------- src/northbridge/intel/i945/northbridge.c | 23 ----------------------- src/southbridge/intel/i82801gx/i82801gx.h | 2 -- src/southbridge/intel/i82801gx/smi.c | 13 ++----------- 6 files changed, 10 insertions(+), 54 deletions(-) diff --git a/src/mainboard/lenovo/t60/mainboard.c b/src/mainboard/lenovo/t60/mainboard.c index 44fa402..d8256d2 100644 --- a/src/mainboard/lenovo/t60/mainboard.c +++ b/src/mainboard/lenovo/t60/mainboard.c @@ -17,12 +17,12 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> -#include <arch/io.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> #include <ec/lenovo/h8/h8.h> @@ -49,13 +49,12 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_init(device_t dev) { struct southbridge_intel_i82801gx_config *config; - device_t dev0, idedev; + device_t idedev; install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/mainboard/lenovo/x60/mainboard.c b/src/mainboard/lenovo/x60/mainboard.c index b1096d2..6661a5f 100644 --- a/src/mainboard/lenovo/x60/mainboard.c +++ b/src/mainboard/lenovo/x60/mainboard.c @@ -17,13 +17,13 @@ #include <console/console.h> #include <device/device.h> +#include <arch/acpi.h> #include <arch/io.h> #include <delay.h> #include <string.h> #include <device/pci_def.h> #include <device/pci_ops.h> #include <device/pci_ids.h> -#include <arch/io.h> #include <arch/interrupt.h> #include <ec/lenovo/pmh7/pmh7.h> #include <ec/acpi/ec.h> @@ -79,7 +79,7 @@ int get_cst_entries(acpi_cstate_t **entries) static void mainboard_init(device_t dev) { - device_t dev0, idedev, sdhci_dev; + device_t idedev, sdhci_dev; ec_clr_bit(0x03, 2); @@ -91,8 +91,7 @@ static void mainboard_init(device_t dev) install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, PANEL, 3); /* If we're resuming from suspend, blink suspend LED */ - dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - if (dev0 && pci_read_config32(dev0, SKPAD) == SKPAD_ACPI_S3_MAGIC) + if (acpi_is_wakeup_s3()) ec_write(0x0c, 0xc7); idedev = dev_find_slot(0, PCI_DEVFN(0x1f,1)); diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 8ebb422..377302a 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -21,6 +21,7 @@ #include <device/pci_def.h> #include <cbmem.h> #include <halt.h> +#include <romstage_handoff.h> #include <string.h> #include "i945.h" #include <pc80/mc146818rtc.h> @@ -197,7 +198,6 @@ static void i945_setup_bars(void) pci_write_config8(PCI_DEV(0, 0x00, 0), PAM5, 0x33); pci_write_config8(PCI_DEV(0, 0x00, 0), PAM6, 0x33); - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, SKPAD_NORMAL_BOOT_MAGIC); printk(BIOS_DEBUG, " done.\n"); /* Wait for MCH BAR to come up */ @@ -901,15 +901,7 @@ static void i945_prepare_resume(int s3resume) cbmem_was_initted = !cbmem_recovery(s3resume); - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume && cbmem_was_initted) { - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, - SKPAD_ACPI_S3_MAGIC); - } + romstage_handoff_init(cbmem_was_initted && s3resume); } void i945_late_initialization(int s3resume) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 5d18591..848bbaa 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -213,26 +213,6 @@ static void intel_set_subsystem(device_t dev, unsigned vendor, unsigned device) } } -#if CONFIG_HAVE_ACPI_RESUME -static void northbridge_init(struct device *dev) -{ - switch (pci_read_config32(dev, SKPAD)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; - } -} -#endif - static struct pci_operations intel_pci_ops = { .set_subsystem = intel_set_subsystem, }; @@ -242,9 +222,6 @@ static struct device_operations mc_ops = { .set_resources = mc_set_resources, .enable_resources = pci_dev_enable_resources, .acpi_fill_ssdt_generator = generate_cpu_entries, -#if CONFIG_HAVE_ACPI_RESUME - .init = northbridge_init, -#endif .scan_bus = 0, .ops_pci = &intel_pci_ops, }; diff --git a/src/southbridge/intel/i82801gx/i82801gx.h b/src/southbridge/intel/i82801gx/i82801gx.h index 7e8b988..d1441e8 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.h +++ b/src/southbridge/intel/i82801gx/i82801gx.h @@ -375,7 +375,5 @@ int southbridge_detect_s3_resume(void); #define SS_CNT 0x50 #define C3_RES 0x54 -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe #endif /* __ACPI__ */ #endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */ diff --git a/src/southbridge/intel/i82801gx/smi.c b/src/southbridge/intel/i82801gx/smi.c index 01fbbfb..b61e068 100644 --- a/src/southbridge/intel/i82801gx/smi.c +++ b/src/southbridge/intel/i82801gx/smi.c @@ -19,6 +19,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> @@ -315,16 +316,6 @@ static void smm_relocate(void) static int smm_handler_copied = 0; -static int is_wakeup(void) -{ - device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - - if (!dev0) - return 0; - - return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; -} - static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -338,7 +329,7 @@ static void smm_install(void) /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ - if (!is_wakeup()) { + if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);

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New patch to review for coreboot: intel/gm45: Use romstage_handoff for S3
by Kyösti Mälkki 01 Dec '16

01 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17674 -gerrit commit abb3d694d86b8d977a713e5752686c10cd34c1bf Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sat Jun 25 11:40:00 2016 +0300 intel/gm45: Use romstage_handoff for S3 Don't use scratchpad registers when we have romstage_handoff to pass S3 resume flag. Also fixes console log from reporting early in ramstage "Normal boot" while on S3 resume path. Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/lenovo/t400/romstage.c | 17 ++++------------- src/mainboard/lenovo/x200/romstage.c | 17 ++++------------- src/mainboard/roda/rk9/romstage.c | 17 ++++------------- src/northbridge/intel/gm45/northbridge.c | 17 ----------------- src/southbridge/intel/i82801ix/i82801ix.h | 4 ---- src/southbridge/intel/i82801ix/smi.c | 13 ++----------- 6 files changed, 14 insertions(+), 71 deletions(-) diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index 821b87f..d110d4f 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -27,6 +27,7 @@ #include <cbmem.h> #include <lib.h> #include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> @@ -156,18 +157,8 @@ void mainboard_romstage_entry(unsigned long bist) outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); cbmem_initted = !cbmem_recovery(s3resume); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume && cbmem_initted) { - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); - } -#endif + + romstage_handoff_init(cbmem_initted && s3resume); + printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index 8c97ae1..49c5528 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -27,6 +27,7 @@ #include <cbmem.h> #include <lib.h> #include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> @@ -157,18 +158,8 @@ void mainboard_romstage_entry(unsigned long bist) outl(inl(DEFAULT_GPIOBASE + 0x38) & ~0x400, DEFAULT_GPIOBASE + 0x38); cbmem_initted = !cbmem_recovery(s3resume); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume && cbmem_initted) { - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); - } -#endif + + romstage_handoff_init(cbmem_initted && s3resume); + printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index e9a6a81..720f628 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -27,6 +27,7 @@ #include <cbmem.h> #include <lib.h> #include <pc80/mc146818rtc.h> +#include <romstage_handoff.h> #include <console/console.h> #include <southbridge/intel/i82801ix/i82801ix.h> #include <northbridge/intel/gm45/gm45.h> @@ -187,18 +188,8 @@ void mainboard_romstage_entry(unsigned long bist) init_iommu(); cbmem_initted = !cbmem_recovery(s3resume); -#if CONFIG_HAVE_ACPI_RESUME - /* If there is no high memory area, we didn't boot before, so - * this is not a resume. In that case we just create the cbmem toc. - */ - if (s3resume && cbmem_initted) { - - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); - } else { - /* Magic for S3 resume */ - pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_NORMAL_BOOT_MAGIC); - } -#endif + + romstage_handoff_init(cbmem_initted && s3resume); + printk(BIOS_SPEW, "exit main()\n"); } diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index aaa6749..af62f12 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -216,28 +216,11 @@ static struct device_operations cpu_bus_ops = { .scan_bus = 0, }; - static void enable_dev(device_t dev) { /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; -#if CONFIG_HAVE_ACPI_RESUME - switch (pci_read_config32(dev_find_slot(0, PCI_DEVFN(0, 0)), /*D0F0_SKPD*/0xdc)) { - case SKPAD_NORMAL_BOOT_MAGIC: - printk(BIOS_DEBUG, "Normal boot.\n"); - acpi_slp_type = 0; - break; - case SKPAD_ACPI_S3_MAGIC: - printk(BIOS_DEBUG, "S3 Resume.\n"); - acpi_slp_type = 3; - break; - default: - printk(BIOS_DEBUG, "Unknown boot method, assuming normal.\n"); - acpi_slp_type = 0; - break; - } -#endif } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { dev->ops = &cpu_bus_ops; } diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index afe4aa7..af4efcd 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -218,10 +218,6 @@ #define FD_SAD1 (1 << 2) /* SATA #1 */ -#define SKPAD_ACPI_S3_MAGIC 0xcafed00d -#define SKPAD_NORMAL_BOOT_MAGIC 0xcafebabe - - #ifndef __ACPI__ #ifndef __ASSEMBLER__ diff --git a/src/southbridge/intel/i82801ix/smi.c b/src/southbridge/intel/i82801ix/smi.c index dd0915a..34fbad4 100644 --- a/src/southbridge/intel/i82801ix/smi.c +++ b/src/southbridge/intel/i82801ix/smi.c @@ -20,6 +20,7 @@ #include <device/pci.h> #include <console/console.h> #include <arch/io.h> +#include <arch/acpi.h> #include <cpu/cpu.h> #include <cpu/x86/cache.h> #include <cpu/x86/smm.h> @@ -314,16 +315,6 @@ static void smm_relocate(void) static int smm_handler_copied = 0; -static int is_wakeup(void) -{ - device_t dev0 = dev_find_slot(0, PCI_DEVFN(0,0)); - - if (!dev0) - return 0; - - return pci_read_config32(dev0, 0xdc) == SKPAD_ACPI_S3_MAGIC; -} - static void smm_install(void) { /* The first CPU running this gets to copy the SMM handler. But not all @@ -337,7 +328,7 @@ static void smm_install(void) /* if we're resuming from S3, the SMM code is already in place, * so don't copy it again to keep the current SMM state */ - if (!is_wakeup()) { + if (!acpi_is_wakeup_s3()) { /* enable the SMM memory window */ pci_write_config8(dev_find_slot(0, PCI_DEVFN(0, 0)), SMRAM, D_OPEN | G_SMRAME | C_BASE_SEG);

1 0

New patch to review for coreboot: intel/sandybridge: Use postcar_frame for MTRR setup
by Kyösti Mälkki 01 Dec '16

01 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17673 -gerrit commit 75177bca3367a2834360258e89df6163eb6338d7 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 10:48:43 2016 +0200 intel/sandybridge: Use postcar_frame for MTRR setup Change-Id: Ica3134a2261d3e84c714264cf75557322f9ef5db Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_206ax/cache_as_ram.inc | 24 ++++++++-- src/northbridge/intel/sandybridge/ram_calc.c | 68 +++++----------------------- 2 files changed, 33 insertions(+), 59 deletions(-) diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index f0d4939..149cae6 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -225,12 +225,29 @@ before_romstage: post_code(0x38) - /* Get number of MTRRs. */ + /* Clear all of the variable MTRRs. */ popl %ebx movl $MTRR_PHYS_BASE(0), %ecx + clr %eax + clr %edx + 1: testl %ebx, %ebx jz 1f + wrmsr /* Write MTRR base. */ + inc %ecx + wrmsr /* Write MTRR mask. */ + inc %ecx + dec %ebx + jmp 1b + +1: + /* Get number of MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx +2: + testl %ebx, %ebx + jz 2f /* Low 32 bits of MTRR base. */ popl %eax @@ -248,8 +265,9 @@ before_romstage: inc %ecx dec %ebx - jmp 1b -1: + jmp 2b +2: + post_code(0x39) /* And enable cache again after setting MTRRs. */ diff --git a/src/northbridge/intel/sandybridge/ram_calc.c b/src/northbridge/intel/sandybridge/ram_calc.c index 026531a..1ac09e5 100644 --- a/src/northbridge/intel/sandybridge/ram_calc.c +++ b/src/northbridge/intel/sandybridge/ram_calc.c @@ -19,6 +19,7 @@ #include <arch/cpu.h> #include <arch/io.h> #include <cbmem.h> +#include <console/console.h> #include <cpu/intel/romstage.h> #include <cpu/x86/mtrr.h> #include <program_loading.h> @@ -43,83 +44,38 @@ void *cbmem_top(void) return (void *) smm_region_start(); } -static inline u32 *stack_push(u32 *stack, u32 value) -{ - stack = &stack[-1]; - *stack = value; - return stack; -} - /* setup_stack_and_mtrrs() determines the stack to use after * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) { - int num_mtrrs; - u32 *slot; - u32 mtrr_mask_upper; - u32 top_of_ram; - - /* Top of stack needs to be aligned to a 4-byte boundary. */ - slot = (void *)romstage_ram_stack_top(); - num_mtrrs = 0; + struct postcar_frame pcf; + uint32_t top_of_ram; - /* The upper bits of the MTRR mask need to set according to the number - * of physical address bits. */ - mtrr_mask_upper = (1 << (cpu_phys_address_size() - 32)) - 1; - - /* The order for each MTRR is value then base with upper 32-bits of - * each value coming before the lower 32-bits. The reasoning for - * this ordering is to create a stack layout like the following: - * +0: Number of MTRRs - * +4: MTRR base 0 31:0 - * +8: MTRR base 0 63:32 - * +12: MTRR mask 0 31:0 - * +16: MTRR mask 0 63:32 - * +20: MTRR base 1 31:0 - * +24: MTRR base 1 63:32 - * +28: MTRR mask 1 31:0 - * +32: MTRR mask 1 63:32 - */ + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); /* Cache the ROM as WP just below 4GiB. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, ~(CACHE_ROM_SIZE - 1) | MTRR_TYPE_WRPROT); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, 0 | MTRR_TYPE_WRBACK); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); top_of_ram = (uint32_t)cbmem_top(); /* Cache 8MiB below the top of ram. On sandybridge systems the top of * ram under 4GiB is the start of the TSEG region. It is required to * be 8MiB aligned. Set this area as cacheable so it can be used later * for ramstage before setting up the entire RAM as cacheable. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, (top_of_ram - (8 << 20)) | MTRR_TYPE_WRBACK); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); /* Cache 8MiB at the top of ram. Top of ram on sandybridge systems * is where the TSEG region resides. However, it is not restricted * to SMM mode until SMM has been relocated. By setting the region * to cacheable it provides faster access when relocating the SMM * handler as well as using the TSEG region for other purposes. */ - slot = stack_push(slot, mtrr_mask_upper); /* upper mask */ - slot = stack_push(slot, ~((8 << 20) - 1) | MTRR_PHYS_MASK_VALID); - slot = stack_push(slot, 0); /* upper base */ - slot = stack_push(slot, top_of_ram | MTRR_TYPE_WRBACK); - num_mtrrs++; + postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. */ - slot = stack_push(slot, num_mtrrs); - - return slot; + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); }

1 0

Patch set updated for coreboot: prog_loaders: Enable stage cache without RELOCATABLE_RAMSTAGE
by Kyösti Mälkki 01 Dec '16

01 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17666 -gerrit commit 11fcbba4e76ed6507a37f4ed9a0dd2a8db41aead Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 07:03:51 2016 +0200 prog_loaders: Enable stage cache without RELOCATABLE_RAMSTAGE Also removes stage_cache allocation from CBMEM, if board does not have HAVE_ACPI_RESUME enabled. We have weak stub for stage_cache_add() that does nothing. Change-Id: Ib6729b37c97939a39076f75bbf5d9f0abcb1201d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/lib/Makefile.inc | 4 ++-- src/lib/cbmem_stage_cache.c | 5 +++++ src/lib/prog_loaders.c | 3 +-- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 55d19d0..7ea039d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -172,8 +172,8 @@ ramstage-y += ext_stage_cache.c romstage-y += ext_stage_cache.c postcar-y += ext_stage_cache.c else -ramstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c -romstage-$(CONFIG_RELOCATABLE_RAMSTAGE) += cbmem_stage_cache.c +ramstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem_stage_cache.c +romstage-$(CONFIG_HAVE_ACPI_RESUME) += cbmem_stage_cache.c endif diff --git a/src/lib/cbmem_stage_cache.c b/src/lib/cbmem_stage_cache.c index 3fc99db..05558af 100644 --- a/src/lib/cbmem_stage_cache.c +++ b/src/lib/cbmem_stage_cache.c @@ -60,6 +60,11 @@ void stage_cache_load_stage(int stage_id, struct prog *stage) size = cbmem_entry_size(e); load_addr = (void *)(uintptr_t)meta->load_addr; + /* Ramstage fills low memory, need to backup OS first.*/ + if (!IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE) && + (stage_id == STAGE_RAMSTAGE)) + backup_ramstage_section(meta->load_addr, size); + memcpy(load_addr, c, size); prog_set_area(stage, load_addr, size); diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 58c1a8a..525b373 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -134,8 +134,7 @@ void run_ramstage(void) * firmware path on resume. */ if (IS_ENABLED(CONFIG_ARCH_X86) && - !IS_ENABLED(CONFIG_NO_STAGE_CACHE) && - IS_ENABLED(CONFIG_EARLY_CBMEM_INIT)) + !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) run_ramstage_from_resume(&ramstage); if (prog_locate(&ramstage))

1 0

Patch set updated for coreboot: ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP default
by Kyösti Mälkki 01 Dec '16

01 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17358 -gerrit commit 71184a5b2bbc5abb94771bea9ce996c264cae7c1 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Nov 10 11:50:21 2016 +0200 ACPI S3: Flip ACPI_HUGE_LOWMEM_BACKUP default Except for K8, f10 and f15 (non-AGESA) romstage ramstack is placed in CBMEM and ramstage loader takes care of tiny backup. Change-Id: I8477944f48ed2493d0a5e436a4088eb9fc3d59c5 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 9 +-------- src/cpu/amd/agesa/Kconfig | 1 - src/cpu/amd/family_10h-family_15h/Kconfig | 1 + src/cpu/amd/model_fxx/Kconfig | 1 + src/cpu/amd/pi/Kconfig | 1 - 5 files changed, 3 insertions(+), 10 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 5cd0254..d291851 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -565,16 +565,9 @@ config HAVE_ACPI_RESUME bool default n -config ACPI_TINY_LOWMEM_BACKUP - bool - default n - help - On S3 resume path, backup only the region of low memory ramstage - will occupy. Requires platform places romstage ramstack in CBMEM. - config ACPI_HUGE_LOWMEM_BACKUP bool - default !ACPI_TINY_LOWMEM_BACKUP + default n help On S3 resume path, backup low memory from RAMBASE..RAMTOP in CBMEM. diff --git a/src/cpu/amd/agesa/Kconfig b/src/cpu/amd/agesa/Kconfig index 7fe24ce..ae5e854 100644 --- a/src/cpu/amd/agesa/Kconfig +++ b/src/cpu/amd/agesa/Kconfig @@ -31,7 +31,6 @@ config CPU_AMD_AGESA select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select ACPI_TINY_LOWMEM_BACKUP if CPU_AMD_AGESA diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index fda7fc8..c65a670 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -12,6 +12,7 @@ config CPU_AMD_MODEL_10XXX select HAVE_MONOTONIC_TIMER select SUPPORT_CPU_UCODE_IN_CBFS select CPU_MICROCODE_MULTIPLE_FILES if !CPU_MICROCODE_CBFS_NONE + select ACPI_HUGE_LOWMEM_BACKUP if CPU_AMD_MODEL_10XXX diff --git a/src/cpu/amd/model_fxx/Kconfig b/src/cpu/amd/model_fxx/Kconfig index c8bae33..804e698 100644 --- a/src/cpu/amd/model_fxx/Kconfig +++ b/src/cpu/amd/model_fxx/Kconfig @@ -10,6 +10,7 @@ config CPU_AMD_MODEL_FXX select TSC_SYNC_LFENCE select UDELAY_LAPIC select SUPPORT_CPU_UCODE_IN_CBFS + select ACPI_HUGE_LOWMEM_BACKUP if CPU_AMD_MODEL_FXX config CPU_ADDR_BITS diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 203fa03..ed379ea 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -28,7 +28,6 @@ config CPU_AMD_PI select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select ACPI_TINY_LOWMEM_BACKUP if CPU_AMD_PI

1 0

Patch set updated for coreboot: ACPI S3: Hide acpi_slp_type
by Kyösti Mälkki 01 Dec '16

01 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/10360 -gerrit commit c8b2e482dcf81b6ff51152f8415f999b739179f6 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri May 29 06:17:23 2015 +0300 ACPI S3: Hide acpi_slp_type Change-Id: I48a20e34f11adc7c61d0ce6b3c005dbd712fbcac Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/acpi_s3.c | 2 +- src/arch/x86/include/arch/acpi.h | 2 -- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/src/arch/x86/acpi_s3.c b/src/arch/x86/acpi_s3.c index f3cb097..0fc1914 100644 --- a/src/arch/x86/acpi_s3.c +++ b/src/arch/x86/acpi_s3.c @@ -27,7 +27,7 @@ #if ENV_RAMSTAGE /* This is filled with acpi_is_wakeup() call early in ramstage. */ -int acpi_slp_type = -1; +static int acpi_slp_type = -1; #if IS_ENABLED(CONFIG_EARLY_CBMEM_INIT) int acpi_get_sleep_type(void) diff --git a/src/arch/x86/include/arch/acpi.h b/src/arch/x86/include/arch/acpi.h index 7c29648..6854573 100644 --- a/src/arch/x86/include/arch/acpi.h +++ b/src/arch/x86/include/arch/acpi.h @@ -691,7 +691,6 @@ static inline int acpi_s3_resume_allowed(void) void *acpi_backup_container(uintptr_t base, size_t size); #if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) -extern int acpi_slp_type; #ifdef __PRE_RAM__ static inline int acpi_is_wakeup_s3(void) @@ -706,7 +705,6 @@ int acpi_is_wakeup_s4(void); void acpi_prepare_for_resume(void); #else -#define acpi_slp_type ACPI_S0 static inline int acpi_is_wakeup(void) { return 0; } static inline int acpi_is_wakeup_s3(void) { return 0; } static inline int acpi_is_wakeup_s4(void) { return 0; }

1 0

Patch set updated for coreboot: intel/nehalem post-car: Use postcar_frame for MTRR setup
by Kyösti Mälkki 01 Dec '16

01 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15793 -gerrit commit e4881b38c55595183b37807c76e504558142cce3 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 22 22:52:14 2016 +0300 intel/nehalem post-car: Use postcar_frame for MTRR setup Adapt implementation from skylake to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: I84f6fa6f37a7348b2d4ad9f08a18bebe4b1e34e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/intel/model_2065x/cache_as_ram.inc | 63 ++++++++++++++++++----------- src/mainboard/lenovo/x201/romstage.c | 1 - src/mainboard/packardbell/ms2290/romstage.c | 1 - src/northbridge/intel/nehalem/Kconfig | 1 + src/northbridge/intel/nehalem/ram_calc.c | 32 ++++++++++++++- 5 files changed, 72 insertions(+), 26 deletions(-) diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 93d6907..b7c59fa 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -170,8 +170,8 @@ before_romstage: /* Call romstage.c main function. */ call romstage_main /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. - */ + * after cache-as-ram is torn down. It also contains the information + * for setting up MTRRs. */ movl %eax, %esp post_code(0x30) @@ -220,31 +220,48 @@ before_romstage: post_code(0x38) - /* Enable Write Back and Speculative Reads for the first MB - * and ramstage. - */ + /* Clear all of the variable MTRRs. */ + popl %ebx movl $MTRR_PHYS_BASE(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx + clr %eax + clr %edx + +1: + testl %ebx, %ebx + jz 1f + wrmsr /* Write MTRR base. */ + inc %ecx + wrmsr /* Write MTRR mask. */ + inc %ecx + dec %ebx + jmp 1b + +1: + /* Get number of MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx +2: + testl %ebx, %ebx + jz 2f + + /* Low 32 bits of MTRR base. */ + popl %eax + /* Upper 32 bits of MTRR base. */ + popl %edx + /* Write MTRR base. */ wrmsr - movl $MTRR_PHYS_MASK(0), %ecx - movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx // 36bit address space + inc %ecx + /* Low 32 bits of MTRR mask. */ + popl %eax + /* Upper 32 bits of MTRR mask. */ + popl %edx + /* Write MTRR mask. */ wrmsr + inc %ecx -#if CACHE_ROM_SIZE - /* Enable Caching and speculative Reads for the - * complete ROM now that we actually have RAM. - */ - movl $MTRR_PHYS_BASE(1), %ecx - movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr -#endif + dec %ebx + jmp 2b +2: post_code(0x39) diff --git a/src/mainboard/lenovo/x201/romstage.c b/src/mainboard/lenovo/x201/romstage.c index 2bfa19c..7b8d7f9 100644 --- a/src/mainboard/lenovo/x201/romstage.c +++ b/src/mainboard/lenovo/x201/romstage.c @@ -282,7 +282,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/mainboard/packardbell/ms2290/romstage.c b/src/mainboard/packardbell/ms2290/romstage.c index 92ee021..04c9513 100644 --- a/src/mainboard/packardbell/ms2290/romstage.c +++ b/src/mainboard/packardbell/ms2290/romstage.c @@ -272,7 +272,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, 0xcafed00d); diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index eee9405..b373107 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -21,6 +21,7 @@ config NORTHBRIDGE_INTEL_NEHALEM select INTEL_EDID select TSC_MONOTONIC_TIMER select INTEL_GMA_ACPI + select RELOCATABLE_RAMSTAGE select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE if NORTHBRIDGE_INTEL_NEHALEM diff --git a/src/northbridge/intel/nehalem/ram_calc.c b/src/northbridge/intel/nehalem/ram_calc.c index 4d73ee9..407fc64 100644 --- a/src/northbridge/intel/nehalem/ram_calc.c +++ b/src/northbridge/intel/nehalem/ram_calc.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2012 ChromeOS Authors * Copyright (C) 2013 Vladimir Serbinenko. * * This program is free software; you can redistribute it and/or modify @@ -15,9 +16,13 @@ #define __SIMPLE_DEVICE__ +#include <arch/cpu.h> #include <arch/io.h> #include <cbmem.h> +#include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> +#include <program_loading.h> #include "nehalem.h" static uintptr_t smm_region_start(void) @@ -32,7 +37,32 @@ void *cbmem_top(void) return (void *) smm_region_start(); } +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) { - return (void*)CONFIG_RAMTOP; + struct postcar_frame pcf; + uint32_t top_of_ram; + + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uint32_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); }

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Patch set updated for coreboot: intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup
by Kyösti Mälkki 01 Dec '16

01 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15791 -gerrit commit 8a68b21e7e3d47f3757bf9176e21bd70a806c1df Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 22 22:53:19 2016 +0300 intel i945 gm45 x4x post-car: Use postcar_frame for MTRR setup Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM. Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/cpu.h | 5 +++ src/arch/x86/postcar_loader.c | 16 +++++++++ src/cpu/intel/car/cache_as_ram_ht.inc | 60 +++++++++++++++++++++----------- src/cpu/intel/car/romstage.c | 28 ++++++++++++--- src/cpu/intel/model_6ex/cache_as_ram.inc | 60 +++++++++++++++++++++----------- src/mainboard/lenovo/t400/romstage.c | 1 - src/mainboard/lenovo/x200/romstage.c | 1 - src/mainboard/roda/rk9/romstage.c | 1 - src/northbridge/intel/gm45/Kconfig | 1 + src/northbridge/intel/gm45/ram_calc.c | 30 +++++++++++++++- src/northbridge/intel/i945/Kconfig | 1 + src/northbridge/intel/i945/early_init.c | 1 - src/northbridge/intel/i945/ram_calc.c | 30 +++++++++++++++- src/northbridge/intel/x4x/Kconfig | 1 + src/northbridge/intel/x4x/ram_calc.c | 30 +++++++++++++++- 15 files changed, 215 insertions(+), 51 deletions(-) diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index faa2375..d33bb92 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -268,6 +268,11 @@ struct postcar_frame { int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size); /* + * Initialize postcar_frame object with a fixed stacktop in low memory. + */ +void postcar_frame_init_lowmem(struct postcar_frame *pcf); + +/* * Add variable MTRR covering the provided range with MTRR type. */ void postcar_frame_add_mtrr(struct postcar_frame *pcf, diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 948e445..928a6ab 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -58,6 +58,22 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size) return 0; } +/* For use with LATE_CBMEM_INIT boards, with a fixed stacktop in low memory. */ +void postcar_frame_init_lowmem(struct postcar_frame *pcf) +{ + msr_t msr; + + msr = rdmsr(MTRR_CAP_MSR); + + pcf->stack = CONFIG_RAMTOP; + + pcf->upper_mask = (1 << (cpu_phys_address_size() - 32)) - 1; + + pcf->max_var_mttrs = msr.lo & MTRR_CAP_VCNT; + + pcf->num_var_mttrs = 0; +} + void postcar_frame_add_mtrr(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type) { diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index 210d356..d8a4fd9 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -337,10 +337,9 @@ before_romstage: post_code(0x2f) /* Call romstage.c main function. */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. - */ + * after cache-as-ram is torn down. It also contains the information + * for setting up MTRRs. */ movl %eax, %esp post_code(0x30) @@ -378,27 +377,48 @@ before_romstage: post_code(0x38) - /* Enable Write Back and Speculative Reads for low RAM. */ + /* Clear all of the variable MTRRs. */ + popl %ebx movl $MTRR_PHYS_BASE(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx - wrmsr - movl $MTRR_PHYS_MASK(0), %ecx - rdmsr - movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax - wrmsr + clr %eax + clr %edx + +1: + testl %ebx, %ebx + jz 1f + wrmsr /* Write MTRR base. */ + inc %ecx + wrmsr /* Write MTRR mask. */ + inc %ecx + dec %ebx + jmp 1b -#if CACHE_ROM_SIZE - /* Enable caching and Speculative Reads for Flash ROM device. */ - movl $MTRR_PHYS_BASE(1), %ecx - movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx +1: + /* Get number of MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx +2: + testl %ebx, %ebx + jz 2f + + /* Low 32 bits of MTRR base. */ + popl %eax + /* Upper 32 bits of MTRR base. */ + popl %edx + /* Write MTRR base. */ wrmsr - movl $MTRR_PHYS_MASK(1), %ecx - rdmsr - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax + inc %ecx + /* Low 32 bits of MTRR mask. */ + popl %eax + /* Upper 32 bits of MTRR mask. */ + popl %edx + /* Write MTRR mask. */ wrmsr -#endif + inc %ecx + + dec %ebx + jmp 2b +2: post_code(0x39) diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 4f60034..903b5fc 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -14,6 +14,7 @@ #include <arch/cpu.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> #include <program_loading.h> #define DCACHE_RAM_ROMSTAGE_STACK_SIZE 0x2000 @@ -41,10 +42,7 @@ void * asmlinkage romstage_main(unsigned long bist) } /* Get the stack to use after cache-as-ram is torn down. */ - if (IS_ENABLED(CONFIG_LATE_CBMEM_INIT)) - romstage_stack_after_car = (void*)CONFIG_RAMTOP; - else - romstage_stack_after_car = setup_stack_and_mtrrs(); + romstage_stack_after_car = setup_stack_and_mtrrs(); return romstage_stack_after_car; } @@ -54,3 +52,25 @@ void asmlinkage romstage_after_car(void) /* Load the ramstage. */ run_ramstage(); } + +#if IS_ENABLED(CONFIG_LATE_CBMEM_INIT) +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ +void *setup_stack_and_mtrrs(void) +{ + struct postcar_frame pcf; + + postcar_frame_init_lowmem(&pcf); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); +} +#endif /* CONFIG_LATE_CBMEM_INIT */ diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index 1673242..21f63ec 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -138,10 +138,9 @@ before_romstage: post_code(0x29) /* Call romstage.c main function. */ call romstage_main - /* Save return value from romstage_main. It contains the stack to use - * after cache-as-ram is torn down. - */ + * after cache-as-ram is torn down. It also contains the information + * for setting up MTRRs. */ movl %eax, %esp post_code(0x30) @@ -179,27 +178,48 @@ before_romstage: post_code(0x38) - /* Enable Write Back and Speculative Reads for low RAM. */ + /* Clear all of the variable MTRRs. */ + popl %ebx movl $MTRR_PHYS_BASE(0), %ecx - movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax - xorl %edx, %edx + clr %eax + clr %edx + +1: + testl %ebx, %ebx + jz 1f + wrmsr /* Write MTRR base. */ + inc %ecx + wrmsr /* Write MTRR mask. */ + inc %ecx + dec %ebx + jmp 1b + +1: + /* Get number of MTRRs. */ + popl %ebx + movl $MTRR_PHYS_BASE(0), %ecx +2: + testl %ebx, %ebx + jz 2f + + /* Low 32 bits of MTRR base. */ + popl %eax + /* Upper 32 bits of MTRR base. */ + popl %edx + /* Write MTRR base. */ wrmsr - movl $MTRR_PHYS_MASK(0), %ecx - movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx + inc %ecx + /* Low 32 bits of MTRR mask. */ + popl %eax + /* Upper 32 bits of MTRR mask. */ + popl %edx + /* Write MTRR mask. */ wrmsr + inc %ecx -#if CACHE_ROM_SIZE - /* Enable caching and Speculative Reads for Flash ROM device. */ - movl $MTRR_PHYS_BASE(1), %ecx - movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax - xorl %edx, %edx - wrmsr - movl $MTRR_PHYS_MASK(1), %ecx - movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax - movl $CPU_PHYSMASK_HI, %edx - wrmsr -#endif + dec %ebx + jmp 2b +2: post_code(0x39) diff --git a/src/mainboard/lenovo/t400/romstage.c b/src/mainboard/lenovo/t400/romstage.c index bba53d1..821b87f 100644 --- a/src/mainboard/lenovo/t400/romstage.c +++ b/src/mainboard/lenovo/t400/romstage.c @@ -161,7 +161,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index c1e193a..8c97ae1 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -162,7 +162,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/mainboard/roda/rk9/romstage.c b/src/mainboard/roda/rk9/romstage.c index 03cbf05..e9a6a81 100644 --- a/src/mainboard/roda/rk9/romstage.c +++ b/src/mainboard/roda/rk9/romstage.c @@ -192,7 +192,6 @@ void mainboard_romstage_entry(unsigned long bist) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0, 0), D0F0_SKPD, SKPAD_ACPI_S3_MAGIC); diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 80447d5..c2e6b9b 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_EDID select INTEL_GMA_ACPI + select RELOCATABLE_RAMSTAGE config CBFS_SIZE hex diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 146bcf2..56d5227 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -18,11 +18,14 @@ #define __SIMPLE_DEVICE__ #include <stdint.h> +#include <arch/cpu.h> #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> #include <cbmem.h> +#include <program_loading.h> #include "gm45.h" /* @@ -87,7 +90,32 @@ void *cbmem_top(void) return (void *) smm_region_start(); } +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) { - return (void*)CONFIG_RAMTOP; + struct postcar_frame pcf; + uint32_t top_of_ram; + + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uint32_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); } diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index d22451a..3c1cb71 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -25,6 +25,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select LAPIC_MONOTONIC_TIMER select VGA select INTEL_GMA_ACPI + select RELOCATABLE_RAMSTAGE config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 16ae55f..8ebb422 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -905,7 +905,6 @@ static void i945_prepare_resume(int s3resume) * this is not a resume. In that case we just create the cbmem toc. */ if (s3resume && cbmem_was_initted) { - acpi_prepare_for_resume(); /* Magic for S3 resume */ pci_write_config32(PCI_DEV(0, 0x00, 0), SKPAD, diff --git a/src/northbridge/intel/i945/ram_calc.c b/src/northbridge/intel/i945/ram_calc.c index 39ede5f..2f724ae 100644 --- a/src/northbridge/intel/i945/ram_calc.c +++ b/src/northbridge/intel/i945/ram_calc.c @@ -17,10 +17,13 @@ #define __SIMPLE_DEVICE__ #include <arch/io.h> +#include <arch/cpu.h> #include <cbmem.h> #include "i945.h" #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> +#include <program_loading.h> static uintptr_t smm_region_start(void) { @@ -71,7 +74,32 @@ u32 decode_igd_memory_size(const u32 gms) return ggc2uma[gms] << 10; } +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) { - return (void*)CONFIG_RAMTOP; + struct postcar_frame pcf; + uint32_t top_of_ram; + + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uint32_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); } diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 43c7b2a..f6feda5 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select VGA select INTEL_GMA_ACPI select EARLY_CBMEM_INIT + select RELOCATABLE_RAMSTAGE config CBFS_SIZE hex diff --git a/src/northbridge/intel/x4x/ram_calc.c b/src/northbridge/intel/x4x/ram_calc.c index 09eec47..6db7a31 100644 --- a/src/northbridge/intel/x4x/ram_calc.c +++ b/src/northbridge/intel/x4x/ram_calc.c @@ -20,11 +20,14 @@ #include <cbmem.h> #include <commonlib/helpers.h> #include <stdint.h> +#include <arch/cpu.h> #include <arch/io.h> #include <device/pci_def.h> #include <console/console.h> #include <cpu/intel/romstage.h> +#include <cpu/x86/mtrr.h> #include <northbridge/intel/x4x/x4x.h> +#include <program_loading.h> /** Decodes used Graphics Mode Select (GMS) to kilobytes. */ u32 decode_igd_memory_size(const u32 gms) @@ -95,7 +98,32 @@ void *cbmem_top(void) return (void*)(ramtop); } +/* setup_stack_and_mtrrs() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use. */ void *setup_stack_and_mtrrs(void) { - return (void*)CONFIG_RAMTOP; + struct postcar_frame pcf; + uint32_t top_of_ram; + + if (postcar_frame_init(&pcf, 1*KiB)) + die("Unable to initialize postcar frame.\n"); + + /* Cache the ROM as WP just below 4GiB. */ + postcar_frame_add_mtrr(&pcf, -CACHE_ROM_SIZE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); + + /* Cache RAM as WB from 0 -> CACHE_TMP_RAMTOP. */ + postcar_frame_add_mtrr(&pcf, 0, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); + + /* Cache at least 8 MiB below the top of ram, and at most 8 MiB + * above top of the ram. This satisfies MTRR alignment requirement + * with different TSEG size configurations. + */ + top_of_ram = ALIGN_DOWN((uint32_t)cbmem_top(), 8*MiB); + postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 8*MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(&pcf, top_of_ram, 8*MiB, MTRR_TYPE_WRBACK); + + /* Save the number of MTRRs to setup. Return the stack location + * pointing to the number of MTRRs. + */ + return postcar_commit_mtrrs(&pcf); }

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coreboot-gerrit December 2016