the following patch was just integrated into master:
commit 91bfa8e7eaf7a91c47a3e86c35ffe2135aa0cd8f
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Sun Nov 20 20:39:56 2016 +0200
PCIEXP_PLUGIN_SUPPORT: Change dependency on PCI access
Some PCI-e capability registers are located starting from
0x100, these are not accessible using the conventional
PCI IO config operations at 0xcf8/0xcfc, unless PCI_CFG_EXT_IO
was selected.
Thus any feature that calls pciexp_find_extended_cap()
depends on either MMCONF_SUPPORT_DEFAULT or PCI_CFG_EXT_IO
being enabled on the platform.
In theory there can be system without MMCONF_SUPPORT, but
with complete PCI Express configuration space available
using PCI_CFG_EXT_IO. Do not use explicit PCI MMCONF
operations here, but rely on the default PCI access
method to be able to access all of the configuration space.
While at it, convert to IS_ENABLED() everywhere in the source
and organize Kconfig file better.
Change-Id: Ica6e16d2fb2adc532e644c4b2c47806490235715
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17546
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17546 for details.
-gerrit
the following patch was just integrated into master:
commit df96a702ba98c1b85e8b4657498e76ec9f543447
Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Date: Tue Nov 29 16:08:38 2016 +0200
PCIEXP_ASPM: Unify code with other PCI-e tuning
Error reporting can be enabled together with ASPM, there
is no other use for function return value.
Change-Id: I58081fac0df5205a5aea65d735d34b375c2af9cd
Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-on: https://review.coreboot.org/17654
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/17654 for details.
-gerrit
Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17659
-gerrit
commit 094cc2890ced666e541934f502542b7f7708df5d
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Wed Nov 30 18:40:38 2016 +0100
nb/x4x: Fix raminit unconditionally resetting
The raminit only succeeds when it starts from a cold boot.
To achieve this it unconditionally did a cold reset.
Now it detects whether it underwent a hot reset (bit 8 of
MCHBAR32(0xf14)) before issuing a cold reset to make raminit work.
It also adds a 2s delay before reset because some disk drives
expect a warm reboot when the OS wants to reboot and therefore are not
shut down properly / in time. If the drive is unexpectedly powered off
which happens during a cold reset, it can cause data loss. Giving the
drive 2 extra seconds can work around this issue.
(A proper fix would be to fix the raminit such that it works on a hot reset)
Change-Id: I6063dd6aed908558155d2523f35d7241ff1f4fde
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
src/northbridge/intel/x4x/raminit_ddr2.c | 22 +++++++++++++++++++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c
index b3ee34a..09eea2a 100644
--- a/src/northbridge/intel/x4x/raminit_ddr2.c
+++ b/src/northbridge/intel/x4x/raminit_ddr2.c
@@ -258,10 +258,19 @@ static void checkreset_ddr2(struct sysinfo *s)
{
u8 pmcon2;
u8 reset = 0;
+ u32 pmir;
+ pmir = pci_read_config32(PCI_DEV(0, 0x1f, 0), 0xac);
pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2);
- if (!(pmcon2 & 0x80)) {
- pmcon2 |= 0x80;
+
+ if ((MCHBAR32(0xf14) & (1 << 8))) {
+ printk(BIOS_DEBUG, "Waiting for disks to timeout...\n");
+ mdelay(2000);
+ reset = 1;
+ }
+
+ if (pmcon2 & 0x80) {
+ pmcon2 &= ~0x80;
pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
reset = 1;
@@ -273,10 +282,17 @@ static void checkreset_ddr2(struct sysinfo *s)
}
if (reset) {
printk(BIOS_DEBUG, "Reset...\n");
+ /* Do a global reset. only useful on ICH10 */
+ pmir |= (1 << 20);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir);
outb(0xe, 0xcf9);
asm ("hlt");
}
- pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80);
+ pmir &= ~(1 << 20);
+ pmcon2 |= 0x80;
+ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2);
+ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, pmir);
+
}
static void setioclk_ddr2(struct sysinfo *s)