coreboot-gerrit December 2016

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New patch to review for coreboot: MMCONF_SUPPORT_DEFAULT: Consolidate resource registration
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17695 -gerrit commit cb5b44a8f29f2108f96c213173eff7160eac8477 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 08:56:05 2016 +0200 MMCONF_SUPPORT_DEFAULT: Consolidate resource registration Change-Id: Id727270bff9e0288747d178c00f3d747fe223b0f Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/device_util.c | 42 +++++++++++++++++++ src/include/device/device.h | 5 +++ src/northbridge/amd/agesa/family10/northbridge.c | 21 +++++----- src/northbridge/amd/agesa/family12/northbridge.c | 13 +++--- src/northbridge/amd/agesa/family14/northbridge.c | 6 +-- src/northbridge/amd/agesa/family15/northbridge.c | 6 +-- src/northbridge/amd/agesa/family15rl/northbridge.c | 6 +-- src/northbridge/amd/agesa/family15tn/northbridge.c | 6 +-- src/northbridge/amd/agesa/family16kb/northbridge.c | 6 +-- src/northbridge/amd/amdfam10/northbridge.c | 9 +---- src/northbridge/amd/pi/00630F01/northbridge.c | 11 +---- src/northbridge/amd/pi/00660F01/northbridge.c | 11 +---- src/northbridge/amd/pi/00670F00/northbridge.c | 11 +---- src/northbridge/amd/pi/00730F01/northbridge.c | 11 +---- src/northbridge/intel/fsp_rangeley/Kconfig | 4 ++ src/northbridge/intel/fsp_rangeley/northbridge.c | 11 ----- src/northbridge/intel/fsp_sandybridge/Kconfig | 4 ++ .../intel/fsp_sandybridge/northbridge.c | 47 ++++++---------------- src/northbridge/intel/i3100/northbridge.c | 10 +---- src/northbridge/intel/i945/northbridge.c | 26 +----------- src/northbridge/intel/nehalem/Kconfig | 4 ++ src/northbridge/intel/nehalem/bootblock.c | 1 + src/northbridge/intel/sandybridge/Kconfig | 4 ++ src/northbridge/intel/sandybridge/northbridge.c | 47 ++++++---------------- src/northbridge/via/vx900/Kconfig | 4 ++ src/northbridge/via/vx900/northbridge.c | 5 +-- src/soc/intel/fsp_baytrail/northcluster.c | 12 ------ src/soc/intel/sch/Kconfig | 4 ++ src/soc/intel/sch/northbridge.c | 43 +++++--------------- 29 files changed, 140 insertions(+), 250 deletions(-) diff --git a/src/device/device_util.c b/src/device/device_util.c index 56afefd..c75095a 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -23,6 +23,7 @@ #include <device/path.h> #include <device/pci_def.h> #include <device/resource.h> +#include <lib.h> #include <string.h> /** @@ -888,6 +889,47 @@ void fixed_mem_resource(device_t dev, unsigned long index, resource->flags |= type; } +int mmconf_resource_init(struct resource *resource, bool bar64, + uintptr_t base, int buses) +{ + resource->base = base; + resource->size = buses * MiB; + resource->align = log2(resource->size); + resource->gran = log2(resource->size); + resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* 64-bit BAR or MSR. */ + if (bar64 && IS_ENABLED(CONFIG_ARCH_RAMSTAGE_X86_64)) + resource->limit = (1ULL << cpu_phys_address_size()) - 1; + else + resource->limit = (1ULL << 32) - 1; + + printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", + (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + return 0; +} + +void mmconf_resource32(struct device *dev, unsigned long index) +{ + struct resource *resource = new_resource(dev, index); + if (!resource) + return; + + mmconf_resource_init(resource, 0, CONFIG_MMCONF_BASE_ADDRESS, + CONFIG_MMCONF_BUS_NUMBER); +} + +void mmconf_resource64(struct device *dev, unsigned long index) +{ + struct resource *resource = new_resource(dev, index); + if (!resource) + return; + + mmconf_resource_init(resource, 1, CONFIG_MMCONF_BASE_ADDRESS, + CONFIG_MMCONF_BUS_NUMBER); +} + void tolm_test(void *gp, struct device *dev, struct resource *new) { struct resource **best_p = gp; diff --git a/src/include/device/device.h b/src/include/device/device.h index 95fabf4..36edb79 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -234,6 +234,11 @@ void pci_domain_scan_bus(struct device *dev); void fixed_mem_resource(device_t dev, unsigned long index, unsigned long basek, unsigned long sizek, unsigned long type); +int mmconf_resource_init(struct resource *res, bool bar64, uintptr_t base, + int buses); +void mmconf_resource32(struct device *dev, unsigned long index); +void mmconf_resource64(struct device *dev, unsigned long index); + void scan_smbus(device_t bus); void scan_static_bus(device_t bus); void scan_lpc_bus(device_t bus); diff --git a/src/northbridge/amd/agesa/family10/northbridge.c b/src/northbridge/amd/agesa/family10/northbridge.c index 2a54892..7408e50 100644 --- a/src/northbridge/amd/agesa/family10/northbridge.c +++ b/src/northbridge/amd/agesa/family10/northbridge.c @@ -424,6 +424,13 @@ static void amdfam10_read_resources(device_t dev) amdfam10_link_read_bases(dev, nodeid, link->link_num); } } + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ + mmconf_resource64(dev, 0xc0010058); } static void amdfam10_set_resource(device_t dev, struct resource *resource, @@ -530,6 +537,11 @@ static void amdfam10_set_resources(device_t dev) assign_resources(bus); } } + + res = find_resource(dev, 0xc0010058); + if (res) { + report_resource_stored(dev, res, " <mmconfig>"); + } } static void mcf0_control_init(struct device *dev) @@ -1096,19 +1108,10 @@ static void cpu_bus_init(device_t dev) static void cpu_bus_read_resources(device_t dev) { - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; } static void cpu_bus_set_resources(device_t dev) { - struct resource *resource = find_resource(dev, 0xc0010058); - if (resource) { - report_resource_stored(dev, resource, " <mmconfig>"); - } pci_dev_set_resources(dev); } diff --git a/src/northbridge/amd/agesa/family12/northbridge.c b/src/northbridge/amd/agesa/family12/northbridge.c index 6f2896a..5ef7a90 100644 --- a/src/northbridge/amd/agesa/family12/northbridge.c +++ b/src/northbridge/amd/agesa/family12/northbridge.c @@ -300,6 +300,14 @@ static void read_resources(device_t dev) amdfam12_link_read_bases(dev, nodeid, link->link_num); } } + + /* + * This MMCONF resource must be reserved in the PCI domain. + * It is not honored by the coreboot resource allocator if it is in + * the CPU_CLUSTER. + */ + mmconf_resource64(dev, 0xc0010058); + printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } @@ -649,11 +657,6 @@ static void cpu_bus_read_resources(device_t dev) { printk(BIOS_DEBUG, "\nFam12h - northbridge.c - %s - Start.\n",__func__); - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; printk(BIOS_DEBUG, "Fam12h - northbridge.c - %s - End.\n",__func__); } diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index f92183e..08d1c49 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -302,11 +302,7 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15/northbridge.c b/src/northbridge/amd/agesa/family15/northbridge.c index 5fc9833..c5e2921 100644 --- a/src/northbridge/amd/agesa/family15/northbridge.c +++ b/src/northbridge/amd/agesa/family15/northbridge.c @@ -326,11 +326,7 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15rl/northbridge.c b/src/northbridge/amd/agesa/family15rl/northbridge.c index b5f7690..2417933 100644 --- a/src/northbridge/amd/agesa/family15rl/northbridge.c +++ b/src/northbridge/amd/agesa/family15rl/northbridge.c @@ -326,11 +326,7 @@ static void read_resources(struct device *dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index 2353126..7862e60 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -325,11 +325,7 @@ static void nb_read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 63e1c2e..23057a9 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -325,11 +325,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the APIC_CLUSTER. */ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 605db3a..4284e1e 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -741,14 +741,7 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); /* We have MMCONF_SUPPORT_DEFAULT, create the resource window. */ - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ - res->align = log2(res->size); - res->gran = log2(res->size); - res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource64(dev, 0xc0010058); /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index 4872db0..1695808 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -309,15 +309,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -335,7 +326,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 4c1254c..9f6ae1f 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -304,15 +304,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -330,7 +321,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 9a39410..521a32c 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -304,15 +304,6 @@ static void amdfam15_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -330,7 +321,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 44f91e2..d97d875 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -312,15 +312,6 @@ static void amdfam16_link_read_bases(device_t dev, u32 nodeid, u32 link) } -static void enable_mmconf_resource(device_t dev) -{ - struct resource *resource = new_resource(dev, 0xc0010058); - resource->base = CONFIG_MMCONF_BASE_ADDRESS; - resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; -} - static void read_resources(device_t dev) { u32 nodeid; @@ -338,7 +329,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - enable_mmconf_resource(dev); + mmconf_resource64(dev, 0xc0010058); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig index bc735264..fdb5566 100644 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/Kconfig @@ -24,6 +24,10 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000 +config MMCONF_BUS_NUMBER + int + default 256 + choice prompt "Set TSEG Size" default SET_TSEG_1MB if SET_DEFAULT_TSEG_1MB diff --git a/src/northbridge/intel/fsp_rangeley/northbridge.c b/src/northbridge/intel/fsp_rangeley/northbridge.c index f01333e..65b794e 100644 --- a/src/northbridge/intel/fsp_rangeley/northbridge.c +++ b/src/northbridge/intel/fsp_rangeley/northbridge.c @@ -84,17 +84,6 @@ static int get_pcie_bar(u32 *base, u32 *len) static int add_fixed_resources(struct device *dev, int index) { struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } resource = new_resource(dev, index++); /* Local APIC */ resource->base = LAPIC_DEFAULT_BASE; diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 89326b4..cfcfc34 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -30,6 +30,10 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/fsp_sandybridge/bootblock.c" +config MMCONF_BUS_NUMBER + int + default 64 + config VGA_BIOS_ID string default "8086,0106" diff --git a/src/northbridge/intel/fsp_sandybridge/northbridge.c b/src/northbridge/intel/fsp_sandybridge/northbridge.c index 50615b5..877d85f 100644 --- a/src/northbridge/intel/fsp_sandybridge/northbridge.c +++ b/src/northbridge/intel/fsp_sandybridge/northbridge.c @@ -62,18 +62,18 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; *base = 0; - *len = 0; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; + /* FIXME: 64bit BAR here. */ pciexbar_reg = pci_read_config32(dev, PCIEXBAR); if (!(pciexbar_reg & (1 << 0))) @@ -82,16 +82,13 @@ static int get_pcie_bar(u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: // 128M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: // 64M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; } return 0; @@ -99,21 +96,8 @@ static int get_pcie_bar(u32 *base, u32 *len) static void add_fixed_resources(struct device *dev, int index) { - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } - mmio_resource(dev, index++, legacy_hole_base_k, legacy_hole_size_k); } @@ -256,24 +240,17 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses; pci_dev_read_resources(dev); - /* So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 0, pcie_config_base, buses); + } } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/i3100/northbridge.c b/src/northbridge/intel/i3100/northbridge.c index 8025ac3..65107de 100644 --- a/src/northbridge/intel/i3100/northbridge.c +++ b/src/northbridge/intel/i3100/northbridge.c @@ -32,9 +32,6 @@ #include <arch/acpi.h> -static u32 max_bus; - - static void pci_domain_set_resources(device_t dev) { device_t mc_dev; @@ -139,14 +136,9 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(device_t dev) { - struct resource *resource; - pci_dev_read_resources(dev); - resource = new_resource(dev, 0xcf); - resource->base = 0xe0000000; - resource->size = max_bus * 4096*256; - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + mmconf_resource32(dev, 0xcf); } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index 5d18591..26d89d0 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -62,21 +62,6 @@ static int get_pcie_bar(u32 *base, u32 *len) return 0; } -static void add_fixed_resources(struct device *dev, int index) -{ - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } -} - static void pci_domain_set_resources(device_t dev) { uint32_t pci_tolm; @@ -153,8 +138,6 @@ static void pci_domain_set_resources(device_t dev) uma_resource(dev, 5, uma_memory_base >> 10, uma_memory_size >> 10); mmio_resource(dev, 6, tseg_memory_base >> 10, tseg_memory_size >> 10); - add_fixed_resources(dev, 7); - assign_resources(dev->link_list); } @@ -178,14 +161,7 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + mmconf_resource32(dev, 0xcf); } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index 4dada50..f3a0b86 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -24,6 +24,10 @@ config NORTHBRIDGE_INTEL_NEHALEM if NORTHBRIDGE_INTEL_NEHALEM +config MMCONF_BUS_NUMBER + int + default 64 + config CBFS_SIZE hex default 0x100000 diff --git a/src/northbridge/intel/nehalem/bootblock.c b/src/northbridge/intel/nehalem/bootblock.c index 8382205..1ffad12 100644 --- a/src/northbridge/intel/nehalem/bootblock.c +++ b/src/northbridge/intel/nehalem/bootblock.c @@ -2,6 +2,7 @@ static void bootblock_northbridge_init(void) { + /* FIXME: Is the allocation for 64 or 256 bus. */ pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x50, DEFAULT_PCIEXBAR | 1); pci_io_write_config32(PCI_DEV(0xff, 0x00, 1), 0x54, 0); } diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index c78b397..15f2aab 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -71,6 +71,10 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "northbridge/intel/sandybridge/bootblock.c" +config MMCONF_BUS_NUMBER + int + default 64 + if USE_NATIVE_RAMINIT config DCACHE_RAM_BASE diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index fe1a07c..a86672b 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -61,18 +61,18 @@ int bridge_silicon_revision(void) static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_size_k = 384; -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; *base = 0; - *len = 0; dev = dev_find_slot(0, PCI_DEVFN(0, 0)); if (!dev) return 0; + /* FIXME: 64bit BAR here. */ pciexbar_reg = pci_read_config32(dev, PCIEXBAR); if (!(pciexbar_reg & (1 << 0))) @@ -81,16 +81,13 @@ static int get_pcie_bar(u32 *base, u32 *len) switch ((pciexbar_reg >> 1) & 3) { case 0: // 256MB *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: // 128M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: // 64M *base = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; } return 0; @@ -98,21 +95,8 @@ static int get_pcie_bar(u32 *base, u32 *len) static void add_fixed_resources(struct device *dev, int index) { - struct resource *resource; - u32 pcie_config_base, pcie_config_size; - mmio_resource(dev, index++, uma_memory_base >> 10, uma_memory_size >> 10); - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } - mmio_resource(dev, index++, legacy_hole_base_k, (0xc0000 >> 10) - legacy_hole_base_k); reserved_ram_resource(dev, index++, 0xc0000 >> 10, @@ -276,24 +260,17 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses; pci_dev_read_resources(dev); - /* So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ - resource = new_resource(dev, 0xcf); - resource->base = DEFAULT_PCIEXBAR; - resource->size = 64 * 1024 * 1024; /* 64MB hard coded PCIe config space */ - resource->flags = - IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED | - IORESOURCE_ASSIGNED; - printk(BIOS_DEBUG, "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 0, pcie_config_base, buses); + } } static void mc_set_resources(device_t dev) diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 73d40ad..4b1e6cc 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -33,6 +33,10 @@ config MMCONF_BASE_ADDRESS hex default 0xe0000000 +config MMCONF_BUS_NUMBER + int + default 256 + config VGA_BIOS_ID string default "1106,7122" diff --git a/src/northbridge/via/vx900/northbridge.c b/src/northbridge/via/vx900/northbridge.c index a4a8ece..ffeaada0 100644 --- a/src/northbridge/via/vx900/northbridge.c +++ b/src/northbridge/via/vx900/northbridge.c @@ -297,10 +297,7 @@ static void vx900_read_resources(device_t dev) /* Now do the same for our MMCONF * We always run with MMCONF enabled. We need to access the extended * config space when configuring PCI-Express links */ - res = new_resource(dev, idx++); - res->size = 256 * MiB; - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + mmconf_resource32(dev, idx++); pci_domain_read_resources(dev); } diff --git a/src/soc/intel/fsp_baytrail/northcluster.c b/src/soc/intel/fsp_baytrail/northcluster.c index bf1a388..c60ea35 100644 --- a/src/soc/intel/fsp_baytrail/northcluster.c +++ b/src/soc/intel/fsp_baytrail/northcluster.c @@ -113,18 +113,6 @@ static int get_pcie_bar(u32 *base, u32 *len) static int add_fixed_resources(struct device *dev, int index) { struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x " - "size=0x%x\n", pcie_config_base, pcie_config_size); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } resource = new_resource(dev, index++); /* Local APIC */ resource->base = LAPIC_DEFAULT_BASE; diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig index 2456df7..abdee44 100644 --- a/src/soc/intel/sch/Kconfig +++ b/src/soc/intel/sch/Kconfig @@ -28,6 +28,10 @@ config BOOTBLOCK_NORTHBRIDGE_INIT string default "soc/intel/sch/bootblock.c" +config MMCONF_BUS_NUMBER + int + default 256 + config VGA_BIOS_ID string default "8086,8108" diff --git a/src/soc/intel/sch/northbridge.c b/src/soc/intel/sch/northbridge.c index 390a0bc..07b17c0 100644 --- a/src/soc/intel/sch/northbridge.c +++ b/src/soc/intel/sch/northbridge.c @@ -27,7 +27,7 @@ #include <arch/acpi.h> #include "sch.h" -static int get_pcie_bar(u32 *base, u32 *len) +static int get_pcie_bar(u32 *base) { device_t dev; u32 pciexbar_reg; @@ -50,18 +50,15 @@ static int get_pcie_bar(u32 *base, u32 *len) case 0: /* 256MB */ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28)); - *len = 256 * 1024 * 1024; - return 1; + return 256; case 1: /* 128M */ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | (1 << 27)); - *len = 128 * 1024 * 1024; - return 1; + return 128; case 2: /* 64M */ *base = pciexbar_reg & ((1 << 31) | (1 << 30) | (1 << 29) | (1 << 28) | (1 << 27) | (1 << 26)); - *len = 64 * 1024 * 1024; - return 1; + return 64; } return 0; @@ -70,16 +67,6 @@ static int get_pcie_bar(u32 *base, u32 *len) static void add_fixed_resources(struct device *dev, int index) { struct resource *resource; - u32 pcie_config_base, pcie_config_size; - - if (get_pcie_bar(&pcie_config_base, &pcie_config_size)) { - printk(BIOS_DEBUG, "Adding PCIe config bar\n"); - resource = new_resource(dev, index++); - resource->base = (resource_t) pcie_config_base; - resource->size = (resource_t) pcie_config_size; - resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - } printk(BIOS_DEBUG, "Adding CMC shadow area\n"); resource = new_resource(dev, index++); @@ -198,28 +185,20 @@ static struct device_operations pci_domain_ops = { static void mc_read_resources(device_t dev) { - struct resource *resource; + u32 pcie_config_base; + int buses; pci_dev_read_resources(dev); /* - * So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - - /* * We use 0xcf as an unused index for our PCIe bar so that we find * it again. */ - resource = new_resource(dev, 0xcf); - resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | - IORESOURCE_STORED | IORESOURCE_ASSIGNED; - get_pcie_bar((u32 *)&resource->base, (u32 *)&resource->size); - printk(BIOS_DEBUG, - "Adding PCIe enhanced config space BAR 0x%08lx-0x%08lx.\n", - (unsigned long)(resource->base), - (unsigned long)(resource->base + resource->size)); + buses = get_pcie_bar(&pcie_config_base); + if (buses) { + struct resource *resource = new_resource(dev, 0xcf); + mmconf_resource_init(resource, 0, pcie_config_base, buses); + } } static void mc_set_resources(device_t dev)

1 0

New patch to review for coreboot: Flip MMCONF_SUPPORT_DEFAULT to enabled
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17694 -gerrit commit 467b0176851d3b2f9a1e2a7aa78f2fa09180da71 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:46:56 2016 +0200 Flip MMCONF_SUPPORT_DEFAULT to enabled Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/agesa/family10/Kconfig | 1 - src/cpu/amd/agesa/family12/Kconfig | 1 - src/cpu/amd/agesa/family14/Kconfig | 1 - src/cpu/amd/agesa/family15/Kconfig | 1 - src/cpu/amd/agesa/family15rl/Kconfig | 1 - src/cpu/amd/agesa/family15tn/Kconfig | 1 - src/cpu/amd/agesa/family16kb/Kconfig | 1 - src/cpu/amd/family_10h-family_15h/Kconfig | 1 - src/cpu/amd/geode_gx2/Kconfig | 1 + src/cpu/amd/geode_lx/Kconfig | 1 + src/cpu/amd/pi/00630F01/Kconfig | 1 - src/cpu/amd/pi/00660F01/Kconfig | 1 - src/cpu/amd/pi/00670F00/Kconfig | 1 - src/cpu/amd/pi/00730F01/Kconfig | 1 - src/device/Kconfig | 4 ++-- src/mainboard/emulation/qemu-i440fx/Kconfig | 1 + src/mainboard/emulation/qemu-q35/Kconfig | 1 - src/northbridge/amd/amdk8/Kconfig | 1 + src/northbridge/intel/e7505/Kconfig | 1 + src/northbridge/intel/fsp_rangeley/Kconfig | 1 - src/northbridge/intel/fsp_sandybridge/Kconfig | 2 -- src/northbridge/intel/gm45/Kconfig | 1 - src/northbridge/intel/haswell/Kconfig | 1 - src/northbridge/intel/i3100/Kconfig | 1 + src/northbridge/intel/i440bx/Kconfig | 1 + src/northbridge/intel/i5000/Kconfig | 1 - src/northbridge/intel/i82810/Kconfig | 1 + src/northbridge/intel/i82830/Kconfig | 1 + src/northbridge/intel/i855/Kconfig | 1 + src/northbridge/intel/i945/Kconfig | 1 - src/northbridge/intel/nehalem/Kconfig | 1 - src/northbridge/intel/pineview/Kconfig | 1 - src/northbridge/intel/sandybridge/Kconfig | 2 -- src/northbridge/intel/x4x/Kconfig | 1 - src/northbridge/via/cn700/Kconfig | 1 + src/northbridge/via/cx700/Kconfig | 1 + src/northbridge/via/vx800/Kconfig | 1 + src/northbridge/via/vx900/Kconfig | 1 - src/soc/intel/apollolake/Kconfig | 1 - src/soc/intel/baytrail/Kconfig | 1 - src/soc/intel/braswell/Kconfig | 1 - src/soc/intel/broadwell/Kconfig | 1 - src/soc/intel/fsp_baytrail/Kconfig | 1 - src/soc/intel/fsp_broadwell_de/Kconfig | 1 - src/soc/intel/sch/Kconfig | 1 - src/soc/intel/skylake/Kconfig | 1 - 46 files changed, 15 insertions(+), 36 deletions(-) diff --git a/src/cpu/amd/agesa/family10/Kconfig b/src/cpu/amd/agesa/family10/Kconfig index 6bb8d43..b1076e1 100644 --- a/src/cpu/amd/agesa/family10/Kconfig +++ b/src/cpu/amd/agesa/family10/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA_FAMILY10 bool select CPU_AMD_MODEL_10XXX - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY10 diff --git a/src/cpu/amd/agesa/family12/Kconfig b/src/cpu/amd/agesa/family12/Kconfig index 8e4c7ba..fa9cd5f 100644 --- a/src/cpu/amd/agesa/family12/Kconfig +++ b/src/cpu/amd/agesa/family12/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY12 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY12 diff --git a/src/cpu/amd/agesa/family14/Kconfig b/src/cpu/amd/agesa/family14/Kconfig index 7be63f5..c539d27 100644 --- a/src/cpu/amd/agesa/family14/Kconfig +++ b/src/cpu/amd/agesa/family14/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY14 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY14 diff --git a/src/cpu/amd/agesa/family15/Kconfig b/src/cpu/amd/agesa/family15/Kconfig index 22e4d8c..3f13b3e 100644 --- a/src/cpu/amd/agesa/family15/Kconfig +++ b/src/cpu/amd/agesa/family15/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY15 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15 diff --git a/src/cpu/amd/agesa/family15rl/Kconfig b/src/cpu/amd/agesa/family15rl/Kconfig index b916e2c..85087ef 100644 --- a/src/cpu/amd/agesa/family15rl/Kconfig +++ b/src/cpu/amd/agesa/family15rl/Kconfig @@ -16,7 +16,6 @@ config CPU_AMD_AGESA_FAMILY15_RL bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_RL diff --git a/src/cpu/amd/agesa/family15tn/Kconfig b/src/cpu/amd/agesa/family15tn/Kconfig index 1f41560..1cc77b8 100644 --- a/src/cpu/amd/agesa/family15tn/Kconfig +++ b/src/cpu/amd/agesa/family15tn/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY15_TN bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY15_TN diff --git a/src/cpu/amd/agesa/family16kb/Kconfig b/src/cpu/amd/agesa/family16kb/Kconfig index 3f65055..0cdf55a 100644 --- a/src/cpu/amd/agesa/family16kb/Kconfig +++ b/src/cpu/amd/agesa/family16kb/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_AGESA_FAMILY16_KB bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_AGESA_FAMILY16_KB diff --git a/src/cpu/amd/family_10h-family_15h/Kconfig b/src/cpu/amd/family_10h-family_15h/Kconfig index fda7fc8..95338df 100644 --- a/src/cpu/amd/family_10h-family_15h/Kconfig +++ b/src/cpu/amd/family_10h-family_15h/Kconfig @@ -6,7 +6,6 @@ config CPU_AMD_MODEL_10XXX select ARCH_RAMSTAGE_X86_32 select SSE select SSE2 - select MMCONF_SUPPORT_DEFAULT select TSC_SYNC_LFENCE select UDELAY_LAPIC select HAVE_MONOTONIC_TIMER diff --git a/src/cpu/amd/geode_gx2/Kconfig b/src/cpu/amd/geode_gx2/Kconfig index 51dece5..c7745ec 100644 --- a/src/cpu/amd/geode_gx2/Kconfig +++ b/src/cpu/amd/geode_gx2/Kconfig @@ -24,6 +24,7 @@ if CPU_AMD_GEODE_GX2 config CPU_SPECIFIC_OPTIONS def_bool y + select NO_MMCONF_SUPPORT config DCACHE_RAM_BASE hex diff --git a/src/cpu/amd/geode_lx/Kconfig b/src/cpu/amd/geode_lx/Kconfig index 3a01828..82a5d46 100644 --- a/src/cpu/amd/geode_lx/Kconfig +++ b/src/cpu/amd/geode_lx/Kconfig @@ -9,6 +9,7 @@ if CPU_AMD_GEODE_LX config CPU_SPECIFIC_OPTIONS def_bool y + select NO_MMCONF_SUPPORT select TSC_MONOTONIC_TIMER config DCACHE_RAM_BASE diff --git a/src/cpu/amd/pi/00630F01/Kconfig b/src/cpu/amd/pi/00630F01/Kconfig index 5c12ab6..910df58 100644 --- a/src/cpu/amd/pi/00630F01/Kconfig +++ b/src/cpu/amd/pi/00630F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00630F01 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00630F01 diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig index b38ea6c..aab0639 100644 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ b/src/cpu/amd/pi/00660F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00660F01 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00660F01 diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig index e47dfa3..b4ba450 100644 --- a/src/cpu/amd/pi/00670F00/Kconfig +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00670F00 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00670F00 diff --git a/src/cpu/amd/pi/00730F01/Kconfig b/src/cpu/amd/pi/00730F01/Kconfig index 83af181..ecbdb53 100644 --- a/src/cpu/amd/pi/00730F01/Kconfig +++ b/src/cpu/amd/pi/00730F01/Kconfig @@ -15,7 +15,6 @@ config CPU_AMD_PI_00730F01 bool - select MMCONF_SUPPORT_DEFAULT select X86_AMD_FIXED_MTRRS if CPU_AMD_PI_00730F01 diff --git a/src/device/Kconfig b/src/device/Kconfig index 693dfc5..48c45fe 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -221,11 +221,11 @@ if PCI config NO_MMCONF_SUPPORT bool - default !MMCONF_SUPPORT_DEFAULT + default n config MMCONF_SUPPORT_DEFAULT bool - default n + default !NO_MMCONF_SUPPORT config HYPERTRANSPORT_PLUGIN_SUPPORT bool diff --git a/src/mainboard/emulation/qemu-i440fx/Kconfig b/src/mainboard/emulation/qemu-i440fx/Kconfig index 1dba29d..9a65f70 100644 --- a/src/mainboard/emulation/qemu-i440fx/Kconfig +++ b/src/mainboard/emulation/qemu-i440fx/Kconfig @@ -3,6 +3,7 @@ if BOARD_EMULATION_QEMU_X86_I440FX config BOARD_SPECIFIC_OPTIONS # dummy def_bool y select CPU_QEMU_X86 + select NO_MMCONF_SUPPORT select SOUTHBRIDGE_INTEL_I82371EB select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 442356e..3000533 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -5,7 +5,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select CPU_QEMU_X86 select SOUTHBRIDGE_INTEL_I82801IX select IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS - select MMCONF_SUPPORT_DEFAULT # select HAVE_OPTION_TABLE # select HAVE_PIRQ_TABLE select HAVE_ACPI_TABLES diff --git a/src/northbridge/amd/amdk8/Kconfig b/src/northbridge/amd/amdk8/Kconfig index f1ee3c3..8a5dddf 100644 --- a/src/northbridge/amd/amdk8/Kconfig +++ b/src/northbridge/amd/amdk8/Kconfig @@ -15,6 +15,7 @@ config NORTHBRIDGE_AMD_AMDK8 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_DEBUG_CAR diff --git a/src/northbridge/intel/e7505/Kconfig b/src/northbridge/intel/e7505/Kconfig index c1faac0..702ba1c 100644 --- a/src/northbridge/intel/e7505/Kconfig +++ b/src/northbridge/intel/e7505/Kconfig @@ -20,6 +20,7 @@ if NORTHBRIDGE_INTEL_E7505 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/fsp_rangeley/Kconfig b/src/northbridge/intel/fsp_rangeley/Kconfig index 506a913..bc735264 100644 --- a/src/northbridge/intel/fsp_rangeley/Kconfig +++ b/src/northbridge/intel/fsp_rangeley/Kconfig @@ -17,7 +17,6 @@ config NORTHBRIDGE_INTEL_FSP_RANGELEY bool select CPU_INTEL_FSP_MODEL_406DX - select MMCONF_SUPPORT_DEFAULT if NORTHBRIDGE_INTEL_FSP_RANGELEY diff --git a/src/northbridge/intel/fsp_sandybridge/Kconfig b/src/northbridge/intel/fsp_sandybridge/Kconfig index 96b2df5..89326b4 100644 --- a/src/northbridge/intel/fsp_sandybridge/Kconfig +++ b/src/northbridge/intel/fsp_sandybridge/Kconfig @@ -18,13 +18,11 @@ config NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE bool select CPU_INTEL_FSP_MODEL_206AX select INTEL_GMA_ACPI - select MMCONF_SUPPORT_DEFAULT config NORTHBRIDGE_INTEL_FSP_IVYBRIDGE bool select CPU_INTEL_FSP_MODEL_306AX select INTEL_GMA_ACPI - select MMCONF_SUPPORT_DEFAULT if NORTHBRIDGE_INTEL_FSP_IVYBRIDGE || NORTHBRIDGE_INTEL_FSP_SANDYBRIDGE diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 80447d5..ca1f9c6 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_GM45 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_EDID select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/haswell/Kconfig b/src/northbridge/intel/haswell/Kconfig index db51dd2..4fc117d 100644 --- a/src/northbridge/intel/haswell/Kconfig +++ b/src/northbridge/intel/haswell/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_INTEL_HASWELL bool select CPU_INTEL_HASWELL - select MMCONF_SUPPORT_DEFAULT select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select INTEL_DDI select INTEL_DP diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 2260664..7d4f4e5 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I3100 bool + select NO_MMCONF_SUPPORT select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i440bx/Kconfig b/src/northbridge/intel/i440bx/Kconfig index 3f574a4..36d4754 100644 --- a/src/northbridge/intel/i440bx/Kconfig +++ b/src/northbridge/intel/i440bx/Kconfig @@ -15,6 +15,7 @@ config NORTHBRIDGE_INTEL_I440BX bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i5000/Kconfig b/src/northbridge/intel/i5000/Kconfig index 9fde6cb..67a21fc 100644 --- a/src/northbridge/intel/i5000/Kconfig +++ b/src/northbridge/intel/i5000/Kconfig @@ -15,7 +15,6 @@ config NORTHBRIDGE_INTEL_I5000 bool - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/i82810/Kconfig b/src/northbridge/intel/i82810/Kconfig index 428505c..7d8c46b 100644 --- a/src/northbridge/intel/i82810/Kconfig +++ b/src/northbridge/intel/i82810/Kconfig @@ -15,6 +15,7 @@ config NORTHBRIDGE_INTEL_I82810 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i82830/Kconfig b/src/northbridge/intel/i82830/Kconfig index 344dfed..d0bee8f 100644 --- a/src/northbridge/intel/i82830/Kconfig +++ b/src/northbridge/intel/i82830/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I82830 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT select UDELAY_IO diff --git a/src/northbridge/intel/i855/Kconfig b/src/northbridge/intel/i855/Kconfig index 25a1fd5..a9439dc 100644 --- a/src/northbridge/intel/i855/Kconfig +++ b/src/northbridge/intel/i855/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_INTEL_I855 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index d22451a..8f59be5 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -20,7 +20,6 @@ if NORTHBRIDGE_INTEL_I945 config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select VGA diff --git a/src/northbridge/intel/nehalem/Kconfig b/src/northbridge/intel/nehalem/Kconfig index eee9405..4dada50 100644 --- a/src/northbridge/intel/nehalem/Kconfig +++ b/src/northbridge/intel/nehalem/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_INTEL_NEHALEM bool select CPU_INTEL_MODEL_2065X - select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_EDID select TSC_MONOTONIC_TIMER diff --git a/src/northbridge/intel/pineview/Kconfig b/src/northbridge/intel/pineview/Kconfig index 188db6d..5b34fb2 100644 --- a/src/northbridge/intel/pineview/Kconfig +++ b/src/northbridge/intel/pineview/Kconfig @@ -21,7 +21,6 @@ if NORTHBRIDGE_INTEL_PINEVIEW config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y - select MMCONF_SUPPORT_DEFAULT select HAVE_DEBUG_RAM_SETUP select LAPIC_MONOTONIC_TIMER select LATE_CBMEM_INIT diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 7ca897e..c78b397 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -16,7 +16,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool - select MMCONF_SUPPORT_DEFAULT select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP @@ -25,7 +24,6 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE config NORTHBRIDGE_INTEL_IVYBRIDGE bool - select MMCONF_SUPPORT_DEFAULT select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 43c7b2a..57e93f9 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -22,7 +22,6 @@ if NORTHBRIDGE_INTEL_X4X config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy def_bool y select HAVE_DEBUG_RAM_SETUP - select MMCONF_SUPPORT_DEFAULT select VGA select INTEL_GMA_ACPI select EARLY_CBMEM_INIT diff --git a/src/northbridge/via/cn700/Kconfig b/src/northbridge/via/cn700/Kconfig index 1889705..98af4e8 100644 --- a/src/northbridge/via/cn700/Kconfig +++ b/src/northbridge/via/cn700/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_VIA_CN700 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select LATE_CBMEM_INIT diff --git a/src/northbridge/via/cx700/Kconfig b/src/northbridge/via/cx700/Kconfig index 03014eb..ec2c75b 100644 --- a/src/northbridge/via/cx700/Kconfig +++ b/src/northbridge/via/cx700/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_VIA_CX700 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_HARD_RESET diff --git a/src/northbridge/via/vx800/Kconfig b/src/northbridge/via/vx800/Kconfig index 9eb84fb..9bcb7cd 100644 --- a/src/northbridge/via/vx800/Kconfig +++ b/src/northbridge/via/vx800/Kconfig @@ -1,5 +1,6 @@ config NORTHBRIDGE_VIA_VX800 bool + select NO_MMCONF_SUPPORT select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select LATE_CBMEM_INIT diff --git a/src/northbridge/via/vx900/Kconfig b/src/northbridge/via/vx900/Kconfig index 182345e..73d40ad 100644 --- a/src/northbridge/via/vx900/Kconfig +++ b/src/northbridge/via/vx900/Kconfig @@ -21,7 +21,6 @@ config NORTHBRIDGE_VIA_VX900 select HAVE_DEBUG_RAM_SETUP select HAVE_DEBUG_SMBUS select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select LATE_CBMEM_INIT if NORTHBRIDGE_VIA_VX900 diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 092102c..6769af0 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -32,7 +32,6 @@ config CPU_SPECIFIC_OPTIONS select GENERIC_GPIO_LIB select HAVE_INTEL_FIRMWARE select HAVE_SMI_HANDLER - select MMCONF_SUPPORT_DEFAULT select MRC_SETTINGS_PROTECT select NO_FIXED_XIP_ROM_SIZE select NO_XIP_EARLY_STAGES diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 5fd88a5..2d07c99 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -18,7 +18,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select HAVE_SMI_HANDLER select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index b3ca1b8..ac4a2ae 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE select RELOCATABLE_MODULES select PARALLEL_MP diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 2c62d29..75cd831 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -23,7 +23,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_HARD_RESET select HAVE_USBDEBUG select IOAPIC - select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select RELOCATABLE_RAMSTAGE select REG_SCRIPT diff --git a/src/soc/intel/fsp_baytrail/Kconfig b/src/soc/intel/fsp_baytrail/Kconfig index 6260630..689e625 100644 --- a/src/soc/intel/fsp_baytrail/Kconfig +++ b/src/soc/intel/fsp_baytrail/Kconfig @@ -30,7 +30,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_RAMSTAGE_X86_32 select HAVE_SMI_HANDLER select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP select REG_SCRIPT diff --git a/src/soc/intel/fsp_broadwell_de/Kconfig b/src/soc/intel/fsp_broadwell_de/Kconfig index 72979de..8442963 100644 --- a/src/soc/intel/fsp_broadwell_de/Kconfig +++ b/src/soc/intel/fsp_broadwell_de/Kconfig @@ -13,7 +13,6 @@ config CPU_SPECIFIC_OPTIONS select ARCH_ROMSTAGE_X86_32 select ARCH_RAMSTAGE_X86_32 select HAVE_HARD_RESET - select MMCONF_SUPPORT_DEFAULT select RELOCATABLE_MODULES select PARALLEL_MP select SMP diff --git a/src/soc/intel/sch/Kconfig b/src/soc/intel/sch/Kconfig index ed3e003..2456df7 100644 --- a/src/soc/intel/sch/Kconfig +++ b/src/soc/intel/sch/Kconfig @@ -15,7 +15,6 @@ config SOC_INTEL_SCH bool - select MMCONF_SUPPORT_DEFAULT select LATE_CBMEM_INIT select INTEL_GMA_ACPI select SOUTHBRIDGE_INTEL_COMMON diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 1778dae..24c2e30 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -28,7 +28,6 @@ config CPU_SPECIFIC_OPTIONS select HAVE_MONOTONIC_TIMER select HAVE_SMI_HANDLER select IOAPIC - select MMCONF_SUPPORT_DEFAULT select NO_FIXED_XIP_ROM_SIZE select MRC_SETTINGS_PROTECT select PARALLEL_MP

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New patch to review for coreboot: PCI ops: MMCONF_SUPPORT_DEFAULT is permanent choice
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17693 -gerrit commit e810bd9f7929abf59e85925f425decaaed0d9bc5 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 22:08:18 2016 +0200 PCI ops: MMCONF_SUPPORT_DEFAULT is permanent choice Doing PCI config operations via MMIO window is here to stay and we do not support the option of making it disabled. Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/Kconfig | 9 --------- src/arch/x86/Makefile.inc | 2 +- src/arch/x86/include/arch/pci_io_cfg.h | 2 +- src/arch/x86/include/arch/pci_mmio_cfg.h | 8 ++++---- src/arch/x86/include/arch/pci_ops.h | 3 --- src/device/Kconfig | 17 ++++++++++++----- src/device/pci_ops.c | 7 +++---- src/mainboard/google/beltino/Kconfig | 1 - src/northbridge/amd/amdfam10/northbridge.c | 25 ++++++++++++------------- src/northbridge/amd/pi/00630F01/northbridge.c | 3 +-- src/northbridge/amd/pi/00660F01/northbridge.c | 3 +-- src/northbridge/amd/pi/00670F00/northbridge.c | 3 +-- src/northbridge/amd/pi/00730F01/northbridge.c | 3 +-- src/northbridge/via/vx900/early_vx900.c | 3 +-- src/southbridge/intel/i82801gx/i82801gx.c | 4 ---- src/southbridge/intel/i82801ix/i82801ix.c | 4 ---- 16 files changed, 38 insertions(+), 59 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index 5cd0254..a22a2b3 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -550,15 +550,6 @@ config MAX_CPUS int default 1 -config MMCONF_SUPPORT_DEFAULT - bool - default n - -config MMCONF_SUPPORT - bool - default y if MMCONF_SUPPORT_DEFAULT - default n - source "src/console/Kconfig" config HAVE_ACPI_RESUME diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index c4bb1cc..848e32c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -332,7 +332,7 @@ ramstage-y += memset.c ramstage-$(CONFIG_X86_TOP4G_BOOTMEDIA_MAP) += mmap_boot.c ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c ramstage-y += pci_ops_conf1.c -ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c +ramstage-$(CONFIG_MMCONF_SUPPORT_DEFAULT) += pci_ops_mmconf.c ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c ramstage-y += tables.c diff --git a/src/arch/x86/include/arch/pci_io_cfg.h b/src/arch/x86/include/arch/pci_io_cfg.h index b838535..47f7067 100644 --- a/src/arch/x86/include/arch/pci_io_cfg.h +++ b/src/arch/x86/include/arch/pci_io_cfg.h @@ -94,7 +94,7 @@ void pci_io_write_config32(pci_devfn_t dev, unsigned where, uint32_t value) outl(value, 0xCFC); } -#if !CONFIG_MMCONF_SUPPORT_DEFAULT +#if IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT) #define pci_read_config8 pci_io_read_config8 #define pci_read_config16 pci_io_read_config16 #define pci_read_config32 pci_io_read_config32 diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index 8caff5a..65cc7be 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -18,7 +18,8 @@ #include <arch/io.h> -#if CONFIG_MMCONF_SUPPORT +#if IS_ENABLED(CONFIG_MMCONF_SUPPORT_DEFAULT) + #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static inline __attribute__ ((always_inline)) @@ -69,7 +70,6 @@ void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) write32(addr, value); } -#if CONFIG_MMCONF_SUPPORT_DEFAULT #define pci_read_config8 pci_mmio_read_config8 #define pci_read_config16 pci_mmio_read_config16 #define pci_read_config32 pci_mmio_read_config32 @@ -77,7 +77,7 @@ void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) #define pci_write_config8 pci_mmio_write_config8 #define pci_write_config16 pci_mmio_write_config16 #define pci_write_config32 pci_mmio_write_config32 -#endif -#endif /* CONFIG_MMCONF_SUPPORT */ +#endif /* CONFIG_MMCONF_SUPPORT_DEFAULT */ + #endif /* _PCI_MMIO_CFG_H */ diff --git a/src/arch/x86/include/arch/pci_ops.h b/src/arch/x86/include/arch/pci_ops.h index b662170..1b245aa 100644 --- a/src/arch/x86/include/arch/pci_ops.h +++ b/src/arch/x86/include/arch/pci_ops.h @@ -17,10 +17,7 @@ #ifndef __SIMPLE_DEVICE__ extern const struct pci_bus_operations pci_cf8_conf1; - -#if CONFIG_MMCONF_SUPPORT extern const struct pci_bus_operations pci_ops_mmconf; -#endif const struct pci_bus_operations *pci_bus_default_ops(device_t dev); diff --git a/src/device/Kconfig b/src/device/Kconfig index fb0aaba..693dfc5 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -217,31 +217,38 @@ config PCI bool default n +if PCI + +config NO_MMCONF_SUPPORT + bool + default !MMCONF_SUPPORT_DEFAULT + +config MMCONF_SUPPORT_DEFAULT + bool + default n + config HYPERTRANSPORT_PLUGIN_SUPPORT bool - depends on PCI default n config PCIX_PLUGIN_SUPPORT bool - depends on PCI default y config CARDBUS_PLUGIN_SUPPORT bool - depends on PCI default y config AZALIA_PLUGIN_SUPPORT bool - depends on PCI default n config PCIEXP_PLUGIN_SUPPORT bool - depends on PCI default y +endif # PCI + if PCIEXP_PLUGIN_SUPPORT config PCIEXP_COMMON_CLOCK diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index 2f896d2..b6fc32d 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -22,11 +22,10 @@ const struct pci_bus_operations *pci_bus_default_ops(device_t dev) { -#if CONFIG_MMCONF_SUPPORT_DEFAULT + if (IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT)) + return &pci_cf8_conf1; + return &pci_ops_mmconf; -#else - return &pci_cf8_conf1; -#endif } static const struct pci_bus_operations *pci_bus_ops(struct bus *bus, struct device *dev) diff --git a/src/mainboard/google/beltino/Kconfig b/src/mainboard/google/beltino/Kconfig index 608523e..c430018 100644 --- a/src/mainboard/google/beltino/Kconfig +++ b/src/mainboard/google/beltino/Kconfig @@ -9,7 +9,6 @@ config BOARD_GOOGLE_BASEBOARD_BELTINO select HAVE_ACPI_TABLES select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME - select MMCONF_SUPPORT select HAVE_SMI_HANDLER select MAINBOARD_HAS_CHROMEOS select MAINBOARD_HAS_LPC_TPM diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index 5634441..605db3a 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -740,19 +740,18 @@ static void amdfam10_domain_read_resources(device_t dev) pci_domain_read_resources(dev); - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) { - struct resource *res = new_resource(dev, 0xc0010058); - res->base = CONFIG_MMCONF_BASE_ADDRESS; - res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ - res->align = log2(res->size); - res->gran = log2(res->size); - res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ - res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | - IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; - - /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ - ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); - } + /* We have MMCONF_SUPPORT_DEFAULT, create the resource window. */ + struct resource *res = new_resource(dev, 0xc0010058); + res->base = CONFIG_MMCONF_BASE_ADDRESS; + res->size = CONFIG_MMCONF_BUS_NUMBER * 1024 * 1024; /* Each bus needs 1M */ + res->align = log2(res->size); + res->gran = log2(res->size); + res->limit = 0xffffffffffffffffULL; /* 64-bit location allowed */ + res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE | + IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED; + + /* Reserve lower DRAM region to force PCI MMIO region to correct location above 0xefffffff */ + ram_resource(dev, 7, 0, rdmsr(TOP_MEM).lo >> 10); if (is_fam15h()) { enable_cc6 = 0; diff --git a/src/northbridge/amd/pi/00630F01/northbridge.c b/src/northbridge/amd/pi/00630F01/northbridge.c index fb115ff..4872db0 100644 --- a/src/northbridge/amd/pi/00630F01/northbridge.c +++ b/src/northbridge/amd/pi/00630F01/northbridge.c @@ -335,8 +335,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c index 115d760..4c1254c 100644 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ b/src/northbridge/amd/pi/00660F01/northbridge.c @@ -330,8 +330,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index ce0dde3..9a39410 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -330,8 +330,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 5b83721..44f91e2 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -338,8 +338,7 @@ static void read_resources(device_t dev) * It is not honored by the coreboot resource allocator if it is in * the CPU_CLUSTER. */ - if (IS_ENABLED(CONFIG_MMCONF_SUPPORT)) - enable_mmconf_resource(dev); + enable_mmconf_resource(dev); } static void set_resource(device_t dev, struct resource *resource, u32 nodeid) diff --git a/src/northbridge/via/vx900/early_vx900.c b/src/northbridge/via/vx900/early_vx900.c index eb5c79c..6e1bc23 100644 --- a/src/northbridge/via/vx900/early_vx900.c +++ b/src/northbridge/via/vx900/early_vx900.c @@ -40,14 +40,13 @@ void vx900_enable_pci_config_space(void) * accessed */ pci_io_write_config8(HOST_CTR, 0x4f, 0x01); -#if CONFIG_MMCONF_SUPPORT /* COOL, now enable MMCONF */ u8 reg8 = pci_io_read_config8(TRAF_CTR, 0x60); reg8 |= 3; pci_io_write_config8(TRAF_CTR, 0x60, reg8); + reg8 = CONFIG_MMCONF_BASE_ADDRESS >> 28; pci_io_write_config8(TRAF_CTR, 0x61, reg8); -#endif } /** diff --git a/src/southbridge/intel/i82801gx/i82801gx.c b/src/southbridge/intel/i82801gx/i82801gx.c index 6d97088..aab674b 100644 --- a/src/southbridge/intel/i82801gx/i82801gx.c +++ b/src/southbridge/intel/i82801gx/i82801gx.c @@ -20,10 +20,6 @@ #include "i82801gx.h" #include "sata.h" -#if !CONFIG_MMCONF_SUPPORT_DEFAULT -#error ICH7 requires CONFIG_MMCONF_SUPPORT_DEFAULT -#endif - void i82801gx_enable(device_t dev) { u32 reg32; diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index f02429a..0f3a08c 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -23,10 +23,6 @@ #include <console/console.h> #include "i82801ix.h" -#if !CONFIG_MMCONF_SUPPORT_DEFAULT -#error ICH9 requires CONFIG_MMCONF_SUPPORT_DEFAULT -#endif - typedef struct southbridge_intel_i82801ix_config config_t; static void i82801ix_enable_device(device_t dev)

1 0

New patch to review for coreboot: AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17692 -gerrit commit 20f0f8dcdad214b7fecd7178e607f9e3ecefeda0 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Thu Dec 1 21:47:50 2016 +0200 AMD fam10h-15h: MMCONF_SUPPORT_DEFAULT is already set It gets selected from CPU_AMD_MODEL10XXX. Change-Id: Iffab43edc1152b07ba2af6273d4b5eb94afe33ba Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/cpu/amd/car/cache_as_ram.inc | 2 +- src/mainboard/asus/kcma-d8/Kconfig | 1 - src/mainboard/asus/kfsn4-dre/Kconfig | 1 - src/mainboard/asus/kgpe-d16/Kconfig | 1 - src/mainboard/hp/dl165_g6_fam10/Kconfig | 1 - src/mainboard/tyan/s2912_fam10/Kconfig | 1 - src/northbridge/amd/amdfam10/Kconfig | 1 - 7 files changed, 1 insertion(+), 7 deletions(-) diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc index 5305603..fefb726 100644 --- a/src/cpu/amd/car/cache_as_ram.inc +++ b/src/cpu/amd/car/cache_as_ram.inc @@ -143,7 +143,7 @@ CAR_FAM10_out: CAR_FAM10_errata_applied: -#if CONFIG_MMCONF_SUPPORT +#if CONFIG_MMCONF_SUPPORT_DEFAULT #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF) #error "MMCONF_BASE_ADDRESS too big" #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF) diff --git a/src/mainboard/asus/kcma-d8/Kconfig b/src/mainboard/asus/kcma-d8/Kconfig index 6e84fa8..6d2e13f 100644 --- a/src/mainboard/asus/kcma-d8/Kconfig +++ b/src/mainboard/asus/kcma-d8/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT select SPI_FLASH select SPI_FLASH_WINBOND select HAVE_ACPI_RESUME diff --git a/src/mainboard/asus/kfsn4-dre/Kconfig b/src/mainboard/asus/kfsn4-dre/Kconfig index f40899d..96260ce 100644 --- a/src/mainboard/asus/kfsn4-dre/Kconfig +++ b/src/mainboard/asus/kfsn4-dre/Kconfig @@ -18,7 +18,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT select DRIVERS_I2C_W83793 select DRIVERS_XGI_Z9S select VGA diff --git a/src/mainboard/asus/kgpe-d16/Kconfig b/src/mainboard/asus/kgpe-d16/Kconfig index 19bf728..8e7a105 100644 --- a/src/mainboard/asus/kgpe-d16/Kconfig +++ b/src/mainboard/asus/kgpe-d16/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_2048 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT select SPI_FLASH select SPI_FLASH_WINBOND select MAINBOARD_HAS_LPC_TPM diff --git a/src/mainboard/hp/dl165_g6_fam10/Kconfig b/src/mainboard/hp/dl165_g6_fam10/Kconfig index a1f55f4..0222de6 100644 --- a/src/mainboard/hp/dl165_g6_fam10/Kconfig +++ b/src/mainboard/hp/dl165_g6_fam10/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT config MAINBOARD_DIR string diff --git a/src/mainboard/tyan/s2912_fam10/Kconfig b/src/mainboard/tyan/s2912_fam10/Kconfig index 861c2e5..9b36df6 100644 --- a/src/mainboard/tyan/s2912_fam10/Kconfig +++ b/src/mainboard/tyan/s2912_fam10/Kconfig @@ -17,7 +17,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select LIFT_BSP_APIC_ID select BOARD_ROMSIZE_KB_1024 select ENABLE_APIC_EXT_ID - select MMCONF_SUPPORT_DEFAULT config MAINBOARD_DIR string diff --git a/src/northbridge/amd/amdfam10/Kconfig b/src/northbridge/amd/amdfam10/Kconfig index 0c6d289..b414d91 100644 --- a/src/northbridge/amd/amdfam10/Kconfig +++ b/src/northbridge/amd/amdfam10/Kconfig @@ -20,7 +20,6 @@ config NORTHBRIDGE_AMD_AMDFAM10 select HAVE_DEBUG_SMBUS select HAVE_DEBUG_CAR select HYPERTRANSPORT_PLUGIN_SUPPORT - select MMCONF_SUPPORT select PCIEXP_ASPM select PCIEXP_COMMON_CLOCK select PCIEXP_CLK_PM

1 0

New patch to review for coreboot: PCI ops: Remove pci_mmio_xx() in ramstage
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17691 -gerrit commit bc30f42d005ddb8124deabf3f1dc6a27c13da155 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Dec 2 08:06:55 2016 +0200 PCI ops: Remove pci_mmio_xx() in ramstage MMCONF operations are already the default so these would never be used. Change-Id: I671f3d2847742e400bc4ecfccc088e3b79d43070 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/device/pci_ops.c | 45 -------------------------------------------- src/include/device/pci_ops.h | 8 -------- 2 files changed, 53 deletions(-) diff --git a/src/device/pci_ops.c b/src/device/pci_ops.c index ab72405..2f896d2 100644 --- a/src/device/pci_ops.c +++ b/src/device/pci_ops.c @@ -118,48 +118,3 @@ void pci_write_config32(struct device *dev, unsigned int where, u32 val) pci_bus_ops(pbus, dev)->write32(pbus, dev->bus->secondary, dev->path.pci.devfn, where, val); } - -#if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(struct device *dev, unsigned int where) -{ - struct bus *pbus = get_pbus(dev); - return pci_ops_mmconf.read8(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); -} - -u16 pci_mmio_read_config16(struct device *dev, unsigned int where) -{ - struct bus *pbus = get_pbus(dev); - return pci_ops_mmconf.read16(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); -} - -u32 pci_mmio_read_config32(struct device *dev, unsigned int where) -{ - struct bus *pbus = get_pbus(dev); - return pci_ops_mmconf.read32(pbus, dev->bus->secondary, - dev->path.pci.devfn, where); -} - -void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val) -{ - struct bus *pbus = get_pbus(dev); - pci_ops_mmconf.write8(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); -} - -void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val) -{ - struct bus *pbus = get_pbus(dev); - pci_ops_mmconf.write16(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); -} - -void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val) -{ - struct bus *pbus = get_pbus(dev); - pci_ops_mmconf.write32(pbus, dev->bus->secondary, dev->path.pci.devfn, - where, val); -} - -#endif diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index 920475a..3310e10 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -13,14 +13,6 @@ void pci_write_config8(struct device *dev, unsigned int where, u8 val); void pci_write_config16(struct device *dev, unsigned int where, u16 val); void pci_write_config32(struct device *dev, unsigned int where, u32 val); -#if CONFIG_MMCONF_SUPPORT -u8 pci_mmio_read_config8(struct device *dev, unsigned int where); -u16 pci_mmio_read_config16(struct device *dev, unsigned int where); -u32 pci_mmio_read_config32(struct device *dev, unsigned int where); -void pci_mmio_write_config8(struct device *dev, unsigned int where, u8 val); -void pci_mmio_write_config16(struct device *dev, unsigned int where, u16 val); -void pci_mmio_write_config32(struct device *dev, unsigned int where, u32 val); -#endif #endif #endif /* PCI_OPS_H */

1 0

New patch to review for coreboot: PCI ops: Define read-modify-write routines globally
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17690 -gerrit commit 9c58a5e0c80703ea8ee1ee29040e1c2d5de6865a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:53:59 2013 +0300 PCI ops: Define read-modify-write routines globally Change-Id: I7d64f46bb4ec3229879a60159efc8a8408512acd Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 33 ++++++++++ src/device/pciexp_device.c | 26 +++----- src/soc/intel/broadwell/pcie.c | 113 +++++++++++++-------------------- src/soc/intel/broadwell/romstage/pch.c | 16 +---- src/southbridge/intel/lynxpoint/pcie.c | 107 ++++++++++++------------------- 5 files changed, 131 insertions(+), 164 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 0d4be86..0d1cadf 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -374,4 +374,37 @@ void pci_or_config32(device_t dev, unsigned int where, u32 ormask) pci_write_config32(dev, where, value | ormask); } +static inline __attribute__ ((always_inline)) +void pci_update_config8(device_t dev, int reg, u8 mask, u8 or) +{ + u8 reg8; + + reg8 = pci_read_config8(dev, reg); + reg8 &= mask; + reg8 |= or; + pci_write_config8(dev, reg, reg8); +} + +static inline __attribute__ ((always_inline)) +void pci_update_config16(device_t dev, int reg, u16 mask, u16 or) +{ + u16 reg16; + + reg16 = pci_read_config16(dev, reg); + reg16 &= mask; + reg16 |= or; + pci_write_config16(dev, reg, reg16); +} + +static inline __attribute__ ((always_inline)) +void pci_update_config32(device_t dev, int reg, u32 mask, u32 or) +{ + u32 reg32; + + reg32 = pci_read_config32(dev, reg); + reg32 &= mask; + reg32 |= or; + pci_write_config32(dev, reg, reg32); +} + #endif diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 7228249..0c36538 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -122,16 +122,6 @@ static void pciexp_enable_clock_power_pm(device_t endp, unsigned endp_cap) pci_write_config16(endp, endp_cap + PCI_EXP_LNKCTL, lnkctl); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - static void pciexp_config_max_latency(device_t root, device_t dev) { unsigned int cap; @@ -150,7 +140,7 @@ static void pciexp_enable_ltr(device_t dev) dev_path(dev)); return; } - pcie_update_cfg(dev, cap + 0x28, ~(1 << 10), 1 << 10); + pci_update_config32(dev, cap + 0x28, ~(1 << 10), 1 << 10); } static unsigned char pciexp_L1_substate_cal(device_t dev, unsigned int endp_cap, @@ -226,26 +216,26 @@ static void pciexp_L1_substate_commit(device_t root, device_t dev, pciexp_enable_ltr(root); - pcie_update_cfg(root, root_cap + 0x08, ~0xff00, + pci_update_config32(root, root_cap + 0x08, ~0xff00, (comm_mode_rst_time << 8)); - pcie_update_cfg(root, root_cap + 0x0c , 0xffffff04, + pci_update_config32(root, root_cap + 0x0c , 0xffffff04, (endp_power_on_value << 3) | (power_on_scale)); - pcie_update_cfg(root, root_cap + 0x08, ~0xe3ff0000, + pci_update_config32(root, root_cap + 0x08, ~0xe3ff0000, (1 << 21) | (1 << 23) | (1 << 30)); - pcie_update_cfg(root, root_cap + 0x08, ~0x1f, + pci_update_config32(root, root_cap + 0x08, ~0x1f, L1SubStateSupport); for (dev_t = dev; dev_t; dev_t = dev_t->sibling) { - pcie_update_cfg(dev_t, end_cap + 0x0c , 0xffffff04, + pci_update_config32(dev_t, end_cap + 0x0c , 0xffffff04, (endp_power_on_value << 3) | (power_on_scale)); - pcie_update_cfg(dev_t, end_cap + 0x08, ~0xe3ff0000, + pci_update_config32(dev_t, end_cap + 0x08, ~0xe3ff0000, (1 << 21) | (1 << 23) | (1 << 30)); - pcie_update_cfg(dev_t, end_cap + 0x08, ~0x1f, + pci_update_config32(dev_t, end_cap + 0x08, ~0x1f, L1SubStateSupport); pciexp_enable_ltr(dev_t); diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 355e17a..c3d9e13 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -30,9 +30,6 @@ #include <soc/cpu.h> #include <delay.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); - /* Low Power variant has 6 root ports. */ #define NUM_ROOT_PORTS 6 @@ -129,14 +126,14 @@ static void root_port_init_config(device_t dev) rpc.num_ports = NUM_ROOT_PORTS; rpc.gbe_port = -1; /* RP0 f5[3:0] = 0101b*/ - pcie_update_cfg8(dev, 0xf5, ~0xa, 0x5); + pci_update_config8(dev, 0xf5, ~0xa, 0x5); pcie_iosf_port_grant_count(dev); rpc.pin_ownership = pci_read_config32(dev, 0x410); root_port_config_update_gbe_port(); - pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); if (dev->chip_info != NULL) { config_t *config = dev->chip_info; rpc.coalesce = config->pcie_port_coalesce; @@ -168,7 +165,7 @@ static void root_port_init_config(device_t dev) break; } - pcie_update_cfg(dev, 0x418, 0, 0x02000430); + pci_update_config32(dev, 0x418, 0, 0x02000430); if (root_port_is_first(dev)) { /* @@ -227,23 +224,23 @@ static void pcie_enable_clock_gating(void) if (!dev->enabled) { /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || rp == 6) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); - pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pcie_update_cfg(dev, 0x420, ~(1 << 31), (1 << 31)); + pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31)); /* Per-Port CLKREQ# handling. */ if (gpio_is_native(18 + rp - 1)) - pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); + pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Enable static clock gating. */ if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } else if (rp == 5 || rp == 6) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } continue; } @@ -251,17 +248,17 @@ static void pcie_enable_clock_gating(void) enabled_ports++; /* Enable dynamic clock gating. */ - pcie_update_cfg8(dev, 0xe1, 0xfc, 0x03); - pcie_update_cfg8(dev, 0xe2, ~(1 << 6), (1 << 6)); - pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2)); + pci_update_config8(dev, 0xe1, 0xfc, 0x03); + pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6)); + pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); /* Update PECR1 register. */ - pcie_update_cfg8(dev, 0xe8, ~0, 3); + pci_update_config8(dev, 0xe8, ~0, 3); if (is_broadwell) { - pcie_update_cfg(dev, 0x324, ~((1 << 5) | (1 << 14)), + pci_update_config32(dev, 0x324, ~((1 << 5) | (1 << 14)), ((1 << 5) | (1 << 14))); } else { - pcie_update_cfg(dev, 0x324, ~(1 << 5), (1 << 5)); + pci_update_config32(dev, 0x324, ~(1 << 5), (1 << 5)); } /* Per-Port CLKREQ# handling. */ if (gpio_is_native(18 + rp - 1)) @@ -269,18 +266,18 @@ static void pcie_enable_clock_gating(void) * In addition to D28Fx PCICFG 420h[30:29] = 11b, * set 420h[17] = 0b and 420[0] = 1b for L1 SubState. */ - pcie_update_cfg(dev, 0x420, ~0x20000, (3 << 29) | 1); + pci_update_config32(dev, 0x420, ~0x20000, (3 << 29) | 1); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || rp == 6) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); /* CLKREQ# VR Idle Enable */ RCBA32_OR(0x2b1c, (1 << (16 + i))); } if (!enabled_ports) - pcie_update_cfg8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); + pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); } static void root_port_commit_config(void) @@ -312,7 +309,7 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* 8.2 Configuration of PCI Express Root Ports */ - pcie_update_cfg(dev, 0x338, ~(1 << 26), 1 << 26); + pci_update_config32(dev, 0x338, ~(1 << 26), 1 << 26); do { reg32 = pci_read_config32(dev, 0x328); @@ -326,7 +323,7 @@ static void root_port_commit_config(void) printk(BIOS_DEBUG, "%s: Timeout waiting for 328h\n", dev_path(dev)); - pcie_update_cfg(dev, 0x408, ~(1 << 27), 1 << 27); + pci_update_config32(dev, 0x408, ~(1 << 27), 1 << 27); /* Disable this device if possible */ pch_disable_devfn(dev); @@ -439,26 +436,6 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) -{ - u8 reg8; - - reg8 = pci_read_config8(dev, reg); - reg8 &= mask; - reg8 |= or; - pci_write_config8(dev, reg, reg8); -} - -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - static void pcie_add_0x0202000_iobp(u32 reg) { u32 reg32; @@ -510,10 +487,10 @@ static void pch_pcie_early(struct device *dev) if (do_aspm) { /* Set ASPM bits in MPC2 register. */ - pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); + pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); /* Set unique clock exit latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); + pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); switch (rp) { case 1: @@ -547,55 +524,55 @@ static void pch_pcie_early(struct device *dev) break; } - pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); + pci_update_config32(dev, 0x338, ~(1 << 26), 0); } /* Enable LTR in Root Port. Disable OBFF. */ - pcie_update_cfg(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); - pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); + pci_update_config32(dev, 0x64, ~(1 << 11) & ~(3 << 18), (1 << 11)); + pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); + pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pcie_update_cfg(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0x0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); + pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); - pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854d74); + pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854d74); /* Set Invalid Receive Range Check Enable in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); + pci_update_config32(dev, 0xd8, ~0, (1 << 25)); - pcie_update_cfg8(dev, 0xf5, 0x0f, 0); + pci_update_config8(dev, 0xf5, 0x0f, 0); /* Set AER Extended Cap ID to 01h and Next Cap Pointer to 200h. */ - pcie_update_cfg(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); + pci_update_config32(dev, 0x100, ~(1 << 29) & ~0xfffff, (1 << 29) | 0x10001); /* Set L1 Sub-State Cap ID to 1Eh and Next Cap Pointer to None. */ - pcie_update_cfg(dev, 0x200, ~0xffff, 0x001e); + pci_update_config32(dev, 0x200, ~0xffff, 0x001e); - pcie_update_cfg(dev, 0x320, ~(3 << 20) & ~(7 << 6), + pci_update_config32(dev, 0x320, ~(3 << 20) & ~(7 << 6), (1 << 20) | (3 << 6)); /* Enable Relaxed Order from Root Port. */ - pcie_update_cfg(dev, 0x320, ~(3 << 23), (3 << 23)); + pci_update_config32(dev, 0x320, ~(3 << 23), (3 << 23)); if (rp == 1 || rp == 5 || rp == 6) - pcie_update_cfg8(dev, 0xf7, ~0xc, 0); + pci_update_config8(dev, 0xf7, ~0xc, 0); /* Set EOI forwarding disable. */ - pcie_update_cfg(dev, 0xd4, ~0, (1 << 1)); + pci_update_config32(dev, 0xd4, ~0, (1 << 1)); /* Read and write back write-once capability registers. */ - pcie_update_cfg(dev, 0x34, ~0, 0); - pcie_update_cfg(dev, 0x40, ~0, 0); - pcie_update_cfg(dev, 0x80, ~0, 0); - pcie_update_cfg(dev, 0x90, ~0, 0); + pci_update_config32(dev, 0x34, ~0, 0); + pci_update_config32(dev, 0x40, ~0, 0); + pci_update_config32(dev, 0x80, ~0, 0); + pci_update_config32(dev, 0x90, ~0, 0); } static void pch_pcie_init(struct device *dev) diff --git a/src/soc/intel/broadwell/romstage/pch.c b/src/soc/intel/broadwell/romstage/pch.c index 74d3125..35a361a 100644 --- a/src/soc/intel/broadwell/romstage/pch.c +++ b/src/soc/intel/broadwell/romstage/pch.c @@ -131,16 +131,6 @@ static void pch_enable_lpc(void) pci_write_config32(PCH_DEV_LPC, LPC_GEN4_DEC, config->gen4_dec); } -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - void pch_early_init(void) { reg_script_run_on_dev(PCH_DEV_LPC, pch_early_init_script); @@ -151,7 +141,7 @@ void pch_early_init(void) enable_smbus(); /* 8.14 Additional PCI Express Programming Steps, step #1 */ - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); - pcie_update_cfg(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x60, 0); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xf4, ~0x80, 0x80); + pci_update_config32(_PCH_DEV(PCIE, 0), 0xe2, ~0x30, 0x30); } diff --git a/src/southbridge/intel/lynxpoint/pcie.c b/src/southbridge/intel/lynxpoint/pcie.c index 17858af..3fd8d1e 100644 --- a/src/southbridge/intel/lynxpoint/pcie.c +++ b/src/southbridge/intel/lynxpoint/pcie.c @@ -22,9 +22,6 @@ #include "pch.h" #include <southbridge/intel/common/gpio.h> -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or); -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or); - /* LynxPoint-LP has 6 root ports while non-LP has 8. */ #define MAX_NUM_ROOT_PORTS 8 #define H_NUM_ROOT_PORTS MAX_NUM_ROOT_PORTS @@ -198,39 +195,39 @@ static void pcie_enable_clock_gating(void) if (!dev->enabled) { /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); if (!is_lp) { if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } if (rp == 5 && !rpc.ports[5]->enabled && !rpc.ports[6]->enabled && !rpc.ports[7]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } continue; } - pcie_update_cfg8(dev, 0xe2, ~(3 << 4), (3 << 4)); - pcie_update_cfg(dev, 0x420, ~(1 << 31), (1 << 31)); + pci_update_config8(dev, 0xe2, ~(3 << 4), (3 << 4)); + pci_update_config32(dev, 0x420, ~(1 << 31), (1 << 31)); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); + pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Enable static clock gating. */ if (rp == 1 && !rpc.ports[1]->enabled && !rpc.ports[2]->enabled && !rpc.ports[3]->enabled) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } else if (rp == 5 || rp == 6) { - pcie_update_cfg8(dev, 0xe2, ~1, 1); - pcie_update_cfg8(dev, 0xe1, 0x7f, 0x80); + pci_update_config8(dev, 0xe2, ~1, 1); + pci_update_config8(dev, 0xe1, 0x7f, 0x80); } continue; } @@ -238,29 +235,29 @@ static void pcie_enable_clock_gating(void) enabled_ports++; /* Enable dynamic clock gating. */ - pcie_update_cfg8(dev, 0xe1, 0xfc, 0x03); + pci_update_config8(dev, 0xe1, 0xfc, 0x03); if (is_lp) { - pcie_update_cfg8(dev, 0xe2, ~(1 << 6), (1 << 6)); - pcie_update_cfg8(dev, 0xe8, ~(3 << 2), (2 << 2)); + pci_update_config8(dev, 0xe2, ~(1 << 6), (1 << 6)); + pci_update_config8(dev, 0xe8, ~(3 << 2), (2 << 2)); } /* Update PECR1 register. */ - pcie_update_cfg8(dev, 0xe8, ~0, 1); + pci_update_config8(dev, 0xe8, ~0, 1); - pcie_update_cfg8(dev, 0x324, ~(1 << 5), (1 < 5)); + pci_update_config8(dev, 0x324, ~(1 << 5), (1 < 5)); /* Per-Port CLKREQ# handling. */ if (is_lp && gpio_is_native(18 + rp - 1)) - pcie_update_cfg(dev, 0x420, ~0, (3 << 29)); + pci_update_config32(dev, 0x420, ~0, (3 << 29)); /* Configure shared resource clock gating. */ if (rp == 1 || rp == 5 || (rp == 6 && is_lp)) - pcie_update_cfg8(dev, 0xe1, 0xc3, 0x3c); + pci_update_config8(dev, 0xe1, 0xc3, 0x3c); } if (!enabled_ports && is_lp) - pcie_update_cfg8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); + pci_update_config8(rpc.ports[0], 0xe1, ~(1 << 6), (1 << 6)); } static void root_port_commit_config(void) @@ -458,26 +455,6 @@ static void root_port_check_disable(device_t dev) } } -static void pcie_update_cfg8(device_t dev, int reg, u8 mask, u8 or) -{ - u8 reg8; - - reg8 = pci_read_config8(dev, reg); - reg8 &= mask; - reg8 |= or; - pci_write_config8(dev, reg, reg8); -} - -static void pcie_update_cfg(device_t dev, int reg, u32 mask, u32 or) -{ - u32 reg32; - - reg32 = pci_read_config32(dev, reg); - reg32 &= mask; - reg32 |= or; - pci_write_config32(dev, reg, reg32); -} - static void pcie_add_0x0202000_iobp(u32 reg) { u32 reg32; @@ -549,13 +526,13 @@ static void pch_pcie_early(struct device *dev) if (do_aspm) { /* Set ASPM bits in MPC2 register. */ - pcie_update_cfg(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); + pci_update_config32(dev, 0xd4, ~(0x3 << 2), (1 << 4) | (0x2 << 2)); /* Set unique clock exit latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); + pci_update_config32(dev, 0xd8, ~(0x7 << 18), (0x7 << 18)); /* Set L1 exit latency in LCAP register. */ - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); if (is_lp) { switch (rp) { @@ -624,50 +601,50 @@ static void pch_pcie_early(struct device *dev) } } - pcie_update_cfg(dev, 0x338, ~(1 << 26), 0); + pci_update_config32(dev, 0x338, ~(1 << 26), 0); } /* Enable LTR in Root Port. */ - pcie_update_cfg(dev, 0x64, ~(1 << 11), (1 << 11)); - pcie_update_cfg(dev, 0x68, ~(1 << 10), (1 << 10)); + pci_update_config32(dev, 0x64, ~(1 << 11), (1 << 11)); + pci_update_config32(dev, 0x68, ~(1 << 10), (1 << 10)); - pcie_update_cfg(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); + pci_update_config32(dev, 0x318, ~(0xffff << 16), (0x1414 << 16)); /* Set L1 exit latency in LCAP register. */ if (!do_aspm && (pci_read_config8(dev, 0xf5) & 0x1)) - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x4 << 15)); else - pcie_update_cfg(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); + pci_update_config32(dev, 0x4c, ~(0x7 << 15), (0x2 << 15)); - pcie_update_cfg(dev, 0x314, 0x0, 0x743a361b); + pci_update_config32(dev, 0x314, 0x0, 0x743a361b); /* Set Common Clock Exit Latency in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); + pci_update_config32(dev, 0xd8, ~(0x7 << 15), (0x3 << 15)); - pcie_update_cfg(dev, 0x33c, ~0x00ffffff, 0x854c74); + pci_update_config32(dev, 0x33c, ~0x00ffffff, 0x854c74); /* Set Invalid Recieve Range Check Enable in MPC register. */ - pcie_update_cfg(dev, 0xd8, ~0, (1 << 25)); + pci_update_config32(dev, 0xd8, ~0, (1 << 25)); - pcie_update_cfg8(dev, 0xf5, 0x3f, 0); + pci_update_config8(dev, 0xf5, 0x3f, 0); if (rp == 1 || rp == 5 || (is_lp && rp == 6)) - pcie_update_cfg8(dev, 0xf7, ~0xc, 0); + pci_update_config8(dev, 0xf7, ~0xc, 0); /* Set EOI forwarding disable. */ - pcie_update_cfg(dev, 0xd4, ~0, (1 << 1)); + pci_update_config32(dev, 0xd4, ~0, (1 << 1)); /* Set something involving advanced error reporting. */ - pcie_update_cfg(dev, 0x100, ~((1 << 20) - 1), 0x10001); + pci_update_config32(dev, 0x100, ~((1 << 20) - 1), 0x10001); if (is_lp) - pcie_update_cfg(dev, 0x100, ~0, (1 << 29)); + pci_update_config32(dev, 0x100, ~0, (1 << 29)); /* Read and write back write-once capability registers. */ - pcie_update_cfg(dev, 0x34, ~0, 0); - pcie_update_cfg(dev, 0x40, ~0, 0); - pcie_update_cfg(dev, 0x80, ~0, 0); - pcie_update_cfg(dev, 0x90, ~0, 0); + pci_update_config32(dev, 0x34, ~0, 0); + pci_update_config32(dev, 0x40, ~0, 0); + pci_update_config32(dev, 0x80, ~0, 0); + pci_update_config32(dev, 0x90, ~0, 0); } static void pci_init(struct device *dev)

1 0

New patch to review for coreboot: intel PCI ops: Remove explicit PCI MMCONF access
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17689 -gerrit commit 22a6690044e9e48d06330f24615f9c0f8349af7c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:53:59 2013 +0300 intel PCI ops: Remove explicit PCI MMCONF access MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. I liked the style of code in pci_mmio_cfg.h more, and used those to replace the ones in io.h. Change-Id: Ib5e6a451866c95d1edb9060c7f94070830b90e92 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/io.h | 43 ++++++++++++++---------- src/arch/x86/include/arch/pci_mmio_cfg.h | 21 ------------ src/northbridge/intel/fsp_sandybridge/finalize.c | 22 ++++++------ src/northbridge/intel/nehalem/finalize.c | 22 ++++++------ src/southbridge/intel/fsp_bd82x6x/finalize.c | 4 +-- src/southbridge/intel/fsp_i89xx/finalize.c | 4 +-- 6 files changed, 51 insertions(+), 65 deletions(-) diff --git a/src/arch/x86/include/arch/io.h b/src/arch/x86/include/arch/io.h index 69922e2..0d4be86 100644 --- a/src/arch/x86/include/arch/io.h +++ b/src/arch/x86/include/arch/io.h @@ -246,24 +246,6 @@ typedef u32 device_t; #include <arch/pci_io_cfg.h> #include <arch/pci_mmio_cfg.h> -static inline __attribute__((always_inline)) -void pci_or_config8(pci_devfn_t dev, unsigned where, uint8_t value) -{ - pci_write_config8(dev, where, pci_read_config8(dev, where) | value); -} - -static inline __attribute__((always_inline)) -void pci_or_config16(pci_devfn_t dev, unsigned where, uint16_t value) -{ - pci_write_config16(dev, where, pci_read_config16(dev, where) | value); -} - -static inline __attribute__((always_inline)) -void pci_or_config32(pci_devfn_t dev, unsigned where, uint32_t value) -{ - pci_write_config32(dev, where, pci_read_config32(dev, where) | value); -} - #define PCI_DEV_INVALID (0xffffffffU) static inline pci_devfn_t pci_io_locate_device(unsigned pci_id, pci_devfn_t dev) { @@ -367,4 +349,29 @@ void pnp_set_drq(pnp_devfn_t dev, unsigned index, unsigned drq) #endif /* __SIMPLE_DEVICE__ */ +#ifndef __SIMPLE_DEVICE__ +#include <device/pci_ops.h> +#endif + +static inline __attribute__ ((always_inline)) +void pci_or_config8(device_t dev, unsigned int where, u8 ormask) +{ + u8 value = pci_read_config8(dev, where); + pci_write_config8(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pci_or_config16(device_t dev, unsigned int where, u16 ormask) +{ + u16 value = pci_read_config16(dev, where); + pci_write_config16(dev, where, value | ormask); +} + +static inline __attribute__ ((always_inline)) +void pci_or_config32(device_t dev, unsigned int where, u32 ormask) +{ + u32 value = pci_read_config32(dev, where); + pci_write_config32(dev, where, value | ormask); +} + #endif diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index 25cdae9..d3eff8f 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -69,27 +69,6 @@ void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) write32(addr, value); } -static inline __attribute__ ((always_inline)) -void pcie_or_config8(pci_devfn_t dev, unsigned int where, u8 ormask) -{ - u8 value = pcie_read_config8(dev, where); - pcie_write_config8(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config16(pci_devfn_t dev, unsigned int where, u16 ormask) -{ - u16 value = pcie_read_config16(dev, where); - pcie_write_config16(dev, where, value | ormask); -} - -static inline __attribute__ ((always_inline)) -void pcie_or_config32(pci_devfn_t dev, unsigned int where, u32 ormask) -{ - u32 value = pcie_read_config32(dev, where); - pcie_write_config32(dev, where, value | ormask); -} - #define pci_mmio_read_config8 pcie_read_config8 #define pci_mmio_read_config16 pcie_read_config16 #define pci_mmio_read_config32 pcie_read_config32 diff --git a/src/northbridge/intel/fsp_sandybridge/finalize.c b/src/northbridge/intel/fsp_sandybridge/finalize.c index 19cfdb7..4ceb756 100644 --- a/src/northbridge/intel/fsp_sandybridge/finalize.c +++ b/src/northbridge/intel/fsp_sandybridge/finalize.c @@ -22,17 +22,17 @@ void intel_sandybridge_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/northbridge/intel/nehalem/finalize.c b/src/northbridge/intel/nehalem/finalize.c index be4397b..0b5cb74 100644 --- a/src/northbridge/intel/nehalem/finalize.c +++ b/src/northbridge/intel/nehalem/finalize.c @@ -22,17 +22,17 @@ void intel_nehalem_finalize_smm(void) { - pcie_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ - pcie_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ - pcie_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ - pcie_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ - pcie_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ - pcie_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ - pcie_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ - pcie_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ - pcie_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ - pcie_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ + pci_or_config16(PCI_DEV_SNB, 0x50, 1 << 0); /* GGC */ + pci_or_config32(PCI_DEV_SNB, 0x5c, 1 << 0); /* DPR */ + pci_or_config32(PCI_DEV_SNB, 0x78, 1 << 10); /* ME */ + pci_or_config32(PCI_DEV_SNB, 0x90, 1 << 0); /* REMAPBASE */ + pci_or_config32(PCI_DEV_SNB, 0x98, 1 << 0); /* REMAPLIMIT */ + pci_or_config32(PCI_DEV_SNB, 0xa0, 1 << 0); /* TOM */ + pci_or_config32(PCI_DEV_SNB, 0xa8, 1 << 0); /* TOUUD */ + pci_or_config32(PCI_DEV_SNB, 0xb0, 1 << 0); /* BDSM */ + pci_or_config32(PCI_DEV_SNB, 0xb4, 1 << 0); /* BGSM */ + pci_or_config32(PCI_DEV_SNB, 0xb8, 1 << 0); /* TSEGMB */ + pci_or_config32(PCI_DEV_SNB, 0xbc, 1 << 0); /* TOLUD */ MCHBAR32_OR(0x5500, 1 << 0); /* PAVP */ MCHBAR32_OR(0x5f00, 1 << 31); /* SA PM */ diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c index 6a8d6f1..22165b9 100644 --- a/src/southbridge/intel/fsp_bd82x6x/finalize.c +++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c @@ -45,10 +45,10 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c index 6a8d6f1..22165b9 100644 --- a/src/southbridge/intel/fsp_i89xx/finalize.c +++ b/src/southbridge/intel/fsp_i89xx/finalize.c @@ -45,10 +45,10 @@ void intel_pch_finalize_smm(void) RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ - pcie_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); + pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ - pcie_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); + pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4);

1 0

Patch set updated for coreboot: intel/i3100: Switch to MMCONF_SUPPORT_DEFAULT
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17548 -gerrit commit 57b0123e1fd984911342e2cf122dc7ec08e19c52 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 29 16:26:23 2016 +0200 intel/i3100: Switch to MMCONF_SUPPORT_DEFAULT TODO: HECBASE in bootblock Change-Id: Ia636bd82ccff542ac03b8799444eef8430a57e2d Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/mainboard/intel/eagleheights/Kconfig | 4 ---- src/northbridge/intel/i3100/Kconfig | 10 +++++++++- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/mainboard/intel/eagleheights/Kconfig b/src/mainboard/intel/eagleheights/Kconfig index 9671fff..7e64004 100644 --- a/src/mainboard/intel/eagleheights/Kconfig +++ b/src/mainboard/intel/eagleheights/Kconfig @@ -22,10 +22,6 @@ config MAINBOARD_PART_NUMBER string default "EagleHeights" -config MMCONF_BASE_ADDRESS - hex - default 0xe0000000 - config IRQ_SLOT_COUNT int default 9 diff --git a/src/northbridge/intel/i3100/Kconfig b/src/northbridge/intel/i3100/Kconfig index 7d4f4e5..7e0b444 100644 --- a/src/northbridge/intel/i3100/Kconfig +++ b/src/northbridge/intel/i3100/Kconfig @@ -1,10 +1,18 @@ config NORTHBRIDGE_INTEL_I3100 bool - select NO_MMCONF_SUPPORT select LATE_CBMEM_INIT select UDELAY_IO if NORTHBRIDGE_INTEL_I3100 + +config MMCONF_BASE_ADDRESS + hex + default 0xe0000000 + +config MMCONF_BUS_NUMBER + int + default 256 + config DIMM_MAP_LOGICAL hex default 0x1248

1 0

Patch set updated for coreboot: PCI ops: Rename pcie_xx() to pci_mmio_xx()
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17530 -gerrit commit fd6b0aa458d634247a3956e969ba6edd1e2f2f24 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Oct 27 14:59:00 2013 +0200 PCI ops: Rename pcie_xx() to pci_mmio_xx() Change-Id: I7fa65197b8165b9b0b74937f9ba455c48308da37 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/arch/x86/include/arch/pci_mmio_cfg.h | 32 ++++++++++++-------------------- 1 file changed, 12 insertions(+), 20 deletions(-) diff --git a/src/arch/x86/include/arch/pci_mmio_cfg.h b/src/arch/x86/include/arch/pci_mmio_cfg.h index d3eff8f..8caff5a 100644 --- a/src/arch/x86/include/arch/pci_mmio_cfg.h +++ b/src/arch/x86/include/arch/pci_mmio_cfg.h @@ -22,7 +22,7 @@ #define DEFAULT_PCIEXBAR CONFIG_MMCONF_BASE_ADDRESS static inline __attribute__ ((always_inline)) -u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) +u8 pci_mmio_read_config8(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); @@ -30,7 +30,7 @@ u8 pcie_read_config8(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) +u16 pci_mmio_read_config16(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); @@ -38,7 +38,7 @@ u16 pcie_read_config16(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) +u32 pci_mmio_read_config32(pci_devfn_t dev, unsigned int where) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); @@ -46,7 +46,7 @@ u32 pcie_read_config32(pci_devfn_t dev, unsigned int where) } static inline __attribute__ ((always_inline)) -void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) +void pci_mmio_write_config8(pci_devfn_t dev, unsigned int where, u8 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | where); @@ -54,7 +54,7 @@ void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) +void pci_mmio_write_config16(pci_devfn_t dev, unsigned int where, u16 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~1)); @@ -62,29 +62,21 @@ void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value) } static inline __attribute__ ((always_inline)) -void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value) +void pci_mmio_write_config32(pci_devfn_t dev, unsigned int where, u32 value) { void *addr; addr = (void *)(uintptr_t)(DEFAULT_PCIEXBAR | dev | (where & ~3)); write32(addr, value); } -#define pci_mmio_read_config8 pcie_read_config8 -#define pci_mmio_read_config16 pcie_read_config16 -#define pci_mmio_read_config32 pcie_read_config32 - -#define pci_mmio_write_config8 pcie_write_config8 -#define pci_mmio_write_config16 pcie_write_config16 -#define pci_mmio_write_config32 pcie_write_config32 - #if CONFIG_MMCONF_SUPPORT_DEFAULT -#define pci_read_config8 pcie_read_config8 -#define pci_read_config16 pcie_read_config16 -#define pci_read_config32 pcie_read_config32 +#define pci_read_config8 pci_mmio_read_config8 +#define pci_read_config16 pci_mmio_read_config16 +#define pci_read_config32 pci_mmio_read_config32 -#define pci_write_config8 pcie_write_config8 -#define pci_write_config16 pcie_write_config16 -#define pci_write_config32 pcie_write_config32 +#define pci_write_config8 pci_mmio_write_config8 +#define pci_write_config16 pci_mmio_write_config16 +#define pci_write_config32 pci_mmio_write_config32 #endif #endif /* CONFIG_MMCONF_SUPPORT */

1 0

Patch set updated for coreboot: intel PCI ops: Remove explicit PCI MMCONF access
by Kyösti Mälkki 02 Dec '16

02 Dec '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17545 -gerrit commit 63309ccf519838b1d3443a5f65dd5b286f1b6415 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Fri Jul 26 08:53:59 2013 +0300 intel PCI ops: Remove explicit PCI MMCONF access MMCONF was explicitly used here to avoid races of 0xcf8/0xcfc access being non-atomic and/or need to access 4kiB of PCI config space. All these platforms now have MMCONF_SUPPORT_DEFAULT. Change-Id: If62537475eb67b7ecf85f2292a2a954a41bc18d1 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- src/soc/intel/broadwell/pcie.c | 2 +- src/soc/intel/skylake/pcie.c | 2 +- src/southbridge/intel/bd82x6x/me.c | 2 +- src/southbridge/intel/bd82x6x/me_8.x.c | 2 +- src/southbridge/intel/bd82x6x/smihandler.c | 2 +- src/southbridge/intel/common/spi.c | 2 +- src/southbridge/intel/fsp_bd82x6x/azalia.c | 18 +++++++++--------- src/southbridge/intel/fsp_rangeley/spi.c | 2 +- src/southbridge/intel/i82801gx/smihandler.c | 7 ------- src/southbridge/intel/ibexpeak/me.c | 2 +- src/southbridge/intel/ibexpeak/smihandler.c | 2 +- 11 files changed, 18 insertions(+), 25 deletions(-) diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index 1c9b50c..355e17a 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -673,7 +673,7 @@ static void pcie_set_subsystem(device_t dev, unsigned vendor, unsigned device) static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) { /* Set max snoop and non-snoop latency for Broadwell */ - pci_mmio_write_config32(dev, off, 0x10031003); + pci_write_config32(dev, off, 0x10031003); } static struct pci_operations pcie_ops = { diff --git a/src/soc/intel/skylake/pcie.c b/src/soc/intel/skylake/pcie.c index 719abf3..d3eecff 100644 --- a/src/soc/intel/skylake/pcie.c +++ b/src/soc/intel/skylake/pcie.c @@ -75,7 +75,7 @@ static void pch_pcie_init(struct device *dev) static void pcie_set_L1_ss_max_latency(device_t dev, unsigned int off) { /* Set max snoop and non-snoop latency for the SOC */ - pci_mmio_write_config32(dev, off, 0x10031003); + pci_write_config32(dev, off, 0x10031003); } static struct pci_operations pcie_ops = { diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 23915c3..0e5187c 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -33,7 +33,7 @@ #include <halt.h> #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 220a176..94cec3e 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -33,7 +33,7 @@ #include <halt.h> #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 71ebb6e..4cef988 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -28,7 +28,7 @@ #include "nvs.h" #include <northbridge/intel/sandybridge/sandybridge.h> -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/gpio.h> #include <cpu/intel/model_206ax/model_206ax.h> diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 36102c2..9e98488 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -35,7 +35,7 @@ #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/fsp_bd82x6x/azalia.c b/src/southbridge/intel/fsp_bd82x6x/azalia.c index b64d923..b8cdd97 100644 --- a/src/southbridge/intel/fsp_bd82x6x/azalia.c +++ b/src/southbridge/intel/fsp_bd82x6x/azalia.c @@ -245,28 +245,28 @@ static void azalia_init(struct device *dev) printk(BIOS_DEBUG, "Azalia: base = %08x\n", (u32)base); if (RCBA32(0x2030) & (1 << 31)) { - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 &= 0xf8ffff01; reg32 |= (1 << 24); // 25 for server reg32 |= RCBA32(0x2030) & 0xfe; - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32); - reg16 = pci_mmio_read_config16(dev, 0x78); + reg16 = pci_read_config16(dev, 0x78); reg16 &= ~(1 << 11); - pci_mmio_write_config16(dev, 0x78, reg16); + pci_write_config16(dev, 0x78, reg16); } else printk(BIOS_DEBUG, "Azalia: V1CTL disabled.\n"); - reg32 = pci_mmio_read_config32(dev, 0x114); + reg32 = pci_read_config32(dev, 0x114); reg32 &= ~0xfe; - pci_mmio_write_config32(dev, 0x114, reg32); + pci_write_config32(dev, 0x114, reg32); // Set VCi enable bit - if (pci_mmio_read_config32(dev, 0x120) & ((1 << 24) | + if (pci_read_config32(dev, 0x120) & ((1 << 24) | (1 << 25) | (1 << 26))) { - reg32 = pci_mmio_read_config32(dev, 0x120); + reg32 = pci_read_config32(dev, 0x120); reg32 |= (1 << 31); - pci_mmio_write_config32(dev, 0x120, reg32); + pci_write_config32(dev, 0x120, reg32); } // Enable HDMI codec: diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 007c612..10d8f87 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -27,7 +27,7 @@ static int ich_status_poll(u16 bitmask, int wait_til_set); #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #define pci_read_config_byte(dev, reg, targ)\ *(targ) = pci_read_config8(dev, reg) #define pci_read_config_word(dev, reg, targ)\ diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index c6425db..2c21ea7 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -212,7 +212,6 @@ static u32 reset_tco_status(void) return reg32; } - static void dump_tco_status(u32 tco_sts) { printk(BIOS_DEBUG, "TCO_STS: "); @@ -232,12 +231,6 @@ static void dump_tco_status(u32 tco_sts) printk(BIOS_DEBUG, "\n"); } -/* We are using PCIe accesses for now - * 1. the chipset can do it - * 2. we don't need to worry about how we leave 0xcf8/0xcfc behind - */ -#include <arch/pci_mmio_cfg.h> - int southbridge_io_trap_handler(int smif) { switch (smif) { diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index e2eb41c..da6bfa8 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -32,7 +32,7 @@ #include <elog.h> #ifdef __SMM__ -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> #else # include <device/device.h> # include <device/pci.h> diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index c3db159..ec91bdf 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -33,7 +33,7 @@ */ #include "northbridge/intel/nehalem/nehalem.h" #include <southbridge/intel/common/gpio.h> -#include <arch/pci_mmio_cfg.h> +#include <arch/io.h> /* While we read PMBASE dynamically in case it changed, let's * initialize it with a sane value

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coreboot-gerrit December 2016