coreboot-gerrit December 2016

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Patch set updated for coreboot: superio/fintek: Add support for Fintek F71889A.
by Marty Plummer 02 Dec '16

02 Dec '16

Marty Plummer (ntzrmtthihu777(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17669 -gerrit commit d7671ca0d30074b00a993062878e8837d43f73ac Author: Marty Plummer <ntzrmtthihu777(a)gmail.com> Date: Thu Dec 1 02:14:39 2016 -0600 superio/fintek: Add support for Fintek F71889A. Datasheet: F71889A rev V0.21P Change-Id: I91c60a3b48cd4872ae7a27de8f49faa40e877a27 Signed-off-by: Marty Plummer <ntzrmtthihu777(a)gmail.com> --- src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f71889a/Kconfig | 19 +++++++++ src/superio/fintek/f71889a/Makefile.inc | 17 ++++++++ src/superio/fintek/f71889a/f71889a.h | 30 ++++++++++++++ src/superio/fintek/f71889a/superio.c | 70 +++++++++++++++++++++++++++++++++ 5 files changed, 137 insertions(+) diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 0d0ae66..5d117e2 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -24,3 +24,4 @@ subdirs-y += f71872 subdirs-y += f81216h subdirs-y += f81865f subdirs-y += f81866d +supdirs-y += f71889a diff --git a/src/superio/fintek/f71889a/Kconfig b/src/superio/fintek/f71889a/Kconfig new file mode 100644 index 0000000..1e561aa --- /dev/null +++ b/src/superio/fintek/f71889a/Kconfig @@ -0,0 +1,19 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +config SUPERIO_FINTEK_F71889A + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE diff --git a/src/superio/fintek/f71889a/Makefile.inc b/src/superio/fintek/f71889a/Makefile.inc new file mode 100644 index 0000000..99dee02 --- /dev/null +++ b/src/superio/fintek/f71889a/Makefile.inc @@ -0,0 +1,17 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F71889A) += superio.c diff --git a/src/superio/fintek/f71889a/f71889a.h b/src/superio/fintek/f71889a/f71889a.h new file mode 100644 index 0000000..c28c55f --- /dev/null +++ b/src/superio/fintek/f71889a/f71889a.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71889A_H +#define SUPERIO_FINTEK_F71889A_H + +/* Logical Device Numbers (LDN). */ +#define F71889A_SP1 0x01 /* UART1 */ +#define F71889A_SP2 0x02 /* UART2 */ +#define F71889A_PP 0x03 /* Parallel Port */ +#define F71889A_HWM 0x04 /* Hardware Monitor */ +#define F71889A_KBC 0x05 /* Keyboard/Mouse */ +#define F71889A_GPIO 0x06 /* GPIO */ +#define F71889A_VID 0x07 /* VID */ +#define F71889A_PM 0x0a /* ACPI/PME */ + +#endif /* SUPERIO_FINTEK_F71889A_H */ diff --git a/src/superio/fintek/f71889a/superio.c b/src/superio/fintek/f71889a/superio.c new file mode 100644 index 0000000..54770b4 --- /dev/null +++ b/src/superio/fintek/f71889a/superio.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f71889a.h" + +static void f71889a_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + + case F71889A_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f71889a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x07f8 etc. values may not be correct. + * double check bitmasks + */ + { &ops, F71889A_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71889A_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, + { &ops, F71889A_GPIO, PNP_IRQ0, }, + { &ops, F71889A_VID, PNP_IO0, {0x0ff8, 0}, }, + { &ops, F71889A_PM, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f71889a_ops = { + CHIP_NAME("Fintek F71889A Super I/O") + .enable_Dev = enable_dev +};

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Patch set updated for coreboot: superio/fintek: Add support for Fintek F71889A.
by Marty Plummer 02 Dec '16

02 Dec '16

Marty Plummer (ntzrmtthihu777(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17669 -gerrit commit d4ca1243651a055dca19337a54fd7e3ab4cb8009 Author: Marty Plummer <ntzrmtthihu777(a)gmail.com> Date: Thu Dec 1 02:14:39 2016 -0600 superio/fintek: Add support for Fintek F71889A. Datasheet: F71889A rev V0.21P Change-Id: I91c60a3b48cd4872ae7a27de8f49faa40e877a27 Signed-off-by: Marty Plummer <ntzrmtthihu777(a)gmail.com> --- src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f71889a/Kconfig | 20 ++++++++++ src/superio/fintek/f71889a/Makefile.inc | 18 +++++++++ src/superio/fintek/f71889a/f71889a.h | 31 ++++++++++++++ src/superio/fintek/f71889a/superio.c | 71 +++++++++++++++++++++++++++++++++ 5 files changed, 141 insertions(+) diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 0d0ae66..5d117e2 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -24,3 +24,4 @@ subdirs-y += f71872 subdirs-y += f81216h subdirs-y += f81865f subdirs-y += f81866d +supdirs-y += f71889a diff --git a/src/superio/fintek/f71889a/Kconfig b/src/superio/fintek/f71889a/Kconfig new file mode 100644 index 0000000..1bfdaa3 --- /dev/null +++ b/src/superio/fintek/f71889a/Kconfig @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +config SUPERIO_FINTEK_F71889A + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE + diff --git a/src/superio/fintek/f71889a/Makefile.inc b/src/superio/fintek/f71889a/Makefile.inc new file mode 100644 index 0000000..2cb644d --- /dev/null +++ b/src/superio/fintek/f71889a/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F71889A) += superio.c + diff --git a/src/superio/fintek/f71889a/f71889a.h b/src/superio/fintek/f71889a/f71889a.h new file mode 100644 index 0000000..e7d9746 --- /dev/null +++ b/src/superio/fintek/f71889a/f71889a.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71889A_H +#define SUPERIO_FINTEK_F71889A_H + +/* Logical Device Numbers (LDN). */ +#define F71889A_SP1 0x01 /* UART1 */ +#define F71889A_SP2 0x02 /* UART2 */ +#define F71889A_PP 0x03 /* Parallel Port */ +#define F71889A_HWM 0x04 /* Hardware Monitor */ +#define F71889A_KBC 0x05 /* Keyboard/Mouse */ +#define F71889A_GPIO 0x06 /* GPIO */ +#define F71889A_VID 0x07 /* VID */ +#define F71889A_PM 0x0a /* ACPI/PME */ + +#endif /* SUPERIO_FINTEK_F71889A_H */ + diff --git a/src/superio/fintek/f71889a/superio.c b/src/superio/fintek/f71889a/superio.c new file mode 100644 index 0000000..b362def --- /dev/null +++ b/src/superio/fintek/f71889a/superio.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marty Plummer <ntzrmtthihu777(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f71889a.h" + +static void f71889a_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + + case F71889A_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f71889a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x07f8 etc. values may not be correct. + * double check bitmasks + */ + { &ops, F71889A_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71889A_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, + { &ops, F71889A_GPIO, PNP_IRQ0, }, + { &ops, F71889A_VID, PNP_IO0, {0x0ff8, 0}, }, + { &ops, F71889A_PM, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f71889a_ops = { + CHIP_NAME("Fintek F71889A Super I/O") + .enable_Dev = enable_dev +}; +

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Patch set updated for coreboot: soc/intel/apollolake: Use the new SPI driver interface
by Furquan Shaikh 02 Dec '16

02 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17562 -gerrit commit ef95cce730ebdbf1e66eea2fcbe5535625de6b52 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Mon Nov 21 12:41:20 2016 -0800 soc/intel/apollolake: Use the new SPI driver interface 1. Define controller for fast SPI. 2. Separate out functions that are specific to SPI and flash controller in different files. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully for reef. Change-Id: If07db9d27bbf4f4eb6024175cb7753c6cf4fb793 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/apollolake/Makefile.inc | 6 + src/soc/intel/apollolake/bootblock/bootblock.c | 3 +- src/soc/intel/apollolake/chip.c | 15 +- src/soc/intel/apollolake/flash_ctrlr.c | 390 ++++++++++++++++++++ src/soc/intel/apollolake/include/soc/flash_ctrlr.h | 93 +++++ src/soc/intel/apollolake/include/soc/spi.h | 91 ----- src/soc/intel/apollolake/mmap_boot.c | 4 +- src/soc/intel/apollolake/romstage.c | 10 +- src/soc/intel/apollolake/spi.c | 404 +-------------------- 9 files changed, 525 insertions(+), 491 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 24b5035..d058ddb 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -12,6 +12,7 @@ bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c +bootblock-y += flash_ctrlr.c bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += itss.c @@ -24,6 +25,7 @@ bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c +romstage-y += flash_ctrlr.c romstage-y += gpio.c romstage-y += heci.c romstage-y += i2c_early.c @@ -38,6 +40,7 @@ romstage-y += pmutil.c romstage-y += reset.c romstage-y += spi.c +smm-y += flash_ctrlr.c smm-y += mmap_boot.c smm-y += pmutil.c smm-y += gpio.c @@ -50,6 +53,7 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-y += cpu.c ramstage-y += chip.c ramstage-y += elog.c +ramstage-y += flash_ctrlr.c ramstage-y += dsp.c ramstage-y += gpio.c ramstage-y += graphics.c @@ -76,6 +80,7 @@ ramstage-y += spi.c ramstage-y += xhci.c postcar-y += exit_car.S +postcar-y += flash_ctrlr.c postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c @@ -83,6 +88,7 @@ postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c verstage-y += car.c +verstage-y += flash_ctrlr.c verstage-y += i2c_early.c verstage-y += heci.c verstage-y += memmap.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 28a9128..4c393bd 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -21,6 +21,7 @@ #include <lib.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/gpio.h> #include <soc/iosf.h> #include <soc/mmap_boot.h> @@ -145,7 +146,7 @@ static void enable_spibar(void) pci_write_config8(dev, PCI_COMMAND, val); /* Initialize SPI to allow BIOS to write/erase on flash. */ - spi_init(); + spi_flash_init(); } static void enable_pmcbar(void) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 32d68cc..d481f3e 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -28,6 +28,7 @@ #include <romstage_handoff.h> #include <soc/iomap.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/vbt.h> #include <soc/itss.h> #include <soc/nvs.h> @@ -497,14 +498,14 @@ void platform_fsp_notify_status(enum fsp_notify_phase phase) } /* - * spi_init() needs to run unconditionally on every boot (including resume) to - * allow write protect to be disabled for eventlog and nvram updates. This needs - * to be done as early as possible in ramstage. Thus, add a callback for entry - * into BS_PRE_DEVICE. + * spi_flash init() needs to run unconditionally on every boot (including + * resume) to allow write protect to be disabled for eventlog and nvram + * updates. This needs to be done as early as possible in ramstage. Thus, add a + * callback for entry into BS_PRE_DEVICE. */ -static void spi_init_cb(void *unused) +static void spi_flash_init_cb(void *unused) { - spi_init(); + spi_flash_init(); } -BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_init_cb, NULL); +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, spi_flash_init_cb, NULL); diff --git a/src/soc/intel/apollolake/flash_ctrlr.c b/src/soc/intel/apollolake/flash_ctrlr.c new file mode 100644 index 0000000..3374928 --- /dev/null +++ b/src/soc/intel/apollolake/flash_ctrlr.c @@ -0,0 +1,390 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define __SIMPLE_DEVICE__ + +#include <arch/early_variables.h> +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <soc/flash_ctrlr.h> +#include <soc/intel/common/spi_flash.h> +#include <soc/pci_devs.h> +#include <spi_flash.h> +#include <spi-generic.h> +#include <stdlib.h> +#include <string.h> + +/* Helper to create a SPI context on API entry. */ +#define BOILERPLATE_CREATE_CTX(ctx) \ + struct spi_flash_ctx real_ctx; \ + struct spi_flash_ctx *ctx = &real_ctx; \ + _get_spi_flash_ctx(ctx) + +/* + * Anything that's not success is <0. Provided solely for readability, as these + * constants are not used outside this file. + */ +enum errors { + SUCCESS = 0, + E_NOT_IMPLEMENTED = -1, + E_TIMEOUT = -2, + E_HW_ERROR = -3, + E_ARGUMENT = -4, +}; + +/* Reduce data-passing burden by grouping transaction data in a context. */ +struct spi_flash_ctx { + uintptr_t mmio_base; + device_t pci_dev; + uint32_t hsfsts_on_last_error; +}; + +static void _get_spi_flash_ctx(struct spi_flash_ctx *ctx) +{ + uint32_t bar; + + /* FIXME: use device definition */ + ctx->pci_dev = SPI_DEV; + + bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); + ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; + ctx->hsfsts_on_last_error = 0; +} + +/* Read register from the SPI flash controller. 'reg' is the register offset. */ +static uint32_t _spi_flash_ctrlr_reg_read(struct spi_flash_ctx *ctx, uint16_t reg) +{ + uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); + return read32((void *)addr); +} + +uint32_t spi_flash_ctrlr_reg_read(uint16_t reg) +{ + BOILERPLATE_CREATE_CTX(ctx); + return _spi_flash_ctrlr_reg_read(ctx, reg); +} + +/* Write to register in SPI flash controller. 'reg' is the register offset. */ +static void _spi_flash_ctrlr_reg_write(struct spi_flash_ctx *ctx, uint16_t reg, + uint32_t val) +{ + uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); + write32((void *)addr, val); + +} + +/* + * The hardware datasheet is not clear on what HORD values actually do. It + * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which + * is the signature and revision fields. HORD_JEDEC provides access to the + * actual flash parameters, and is most likely what you want to use when + * probing the flash from software. + * It's okay to rely on SFPD, since the SPI flash controller requires an SFDP + * 1.5 or newer compliant SPI flash chip. + * NOTE: Due to the register layout of the hardware, all accesses will be + * aligned to a 4 byte boundary. + */ +static uint32_t read_spi_flash_sfdp_param(struct spi_flash_ctx *ctx, + uint16_t sfdp_reg) +{ + uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK; + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_PTINX, + ptinx_index | SPIBAR_PTINX_HORD_JEDEC); + return _spi_flash_ctrlr_reg_read(ctx, SPIBAR_PTDATA); +} + +/* Fill FDATAn FIFO in preparation for a write transaction. */ +static void fill_xfer_fifo(struct spi_flash_ctx *ctx, const void *data, + size_t len) +{ + len = min(len, SPIBAR_FDATA_FIFO_SIZE); + + /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ + memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); +} + +/* Drain FDATAn FIFO after a read transaction populates data. */ +static void drain_xfer_fifo(struct spi_flash_ctx *ctx, void *dest, size_t len) +{ + len = min(len, SPIBAR_FDATA_FIFO_SIZE); + + /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ + memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len); +} + +/* Fire up a transfer using the hardware sequencer. */ +static void start_hwseq_xfer(struct spi_flash_ctx *ctx, uint32_t hsfsts_cycle, + uint32_t flash_addr, size_t len) +{ + /* Make sure all W1C status bits get cleared. */ + uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS; + /* Set up transaction parameters. */ + hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK; + hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1); + + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr); + _spi_flash_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL, + hsfsts | SPIBAR_HSFSTS_FGO); +} + +static void print_xfer_error(struct spi_flash_ctx *ctx, + const char *failure_reason, uint32_t flash_addr) +{ + printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n" + "\tHSFSTS = 0x%08x\n", + failure_reason, flash_addr, ctx->hsfsts_on_last_error); +} + +static int wait_for_hwseq_xfer(struct spi_flash_ctx *ctx) +{ + uint32_t hsfsts; + do { + hsfsts = _spi_flash_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL); + + if (hsfsts & SPIBAR_HSFSTS_FCERR) { + ctx->hsfsts_on_last_error = hsfsts; + return E_HW_ERROR; + } + /* TODO: set up timer and abort on timeout */ + } while (!(hsfsts & SPIBAR_HSFSTS_FDONE)); + + return SUCCESS; +} + +/* Execute SPI flash transfer. This is a blocking call. */ +static int exec_sync_hwseq_xfer(struct spi_flash_ctx *ctx, + uint32_t hsfsts_cycle, uint32_t flash_addr, + size_t len) +{ + int ret; + start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len); + ret = wait_for_hwseq_xfer(ctx); + if (ret != SUCCESS) { + const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error"; + print_xfer_error(ctx, reason, flash_addr); + } + return ret; +} + +unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) +{ + return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); +} + +/* + * Write-protection status for BIOS region (BIOS_CONTROL register): + * EISS/WPD bits 00 01 10 11 + * -- -- -- -- + * normal mode RO RW RO RO + * SMM mode RO RW RO RW + */ +void spi_flash_init(void) +{ + uint32_t bios_ctl; + + BOILERPLATE_CREATE_CTX(ctx); + + bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); + bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; + bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; + + /* Enable Prefetching and caching. */ + bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; + bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; + + pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); +} + +/* Flash device operations. */ +static struct spi_flash boot_flash CAR_GLOBAL; + +static int nuclear_spi_flash_erase(const struct spi_flash *flash, + uint32_t offset, size_t len) +{ + int ret; + size_t erase_size; + uint32_t erase_cycle; + + BOILERPLATE_CREATE_CTX(ctx); + + if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) { + printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n"); + return E_ARGUMENT; + } + + while (len) { + if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) { + erase_size = 64 * KiB; + erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE; + } else { + erase_size = 4 * KiB; + erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE; + } + printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n", + offset, erase_size / KiB); + + ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0); + if (ret != SUCCESS) + return ret; + + offset += erase_size; + len -= erase_size; + } + + return SUCCESS; +} + +/* + * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and + * that the operation does not cross 256-byte boundary. + */ +static size_t get_xfer_len(uint32_t addr, size_t len) +{ + size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); + size_t bytes_left = ALIGN_UP(addr, 256) - addr; + + if (bytes_left) + xfer_len = min(xfer_len, bytes_left); + + return xfer_len; +} + +static int nuclear_spi_flash_read(const struct spi_flash *flash, uint32_t addr, + size_t len, void *buf) +{ + int ret; + size_t xfer_len; + uint8_t *data = buf; + + BOILERPLATE_CREATE_CTX(ctx); + + while (len) { + xfer_len = get_xfer_len(addr, len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ, + addr, xfer_len); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, data, xfer_len); + + addr += xfer_len; + data += xfer_len; + len -= xfer_len; + } + + return SUCCESS; +} + +static int nuclear_spi_flash_write(const struct spi_flash *flash, uint32_t addr, + size_t len, const void *buf) +{ + int ret; + size_t xfer_len; + const uint8_t *data = buf; + + BOILERPLATE_CREATE_CTX(ctx); + + while (len) { + xfer_len = get_xfer_len(addr, len); + fill_xfer_fifo(ctx, data, xfer_len); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE, + addr, xfer_len); + if (ret != SUCCESS) + return ret; + + addr += xfer_len; + data += xfer_len; + len -= xfer_len; + } + + return SUCCESS; +} + +static int nuclear_spi_flash_status(const struct spi_flash *flash, uint8_t *reg) +{ + int ret; + BOILERPLATE_CREATE_CTX(ctx); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, + sizeof(*reg)); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, reg, sizeof(*reg)); + return ret; +} + +/* + * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. + * For details see: + * Ch 31, SPI: p. 194 + * The size of the flash component is always taken from density field in the + * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. + */ +struct spi_flash *spi_flash_programmer_probe(struct spi_slave *dev, int force) +{ + BOILERPLATE_CREATE_CTX(ctx); + struct spi_flash *flash; + uint32_t flash_bits; + + flash = car_get_var_ptr(&boot_flash); + + /* + * bytes = (bits + 1) / 8; + * But we need to do the addition in a way which doesn't overflow for + * 4 Gbit devices (flash_bits == 0xffffffff). + */ + /* FIXME: Don't hardcode 0x04 ? */ + flash_bits = read_spi_flash_sfdp_param(ctx, 0x04); + flash->size = (flash_bits >> 3) + 1; + + flash->spi = dev; + flash->name = "Apollolake hardware sequencer"; + + /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ + flash->sector_size = 4 * KiB; + /* + * FIXME: Get erase+cmd, and status_cmd from SFDP. + * + * flash->erase_cmd = ??? + * flash->status_cmd = ??? + */ + + flash->internal_write = nuclear_spi_flash_write; + flash->internal_erase = nuclear_spi_flash_erase; + flash->internal_read = nuclear_spi_flash_read; + flash->internal_status = nuclear_spi_flash_status; + + return flash; +} + +int spi_flash_get_fpr_info(struct fpr_info *info) +{ + BOILERPLATE_CREATE_CTX(ctx); + + if (!ctx->mmio_base) + return -1; + + info->base = ctx->mmio_base + SPIBAR_FPR_BASE; + info->max = SPIBAR_FPR_MAX; + + return 0; +} diff --git a/src/soc/intel/apollolake/include/soc/flash_ctrlr.h b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h new file mode 100644 index 0000000..5b9c622 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/flash_ctrlr.h @@ -0,0 +1,93 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_SPI_H_ +#define _SOC_APOLLOLAKE_SPI_H_ + +/* PCI configuration registers */ +#define SPIBAR_BIOS_CONTROL 0xdc +/* Bit definitions for BIOS_CONTROL */ +#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) +#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) +#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) +#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) + +/* Maximum bytes of data that can fit in FDATAn registers */ +#define SPIBAR_FDATA_FIFO_SIZE 0x40 + +/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ +#define SPIBAR_BIOS_BFPREG 0x00 +#define SPIBAR_HSFSTS_CTL 0x04 +#define SPIBAR_FADDR 0x08 +#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) +#define SPIBAR_FPR_BASE 0x84 +#define SPIBAR_PTINX 0xcc +#define SPIBAR_PTDATA 0xd0 + +#define SPIBAR_FPR_MAX 5 + +/* Bit definitions and masks for BIOS_BFPREG register. */ +#define SPIBAR_BFPREG_PRB_MASK (0x7fff) +#define SPIBAR_BFPREG_PRL_SHIFT (16) +#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) +#define SPIBAR_BFPREG_SBRS (1 << 31) + +/* Bit definitions for HSFSTS_CTL register */ +#define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) +#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) +#define SPIBAR_HSFSTS_WET (1 << 21) +#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) +#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) +#define SPIBAR_HSFSTS_FGO (1 << 16) +#define SPIBAR_HSFSTS_FLOCKDN (1 << 15) +#define SPIBAR_HSFSTS_FDV (1 << 14) +#define SPIBAR_HSFSTS_FDOPSS (1 << 13) +#define SPIBAR_HSFSTS_SAF_CE (1 << 8) +#define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) +#define SPIBAR_HSFSTS_SAF_LE (1 << 6) +#define SPIBAR_HSFSTS_SCIP (1 << 5) +#define SPIBAR_HSFSTS_SAF_DLE (1 << 4) +#define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) +#define SPIBAR_HSFSTS_AEL (1 << 2) +#define SPIBAR_HSFSTS_FCERR (1 << 1) +#define SPIBAR_HSFSTS_FDONE (1 << 0) +#define SPIBAR_HSFSTS_W1C_BITS (0xff) +/* Supported flash cycle types */ +#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) +#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) +#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) +#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) +#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) + +/* Bit definitions for PTINX register */ +#define SPIBAR_PTINX_COMP_0 (0 << 14) +#define SPIBAR_PTINX_COMP_1 (1 << 14) +#define SPIBAR_PTINX_HORD_SFDP (0 << 12) +#define SPIBAR_PTINX_HORD_PARAM (1 << 12) +#define SPIBAR_PTINX_HORD_JEDEC (2 << 12) +#define SPIBAR_PTINX_IDX_MASK 0xffc + +/* + * Reads status register. On success returns 0 and status contains the value + * read from the status register. On error returns -1. + */ +int spi_flash_read_status(uint8_t *status); + +/* Read SPI controller register. */ +uint32_t spi_flash_ctrlr_reg_read(uint16_t reg); + +void spi_flash_init(void); +#endif diff --git a/src/soc/intel/apollolake/include/soc/spi.h b/src/soc/intel/apollolake/include/soc/spi.h deleted file mode 100644 index 4f16a85..0000000 --- a/src/soc/intel/apollolake/include/soc/spi.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2016 Intel Corp. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_APOLLOLAKE_SPI_H_ -#define _SOC_APOLLOLAKE_SPI_H_ - -/* PCI configuration registers */ -#define SPIBAR_BIOS_CONTROL 0xdc -/* Bit definitions for BIOS_CONTROL */ -#define SPIBAR_BIOS_CONTROL_WPD (1 << 0) -#define SPIBAR_BIOS_CONTROL_CACHE_DISABLE (1 << 2) -#define SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE (1 << 3) -#define SPIBAR_BIOS_CONTROL_EISS (1 << 5) - -/* Maximum bytes of data that can fit in FDATAn registers */ -#define SPIBAR_FDATA_FIFO_SIZE 0x40 - -/* Register offsets from the MMIO region base (PCI_BASE_ADDRESS_0) */ -#define SPIBAR_BIOS_BFPREG 0x00 -#define SPIBAR_HSFSTS_CTL 0x04 -#define SPIBAR_FADDR 0x08 -#define SPIBAR_FDATA(n) (0x10 + ((n) & 0xf) * 4) -#define SPIBAR_FPR_BASE 0x84 -#define SPIBAR_PTINX 0xcc -#define SPIBAR_PTDATA 0xd0 - -#define SPIBAR_FPR_MAX 5 - -/* Bit definitions and masks for BIOS_BFPREG register. */ -#define SPIBAR_BFPREG_PRB_MASK (0x7fff) -#define SPIBAR_BFPREG_PRL_SHIFT (16) -#define SPIBAR_BFPREG_PRL_MASK (0x7fff << SPIBAR_BFPREG_PRL_SHIFT) -#define SPIBAR_BFPREG_SBRS (1 << 31) - -/* Bit definitions for HSFSTS_CTL register */ -#define SPIBAR_HSFSTS_FBDC_MASK (0x3f << 24) -#define SPIBAR_HSFSTS_FBDC(n) (((n) << 24) & SPIBAR_HSFSTS_FBDC_MASK) -#define SPIBAR_HSFSTS_WET (1 << 21) -#define SPIBAR_HSFSTS_FCYCLE_MASK (0xf << 17) -#define SPIBAR_HSFSTS_FCYCLE(cyc) (((cyc) << 17) & SPIBAR_HSFSTS_FCYCLE_MASK) -#define SPIBAR_HSFSTS_FGO (1 << 16) -#define SPIBAR_HSFSTS_FLOCKDN (1 << 15) -#define SPIBAR_HSFSTS_FDV (1 << 14) -#define SPIBAR_HSFSTS_FDOPSS (1 << 13) -#define SPIBAR_HSFSTS_SAF_CE (1 << 8) -#define SPIBAR_HSFSTS_SAF_ACTIVE (1 << 7) -#define SPIBAR_HSFSTS_SAF_LE (1 << 6) -#define SPIBAR_HSFSTS_SCIP (1 << 5) -#define SPIBAR_HSFSTS_SAF_DLE (1 << 4) -#define SPIBAR_HSFSTS_SAF_ERROR (1 << 3) -#define SPIBAR_HSFSTS_AEL (1 << 2) -#define SPIBAR_HSFSTS_FCERR (1 << 1) -#define SPIBAR_HSFSTS_FDONE (1 << 0) -#define SPIBAR_HSFSTS_W1C_BITS (0xff) -/* Supported flash cycle types */ -#define SPIBAR_HSFSTS_CYCLE_READ SPIBAR_HSFSTS_FCYCLE(0) -#define SPIBAR_HSFSTS_CYCLE_WRITE SPIBAR_HSFSTS_FCYCLE(2) -#define SPIBAR_HSFSTS_CYCLE_4K_ERASE SPIBAR_HSFSTS_FCYCLE(3) -#define SPIBAR_HSFSTS_CYCLE_64K_ERASE SPIBAR_HSFSTS_FCYCLE(4) -#define SPIBAR_HSFSTS_CYCLE_RD_STATUS SPIBAR_HSFSTS_FCYCLE(8) - -/* Bit definitions for PTINX register */ -#define SPIBAR_PTINX_COMP_0 (0 << 14) -#define SPIBAR_PTINX_COMP_1 (1 << 14) -#define SPIBAR_PTINX_HORD_SFDP (0 << 12) -#define SPIBAR_PTINX_HORD_PARAM (1 << 12) -#define SPIBAR_PTINX_HORD_JEDEC (2 << 12) -#define SPIBAR_PTINX_IDX_MASK 0xffc - -/* - * Reads status register. On success returns 0 and status contains the value - * read from the status register. On error returns -1. - */ -int spi_read_status(uint8_t *status); - -/* Read SPI controller register. */ -uint32_t spi_ctrlr_reg_read(uint16_t reg); -#endif diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index bf2e5b9..7159c24 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -22,9 +22,9 @@ #include <commonlib/region.h> #include <console/console.h> #include <fmap.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/nvm.h> #include <soc/mmap_boot.h> -#include <soc/spi.h> /* * BIOS region on the flash is mapped right below 4GiB in the address @@ -81,7 +81,7 @@ static void bios_mmap_init(void) * Base and Limit. * Base and Limit fields are in units of 4KiB. */ - uint32_t val = spi_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); + uint32_t val = spi_flash_ctrlr_reg_read(SPIBAR_BIOS_BFPREG); start = (val & SPIBAR_BFPREG_PRB_MASK) * 4 * KiB; bios_end = (((val & SPIBAR_BFPREG_PRL_MASK) >> diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 039b586..77562c4 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -32,14 +32,15 @@ #include <fsp/memmap.h> #include <fsp/util.h> #include <soc/cpu.h> +#include <soc/flash_ctrlr.h> #include <soc/intel/common/mrc_cache.h> #include <soc/iomap.h> #include <soc/northbridge.h> #include <soc/pci_devs.h> #include <soc/pm.h> #include <soc/romstage.h> -#include <soc/spi.h> #include <soc/uart.h> +#include <spi_flash.h> #include <string.h> #include <timestamp.h> #include <timer.h> @@ -316,7 +317,12 @@ void mainboard_save_dimm_info(void) int get_sw_write_protect_state(void) { uint8_t status; + struct spi_flash *flash; + + flash = spi_flash_probe(CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, 0); + if (!flash) + return 0; /* Return unprotected status if status read fails. */ - return spi_read_status(&status) ? 0 : !!(status & 0x80); + return spi_flash_status(flash, &status) ? 0 : !!(status & 0x80); } diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 8992fa5..87d4d01 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -1,8 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corp. - * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * Copyright 2016 Google Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,400 +14,29 @@ * GNU General Public License for more details. */ -#define __SIMPLE_DEVICE__ - -#include <arch/early_variables.h> -#include <arch/io.h> #include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <soc/intel/common/spi_flash.h> -#include <soc/pci_devs.h> -#include <soc/spi.h> -#include <spi_flash.h> #include <spi-generic.h> -#include <stdlib.h> -#include <string.h> - -/* Helper to create a SPI context on API entry. */ -#define BOILERPLATE_CREATE_CTX(ctx) \ - struct spi_ctx real_ctx; \ - struct spi_ctx *ctx = &real_ctx; \ - _spi_get_ctx(ctx) - -/* - * Anything that's not success is <0. Provided solely for readability, as these - * constants are not used outside this file. - */ -enum errors { - SUCCESS = 0, - E_NOT_IMPLEMENTED = -1, - E_TIMEOUT = -2, - E_HW_ERROR = -3, - E_ARGUMENT = -4, -}; - -/* Reduce data-passing burden by grouping transaction data in a context. */ -struct spi_ctx { - uintptr_t mmio_base; - device_t pci_dev; - uint32_t hsfsts_on_last_error; -}; - -static void _spi_get_ctx(struct spi_ctx *ctx) -{ - uint32_t bar; - - /* FIXME: use device definition */ - ctx->pci_dev = SPI_DEV; - - bar = pci_read_config32(ctx->pci_dev, PCI_BASE_ADDRESS_0); - ctx->mmio_base = bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK; - ctx->hsfsts_on_last_error = 0; -} - -/* Read register from the SPI controller. 'reg' is the register offset. */ -static uint32_t _spi_ctrlr_reg_read(struct spi_ctx *ctx, uint16_t reg) -{ - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - return read32((void *)addr); -} - -uint32_t spi_ctrlr_reg_read(uint16_t reg) -{ - BOILERPLATE_CREATE_CTX(ctx); - return _spi_ctrlr_reg_read(ctx, reg); -} - -/* Write to register in the SPI controller. 'reg' is the register offset. */ -static void _spi_ctrlr_reg_write(struct spi_ctx *ctx, uint16_t reg, - uint32_t val) -{ - uintptr_t addr = ALIGN_DOWN(ctx->mmio_base + reg, 4); - write32((void *)addr, val); - -} - -/* - * The hardware datasheet is not clear on what HORD values actually do. It - * seems that HORD_SFDP provides access to the first 8 bytes of the SFDP, which - * is the signature and revision fields. HORD_JEDEC provides access to the - * actual flash parameters, and is most likely what you want to use when - * probing the flash from software. - * It's okay to rely on SFPD, since the SPI controller requires an SFDP 1.5 or - * newer compliant SPI chip. - * NOTE: Due to the register layout of the hardware, all accesses will be - * aligned to a 4 byte boundary. - */ -static uint32_t read_spi_sfdp_param(struct spi_ctx *ctx, uint16_t sfdp_reg) -{ - uint32_t ptinx_index = sfdp_reg & SPIBAR_PTINX_IDX_MASK; - _spi_ctrlr_reg_write(ctx, SPIBAR_PTINX, - ptinx_index | SPIBAR_PTINX_HORD_JEDEC); - return _spi_ctrlr_reg_read(ctx, SPIBAR_PTDATA); -} - -/* Fill FDATAn FIFO in preparation for a write transaction. */ -static void fill_xfer_fifo(struct spi_ctx *ctx, const void *data, size_t len) -{ - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy((void*)(ctx->mmio_base + SPIBAR_FDATA(0)), data, len); -} - -/* Drain FDATAn FIFO after a read transaction populates data. */ -static void drain_xfer_fifo(struct spi_ctx *ctx, void *dest, size_t len) -{ - len = min(len, SPIBAR_FDATA_FIFO_SIZE); - - /* YES! memcpy() works. FDATAn does not require 32-bit accesses. */ - memcpy(dest, (void*)(ctx->mmio_base + SPIBAR_FDATA(0)), len); -} - -/* Fire up a transfer using the hardware sequencer. */ -static void start_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle, - uint32_t flash_addr, size_t len) -{ - /* Make sure all W1C status bits get cleared. */ - uint32_t hsfsts = SPIBAR_HSFSTS_W1C_BITS; - /* Set up transaction parameters. */ - hsfsts |= hsfsts_cycle & SPIBAR_HSFSTS_FCYCLE_MASK; - hsfsts |= SPIBAR_HSFSTS_FBDC(len - 1); - - _spi_ctrlr_reg_write(ctx, SPIBAR_FADDR, flash_addr); - _spi_ctrlr_reg_write(ctx, SPIBAR_HSFSTS_CTL, - hsfsts | SPIBAR_HSFSTS_FGO); -} - -static void print_xfer_error(struct spi_ctx *ctx, const char *failure_reason, - uint32_t flash_addr) -{ - printk(BIOS_ERR, "SPI Transaction %s at flash offset %x.\n" - "\tHSFSTS = 0x%08x\n", - failure_reason, flash_addr, ctx->hsfsts_on_last_error); -} - -static int wait_for_hwseq_xfer(struct spi_ctx *ctx) -{ - uint32_t hsfsts; - do { - hsfsts = _spi_ctrlr_reg_read(ctx, SPIBAR_HSFSTS_CTL); - - if (hsfsts & SPIBAR_HSFSTS_FCERR) { - ctx->hsfsts_on_last_error = hsfsts; - return E_HW_ERROR; - } - /* TODO: set up timer and abort on timeout */ - } while (!(hsfsts & SPIBAR_HSFSTS_FDONE)); - - return SUCCESS; -} - -/* Execute SPI transfer. This is a blocking call. */ -static int exec_sync_hwseq_xfer(struct spi_ctx *ctx, uint32_t hsfsts_cycle, - uint32_t flash_addr, size_t len) -{ - int ret; - start_hwseq_xfer(ctx, hsfsts_cycle, flash_addr, len); - ret = wait_for_hwseq_xfer(ctx); - if (ret != SUCCESS) { - const char *reason = (ret == E_TIMEOUT) ? "timeout" : "error"; - print_xfer_error(ctx, reason, flash_addr); - } - return ret; -} - -unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) -{ - return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); -} - -/* - * Write-protection status for BIOS region (BIOS_CONTROL register): - * EISS/WPD bits 00 01 10 11 - * -- -- -- -- - * normal mode RO RW RO RO - * SMM mode RO RW RO RW - */ -void spi_init(void) -{ - uint32_t bios_ctl; - - BOILERPLATE_CREATE_CTX(ctx); - - bios_ctl = pci_read_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL); - bios_ctl |= SPIBAR_BIOS_CONTROL_WPD; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_EISS; - - /* Enable Prefetching and caching. */ - bios_ctl |= SPIBAR_BIOS_CONTROL_PREFETCH_ENABLE; - bios_ctl &= ~SPIBAR_BIOS_CONTROL_CACHE_DISABLE; - - pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); -} - -static int nuclear_spi_erase(const struct spi_flash *flash, uint32_t offset, - size_t len) -{ - int ret; - size_t erase_size; - uint32_t erase_cycle; - - BOILERPLATE_CREATE_CTX(ctx); - - if (!IS_ALIGNED(offset, 4 * KiB) || !IS_ALIGNED(len, 4 * KiB)) { - printk(BIOS_ERR, "BUG! SPI erase region not sector aligned.\n"); - return E_ARGUMENT; - } - - while (len) { - if (IS_ALIGNED(offset, 64 * KiB) && (len >= 64 * KiB)) { - erase_size = 64 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_64K_ERASE; - } else { - erase_size = 4 * KiB; - erase_cycle = SPIBAR_HSFSTS_CYCLE_4K_ERASE; - } - printk(BIOS_SPEW, "Erasing flash addr %x + %zu KiB\n", - offset, erase_size / KiB); - - ret = exec_sync_hwseq_xfer(ctx, erase_cycle, offset, 0); - if (ret != SUCCESS) - return ret; - - offset += erase_size; - len -= erase_size; - } - - return SUCCESS; -} - -/* - * Ensure read/write xfer len is not greater than SPIBAR_FDATA_FIFO_SIZE and - * that the operation does not cross 256-byte boundary. - */ -static size_t get_xfer_len(uint32_t addr, size_t len) -{ - size_t xfer_len = min(len, SPIBAR_FDATA_FIFO_SIZE); - size_t bytes_left = ALIGN_UP(addr, 256) - addr; - - if (bytes_left) - xfer_len = min(xfer_len, bytes_left); - - return xfer_len; -} - -static int nuclear_spi_read(const struct spi_flash *flash, uint32_t addr, - size_t len, void *buf) -{ - int ret; - size_t xfer_len; - uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = get_xfer_len(addr, len); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_READ, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - drain_xfer_fifo(ctx, data, xfer_len); - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_write(const struct spi_flash *flash, uint32_t addr, - size_t len, const void *buf) -{ - int ret; - size_t xfer_len; - const uint8_t *data = buf; - - BOILERPLATE_CREATE_CTX(ctx); - - while (len) { - xfer_len = get_xfer_len(addr, len); - fill_xfer_fifo(ctx, data, xfer_len); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_WRITE, - addr, xfer_len); - if (ret != SUCCESS) - return ret; - - addr += xfer_len; - data += xfer_len; - len -= xfer_len; - } - - return SUCCESS; -} - -static int nuclear_spi_status(const struct spi_flash *flash, uint8_t *reg) -{ - int ret; - BOILERPLATE_CREATE_CTX(ctx); - - ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, - sizeof(*reg)); - if (ret != SUCCESS) - return ret; - - drain_xfer_fifo(ctx, reg, sizeof(*reg)); - return ret; -} - -static struct spi_flash boot_flash CAR_GLOBAL; - -/* - * We can't use FDOC and FDOD to read FLCOMP, as previous platforms did. - * For details see: - * Ch 31, SPI: p. 194 - * The size of the flash component is always taken from density field in the - * SFDP table. FLCOMP.C0DEN is no longer used by the Flash Controller. - */ -struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) -{ - BOILERPLATE_CREATE_CTX(ctx); - struct spi_flash *flash; - uint32_t flash_bits; - - flash = car_get_var_ptr(&boot_flash); - - /* - * bytes = (bits + 1) / 8; - * But we need to do the addition in a way which doesn't overflow for - * 4 Gbit devices (flash_bits == 0xffffffff). - */ - /* FIXME: Don't hardcode 0x04 ? */ - flash_bits = read_spi_sfdp_param(ctx, 0x04); - flash->size = (flash_bits >> 3) + 1; - - flash->spi = spi; - flash->name = "Apollolake hardware sequencer"; - - /* Can erase both 4 KiB and 64 KiB chunks. Declare the smaller size. */ - flash->sector_size = 4 * KiB; - /* - * FIXME: Get erase+cmd, and status_cmd from SFDP. - * - * flash->erase_cmd = ??? - * flash->status_cmd = ??? - */ - - flash->internal_write = nuclear_spi_write; - flash->internal_erase = nuclear_spi_erase; - flash->internal_read = nuclear_spi_read; - flash->internal_status = nuclear_spi_status; - - return flash; -} - -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - BOILERPLATE_CREATE_CTX(ctx); - - /* This is special hardware. We expect bus 0 and CS line 0 here. */ - if ((bus != 0) || (cs != 0)) - return -1; - slave->bus = bus; - slave->cs = cs; - slave->ctrlr = NULL; - - return 0; -} - -int spi_read_status(uint8_t *status) +/* SPI controller managing the fast SPI. */ +static int fast_spi_ctrlr_setup(const struct spi_slave *dev) { - BOILERPLATE_CREATE_CTX(ctx); - - if (exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, - sizeof(*status)) != SUCCESS) + if ((dev->bus != 0) && (dev->cs != 0)) { + printk(BIOS_ERR, "%s: Unsupported device " + "bus=0x%x,cs=0x%x!\n", __func__, dev->bus, dev->cs); return -1; + } - drain_xfer_fifo(ctx, status, sizeof(*status)); - + printk(BIOS_INFO, "%s: Found controller for device " + "(bus=0x%x,cs=0x%x)!!\n", __func__, dev->bus, dev->cs); return 0; } -int spi_flash_get_fpr_info(struct fpr_info *info) -{ - BOILERPLATE_CREATE_CTX(ctx); - - if (!ctx->mmio_base) - return -1; +static const struct spi_ctrlr fast_spi_ctrlr = { + .setup = fast_spi_ctrlr_setup, +}; - info->base = ctx->mmio_base + SPIBAR_FPR_BASE; - info->max = SPIBAR_FPR_MAX; +const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { + { .ctrlr = &fast_spi_ctrlr, .bus_start = 0, .bus_end = 0 }, +}; - return 0; -} +const size_t spi_ctrlr_bus_map_count = ARRAY_SIZE(spi_ctrlr_bus_map);

1 0

Patch set updated for coreboot: spi: Clean up SPI driver interface
by Furquan Shaikh 02 Dec '16

02 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17561 -gerrit commit 86232531de852b80e718dfe215e95eaac030dd52 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Dec 1 07:25:31 2016 -0800 spi: Clean up SPI driver interface 1. Add new structure spi_ctrlr_buses that allows platform to define a mapping from SPI controller to buses managed by the controller. 2. Provide weak implementations of spi_init and spi_setup_slave that will be used by platforms using the new interface. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia6f47941b786299f4d823895898ffb1b36e02f73 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/spi-generic.c | 35 +++++++++++++++++++++++++++++++++++ src/include/spi-generic.h | 19 +++++++++++++++++++ 2 files changed, 54 insertions(+) diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c index 7398ee9..4fcd04c 100644 --- a/src/drivers/spi/spi-generic.c +++ b/src/drivers/spi/spi-generic.c @@ -41,3 +41,38 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, return -1; } + +void __attribute__((weak)) spi_init(void) +{ + /* Default weak implementation - do nothing. */ +} + +const struct spi_ctrlr_buses spi_ctrlr_bus_map[0] __attribute__((weak)); +const size_t spi_ctrlr_bus_map_count __attribute__((weak)); + +int __attribute__((weak)) spi_setup_slave(unsigned int bus, unsigned int cs, + struct spi_slave *slave) +{ + size_t i; + + memset(slave, 0, sizeof(*slave)); + + for (i = 0; i < spi_ctrlr_bus_map_count; i++) { + if ((spi_ctrlr_bus_map[i].bus_start <= bus) && + (spi_ctrlr_bus_map[i].bus_end >= bus)) { + slave->ctrlr = spi_ctrlr_bus_map[i].ctrlr; + break; + } + } + + if (slave->ctrlr == NULL) + return -1; + + slave->bus = bus; + slave->cs = cs; + + if (slave->ctrlr->setup) + return slave->ctrlr->setup(slave); + + return 0; +} diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index b4a10af..d28fefd 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -42,15 +42,34 @@ struct spi_slave { * claim_bus: Claim SPI bus and prepare for communication. * release_bus: Release SPI bus. * xfer: SPI transfer + * setup: Setup given SPI device bus. */ struct spi_ctrlr { int (*claim_bus)(const struct spi_slave *slave); void (*release_bus)(const struct spi_slave *slave); int (*xfer)(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin); + int (*setup)(const struct spi_slave *slave); }; /*----------------------------------------------------------------------- + * Structure defining mapping of SPI buses to controller. + * + * ctrlr: Pointer to controller structure managing the given SPI buses. + * bus_start: Start bus number managed by the controller. + * bus_end: End bus number manager by the controller. + */ +struct spi_ctrlr_buses { + const struct spi_ctrlr *ctrlr; + unsigned int bus_start; + unsigned int bus_end; +}; + +/* Mapping of SPI buses to controllers - should be defined by platform. */ +extern const struct spi_ctrlr_buses spi_ctrlr_bus_map[]; +extern const size_t spi_ctrlr_bus_map_count; + +/*----------------------------------------------------------------------- * Initialization, must be called once on start up. * */

1 0

Patch set updated for coreboot: spi: Define and use spi_ctrlr structure
by Furquan Shaikh 02 Dec '16

02 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17684 -gerrit commit 3649b2683b9bdbddf8605e88b9e132ecf44b9aec Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Dec 1 07:12:32 2016 -0800 spi: Define and use spi_ctrlr structure 1. Define a new structure spi_ctrlr that allows platforms to define callbacks for spi operations (claim bus, release bus, transfer). 2. Add a new member (pointer to spi_ctrlr structure) in spi_slave structure which will be initialized by call to spi_setup_slave. 3. Define spi_claim_bus, spi_release_bus and spi_xfer in spi-generic.c which will make appropriate calls to ctrlr functions. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Icb2326e3aab1e8f4bef53f553f82b3836358c55e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/Makefile.inc | 5 ++ src/drivers/spi/spi-generic.c | 43 +++++++++++++ src/include/spi-generic.h | 18 ++++++ src/soc/broadcom/cygnus/spi.c | 87 +++++++++++++------------ src/soc/imgtec/pistachio/spi.c | 105 ++++++++++++++++--------------- src/soc/intel/apollolake/spi.c | 19 +----- src/soc/intel/baytrail/spi.c | 34 +++++----- src/soc/intel/braswell/spi.c | 34 +++++----- src/soc/intel/broadwell/spi.c | 34 +++++----- src/soc/intel/fsp_baytrail/spi.c | 34 +++++----- src/soc/intel/fsp_broadwell_de/spi.c | 34 +++++----- src/soc/intel/skylake/flash_controller.c | 19 +----- src/soc/marvell/armada38x/spi.c | 37 ++++++----- src/soc/marvell/bg4cd/spi.c | 15 ----- src/soc/mediatek/mt8173/spi.c | 60 ++++++++++-------- src/soc/nvidia/tegra124/spi.c | 15 +++-- src/soc/nvidia/tegra210/spi.c | 15 +++-- src/soc/qualcomm/ipq40xx/spi.c | 93 ++++++++++++++------------- src/soc/qualcomm/ipq806x/spi.c | 103 ++++++++++++++++-------------- src/soc/rockchip/common/spi.c | 35 ++++++----- src/soc/samsung/exynos5420/spi.c | 47 ++++++++------ src/southbridge/amd/agesa/hudson/spi.c | 18 ++---- src/southbridge/amd/cimx/sb800/spi.c | 19 ++---- src/southbridge/amd/sb700/spi.c | 32 ++++------ src/southbridge/intel/common/spi.c | 32 ++++------ src/southbridge/intel/fsp_rangeley/spi.c | 32 ++++------ 26 files changed, 524 insertions(+), 495 deletions(-) diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc index 92baf62..c1bf307 100644 --- a/src/drivers/spi/Makefile.inc +++ b/src/drivers/spi/Makefile.inc @@ -7,6 +7,7 @@ ramstage-y += spiconsole.c smm-$(CONFIG_DEBUG_SMI) += spiconsole.c endif +bootblock-y += spi-generic.c bootblock-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c bootblock-$(CONFIG_SPI_FLASH) += spi_flash.c bootblock-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY) += boot_device_rw_nommap.c @@ -22,6 +23,7 @@ bootblock-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c bootblock-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c bootblock-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c +romstage-y += spi-generic.c romstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c romstage-$(CONFIG_SPI_FLASH) += spi_flash.c romstage-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY) += boot_device_rw_nommap.c @@ -37,6 +39,7 @@ romstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c romstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c romstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c +verstage-y += spi-generic.c verstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c verstage-$(CONFIG_SPI_FLASH) += spi_flash.c verstage-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY) += boot_device_rw_nommap.c @@ -52,6 +55,7 @@ verstage-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.c verstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c verstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c +ramstage-y += spi-generic.c ramstage-$(CONFIG_COMMON_CBFS_SPI_WRAPPER) += cbfs_spi.c ramstage-$(CONFIG_SPI_FLASH) += spi_flash.c ramstage-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP) += boot_device_rw_nommap.c @@ -68,6 +72,7 @@ ramstage-$(CONFIG_SPI_FLASH_WINBOND) += winbond.c ramstage-$(CONFIG_SPI_FRAM_RAMTRON) += ramtron.c ifeq ($(CONFIG_SPI_FLASH_SMM),y) +smm-y += spi-generic.c # SPI flash driver interface smm-$(CONFIG_SPI_FLASH) += spi_flash.c smm-$(CONFIG_BOOT_DEVICE_SPI_FLASH_RW_NOMMAP) += boot_device_rw_nommap.c diff --git a/src/drivers/spi/spi-generic.c b/src/drivers/spi/spi-generic.c new file mode 100644 index 0000000..7398ee9 --- /dev/null +++ b/src/drivers/spi/spi-generic.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <spi-generic.h> +#include <string.h> + +int spi_claim_bus(const struct spi_slave *slave) +{ + const struct spi_ctrlr *ctrlr = slave->ctrlr; + if (ctrlr && ctrlr->claim_bus) + return ctrlr->claim_bus(slave); + return 0; +} + +void spi_release_bus(const struct spi_slave *slave) +{ + const struct spi_ctrlr *ctrlr = slave->ctrlr; + if (ctrlr && ctrlr->release_bus) + ctrlr->release_bus(slave); +} + +int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, + void *din, size_t bytesin) +{ + const struct spi_ctrlr *ctrlr = slave->ctrlr; + if (ctrlr && ctrlr->xfer) + return ctrlr->xfer(slave, dout, bytesout, din, bytesin); + + return -1; +} diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index c8b209d..b4a10af 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -21,15 +21,33 @@ /* Controller-specific definitions: */ +struct spi_ctrlr; + /*----------------------------------------------------------------------- * Representation of a SPI slave, i.e. what we're communicating with. * * bus: ID of the bus that the slave is attached to. * cs: ID of the chip select connected to the slave. + * ctrlr: Pointer to SPI controller structure. */ struct spi_slave { unsigned int bus; unsigned int cs; + const struct spi_ctrlr *ctrlr; +}; + +/*----------------------------------------------------------------------- + * Representation of a SPI contoller. + * + * claim_bus: Claim SPI bus and prepare for communication. + * release_bus: Release SPI bus. + * xfer: SPI transfer + */ +struct spi_ctrlr { + int (*claim_bus)(const struct spi_slave *slave); + void (*release_bus)(const struct spi_slave *slave); + int (*xfer)(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin); }; /*----------------------------------------------------------------------- diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c index 810f2c2..e597efc 100644 --- a/src/soc/broadcom/cygnus/spi.c +++ b/src/soc/broadcom/cygnus/spi.c @@ -96,42 +96,6 @@ static struct qspi_priv *to_qspi_slave(const struct spi_slave *slave) return &qspi_slave; } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - struct qspi_priv *priv = &qspi_slave; - unsigned int spbr; - - slave->bus = bus; - slave->cs = cs; - - priv->max_hz = QSPI_MAX_HZ; - priv->spi_mode = QSPI_MODE; - priv->reg = (void *)(IPROC_QSPI_BASE); - priv->mspi_enabled = 0; - priv->bus_claimed = 0; - - /* MSPI: Basic hardware initialization */ - REG_WR(priv->reg + MSPI_SPCR1_LSB_REG, 0); - REG_WR(priv->reg + MSPI_SPCR1_MSB_REG, 0); - REG_WR(priv->reg + MSPI_NEWQP_REG, 0); - REG_WR(priv->reg + MSPI_ENDQP_REG, 0); - REG_WR(priv->reg + MSPI_SPCR2_REG, 0); - - /* MSPI: SCK configuration */ - spbr = (IPROC_QSPI_CLK - 1) / (2 * priv->max_hz) + 1; - REG_WR(priv->reg + MSPI_SPCR0_LSB_REG, - MAX(MIN(spbr, SPBR_MAX), SPBR_MIN)); - - /* MSPI: Mode configuration (8 bits by default) */ - priv->mspi_16bit = 0; - REG_WR(priv->reg + MSPI_SPCR0_MSB_REG, - 0x80 | /* Master */ - (8 << 2) | /* 8 bits per word */ - (priv->spi_mode & 3)); /* mode: CPOL / CPHA */ - - return 0; -} - static int mspi_enable(struct qspi_priv *priv) { struct stopwatch sw; @@ -156,7 +120,7 @@ static int mspi_enable(struct qspi_priv *priv) return 0; } -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct qspi_priv *priv = to_qspi_slave(slave); @@ -175,7 +139,7 @@ int spi_claim_bus(const struct spi_slave *slave) return 0; } -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct qspi_priv *priv = to_qspi_slave(slave); @@ -189,8 +153,8 @@ void spi_release_bus(const struct spi_slave *slave) #define RXRAM_8B(p, i) (REG_RD((p)->reg + MSPI_RXRAM_REG + \ ((((i) << 1) + 1) << 2)) & 0xff) -int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, - void *din, size_t bytesin) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) { struct qspi_priv *priv = to_qspi_slave(slave); const u8 *tx = (const u8 *)dout; @@ -311,6 +275,49 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, return 0; } +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + struct qspi_priv *priv = &qspi_slave; + unsigned int spbr; + + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + + priv->max_hz = QSPI_MAX_HZ; + priv->spi_mode = QSPI_MODE; + priv->reg = (void *)(IPROC_QSPI_BASE); + priv->mspi_enabled = 0; + priv->bus_claimed = 0; + + /* MSPI: Basic hardware initialization */ + REG_WR(priv->reg + MSPI_SPCR1_LSB_REG, 0); + REG_WR(priv->reg + MSPI_SPCR1_MSB_REG, 0); + REG_WR(priv->reg + MSPI_NEWQP_REG, 0); + REG_WR(priv->reg + MSPI_ENDQP_REG, 0); + REG_WR(priv->reg + MSPI_SPCR2_REG, 0); + + /* MSPI: SCK configuration */ + spbr = (IPROC_QSPI_CLK - 1) / (2 * priv->max_hz) + 1; + REG_WR(priv->reg + MSPI_SPCR0_LSB_REG, + MAX(MIN(spbr, SPBR_MAX), SPBR_MIN)); + + /* MSPI: Mode configuration (8 bits by default) */ + priv->mspi_16bit = 0; + REG_WR(priv->reg + MSPI_SPCR0_MSB_REG, + 0x80 | /* Master */ + (8 << 2) | /* 8 bits per word */ + (priv->spi_mode & 3)); /* mode: CPOL / CPHA */ + + return 0; +} + unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) { return min(65535, buf_len); diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index 2dd3ecd..bd7ea46 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -417,53 +417,8 @@ void spi_init(void) memset(img_spi_slaves, 0, sizeof(img_spi_slaves)); } -/* Set up communications parameters for a SPI slave. */ -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - struct img_spi_slave *img_slave = NULL; - struct spim_device_parameters *device_parameters; - u32 base; - - switch (bus) { - case 0: - base = IMG_SPIM0_BASE_ADDRESS; - break; - case 1: - base = IMG_SPIM1_BASE_ADDRESS; - break; - default: - printk(BIOS_ERR, "%s: Error: unsupported bus.\n", - __func__); - return -1; - } - if (cs > SPIM_DEVICE4) { - printk(BIOS_ERR, "%s: Error: unsupported chipselect.\n", - __func__); - return -1; - } - - slave->bus = bus; - slave->cs = cs; - - img_slave = get_img_slave(slave); - device_parameters = &(img_slave->device_parameters); - - img_slave->base = base; - - device_parameters->bitrate = 64; - device_parameters->cs_setup = 0; - device_parameters->cs_hold = 0; - device_parameters->cs_delay = 0; - device_parameters->spi_mode = SPIM_MODE_0; - device_parameters->cs_idle_level = 1; - device_parameters->data_idle_level = 0; - img_slave->initialised = IMG_FALSE; - - return 0; -} - /* Claim the bus and prepare it for communication */ -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { int ret; struct img_spi_slave *img_slave; @@ -494,7 +449,7 @@ int spi_claim_bus(const struct spi_slave *slave) } /* Release the SPI bus */ -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct img_spi_slave *img_slave; @@ -536,8 +491,8 @@ static int do_spi_xfer(const struct spi_slave *slave, const void *dout, return spim_io(slave, &buff_0, (dout && din) ? &buff_1 : NULL); } -int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, - void *din, size_t bytesin) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) { unsigned int in_sz, out_sz; int ret; @@ -578,6 +533,58 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, return SPIM_OK; } +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + +/* Set up communications parameters for a SPI slave. */ +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + struct img_spi_slave *img_slave = NULL; + struct spim_device_parameters *device_parameters; + u32 base; + + switch (bus) { + case 0: + base = IMG_SPIM0_BASE_ADDRESS; + break; + case 1: + base = IMG_SPIM1_BASE_ADDRESS; + break; + default: + printk(BIOS_ERR, "%s: Error: unsupported bus.\n", + __func__); + return -1; + } + if (cs > SPIM_DEVICE4) { + printk(BIOS_ERR, "%s: Error: unsupported chipselect.\n", + __func__); + return -1; + } + + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + + img_slave = get_img_slave(slave); + device_parameters = &(img_slave->device_parameters); + + img_slave->base = base; + + device_parameters->bitrate = 64; + device_parameters->cs_setup = 0; + device_parameters->cs_hold = 0; + device_parameters->cs_delay = 0; + device_parameters->spi_mode = SPIM_MODE_0; + device_parameters->cs_idle_level = 1; + device_parameters->data_idle_level = 0; + img_slave->initialised = IMG_FALSE; + + return 0; +} + unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) { return min(IMGTEC_SPI_MAX_TRANSFER_SIZE, buf_len); diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index ca56702..8992fa5 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -184,13 +184,6 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return MIN(buf_len, SPIBAR_FDATA_FIFO_SIZE); } -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - printk(BIOS_DEBUG, "NOT IMPLEMENTED: %s() !!!\n", __func__); - return E_NOT_IMPLEMENTED; -} - /* * Write-protection status for BIOS region (BIOS_CONTROL register): * EISS/WPD bits 00 01 10 11 @@ -215,17 +208,6 @@ void spi_init(void) pci_write_config32(ctx->pci_dev, SPIBAR_BIOS_CONTROL, bios_ctl); } -int spi_claim_bus(const struct spi_slave *slave) -{ - /* There's nothing we need to to here. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* No magic needed here. */ -} - static int nuclear_spi_erase(const struct spi_flash *flash, uint32_t offset, size_t len) { @@ -400,6 +382,7 @@ int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) slave->bus = bus; slave->cs = cs; + slave->ctrlr = NULL; return 0; } diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index b4f95aa..0f7b0c6 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -260,13 +260,6 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - slave->bus = bus; - slave->cs = cs; - return 0; -} - static ich9_spi_regs *spi_regs(void) { device_t dev; @@ -308,17 +301,6 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - typedef struct spi_transaction { const uint8_t *out; uint32_t bytesout; @@ -480,8 +462,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(cntlr.databytes, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) { uint16_t control; int16_t opcode_index; @@ -627,3 +609,15 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, return 0; } + +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + return 0; +} diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 4236e6f..2a0ddf8 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -229,13 +229,6 @@ static void read_reg(void *src, void *value, uint32_t size) } } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - slave->bus = bus; - slave->cs = cs; - return 0; -} - static ich9_spi_regs *spi_regs(void) { device_t dev; @@ -287,17 +280,6 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - typedef struct spi_transaction { const uint8_t *out; uint32_t bytesout; @@ -461,8 +443,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(cntlr.databytes, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) { uint16_t control; int16_t opcode_index; @@ -611,3 +593,15 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, return 0; } + +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + return 0; +} diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 5220970..d2ae943 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -259,13 +259,6 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - slave->bus = bus; - slave->cs = cs; - return 0; -} - void spi_init(void) { uint8_t *rcrb; /* Root Complex Register Block */ @@ -304,17 +297,6 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - typedef struct spi_transaction { const uint8_t *out; uint32_t bytesout; @@ -476,8 +458,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(cntlr.databytes, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) { uint16_t control; int16_t opcode_index; @@ -661,3 +643,15 @@ int spi_flash_protect(u32 start, u32 size) __func__, prr, start, end); return 0; } + +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + return 0; +} diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 06b160c..997bd13 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -249,13 +249,6 @@ static void read_reg(const void *src, void *value, uint32_t size) } } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - slave->bus = bus; - slave->cs = cs; - return 0; -} - static ich9_spi_regs *spi_regs(void) { device_t dev; @@ -288,17 +281,6 @@ void spi_init(void) cntlr.preop = &ich9_spi->preop; } -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - typedef struct spi_transaction { const uint8_t *out; uint32_t bytesout; @@ -460,8 +442,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(cntlr.databytes, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) { uint16_t control; int16_t opcode_index; @@ -607,3 +589,15 @@ spi_xfer_exit: return 0; } + +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + return 0; +} diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index 8af5686..5848966 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -259,13 +259,6 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave * slave) -{ - slave->bus = bus; - slave->cs = cs; - return 0; -} - void spi_init(void) { uint8_t *rcrb; /* Root Complex Register Block */ @@ -303,17 +296,6 @@ void spi_init(void) pci_write_config_byte(dev, 0xdc, bios_cntl | 0x1); } -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - typedef struct spi_transaction { const uint8_t *out; uint32_t bytesout; @@ -475,8 +457,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(cntlr.databytes, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytesout, void *din, size_t bytesin) { uint16_t control; int16_t opcode_index; @@ -624,3 +606,15 @@ spi_xfer_exit: return 0; } + +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + return 0; +} diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index 734d9d3..e0ac93d 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -151,13 +151,6 @@ static size_t spi_get_flash_size(pch_spi_regs *spi_bar) return size; } -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t bytesout, void *din, size_t bytesin) -{ - /* TODO: Define xfer for hardware sequencing. */ - return -1; -} - void spi_init(void) { uint8_t bios_cntl; @@ -170,17 +163,6 @@ void spi_init(void) pci_write_config_byte(dev, SPIBAR_BIOS_CNTL, bios_cntl); } -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Handled by PCH automatically. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Handled by PCH automatically. */ -} - int pch_hwseq_erase(const struct spi_flash *flash, u32 offset, size_t len) { u32 start, end, erase_size; @@ -377,6 +359,7 @@ int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) slave->bus = bus; slave->cs = cs; + slave->ctrlr = NULL; return 0; } diff --git a/src/soc/marvell/armada38x/spi.c b/src/soc/marvell/armada38x/spi.c index b628170..3a6517b 100644 --- a/src/soc/marvell/armada38x/spi.c +++ b/src/soc/marvell/armada38x/spi.c @@ -442,22 +442,14 @@ static int mrvl_spi_xfer(const struct spi_slave *slave, return 0; } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - slave->bus = bus; - slave->cs = cs; - mv_spi_sys_init(bus, cs, CONFIG_SF_DEFAULT_SPEED); - return 0; -} - -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { mv_spi_cs_set(slave->bus, slave->cs); mv_spi_cs_assert(slave->bus); return 0; } -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { mv_spi_cs_deassert(slave->bus); } @@ -467,11 +459,11 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return buf_len; } -int spi_xfer(const struct spi_slave *slave, - const void *dout, - size_t out_bytes, - void *din, - size_t in_bytes) +static int spi_ctrlr_xfer(const struct spi_slave *slave, + const void *dout, + size_t out_bytes, + void *din, + size_t in_bytes) { int ret = 0; @@ -481,3 +473,18 @@ int spi_xfer(const struct spi_slave *slave, ret = mrvl_spi_xfer(slave, in_bytes * 8, NULL, din); return ret; } + +static const spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + mv_spi_sys_init(bus, cs, CONFIG_SF_DEFAULT_SPEED); + return 0; +} diff --git a/src/soc/marvell/bg4cd/spi.c b/src/soc/marvell/bg4cd/spi.c index 54161bc..188a6bd 100644 --- a/src/soc/marvell/bg4cd/spi.c +++ b/src/soc/marvell/bg4cd/spi.c @@ -19,18 +19,3 @@ int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { return -1; } - -int spi_claim_bus(const struct spi_slave *slave) -{ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ -} - -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) -{ - return 0; -} diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index d02f02d..120b652 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -160,29 +160,7 @@ static void mtk_spi_dump_data(const char *name, const uint8_t *data, #endif } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - struct mtk_spi_bus *eslave; - - switch (bus) { - case CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS: - slave->bus = bus; - slave->cs = cs; - eslave = to_mtk_spi(slave); - assert(read32(&eslave->regs->spi_cfg0_reg) != 0); - spi_sw_reset(eslave->regs); - return 0; - case CONFIG_BOOT_DEVICE_SPI_FLASH_BUS: - slave->bus = bus; - slave->cs = cs; - return 0; - default: - die ("wrong bus number.\n"); - }; - return -1; -} - -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); struct mtk_spi_regs *regs = mtk_slave->regs; @@ -269,8 +247,8 @@ error: return -1; } -int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytes_out, - void *din, size_t bytes_in) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t bytes_out, void *din, size_t bytes_in) { size_t min_size = 0; int ret; @@ -301,7 +279,7 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t bytes_out, return 0; } -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct mtk_spi_bus *mtk_slave = to_mtk_spi(slave); struct mtk_spi_regs *regs = mtk_slave->regs; @@ -310,3 +288,33 @@ void spi_release_bus(const struct spi_slave *slave) spi_sw_reset(regs); mtk_slave->state = MTK_SPI_IDLE; } + +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + struct mtk_spi_bus *eslave; + + slave->ctrlr = &spi_ctrlr; + + switch (bus) { + case CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS: + slave->bus = bus; + slave->cs = cs; + eslave = to_mtk_spi(slave); + assert(read32(&eslave->regs->spi_cfg0_reg) != 0); + spi_sw_reset(eslave->regs); + return 0; + case CONFIG_BOOT_DEVICE_SPI_FLASH_BUS: + slave->bus = bus; + slave->cs = cs; + return 0; + default: + die ("wrong bus number.\n"); + }; + return -1; +} diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index d5b2915..e7844ce 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -209,7 +209,7 @@ static unsigned int tegra_spi_speed(unsigned int bus) return 50000000; } -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; u32 val; @@ -232,7 +232,7 @@ int spi_claim_bus(const struct spi_slave *slave) return 0; } -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; u32 val; @@ -798,8 +798,8 @@ static int __spi_xfer(const struct spi_slave *slave, const void *dout, return ret; } -int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, - void *din, size_t in_bytes) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { int ret = 0; @@ -811,6 +811,12 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, return ret; } +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { struct tegra_spi_channel *channel = to_tegra_spi(bus); @@ -819,6 +825,7 @@ int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) slave->bus = channel->slave.bus; slave->cs = channel->slave.cs; + slave->ctrlr = &spi_ctrlr; return 0; } diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index cecf573..6a70f48 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -208,7 +208,7 @@ static struct tegra_spi_channel * const to_tegra_spi(int bus) { return &tegra_spi_channels[bus - 1]; } -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; u32 val; @@ -231,7 +231,7 @@ int spi_claim_bus(const struct spi_slave *slave) return 0; } -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct tegra_spi_regs *regs = to_tegra_spi(slave->bus)->regs; u32 val; @@ -834,8 +834,8 @@ static int __spi_xfer(const struct spi_slave *slave, const void *dout, return ret; } -int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, - void *din, size_t in_bytes) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { int ret = 0; @@ -847,6 +847,12 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, return ret; } +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { struct tegra_spi_channel *channel = to_tegra_spi(bus); @@ -855,6 +861,7 @@ int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) slave->cs = channel->slave.cs; slave->bus = channel->slave.bus; + slave->ctrlr = &spi_ctrlr; return 0; } diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index cda3bea..6d044b3 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -226,45 +226,6 @@ static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) return NULL; } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = NULL; - int i; - - if ((bus < BLSP0_SPI) || (bus > BLSP1_SPI) - || ((bus == BLSP0_SPI) && (cs > 2)) - || ((bus == BLSP1_SPI) && (cs > 0))) { - printk(BIOS_ERR, - "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " - "or chipselect\n", bus); - return -1; - } - - for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { - if (spi_slave_pool[i].allocated) - continue; - ds = spi_slave_pool + i; - - ds->slave.bus = slave->bus = bus; - ds->slave.cs = slave->cs = cs; - ds->regs = &spi_reg[bus]; - - /* - * TODO(vbendeb): - * hardcoded frequency and mode - we might need to find a way - * to configure this - */ - ds->freq = 10000000; - ds->mode = SPI_MODE3; - ds->allocated = 1; - - return 0; - } - - printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); - return -1; -} - /* * BLSP QUPn SPI Hardware Initialisation */ @@ -340,7 +301,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) return SUCCESS; } -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct ipq_spi_slave *ds = to_ipq_spi(slave); unsigned int ret; @@ -352,7 +313,7 @@ int spi_claim_bus(const struct spi_slave *slave) return SUCCESS; } -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -653,8 +614,8 @@ static int blsp_spi_write(struct ipq_spi_slave *ds, u8 *cmd_buffer, * This function is invoked with either tx_buf or rx_buf. * Calling this function with both null does a chip select change. */ -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { struct ipq_spi_slave *ds = to_ipq_spi(slave); u8 *txp = (u8 *)dout; @@ -690,3 +651,49 @@ out: return ret; } + +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = NULL; + int i; + + if ((bus < BLSP0_SPI) || (bus > BLSP1_SPI) + || ((bus == BLSP0_SPI) && (cs > 2)) + || ((bus == BLSP1_SPI) && (cs > 0))) { + printk(BIOS_ERR, + "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " + "or chipselect\n", bus); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + if (spi_slave_pool[i].allocated) + continue; + ds = spi_slave_pool + i; + + ds->slave.bus = slave->bus = bus; + ds->slave.cs = slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + ds->regs = &spi_reg[bus]; + + /* + * TODO(vbendeb): + * hardcoded frequency and mode - we might need to find a way + * to configure this + */ + ds->freq = 10000000; + ds->mode = SPI_MODE3; + ds->allocated = 1; + + return 0; + } + + printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); + return -1; +} diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index 81dc508..b5e7e73 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -518,49 +518,6 @@ static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) return NULL; } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - struct ipq_spi_slave *ds = NULL; - int i; - - /* - * IPQ GSBI (Generic Serial Bus Interface) supports SPI Flash - * on different GSBI5, GSBI6 and GSBI7 - * with different number of chip selects (CS, channels): - */ - if ((bus < GSBI5_SPI) || (bus > GSBI7_SPI) - || ((bus == GSBI5_SPI) && (cs > 3)) - || ((bus == GSBI6_SPI) && (cs > 0)) - || ((bus == GSBI7_SPI) && (cs > 0))) { - printk(BIOS_ERR, "SPI error: unsupported bus %d " - "(Supported busses 0,1 and 2) or chipselect\n", bus); - } - - for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { - if (spi_slave_pool[i].allocated) - continue; - ds = spi_slave_pool + i; - - ds->slave.bus = slave->bus = bus; - ds->slave.cs = slave->cs = cs; - ds->regs = &spi_reg[bus]; - - /* - * TODO(vbendeb): - * hardcoded frequency and mode - we might need to find a way - * to configure this - */ - ds->freq = 10000000; - ds->mode = GSBI_SPI_MODE_0; - ds->allocated = 1; - - return 0; - } - - printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); - return -1; -} - /* * GSBIn SPI Hardware Initialisation */ @@ -638,7 +595,7 @@ static int spi_hw_init(struct ipq_spi_slave *ds) return SUCCESS; } -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct ipq_spi_slave *ds = to_ipq_spi(slave); unsigned int ret; @@ -661,7 +618,7 @@ int spi_claim_bus(const struct spi_slave *slave) return SUCCESS; } -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -731,8 +688,8 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(MAX_PACKET_COUNT, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, - size_t out_bytes, void *din, size_t in_bytes) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { int ret; struct ipq_spi_slave *ds = to_ipq_spi(slave); @@ -799,3 +756,55 @@ out: return ret; } + +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + struct ipq_spi_slave *ds = NULL; + int i; + + /* + * IPQ GSBI (Generic Serial Bus Interface) supports SPI Flash + * on different GSBI5, GSBI6 and GSBI7 + * with different number of chip selects (CS, channels): + */ + if ((bus < GSBI5_SPI) || (bus > GSBI7_SPI) + || ((bus == GSBI5_SPI) && (cs > 3)) + || ((bus == GSBI6_SPI) && (cs > 0)) + || ((bus == GSBI7_SPI) && (cs > 0))) { + printk(BIOS_ERR, "SPI error: unsupported bus %d " + "(Supported busses 0,1 and 2) or chipselect\n", bus); + } + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + if (spi_slave_pool[i].allocated) + continue; + ds = spi_slave_pool + i; + + ds->slave.bus = slave->bus = bus; + ds->slave.cs = slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + ds->regs = &spi_reg[bus]; + + /* + * TODO(vbendeb): + * hardcoded frequency and mode - we might need to find a way + * to configure this + */ + ds->freq = 10000000; + ds->mode = GSBI_SPI_MODE_0; + ds->allocated = 1; + + return 0; + } + + printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); + return -1; +} + + diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index 5f8eac5..6e7ca40 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -67,16 +67,6 @@ static struct rockchip_spi_slave *to_rockchip_spi(const struct spi_slave *slave) return &rockchip_spi_slaves[slave->bus]; } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); - - slave->bus = bus; - slave->cs = cs; - - return 0; -} - static void spi_cs_activate(const struct spi_slave *slave) { struct rockchip_spi *regs = to_rockchip_spi(slave)->regs; @@ -155,13 +145,13 @@ void rockchip_spi_set_sample_delay(unsigned int bus, unsigned int delay_ns) rsd << SPI_RXDSD_OFFSET); } -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { spi_cs_activate(slave); return 0; } -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { spi_cs_deactivate(slave); } @@ -338,8 +328,8 @@ static int __spi_xfer(const struct spi_slave *slave, const void *dout, return ret < 0 ? ret : 0; } -int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, - void *din, size_t in_bytes) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { int ret = 0; @@ -350,3 +340,20 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, return ret; } + +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); + + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + + return 0; +} diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index c809bb3..a3ac180 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -117,23 +117,7 @@ static void exynos_spi_init(struct exynos_spi *regs) spi_sw_reset(regs, 1); } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - ASSERT(bus >= 0 && bus < 3); - struct exynos_spi_slave *eslave; - - slave->bus = bus; - slave->cs = cs; - - eslave = to_exynos_spi(slave); - if (!eslave->initialized) { - exynos_spi_init(eslave->regs); - eslave->initialized = 1; - } - return 0; -} - -int spi_claim_bus(const struct spi_slave *slave) +static int spi_ctrlr_claim_bus(const struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; // TODO(hungte) Add some delay if too many transactions happen at once. @@ -218,8 +202,8 @@ static int __spi_xfer(const struct spi_slave *slave, const void *dout, return 0; } -int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, - void *din, size_t in_bytes) +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, + size_t out_bytes, void *din, size_t in_bytes) { int ret = 0; @@ -231,12 +215,35 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, return ret; } -void spi_release_bus(const struct spi_slave *slave) +static void spi_ctrlr_release_bus(const struct spi_slave *slave) { struct exynos_spi *regs = to_exynos_spi(slave)->regs; setbits_le32(&regs->cs_reg, SPI_SLAVE_SIG_INACT); } +static const struct spi_ctrlr spi_ctrlr = { + .claim_bus = spi_ctrlr_claim_bus, + .release_bus = spi_ctrlr_release_bus, + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + ASSERT(bus >= 0 && bus < 3); + struct exynos_spi_slave *eslave; + + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + + eslave = to_exynos_spi(slave); + if (!eslave->initialized) { + exynos_spi_init(eslave->regs); + eslave->initialized = 1; + } + return 0; +} + static int exynos_spi_read(struct spi_slave *slave, void *dest, uint32_t len, uint32_t off) { diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index a8b3b2a..e228d1f 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -90,7 +90,7 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(AMD_SB_SPI_TX_LEN - cmd_len, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, +static xsint spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { /* First byte is cmd which can not being sent through FIFO. */ @@ -147,17 +147,6 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, return 0; } -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Nothing is required. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Nothing is required. */ -} - int chipset_volatile_group_begin(const struct spi_flash *flash) { if (!IS_ENABLED (CONFIG_HUDSON_IMC_FWM)) @@ -176,9 +165,14 @@ int chipset_volatile_group_end(const struct spi_flash *flash) return 0; } +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { slave->bus = bus; slave->cs = cs; + slave->ctrlr = &spi_ctrlr; return 0; } diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index d331060..edf192a 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -59,7 +59,7 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(AMD_SB_SPI_TX_LEN - cmd_len, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { /* First byte is cmd which can not being sent through FIFO. */ @@ -138,18 +138,6 @@ static void ImcWakeup(void) WaitForEcLDN9MailboxCmdAck(); } -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Nothing is required. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Nothing is required. */ - return; -} - int chipset_volatile_group_begin(const struct spi_flash *flash) { if (!IS_ENABLED(CONFIG_SB800_IMC_FWM)) @@ -168,9 +156,14 @@ int chipset_volatile_group_end(const struct spi_flash *flash) return 0; } +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { slave->bus = bus; slave->cs = cs; + slave->ctrlr = &spi_ctrlr; return 0; } diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index fca401c..2e16ca8 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -65,25 +65,7 @@ static void execute_command(void) (read8((void *)(spibar+3)) & 0x80)); } -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Handled internally by the SB700 */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Handled internally by the SB700 */ -} - -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - slave->bus = bus; - slave->cs = cs; - return 0; -} - -int spi_xfer(const struct spi_slave *slave, const void *dout, +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { /* First byte is cmd which cannot be sent through the FIFO. */ @@ -135,3 +117,15 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, return 0; } + +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + return 0; +} diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 7e0cc20..42a2a74 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -285,13 +285,6 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - slave->bus = bus; - slave->cs = cs; - return 0; -} - void spi_init(void) { uint8_t *rcrb; /* Root Complex Register Block */ @@ -348,17 +341,6 @@ static void spi_init_cb(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, spi_init_cb, NULL); -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - typedef struct spi_transaction { const uint8_t *out; uint32_t bytesout; @@ -527,7 +509,7 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(cntlr.databytes, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { uint16_t control; @@ -675,6 +657,18 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, return 0; } +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + return 0; +} + /* Sets FLA in FADDR to (addr & 0x01FFFFFF) without touching other bits. */ static void ich_hwseq_set_addr(uint32_t addr) { diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index de676a9..acdb072 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -322,13 +322,6 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) -{ - slave->bus = bus; - slave->cs = cs; - return 0; -} - /* * Check if this device ID matches one of supported Intel SOC devices. * @@ -420,17 +413,6 @@ void spi_init(void) } } -int spi_claim_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ - return 0; -} - -void spi_release_bus(const struct spi_slave *slave) -{ - /* Handled by ICH automatically. */ -} - typedef struct spi_transaction { const uint8_t *out; uint32_t bytesout; @@ -592,7 +574,7 @@ unsigned int spi_crop_chunk(unsigned int cmd_len, unsigned int buf_len) return min(cntlr.databytes, buf_len); } -int spi_xfer(const struct spi_slave *slave, const void *dout, +static int spi_ctrlr_xfer(const struct spi_slave *slave, const void *dout, size_t bytesout, void *din, size_t bytesin) { uint16_t control; @@ -739,3 +721,15 @@ spi_xfer_exit: return 0; } + +static const struct spi_ctrlr spi_ctrlr = { + .xfer = spi_ctrlr_xfer, +}; + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) +{ + slave->bus = bus; + slave->cs = cs; + slave->ctrlr = &spi_ctrlr; + return 0; +}

1 0

Patch set updated for coreboot: spi: Pass pointer to spi_slave structure in spi_setup_slave
by Furquan Shaikh 02 Dec '16

02 Dec '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17683 -gerrit commit 66311d15a781aea633cedbadfc4a5f502829f760 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Dec 1 01:02:44 2016 -0800 spi: Pass pointer to spi_slave structure in spi_setup_slave For spi_setup_slave, instead of making the platform driver return a pointer to spi_slave structure, pass in a structure pointer that can be filled in by the driver as required. This removes the need for platform drivers to maintain a slave structure in data/CAR section. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully Change-Id: Ia15a4f88ef4dcfdf616bb1c22261e7cb642a7573 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/spi/spi_flash.c | 11 ++++--- src/drivers/spi/tpm/tis.c | 10 +++++-- src/drivers/spi/tpm/tpm.c | 18 ++++++------ src/ec/google/chromeec/ec_spi.c | 14 +++++---- src/include/spi-generic.h | 7 +++-- src/soc/broadcom/cygnus/spi.c | 18 ++++++------ src/soc/imgtec/pistachio/spi.c | 46 ++++++++++++++++++------------ src/soc/intel/apollolake/spi.c | 9 ++---- src/soc/intel/baytrail/spi.c | 13 ++------- src/soc/intel/braswell/spi.c | 13 ++------- src/soc/intel/broadwell/spi.c | 13 ++------- src/soc/intel/fsp_baytrail/spi.c | 13 ++------- src/soc/intel/fsp_broadwell_de/spi.c | 13 ++------- src/soc/intel/skylake/flash_controller.c | 9 ++---- src/soc/marvell/armada38x/spi.c | 8 ++---- src/soc/marvell/bg4cd/spi.c | 4 +-- src/soc/mediatek/mt8173/spi.c | 22 +++++++------- src/soc/nvidia/tegra124/spi.c | 9 ++++-- src/soc/nvidia/tegra210/spi.c | 9 ++++-- src/soc/qualcomm/ipq40xx/include/soc/spi.h | 5 ---- src/soc/qualcomm/ipq40xx/spi.c | 34 +++++++++++++++++----- src/soc/qualcomm/ipq806x/include/soc/spi.h | 5 ---- src/soc/qualcomm/ipq806x/spi.c | 32 +++++++++++++++++---- src/soc/rockchip/common/spi.c | 20 ++++++------- src/soc/samsung/exynos5420/spi.c | 13 ++++++--- src/southbridge/amd/agesa/hudson/spi.c | 14 +++------ src/southbridge/amd/cimx/sb800/spi.c | 14 +++------ src/southbridge/amd/sb700/spi.c | 14 +++------ src/southbridge/intel/common/spi.c | 13 ++------- src/southbridge/intel/fsp_rangeley/spi.c | 13 ++------- 30 files changed, 201 insertions(+), 235 deletions(-) diff --git a/src/drivers/spi/spi_flash.c b/src/drivers/spi/spi_flash.c index 54a7c11..16ebc9c 100644 --- a/src/drivers/spi/spi_flash.c +++ b/src/drivers/spi/spi_flash.c @@ -313,25 +313,24 @@ static struct spi_flash *__spi_flash_probe(struct spi_slave *spi) struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs) { - struct spi_slave *spi; + struct spi_slave spi; struct spi_flash *flash; - spi = spi_setup_slave(bus, cs); - if (!spi) { + if (spi_setup_slave(bus, cs, &spi)) { printk(BIOS_WARNING, "SF: Failed to set up slave\n"); return NULL; } /* Try special programmer probe if any (without force). */ - flash = spi_flash_programmer_probe(spi, 0); + flash = spi_flash_programmer_probe(&spi, 0); /* If flash is not found, try generic spi flash probe. */ if (!flash) - flash = __spi_flash_probe(spi); + flash = __spi_flash_probe(&spi); /* If flash is not yet found, force special programmer probe if any. */ if (!flash) - flash = spi_flash_programmer_probe(spi, 1); + flash = spi_flash_programmer_probe(&spi, 1); /* Give up -- nothing more to try if flash is not found. */ if (!flash) { diff --git a/src/drivers/spi/tpm/tis.c b/src/drivers/spi/tpm/tis.c index 055525b..d3c727c 100644 --- a/src/drivers/spi/tpm/tis.c +++ b/src/drivers/spi/tpm/tis.c @@ -58,10 +58,16 @@ int tis_close(void) int tis_init(void) { + struct spi_slave spi; struct tpm2_info info; - if (tpm2_init(spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS, - CONFIG_DRIVER_TPM_SPI_CHIP))) { + if (spi_setup_slave(CONFIG_DRIVER_TPM_SPI_BUS, + CONFIG_DRIVER_TPM_SPI_CHIP, &spi)) { + printk(BIOS_ERR, "Failed to setup TPM SPI slave\n"); + return -1; + } + + if (tpm2_init(&spi)) { printk(BIOS_ERR, "Failed to initialize TPM SPI interface\n"); return -1; } diff --git a/src/drivers/spi/tpm/tpm.c b/src/drivers/spi/tpm/tpm.c index d364cb9..5abfc45 100644 --- a/src/drivers/spi/tpm/tpm.c +++ b/src/drivers/spi/tpm/tpm.c @@ -36,7 +36,7 @@ /* SPI Interface descriptor used by the driver. */ struct tpm_spi_if { - struct spi_slave *slave; + struct spi_slave slave; int (*cs_assert)(const struct spi_slave *slave); void (*cs_deassert)(const struct spi_slave *slave); int (*xfer)(const struct spi_slave *slave, const void *dout, @@ -130,7 +130,7 @@ static void start_transaction(int read_write, size_t bytes, unsigned addr) header.body[i + 1] = (addr >> (8 * (2 - i))) & 0xff; /* CS assert wakes up the slave. */ - tpm_if.cs_assert(tpm_if.slave); + tpm_if.cs_assert(&tpm_if.slave); /* * The TCG TPM over SPI specification introduces the notion of SPI @@ -157,11 +157,11 @@ static void start_transaction(int read_write, size_t bytes, unsigned addr) * to require to stall the master, this would present an issue. * crosbug.com/p/52132 has been opened to track this. */ - tpm_if.xfer(tpm_if.slave, header.body, sizeof(header.body), NULL, 0); + tpm_if.xfer(&tpm_if.slave, header.body, sizeof(header.body), NULL, 0); /* Now poll the bus until TPM removes the stall bit. */ do { - tpm_if.xfer(tpm_if.slave, NULL, 0, &byte, 1); + tpm_if.xfer(&tpm_if.slave, NULL, 0, &byte, 1); } while (!(byte & 1)); } @@ -227,7 +227,7 @@ static void trace_dump(const char *prefix, uint32_t reg, */ static void write_bytes(const void *buffer, size_t bytes) { - tpm_if.xfer(tpm_if.slave, buffer, bytes, NULL, 0); + tpm_if.xfer(&tpm_if.slave, buffer, bytes, NULL, 0); } /* @@ -236,7 +236,7 @@ static void write_bytes(const void *buffer, size_t bytes) */ static void read_bytes(void *buffer, size_t bytes) { - tpm_if.xfer(tpm_if.slave, NULL, 0, buffer, bytes); + tpm_if.xfer(&tpm_if.slave, NULL, 0, buffer, bytes); } /* @@ -251,7 +251,7 @@ static int tpm2_write_reg(unsigned reg_number, const void *buffer, size_t bytes) trace_dump("W", reg_number, bytes, buffer, 0); start_transaction(false, bytes, reg_number); write_bytes(buffer, bytes); - tpm_if.cs_deassert(tpm_if.slave); + tpm_if.cs_deassert(&tpm_if.slave); return 1; } @@ -266,7 +266,7 @@ static int tpm2_read_reg(unsigned reg_number, void *buffer, size_t bytes) { start_transaction(true, bytes, reg_number); read_bytes(buffer, bytes); - tpm_if.cs_deassert(tpm_if.slave); + tpm_if.cs_deassert(&tpm_if.slave); trace_dump("R", reg_number, bytes, buffer, 0); return 1; } @@ -303,7 +303,7 @@ int tpm2_init(struct spi_slave *spi_if) uint32_t did_vid, status; uint8_t cmd; - tpm_if.slave = spi_if; + memcpy(&tpm_if.slave, spi_if, sizeof(*spi_if)); tpm2_read_reg(TPM_DID_VID_REG, &did_vid, sizeof(did_vid)); diff --git a/src/ec/google/chromeec/ec_spi.c b/src/ec/google/chromeec/ec_spi.c index a0049c6..810979e 100644 --- a/src/ec/google/chromeec/ec_spi.c +++ b/src/ec/google/chromeec/ec_spi.c @@ -101,13 +101,17 @@ out: int google_chromeec_command(struct chromeec_command *cec_command) { - static struct spi_slave *slave = NULL; - if (!slave) { - slave = spi_setup_slave(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, - CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP); + static int done = 0; + static struct spi_slave slave; + + if (!done) { + if (spi_setup_slave(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, + CONFIG_EC_GOOGLE_CHROMEEC_SPI_CHIP, &slave)) + return -1; stopwatch_init(&cs_cooldown_sw); + done = 1; } - return crosec_command_proto(cec_command, crosec_spi_io, slave); + return crosec_command_proto(cec_command, crosec_spi_io, &slave); } #ifndef __PRE_RAM__ diff --git a/src/include/spi-generic.h b/src/include/spi-generic.h index 7c53611..c8b209d 100644 --- a/src/include/spi-generic.h +++ b/src/include/spi-generic.h @@ -48,11 +48,12 @@ void spi_init(void); * * bus: Bus ID of the slave chip. * cs: Chip select ID of the slave chip on the specified bus. + * slave: Pointer to slave structure that needs to be initialized. * - * Returns: A spi_slave reference that can be used in subsequent SPI - * calls, or NULL if one or more of the parameters are not supported. + * Returns: + * 0 on success, -1 on error */ -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs); +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave); /*----------------------------------------------------------------------- * Claim the bus and prepare it for communication with a given slave. diff --git a/src/soc/broadcom/cygnus/spi.c b/src/soc/broadcom/cygnus/spi.c index 13b6976..810f2c2 100644 --- a/src/soc/broadcom/cygnus/spi.c +++ b/src/soc/broadcom/cygnus/spi.c @@ -76,9 +76,6 @@ /* QSPI private data */ struct qspi_priv { - /* Slave entry */ - struct spi_slave slave; - /* Specified SPI parameters */ unsigned int max_hz; unsigned int spi_mode; @@ -94,16 +91,19 @@ struct qspi_priv { static struct qspi_priv qspi_slave; -/* Macro to get the private data */ -#define to_qspi_slave(s) container_of(s, struct qspi_priv, slave) +static struct qspi_priv *to_qspi_slave(const struct spi_slave *slave) +{ + return &qspi_slave; +} -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { struct qspi_priv *priv = &qspi_slave; unsigned int spbr; - priv->slave.bus = bus; - priv->slave.cs = cs; + slave->bus = bus; + slave->cs = cs; + priv->max_hz = QSPI_MAX_HZ; priv->spi_mode = QSPI_MODE; priv->reg = (void *)(IPROC_QSPI_BASE); @@ -129,7 +129,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) (8 << 2) | /* 8 bits per word */ (priv->spi_mode & 3)); /* mode: CPOL / CPHA */ - return &priv->slave; + return 0; } static int mspi_enable(struct qspi_priv *priv) diff --git a/src/soc/imgtec/pistachio/spi.c b/src/soc/imgtec/pistachio/spi.c index 9664989..2dd3ecd 100644 --- a/src/soc/imgtec/pistachio/spi.c +++ b/src/soc/imgtec/pistachio/spi.c @@ -26,7 +26,6 @@ #define IMGTEC_SPI_MAX_TRANSFER_SIZE ((1 << 16) - 1) struct img_spi_slave { - struct spi_slave slave; /* SPIM instance device parameters */ struct spim_device_parameters device_parameters; /* SPIM instance base address */ @@ -55,13 +54,20 @@ static int wait_status(u32 reg, u32 shift) return SPIM_OK; } +static struct img_spi_slave *get_img_slave(const struct spi_slave *slave) +{ + return img_spi_slaves + slave->bus * SPIM_NUM_PORTS_PER_BLOCK + + slave->cs; +} + /* Transmitter function. Fills TX FIFO with data before enabling SPIM */ static int transmitdata(const struct spi_slave *slave, u8 *buffer, u32 size) { u32 blocksize, base, write_data; int ret; + struct img_spi_slave *img_slave = get_img_slave(slave); - base = container_of(slave, struct img_spi_slave, slave)->base; + base = img_slave->base; while (size) { /* Wait until FIFO empty */ write32(base + SPFI_INT_CLEAR_REG_OFFSET, SPFI_SDE_MASK); @@ -97,8 +103,9 @@ static int receivedata(const struct spi_slave *slave, u8 *buffer, u32 size) { u32 read_data, base; int ret; + struct img_spi_slave *img_slave = get_img_slave(slave); - base = container_of(slave, struct img_spi_slave, slave)->base; + base = img_slave->base; /* * Do 32bit reads first. Clear status GDEX32BIT here so that the first * status reg. read gets the actual bit state @@ -141,10 +148,10 @@ static void setparams(const struct spi_slave *slave, u32 port, struct spim_device_parameters *params) { u32 spim_parameters, port_state, base; + struct img_spi_slave *img_slave = get_img_slave(slave); + base = img_slave->base; spim_parameters = 0; - - base = container_of(slave, struct img_spi_slave, slave)->base; port_state = read32(base + SPFI_PORT_STATE_REG_OFFSET); port_state &= ~((SPIM_PORT0_MASK>>port)|SPFI_PORT_SELECT_MASK); port_state |= params->cs_idle_level<<(SPIM_CS0_IDLE_SHIFT-port); @@ -246,7 +253,9 @@ static u32 control_reg_setup(struct spim_buffer *first, static int check_buffers(const struct spi_slave *slave, struct spim_buffer *first, struct spim_buffer *second){ - if (!(container_of(slave, struct img_spi_slave, slave)->initialised)) + struct img_spi_slave *img_slave = get_img_slave(slave); + + if (!(img_slave->initialised)) return -SPIM_API_NOT_INITIALISED; /* * First operation must always be defined @@ -327,8 +336,9 @@ static int spim_io(const struct spi_slave *slave, struct spim_buffer *first, u32 reg, base; int i, trans_count, ret; struct spim_buffer *transaction[2]; + struct img_spi_slave *img_slave = get_img_slave(slave); - base = container_of(slave, struct img_spi_slave, slave)->base; + base = img_slave->base; ret = check_buffers(slave, first, second); if (ret) @@ -408,11 +418,9 @@ void spi_init(void) } /* Set up communications parameters for a SPI slave. */ -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - struct img_spi_slave *img_slave = NULL; - struct spi_slave *slave; struct spim_device_parameters *device_parameters; u32 base; @@ -426,21 +434,21 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) default: printk(BIOS_ERR, "%s: Error: unsupported bus.\n", __func__); - return NULL; + return -1; } if (cs > SPIM_DEVICE4) { printk(BIOS_ERR, "%s: Error: unsupported chipselect.\n", __func__); - return NULL; + return -1; } - img_slave = img_spi_slaves + bus * SPIM_NUM_PORTS_PER_BLOCK + cs; - slave = &(img_slave->slave); + slave->bus = bus; + slave->cs = cs; + + img_slave = get_img_slave(slave); device_parameters = &(img_slave->device_parameters); img_slave->base = base; - slave->bus = bus; - slave->cs = cs; device_parameters->bitrate = 64; device_parameters->cs_setup = 0; @@ -451,7 +459,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) device_parameters->data_idle_level = 0; img_slave->initialised = IMG_FALSE; - return slave; + return 0; } /* Claim the bus and prepare it for communication */ @@ -465,7 +473,7 @@ int spi_claim_bus(const struct spi_slave *slave) __func__); return -SPIM_API_NOT_INITIALISED; } - img_slave = container_of(slave, struct img_spi_slave, slave); + img_slave = get_img_slave(slave); if (img_slave->initialised) return SPIM_OK; /* Check device parameters */ @@ -495,7 +503,7 @@ void spi_release_bus(const struct spi_slave *slave) __func__); return; } - img_slave = container_of(slave, struct img_spi_slave, slave); + img_slave = get_img_slave(slave); img_slave->initialised = IMG_FALSE; /* Soft reset peripheral internals */ write32(img_slave->base + SPFI_CONTROL_REG_OFFSET, diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 6e873f4..ca56702 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -344,7 +344,6 @@ static int nuclear_spi_status(const struct spi_flash *flash, uint8_t *reg) return ret; } -static struct spi_slave boot_spi CAR_GLOBAL; static struct spi_flash boot_flash CAR_GLOBAL; /* @@ -391,20 +390,18 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) return flash; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { BOILERPLATE_CREATE_CTX(ctx); /* This is special hardware. We expect bus 0 and CS line 0 here. */ if ((bus != 0) || (cs != 0)) - return NULL; - - struct spi_slave *slave = car_get_var_ptr(&boot_spi); + return -1; slave->bus = bus; slave->cs = cs; - return slave; + return 0; } int spi_read_status(uint8_t *status) diff --git a/src/soc/intel/baytrail/spi.c b/src/soc/intel/baytrail/spi.c index 13f8806..b4f95aa 100644 --- a/src/soc/intel/baytrail/spi.c +++ b/src/soc/intel/baytrail/spi.c @@ -260,20 +260,11 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - ich_spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - slave->bus = bus; slave->cs = cs; - return slave; + return 0; } static ich9_spi_regs *spi_regs(void) diff --git a/src/soc/intel/braswell/spi.c b/src/soc/intel/braswell/spi.c index 34e031b..4236e6f 100644 --- a/src/soc/intel/braswell/spi.c +++ b/src/soc/intel/braswell/spi.c @@ -229,20 +229,11 @@ static void read_reg(void *src, void *value, uint32_t size) } } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - ich_spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - printk(BIOS_ERR, "ICH SPI: Bad allocation\n"); - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - slave->bus = bus; slave->cs = cs; - return slave; + return 0; } static ich9_spi_regs *spi_regs(void) diff --git a/src/soc/intel/broadwell/spi.c b/src/soc/intel/broadwell/spi.c index 6aa7dd3..5220970 100644 --- a/src/soc/intel/broadwell/spi.c +++ b/src/soc/intel/broadwell/spi.c @@ -259,20 +259,11 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - ich_spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - slave->bus = bus; slave->cs = cs; - return slave; + return 0; } void spi_init(void) diff --git a/src/soc/intel/fsp_baytrail/spi.c b/src/soc/intel/fsp_baytrail/spi.c index 232366c..06b160c 100644 --- a/src/soc/intel/fsp_baytrail/spi.c +++ b/src/soc/intel/fsp_baytrail/spi.c @@ -249,20 +249,11 @@ static void read_reg(const void *src, void *value, uint32_t size) } } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - ich_spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - slave->bus = bus; slave->cs = cs; - return slave; + return 0; } static ich9_spi_regs *spi_regs(void) diff --git a/src/soc/intel/fsp_broadwell_de/spi.c b/src/soc/intel/fsp_broadwell_de/spi.c index c38fbce..8af5686 100644 --- a/src/soc/intel/fsp_broadwell_de/spi.c +++ b/src/soc/intel/fsp_broadwell_de/spi.c @@ -259,20 +259,11 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave * slave) { - ich_spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - slave->bus = bus; slave->cs = cs; - return slave; + return 0; } void spi_init(void) diff --git a/src/soc/intel/skylake/flash_controller.c b/src/soc/intel/skylake/flash_controller.c index 8aee796..734d9d3 100644 --- a/src/soc/intel/skylake/flash_controller.c +++ b/src/soc/intel/skylake/flash_controller.c @@ -342,7 +342,6 @@ int pch_hwseq_read_status(const struct spi_flash *flash, u8 *reg) return 0; } -static struct spi_slave boot_spi CAR_GLOBAL; static struct spi_flash boot_flash CAR_GLOBAL; struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) @@ -370,18 +369,16 @@ struct spi_flash *spi_flash_programmer_probe(struct spi_slave *spi, int force) return flash; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { /* This is special hardware. We expect bus 0 and CS line 0 here. */ if ((bus != 0) || (cs != 0)) - return NULL; - - struct spi_slave *slave = car_get_var_ptr(&boot_spi); + return -1; slave->bus = bus; slave->cs = cs; - return slave; + return 0; } int spi_flash_get_fpr_info(struct fpr_info *info) diff --git a/src/soc/marvell/armada38x/spi.c b/src/soc/marvell/armada38x/spi.c index 9a0b963..b628170 100644 --- a/src/soc/marvell/armada38x/spi.c +++ b/src/soc/marvell/armada38x/spi.c @@ -153,8 +153,6 @@ static MV_SPI_TYPE_INFO spi_types[] = { {.en16_bit = MV_TRUE, param define end *******************************************************************************/ -static struct spi_slave s_spi; - static int mv_spi_baud_rate_set(unsigned char spi_id, unsigned int serial_baud_rate); static void mv_spi_cs_deassert(unsigned char spi_id); @@ -444,14 +442,12 @@ static int mrvl_spi_xfer(const struct spi_slave *slave, return 0; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - struct spi_slave *slave = &s_spi; - slave->bus = bus; slave->cs = cs; mv_spi_sys_init(bus, cs, CONFIG_SF_DEFAULT_SPEED); - return slave; + return 0; } int spi_claim_bus(const struct spi_slave *slave) diff --git a/src/soc/marvell/bg4cd/spi.c b/src/soc/marvell/bg4cd/spi.c index 9a999b0..54161bc 100644 --- a/src/soc/marvell/bg4cd/spi.c +++ b/src/soc/marvell/bg4cd/spi.c @@ -15,9 +15,9 @@ #include <stddef.h> #include <spi-generic.h> -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - return NULL; + return -1; } int spi_claim_bus(const struct spi_slave *slave) diff --git a/src/soc/mediatek/mt8173/spi.c b/src/soc/mediatek/mt8173/spi.c index f60de6c..d02f02d 100644 --- a/src/soc/mediatek/mt8173/spi.c +++ b/src/soc/mediatek/mt8173/spi.c @@ -47,9 +47,6 @@ enum { static struct mtk_spi_bus spi_bus[1] = { { - .slave = { - .bus = 0, - }, .regs = (void *)SPI_BASE, .state = MTK_SPI_IDLE, } @@ -57,7 +54,8 @@ static struct mtk_spi_bus spi_bus[1] = { static inline struct mtk_spi_bus *to_mtk_spi(const struct spi_slave *slave) { - return container_of(slave, struct mtk_spi_bus, slave); + assert(slave->bus >= ARRAY_SIZE(spi_bus)); + return &spi_bus[slave->bus]; } static void spi_sw_reset(struct mtk_spi_regs *regs) @@ -162,24 +160,26 @@ static void mtk_spi_dump_data(const char *name, const uint8_t *data, #endif } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { struct mtk_spi_bus *eslave; - static struct spi_slave slave; switch (bus) { case CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS: - eslave = &spi_bus[bus]; + slave->bus = bus; + slave->cs = cs; + eslave = to_mtk_spi(slave); assert(read32(&eslave->regs->spi_cfg0_reg) != 0); spi_sw_reset(eslave->regs); - return &eslave->slave; + return 0; case CONFIG_BOOT_DEVICE_SPI_FLASH_BUS: - slave.bus = bus; - slave.cs = cs; - return &slave; + slave->bus = bus; + slave->cs = cs; + return 0; default: die ("wrong bus number.\n"); }; + return -1; } int spi_claim_bus(const struct spi_slave *slave) diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 71b8735..d5b2915 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -811,11 +811,14 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, return ret; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { struct tegra_spi_channel *channel = to_tegra_spi(bus); if (!channel) - return NULL; + return -1; - return &channel->slave; + slave->bus = channel->slave.bus; + slave->cs = channel->slave.cs; + + return 0; } diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index df3b8a1..cecf573 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -847,11 +847,14 @@ int spi_xfer(const struct spi_slave *slave, const void *dout, size_t out_bytes, return ret; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { struct tegra_spi_channel *channel = to_tegra_spi(bus); if (!channel) - return NULL; + return -1; - return &channel->slave; + slave->cs = channel->slave.cs; + slave->bus = channel->slave.bus; + + return 0; } diff --git a/src/soc/qualcomm/ipq40xx/include/soc/spi.h b/src/soc/qualcomm/ipq40xx/include/soc/spi.h index 8ef1fbf..b91e6ca 100644 --- a/src/soc/qualcomm/ipq40xx/include/soc/spi.h +++ b/src/soc/qualcomm/ipq40xx/include/soc/spi.h @@ -186,9 +186,4 @@ struct ipq_spi_slave { int allocated; }; -static inline struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) -{ - return container_of(slave, struct ipq_spi_slave, slave); -} - #endif /* _IPQ40XX_SPI_H_ */ diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 871f24b..cda3bea 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -207,7 +207,26 @@ void spi_init(void) memset(spi_slave_pool, 0, sizeof(spi_slave_pool)); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds; + size_t i; + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + ds = spi_slave_pool + i; + + if (!ds->allocated) + continue; + + if ((ds->slave.bus == slave->bus) && + (ds->slave.cs == slave->cs)) + return ds; + } + + return NULL; +} + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { struct ipq_spi_slave *ds = NULL; int i; @@ -218,16 +237,17 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) printk(BIOS_ERR, "SPI error: unsupported bus %d (Supported busses 0, 1 and 2) " "or chipselect\n", bus); - return NULL; + return -1; } for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { if (spi_slave_pool[i].allocated) continue; ds = spi_slave_pool + i; - ds->slave.bus = bus; - ds->slave.cs = cs; - ds->regs = &spi_reg[bus]; + + ds->slave.bus = slave->bus = bus; + ds->slave.cs = slave->cs = cs; + ds->regs = &spi_reg[bus]; /* * TODO(vbendeb): @@ -238,11 +258,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) ds->mode = SPI_MODE3; ds->allocated = 1; - return &ds->slave; + return 0; } printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); - return NULL; + return -1; } /* diff --git a/src/soc/qualcomm/ipq806x/include/soc/spi.h b/src/soc/qualcomm/ipq806x/include/soc/spi.h index 5dedcda..98a15b8 100644 --- a/src/soc/qualcomm/ipq806x/include/soc/spi.h +++ b/src/soc/qualcomm/ipq806x/include/soc/spi.h @@ -271,9 +271,4 @@ struct ipq_spi_slave { int allocated; }; -static inline struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) -{ - return container_of(slave, struct ipq_spi_slave, slave); -} - #endif /* _IPQ806X_SPI_H_ */ diff --git a/src/soc/qualcomm/ipq806x/spi.c b/src/soc/qualcomm/ipq806x/spi.c index d1af720..81dc508 100644 --- a/src/soc/qualcomm/ipq806x/spi.c +++ b/src/soc/qualcomm/ipq806x/spi.c @@ -499,7 +499,26 @@ void spi_init() memset(spi_slave_pool, 0, sizeof(spi_slave_pool)); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +static struct ipq_spi_slave *to_ipq_spi(const struct spi_slave *slave) +{ + struct ipq_spi_slave *ds; + size_t i; + + for (i = 0; i < ARRAY_SIZE(spi_slave_pool); i++) { + ds = spi_slave_pool + i; + + if (!ds->allocated) + continue; + + if ((ds->slave.bus == slave->bus) && + (ds->slave.cs == slave->cs)) + return ds; + } + + return NULL; +} + +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { struct ipq_spi_slave *ds = NULL; int i; @@ -521,9 +540,10 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) if (spi_slave_pool[i].allocated) continue; ds = spi_slave_pool + i; - ds->slave.bus = bus; - ds->slave.cs = cs; - ds->regs = &spi_reg[bus]; + + ds->slave.bus = slave->bus = bus; + ds->slave.cs = slave->cs = cs; + ds->regs = &spi_reg[bus]; /* * TODO(vbendeb): @@ -534,11 +554,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) ds->mode = GSBI_SPI_MODE_0; ds->allocated = 1; - return &ds->slave; + return 0; } printk(BIOS_ERR, "SPI error: all %d pools busy\n", i); - return NULL; + return -1; } /* diff --git a/src/soc/rockchip/common/spi.c b/src/soc/rockchip/common/spi.c index c5e5018..5f8eac5 100644 --- a/src/soc/rockchip/common/spi.c +++ b/src/soc/rockchip/common/spi.c @@ -27,7 +27,6 @@ #include <timer.h> struct rockchip_spi_slave { - struct spi_slave slave; struct rockchip_spi *regs; }; @@ -37,30 +36,24 @@ struct rockchip_spi_slave { static struct rockchip_spi_slave rockchip_spi_slaves[] = { { - .slave = { .bus = 0, }, .regs = (void *)SPI0_BASE, }, { - .slave = { .bus = 1, }, .regs = (void *)SPI1_BASE, }, { - .slave = { .bus = 2, }, .regs = (void *)SPI2_BASE, }, #ifdef SPI3_BASE { - .slave = { .bus = 3, }, .regs = (void *)SPI3_BASE, }, #ifdef SPI4_BASE { - .slave = { .bus = 4, }, .regs = (void *)SPI4_BASE, }, #ifdef SPI5_BASE { - .slave = { .bus = 5, }, .regs = (void *)SPI5_BASE, }, #endif @@ -70,13 +63,18 @@ static struct rockchip_spi_slave rockchip_spi_slaves[] = { static struct rockchip_spi_slave *to_rockchip_spi(const struct spi_slave *slave) { - return container_of(slave, struct rockchip_spi_slave, slave); + assert(slave->bus < ARRAY_SIZE(rockchip_spi_slaves)); + return &rockchip_spi_slaves[slave->bus]; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - assert(bus >= 0 && bus < ARRAY_SIZE(rockchip_spi_slaves)); - return &(rockchip_spi_slaves[bus].slave); + assert(bus < ARRAY_SIZE(rockchip_spi_slaves)); + + slave->bus = bus; + slave->cs = cs; + + return 0; } static void spi_cs_activate(const struct spi_slave *slave) diff --git a/src/soc/samsung/exynos5420/spi.c b/src/soc/samsung/exynos5420/spi.c index 02f04df..c809bb3 100644 --- a/src/soc/samsung/exynos5420/spi.c +++ b/src/soc/samsung/exynos5420/spi.c @@ -60,7 +60,7 @@ static struct exynos_spi_slave exynos_spi_slaves[3] = { static inline struct exynos_spi_slave *to_exynos_spi(const struct spi_slave *slave) { - return container_of(slave, struct exynos_spi_slave, slave); + return &exynos_spi_slaves[slave->bus]; } static void spi_sw_reset(struct exynos_spi *regs, int word) @@ -117,15 +117,20 @@ static void exynos_spi_init(struct exynos_spi *regs) spi_sw_reset(regs, 1); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { ASSERT(bus >= 0 && bus < 3); - struct exynos_spi_slave *eslave = &exynos_spi_slaves[bus]; + struct exynos_spi_slave *eslave; + + slave->bus = bus; + slave->cs = cs; + + eslave = to_exynos_spi(slave); if (!eslave->initialized) { exynos_spi_init(eslave->regs); eslave->initialized = 1; } - return &eslave->slave; + return 0; } int spi_claim_bus(const struct spi_slave *slave) diff --git a/src/southbridge/amd/agesa/hudson/spi.c b/src/southbridge/amd/agesa/hudson/spi.c index 7bb0e3f..a8b3b2a 100644 --- a/src/southbridge/amd/agesa/hudson/spi.c +++ b/src/southbridge/amd/agesa/hudson/spi.c @@ -176,15 +176,9 @@ int chipset_volatile_group_end(const struct spi_flash *flash) return 0; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - struct spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - - return slave; + slave->bus = bus; + slave->cs = cs; + return 0; } diff --git a/src/southbridge/amd/cimx/sb800/spi.c b/src/southbridge/amd/cimx/sb800/spi.c index 2522c2e..d331060 100644 --- a/src/southbridge/amd/cimx/sb800/spi.c +++ b/src/southbridge/amd/cimx/sb800/spi.c @@ -168,15 +168,9 @@ int chipset_volatile_group_end(const struct spi_flash *flash) return 0; } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - struct spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - - return slave; + slave->bus = bus; + slave->cs = cs; + return 0; } diff --git a/src/southbridge/amd/sb700/spi.c b/src/southbridge/amd/sb700/spi.c index 2b1ae2d..fca401c 100644 --- a/src/southbridge/amd/sb700/spi.c +++ b/src/southbridge/amd/sb700/spi.c @@ -76,17 +76,11 @@ void spi_release_bus(const struct spi_slave *slave) /* Handled internally by the SB700 */ } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - struct spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - - return slave; + slave->bus = bus; + slave->cs = cs; + return 0; } int spi_xfer(const struct spi_slave *slave, const void *dout, diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 2d36d38..7e0cc20 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -285,20 +285,11 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - ich_spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - slave->bus = bus; slave->cs = cs; - return slave; + return 0; } void spi_init(void) diff --git a/src/southbridge/intel/fsp_rangeley/spi.c b/src/southbridge/intel/fsp_rangeley/spi.c index 8a0fac2..de676a9 100644 --- a/src/southbridge/intel/fsp_rangeley/spi.c +++ b/src/southbridge/intel/fsp_rangeley/spi.c @@ -322,20 +322,11 @@ static void ich_set_bbar(uint32_t minaddr) writel_(ichspi_bbar, cntlr.bbar); } -struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs) +int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave) { - ich_spi_slave *slave = malloc(sizeof(*slave)); - - if (!slave) { - printk(BIOS_DEBUG, "ICH SPI: Bad allocation\n"); - return NULL; - } - - memset(slave, 0, sizeof(*slave)); - slave->bus = bus; slave->cs = cs; - return slave; + return 0; } /*

1 0

Patch set updated for coreboot: util/crossgcc: Toolchain verified sources
by Philipp Deppenwiese 01 Dec '16

01 Dec '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15170 -gerrit commit 1df0c3c3ee27f4e7a10ac9f2175503bca03191df Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Mon Jun 13 17:01:07 2016 -0700 util/crossgcc: Toolchain verified sources Currently there is no toolchain verification in coreboot. This patchset extends the existing buildgcc script in the following way: Before download or unpack operations the checksum of all used packages are checked against the trustworthy checksums in util/crossgcc/sum. With the option -g checksum can be automatically generated for updated packages as long they support gpg. Only the maintainers can commit checksum changes to the coreboot repository. Some libraries don't offer this possiblity and on update maintainers need to check the sources by themself adding checksums manually! The checksum algorithm changed from sha1 to sha384. If you ask yourself why we don't use sha256 or sha512 for the checksum verification. You should take a look at following wiki article. https://en.wikipedia.org/wiki/Length_extension_attack Also the url changed from http to https for security reasons where it was possible to do that. Change-Id: Id45097fc7e8435fadce4bda75769592af2730b0c Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- util/crossgcc/buildgcc | 222 +++++++++++++++++---- util/crossgcc/gpg.keyring | Bin 0 -> 222182 bytes util/crossgcc/sum/Python-3.5.1.tar.xz.cksum | 2 +- .../sum/acpica-unix2-20160831.tar.gz.cksum | 2 +- util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum | 2 +- .../sum/clang-tools-extra-3.8.0.src.tar.xz.cksum | 2 +- .../sum/compiler-rt-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum | 2 +- util/crossgcc/sum/gdb-7.11.tar.xz.cksum | 2 +- util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum | 2 +- util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum | 2 +- util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/make-4.2.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum | 2 +- util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum | 2 +- util/lint/lint-stable-003-whitespace | 2 +- 18 files changed, 197 insertions(+), 57 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index d64b687..4cbc6ea 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -5,6 +5,7 @@ # Stefan Reinauer <stefan.reinauer(a)coresystems.de> # # Copyright (C) 2011 by Sage Electronic Engineering +# Copyright (C) 2016 by Philipp Deppenwiese # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -18,9 +19,9 @@ cd $(dirname $0) -CROSSGCC_DATE="August 31st, 2016" -CROSSGCC_VERSION="1.43" -CROSSGCC_COMMIT=$( git describe ) +CROSSGCC_DATE="November 07th, 2016" +CROSSGCC_VERSION="1.44" +CROSSGCC_COMMIT=$(git describe) # default settings PACKAGE=GCC @@ -32,6 +33,7 @@ DESTDIR= SAVETEMPS=0 SKIPPYTHON=1 BOOTSTRAP=0 +GENERATE_CHECKSUMS=0 THREADS=1 # GCC toolchain version numbers @@ -50,6 +52,8 @@ EXPAT_VERSION=2.1.1 CLANG_VERSION=3.8.0 MAKE_VERSION=4.2.1 +GPG_KEYRING="$PWD"/gpg.keyring + # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if # a completely new URL is added here, it probably needs to be added @@ -100,6 +104,8 @@ red='\033[0;31m' RED='\033[1;31m' green='\033[0;32m' GREEN='\033[1;32m' +yellow='\033[0;33m' +YELLOW='\033[1;33m' blue='\033[0;34m' BLUE='\033[1;34m' cyan='\033[0;36m' @@ -261,49 +267,163 @@ check_cc() { fi } -check_sum() { - test -z "$CHECKSUM" || \ - test "$(cat sum/$1.cksum 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" = \ - "$($CHECKSUM tarballs/$1 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" +verify_signature() { + SIGNATURE_FILE="$1" + SOURCE_FILE="$2" + + if [ -z "${GPG}" ] ; then + printf "\n * ${RED}GPG tool not found. Please install gnupg on your os.${NC}\n" + return 1 + fi + + if [ ! -f "${GPG_KEYRING}" ]; then + printf "\n * ${RED}The gpg keyring can't be found.${NC}\n" + return 1 + fi + + if [ ! -f "tarballs/${SIGNATURE_FILE}" ]; then + printf "\n * ${RED}No signature file found for package: ${SOURCE_FILE} !! PLEASE CHECK MANUALLY WHAT YOU DOWNLOADED, ABORTING CHECKSUM CREATION.${NC}\n" + return 1 + fi + + if [ ! -f "tarballs/${SOURCE_FILE}" ]; then + printf "\n * ${RED}Source file couldn't be downloaded.${NC}\n" + return 1 + fi + + GPG_OUTPUT=$(${GPG} --no-default-keyring --keyring ${GPG_KEYRING} --status-fd 1 --verify "tarballs/${SIGNATURE_FILE}" "tarballs/${SOURCE_FILE}" 2>&1) + if [ "${?}" = "0" ] ; then + printf "\n * ${GREEN}Signature is good and verified!${NC}" + return 0 + fi + + printf "\n * ${RED}Failed to verify signature of package.${NC}\n" + printf "\n * ${RED}Error: ${GPG_OUTPUT} ${NC}\n" + return 1 +} + +calculate_checksum() { + SOURCE_FILE=$1 + + test ! -f sum/"${SOURCE_FILE}".cksum && test -f tarballs/"${SOURCE_FILE}" && \ + ("${OPENSSL}" sha384 tarballs/"${SOURCE_FILE}" > sum/"${SOURCE_FILE}".cksum ) && \ + printf "\n * Checksum created. ${CYAN}Note. Please upload sum/"${SOURCE_FILE}".cksum if the corresponding archive is upgraded.${NC}" +} + +verify_checksum() { + STATIC_HASH=$(${AWK} '{ print $2 }' <sum/$1.cksum) + FILE_HASH=$(${OPENSSL} sha384 tarballs/$1 | ${AWK} '{ print $2 }') + + if [ "${STATIC_HASH}" != "${FILE_HASH}" ]; then + printf "\n * ${RED}Failed to verify checksum of package ${1}.${NC}\n" + exit 1 + fi + + printf "\n * ${GREEN}Checksum 0x${FILE_HASH} verified.${NC}\n" } -compute_sum() { - test ! -f sum/$1.cksum && test -f tarballs/$1 && \ - (test -z "$CHECKSUM" || $CHECKSUM tarballs/$1 > sum/$1.cksum ) && \ - printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}" +validate_url() { + CHECK_URL=$(wget -S --spider $1 2>&1 | grep 'HTTP/1.1 200 OK') + if [ "${?}" = "0" ] ; then + return 1 + else + return 0 + fi } download_showing_percentage() { - url=$1 - printf " ..${red} 0%%" - wget --no-check-certificate $url 2>&1 | while read line; do - echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' - done - printf "${NC}" + NO_WARNING="$2" + URL=$1 + printf " ..${YELLOW} 0%%${NC}" + + if ! validate_url ${URL}; then + wget ${URL} 2>&1 | while read line; do + printf "${YELLOW}" + echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' + printf "${NC}" + done + if [ ${?} != "0" ]; then + printf "\n${YELLOW} * ${URL} is not valid.${NC}" + return 1 + fi + elif [ "$NO_WARNING" = "0" ]; then + printf "\n${YELLOW} * ${URL} is not valid.${NC}" + return 1 + fi + + return 0 } download() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" - FILE=$(basename $archive) - printf " * $FILE " + SOURCE_FILE=$(basename ${archive}) - if test -f tarballs/$FILE && check_sum $FILE ; then + if test -f tarballs/${SOURCE_FILE} ; then printf "(cached)" else + rm -f tarballs/${SOURCE_FILE}* + cd tarballs || exit 1 + + printf " * ${SOURCE_FILE} " printf "(downloading from $archive)" - rm -f tarballs/$FILE - cd tarballs - download_showing_percentage $archive + download_showing_percentage ${archive} 0 + cd .. - compute_sum $FILE fi - if [ ! -f tarballs/$FILE ]; then - printf "\n${RED}Failed to download $FILE.${NC}\n" + if [ ! -f tarballs/${SOURCE_FILE} ]; then + printf "\n${RED} * Failed to download ${SOURCE_FILE}.${NC}\n" exit 1 fi + + printf "\n" +} + +generate_checksums() { + package=$1 + archive="$(eval echo \$$package"_ARCHIVE")" + SOURCE_FILE=$(basename ${archive}) + SIGNATURE_FILE="dummy" + + rm -f tarballs/${SOURCE_FILE}* + rm -f sum/${SOURCE_FILE}.cksum* + cd tarballs || exit 1 + + printf " * ${SOURCE_FILE} " + printf "(downloading from ${archive})" + download_showing_percentage ${archive} 0 + + printf "\n * ${SOURCE_FILE} " + printf "(downloading signature file ${archive}.sig)" + + download_showing_percentage "${archive}.sig" 0 + if [ "${?}" = "0" ] ; then + SIGNATURE_FILE=$(basename ${archive}.sig) + fi + + printf "\n * ${SOURCE_FILE} " + printf "(downloading signature file ${archive}.asc)" + + download_showing_percentage "${archive}.asc" 0 + if [ "${?}" = "0" ] ; then + SIGNATURE_FILE=$(basename ${archive}.asc) + fi + + cd .. + + verify_signature ${SIGNATURE_FILE} ${SOURCE_FILE} + if [ "${?}" = "0" ] ; then + calculate_checksum ${SOURCE_FILE} + verify_checksum ${SOURCE_FILE} ${archive} + fi + + if [ ! -f tarballs/${SOURCE_FILE} ]; then + printf "\n${RED}Failed to download ${SOURCE_FILE}.${NC}\n" + exit 1 + fi + printf "\n" } @@ -311,6 +431,10 @@ unpack_and_patch() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" dir="$(eval echo \$$package"_DIR")" + FILE="$(basename $archive)" + + verify_checksum ${FILE} ${archive} + test -d ${dir} && test -f ${dir}/.unpack_success || ( printf " * $(basename $archive)\n" FLAGS=zxf @@ -434,7 +558,7 @@ cleanup() myhelp() { - printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S]\n" + printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S] [-g]\n" printf " $0 [-V|--version]\n" printf " $0 [-h|--help]\n\n" @@ -464,7 +588,9 @@ myhelp() printf "GDB specific options:\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" - printf " [-S|--scripting] build scripting support for GDB\n\n" + printf " [-S|--scripting] build scripting support for GDB\n" + printf " [-g|--generate-checksums] re-generates the checksum for all packages and\n" + printf " verifies them with the help of gpg signatures\n\n" printf "Platforms for GCC & GDB:\n" printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n" printf " powerpc64le-linux-gnu nds32le-elf\n\n" @@ -481,6 +607,7 @@ myversion() cat << EOF Copyright (C) 2008-2010 by coresystems GmbH Copyright (C) 2011 by Sage Electronic Engineering +Copyright (C) 2016 by Philipp Deppenwiese This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -749,12 +876,12 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:,urls,nocolor -o Vhcd:bp:l:P:j:D:tSys:un -- "$@") + args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:,generate_checksums,urls,nocolor -o Vhcd:bp:l:P:j:D:tSys:gun -- "$@") getopt_ret=$? eval set -- "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:bp:l:P:j:D:tSys:un $*) + args=$(getopt Vhcd:bp:l:P:j:D:tSys:gun $*) getopt_ret=$? set -- $args fi @@ -782,7 +909,8 @@ while true ; do -s|--supported) shift; PRINTSTABLE="$1"; shift;; -u|--urls) shift; printf "%s\n" "$ALL_ARCHIVES"; exit 0;; -n|--nocolor) shift; \ - unset red RED green GREEN blue BLUE cyan CYAN NC;; + unset red RED green GREEN blue BLUE cyan CYAN yellow YELLOW NC;; + -g|--generate-checksums) shift; GENERATE_CHECKSUMS=1;; --) shift; break;; *) break;; esac @@ -848,6 +976,10 @@ case "$PACKAGE" in NAME="GNU Make" PACKAGES=MAKE ;; + ALL|all) + NAME="All packages" + PACKAGES="GMP MPFR MPC LIBELF BINUTILS GCC EXPAT PYTHON GDB LLVM CFE CRT CTE IASL MAKE" + ;; *) printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL, MAKE)${NC}\n\n"; exit 1 @@ -856,15 +988,14 @@ esac # Find all the required tools: -TAR=$(searchtool tar) || exit $? -PATCH=$(searchtool patch) || exit $? -MAKE=$(searchtool make) || exit $? -SHA1SUM=$(searchtool sha1sum) -#SHA512SUM=$(searchtool sha512sum) -#MD5SUM=$(searchtool md5sum) -CHECKSUM=$SHA1SUM -LBZIP2=$(searchtool lbzip2 "" nofail) -PIGZ=$(searchtool pigz "" nofail) +TAR=$(searchtool tar "tar") +PATCH=$(searchtool patch "patch") +MAKE=$(searchtool make "Make") +LBZIP2=$(searchtool lbzip2 "bzip2" nofail) +PIGZ=$(searchtool pigz "pigz" nofail) +GPG=$(searchtool gpg "gpg" nofail) +OPENSSL=$(searchtool openssl "openssl") +AWK=$(searchtool awk "Awk") searchtool m4 > /dev/null searchtool bison > /dev/null @@ -946,6 +1077,15 @@ if [ "$USECCACHE" = 1 ]; then CC="ccache $CC" fi +if [ "$GENERATE_CHECKSUMS" = 1 ]; then + mkdir -p tarballs + for P in $PACKAGES; do + generate_checksums $P + done + + exit 0 +fi + # Prepare target directory for building GCC # (dependencies must be in the PATH) mkdir -p $DESTDIR$TARGETDIR/bin @@ -977,7 +1117,7 @@ printf "Packages built ... ${green}ok${NC}\n" # for reproducibility PROGNAME=$(basename "$0") rm -f "$DESTDIR$TARGETDIR/share/$PROGNAME-*" -cp "$PROGNAME" "$DESTDIR$TARGETDIR/share/$PROGNAME-$CROSSGCC_VERSION-$CROSGCC_COMMIT" +cp "$PROGNAME" "$DESTDIR$TARGETDIR/share/$PROGNAME-$CROSSGCC_VERSION-$CROSSGCC_COMMIT" cleanup diff --git a/util/crossgcc/gpg.keyring b/util/crossgcc/gpg.keyring new file mode 100644 index 0000000..8cbce7e Binary files /dev/null and b/util/crossgcc/gpg.keyring differ diff --git a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum index 58affb0..46f43a3 100644 --- a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum +++ b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum @@ -1 +1 @@ -0186da436db76776196612b98bb9c2f76acfe90e tarballs/Python-3.5.1.tar.xz +SHA384(tarballs/Python-3.5.1.tar.xz)= 9aca49d2cde4760035f4fff23e8a446f6451e8effb6e6fab3f259645a631593acb2ce3412aadf810f103f3f6b561abe7 diff --git a/util/crossgcc/sum/acpica-unix2-20160831.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20160831.tar.gz.cksum index d7e538b..6b39768 100644 --- a/util/crossgcc/sum/acpica-unix2-20160831.tar.gz.cksum +++ b/util/crossgcc/sum/acpica-unix2-20160831.tar.gz.cksum @@ -1 +1 @@ -7e7449f15a195fefd72b65b1671df18e4dccf665 tarballs/acpica-unix2-20160831.tar.gz +SHA384(tarballs/acpica-unix2-20160831.tar.gz)= 171f914bbfc71a69011494cd3484bc87e5ce6b28558699585c8719c250094140357793ead18d2432573a61a1ea5afc6c diff --git a/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum b/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum index 4bd0bce..b3a7126 100644 --- a/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum +++ b/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum @@ -1 +1 @@ -624cd377e3a8eef3db83a56ce289a60f556b3ec2 tarballs/binutils-2.26.1.tar.bz2 +SHA384(tarballs/binutils-2.26.1.tar.bz2)= 30cc8be8c230d69b966b80268223b823b3d301c83472317a4b6ff3aa9dd528a31cb1af33640097854e0e34743b1339b7 diff --git a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum index 7ba8c8c..48ccfbf 100644 --- a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -2230ef962f2df3c13ec93f5b04b0e3cdff94b2ce tarballs/cfe-3.8.0.src.tar.xz +SHA384(tarballs/cfe-3.8.0.src.tar.xz)= 3edbe3cafc58ad6fc3d3a133156a656ea7756e8a36176b29bba63434d6f073cef63241cc6df8337fcab3832dd5b5c485 diff --git a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum index e9d8d72..2c4154c 100644 --- a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -a99d8b6fc5e593c4671424b327779318a1856acf tarballs/clang-tools-extra-3.8.0.src.tar.xz +SHA384(tarballs/clang-tools-extra-3.8.0.src.tar.xz)= abd447239f09295f8592225bb7e07ba57cedc3d19a4972b45cd7d70a2db82106d1874a5be03656f8209a0e8a1308fb31 diff --git a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum index 081705d..8637b48 100644 --- a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -480ea09e369dac6de1f3759b27fa19417b26b69e tarballs/compiler-rt-3.8.0.src.tar.xz +SHA384(tarballs/compiler-rt-3.8.0.src.tar.xz)= 4560d512f3c3a0dbcc5c29ab7754b07d91ffa1ddc1c06a5215f3d325bc3f138ebf483e2a37abb10fc36cd125e6bf559e diff --git a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum b/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum index 882e501..e3a94fa 100644 --- a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum +++ b/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum @@ -1 +1 @@ -ff91419882ac52151050dad0ee8190645fbeee08 tarballs/expat-2.1.1.tar.bz2 +SHA384(tarballs/expat-2.1.1.tar.bz2)= 816e8ca9ac57b6aac76e9979d11714313246492a49c228bb0a16d349174be45cd780d760524eb45acf12ff371e8b96a3 diff --git a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum index bb05e39..073390b 100644 --- a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum +++ b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum @@ -1 +1 @@ -0612270b103941da08376df4d0ef4e5662a2e9eb tarballs/gcc-5.3.0.tar.bz2 +SHA384(tarballs/gcc-5.3.0.tar.bz2)= 4184972f66dc929686c30936cf8f5085829d8584118ebc3e2ec53a40754afbefc351cfd2c211c09dd3b6eb4ab4759820 diff --git a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum index ffe5a1c..f3082e7 100644 --- a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum +++ b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum @@ -1 +1 @@ -466208d771d97d3dfcf965d5c835a669cff8d847 tarballs/gdb-7.11.tar.xz +SHA384(tarballs/gdb-7.11.tar.xz)= 82f89ef35ea1916d5faa67b7fefa2ac3627894d245c43fb4e20828274566cbbb5d7f83899baad77a3cf7fe9fec6f8c7b diff --git a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum index 348b80f..e0ebab2 100644 --- a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum +++ b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum @@ -1 +1 @@ -99d691607613e749aa5d7c0c2a89aeab38fec070 tarballs/gmp-6.1.0.tar.xz +SHA384(tarballs/gmp-6.1.0.tar.xz)= ec69b394cbcf887ab0717473b04bb70ce30102abf24869eca5acb781de405d3a5670fabb776ba68cfe6e117631522d9f diff --git a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum index daa27c6..46f991d 100644 --- a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum +++ b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum @@ -1 +1 @@ -c1d6ac5f182d19dd685c4dfd74eedbfe3992425d tarballs/libelf-0.8.13.tar.gz +SHA384(tarballs/libelf-0.8.13.tar.gz)= 07fc0b1a40ba3d2b003899df199d1043bb5d44cf7d913e6460c985582e5275b634edb6af6779255d770010fd7d09580e diff --git a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum index 2f0af53..e407716 100644 --- a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -723ac918979255706434a05f5af34b71c49c9971 tarballs/llvm-3.8.0.src.tar.xz +SHA384(tarballs/llvm-3.8.0.src.tar.xz)= 5d5a012e4d494a4534fcec7643ad28bab7467b96029b6d497e1d523357ae7c9e8bd86400dc90e261d791d6391a369b30 diff --git a/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum b/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum index 34af72c..5c8a69c9 100644 --- a/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum +++ b/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum @@ -1 +1 @@ -7d9d11eb36cfb752da1fb11bb3e521d2a3cc8830 tarballs/make-4.2.1.tar.bz2 +SHA384(tarballs/make-4.2.1.tar.bz2)= 07fed67f907c8139cd27d606069ce20f219ccf1d047d2ebb2a2b3242d4332957a64b7ff8c3b5db4b28dcbbfdb2ad1e01 diff --git a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum index c7ca1ac..50c2c67 100644 --- a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum +++ b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum @@ -1 +1 @@ -b8be66396c726fdc36ebb0f692ed8a8cca3bcc66 tarballs/mpc-1.0.3.tar.gz +SHA384(tarballs/mpc-1.0.3.tar.gz)= dceeb2566d6145fa771641d22de3bef866fa601fe1fa964bc680a275919080bd12bc1abab4f68cecdbaef71d295b7397 diff --git a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum index 90f90eb..88cd06c 100644 --- a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum +++ b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum @@ -1 +1 @@ -cedc0055d55b6ee4cd17e1e6119ed412520ff81a tarballs/mpfr-3.1.4.tar.xz +SHA384(tarballs/mpfr-3.1.4.tar.xz)= 30a2807378f578544538810b24bb65d44268015e5d2390d8ae6383fe3939b3bba1e85279789400a226b365010de4bbcd diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 3dbd473..144cda1 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -15,5 +15,5 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.keyring$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

1 0

Patch set updated for coreboot: util/crossgcc: Toolchain verified sources
by Philipp Deppenwiese 01 Dec '16

01 Dec '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15170 -gerrit commit cff9e5a3693cf8eb935ac885242d3f8daf98e162 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Mon Jun 13 17:01:07 2016 -0700 util/crossgcc: Toolchain verified sources Currently there is no toolchain verification in coreboot. This patchset extends the existing buildgcc script in the following way: Before download or unpack operations the checksum of all used packages are checked against the trustworthy checksums in util/crossgcc/sum. With the option -g checksum can be automatically generated for updated packages as long they support gpg. Only the maintainers can commit checksum changes to the coreboot repository. Some libraries don't offer this possiblity and on update maintainers need to check the sources by themself adding checksums manually! The checksum algorithm changed from sha1 to sha384. If you ask yourself why we don't use sha256 or sha512 for the checksum verification. You should take a look at following wiki article. https://en.wikipedia.org/wiki/Length_extension_attack Also the url changed from http to https for security reasons where it was possible to do that. Change-Id: Id45097fc7e8435fadce4bda75769592af2730b0c Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- util/crossgcc/buildgcc | 222 +++++++++++++++++---- util/crossgcc/gpg.keyring | Bin 0 -> 222182 bytes util/crossgcc/sum/Python-3.5.1.tar.xz.cksum | 2 +- .../sum/acpica-unix2-20160831.tar.gz.cksum | 2 +- util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum | 2 +- .../sum/clang-tools-extra-3.8.0.src.tar.xz.cksum | 2 +- .../sum/compiler-rt-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum | 2 +- util/crossgcc/sum/gdb-7.11.tar.xz.cksum | 2 +- util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum | 2 +- util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum | 2 +- util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/make-4.2.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum | 2 +- util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum | 2 +- util/lint/lint-stable-003-whitespace | 2 +- 18 files changed, 197 insertions(+), 57 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index d64b687..b8fb212 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -5,6 +5,7 @@ # Stefan Reinauer <stefan.reinauer(a)coresystems.de> # # Copyright (C) 2011 by Sage Electronic Engineering +# Copyright (C) 2016 by Philipp Deppenwiese # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -18,9 +19,9 @@ cd $(dirname $0) -CROSSGCC_DATE="August 31st, 2016" -CROSSGCC_VERSION="1.43" -CROSSGCC_COMMIT=$( git describe ) +CROSSGCC_DATE="November 07th, 2016" +CROSSGCC_VERSION="1.44" +CROSSGCC_COMMIT=$(git describe) # default settings PACKAGE=GCC @@ -32,6 +33,7 @@ DESTDIR= SAVETEMPS=0 SKIPPYTHON=1 BOOTSTRAP=0 +GENERATE_CHECKSUMS=0 THREADS=1 # GCC toolchain version numbers @@ -50,6 +52,8 @@ EXPAT_VERSION=2.1.1 CLANG_VERSION=3.8.0 MAKE_VERSION=4.2.1 +GPG_KEYRING=$(pwd)/gpg.keyring + # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if # a completely new URL is added here, it probably needs to be added @@ -100,6 +104,8 @@ red='\033[0;31m' RED='\033[1;31m' green='\033[0;32m' GREEN='\033[1;32m' +yellow='\033[0;33m' +YELLOW='\033[1;33m' blue='\033[0;34m' BLUE='\033[1;34m' cyan='\033[0;36m' @@ -261,49 +267,163 @@ check_cc() { fi } -check_sum() { - test -z "$CHECKSUM" || \ - test "$(cat sum/$1.cksum 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" = \ - "$($CHECKSUM tarballs/$1 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" +verify_signature() { + SIGNATURE_FILE="$1" + SOURCE_FILE="$2" + + if [ -z "${GPG}" ] ; then + printf "\n * ${RED}GPG tool not found. Please install gnupg on your os.${NC}\n" + return 1 + fi + + if [ ! -f "${GPG_KEYRING}" ]; then + printf "\n * ${RED}The gpg keyring can't be found.${NC}\n" + return 1 + fi + + if [ ! -f "tarballs/${SIGNATURE_FILE}" ]; then + printf "\n * ${RED}No signature file found for package: ${SOURCE_FILE} !! PLEASE CHECK MANUALLY WHAT YOU DOWNLOADED, ABORTING CHECKSUM CREATION.${NC}\n" + return 1 + fi + + if [ ! -f "tarballs/${SOURCE_FILE}" ]; then + printf "\n * ${RED}Source file couldn't be downloaded.${NC}\n" + return 1 + fi + + GPG_OUTPUT=$(${GPG} --no-default-keyring --keyring ${GPG_KEYRING} --status-fd 1 --verify "tarballs/${SIGNATURE_FILE}" "tarballs/${SOURCE_FILE}" 2>&1) + if [ "${?}" = "0" ] ; then + printf "\n * ${GREEN}Signature is good and verified!${NC}" + return 0 + fi + + printf "\n * ${RED}Failed to verify signature of package.${NC}\n" + printf "\n * ${RED}Error: ${GPG_OUTPUT} ${NC}\n" + return 1 +} + +calculate_checksum() { + SOURCE_FILE=$1 + + test ! -f sum/"${SOURCE_FILE}".cksum && test -f tarballs/"${SOURCE_FILE}" && \ + ("${OPENSSL}" sha384 tarballs/"${SOURCE_FILE}" > sum/"${SOURCE_FILE}".cksum ) && \ + printf "\n * Checksum created. ${CYAN}Note. Please upload sum/"${SOURCE_FILE}".cksum if the corresponding archive is upgraded.${NC}" +} + +verify_checksum() { + STATIC_HASH=$(${AWK} '{ print $2 }' <sum/$1.cksum) + FILE_HASH=$(${OPENSSL} sha384 tarballs/$1 | ${AWK} '{ print $2 }') + + if [ "${STATIC_HASH}" != "${FILE_HASH}" ]; then + printf "\n * ${RED}Failed to verify checksum of package ${1}.${NC}\n" + exit 1 + fi + + printf "\n * ${GREEN}Checksum 0x${FILE_HASH} verified.${NC}\n" } -compute_sum() { - test ! -f sum/$1.cksum && test -f tarballs/$1 && \ - (test -z "$CHECKSUM" || $CHECKSUM tarballs/$1 > sum/$1.cksum ) && \ - printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}" +validate_url() { + CHECK_URL=$(wget -S --spider $1 2>&1 | grep 'HTTP/1.1 200 OK') + if [ "${?}" = "0" ] ; then + return 1 + else + return 0 + fi } download_showing_percentage() { - url=$1 - printf " ..${red} 0%%" - wget --no-check-certificate $url 2>&1 | while read line; do - echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' - done - printf "${NC}" + NO_WARNING="$2" + URL=$1 + printf " ..${YELLOW} 0%%${NC}" + + if ! validate_url ${URL}; then + wget ${URL} 2>&1 | while read line; do + printf "${YELLOW}" + echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' + printf "${NC}" + done + if [ ${?} != "0" ]; then + printf "\n${YELLOW} * ${URL} is not valid.${NC}" + return 1 + fi + elif [ "$NO_WARNING" = "0" ]; then + printf "\n${YELLOW} * ${URL} is not valid.${NC}" + return 1 + fi + + return 0 } download() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" - FILE=$(basename $archive) - printf " * $FILE " + SOURCE_FILE=$(basename ${archive}) - if test -f tarballs/$FILE && check_sum $FILE ; then + if test -f tarballs/${SOURCE_FILE} ; then printf "(cached)" else + rm -f tarballs/${SOURCE_FILE}* + cd tarballs || exit 1 + + printf " * ${SOURCE_FILE} " printf "(downloading from $archive)" - rm -f tarballs/$FILE - cd tarballs - download_showing_percentage $archive + download_showing_percentage ${archive} 0 + cd .. - compute_sum $FILE fi - if [ ! -f tarballs/$FILE ]; then - printf "\n${RED}Failed to download $FILE.${NC}\n" + if [ ! -f tarballs/${SOURCE_FILE} ]; then + printf "\n${RED} * Failed to download ${SOURCE_FILE}.${NC}\n" exit 1 fi + + printf "\n" +} + +generate_checksums() { + package=$1 + archive="$(eval echo \$$package"_ARCHIVE")" + SOURCE_FILE=$(basename ${archive}) + SIGNATURE_FILE="dummy" + + rm -f tarballs/${SOURCE_FILE}* + rm -f sum/${SOURCE_FILE}.cksum* + cd tarballs || exit 1 + + printf " * ${SOURCE_FILE} " + printf "(downloading from ${archive})" + download_showing_percentage ${archive} 0 + + printf "\n * ${SOURCE_FILE} " + printf "(downloading signature file ${archive}.sig)" + + download_showing_percentage "${archive}.sig" 0 + if [ "${?}" = "0" ] ; then + SIGNATURE_FILE=$(basename ${archive}.sig) + fi + + printf "\n * ${SOURCE_FILE} " + printf "(downloading signature file ${archive}.asc)" + + download_showing_percentage "${archive}.asc" 0 + if [ "${?}" = "0" ] ; then + SIGNATURE_FILE=$(basename ${archive}.asc) + fi + + cd .. + + verify_signature ${SIGNATURE_FILE} ${SOURCE_FILE} + if [ "${?}" = "0" ] ; then + calculate_checksum ${SOURCE_FILE} + verify_checksum ${SOURCE_FILE} ${archive} + fi + + if [ ! -f tarballs/${SOURCE_FILE} ]; then + printf "\n${RED}Failed to download ${SOURCE_FILE}.${NC}\n" + exit 1 + fi + printf "\n" } @@ -311,6 +431,10 @@ unpack_and_patch() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" dir="$(eval echo \$$package"_DIR")" + FILE="$(basename $archive)" + + verify_checksum ${FILE} ${archive} + test -d ${dir} && test -f ${dir}/.unpack_success || ( printf " * $(basename $archive)\n" FLAGS=zxf @@ -434,7 +558,7 @@ cleanup() myhelp() { - printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S]\n" + printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S] [-g]\n" printf " $0 [-V|--version]\n" printf " $0 [-h|--help]\n\n" @@ -464,7 +588,9 @@ myhelp() printf "GDB specific options:\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" - printf " [-S|--scripting] build scripting support for GDB\n\n" + printf " [-S|--scripting] build scripting support for GDB\n" + printf " [-g|--generate-checksums] re-generates the checksum for all packages and\n" + printf " verifies them with the help of gpg signatures\n\n" printf "Platforms for GCC & GDB:\n" printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n" printf " powerpc64le-linux-gnu nds32le-elf\n\n" @@ -481,6 +607,7 @@ myversion() cat << EOF Copyright (C) 2008-2010 by coresystems GmbH Copyright (C) 2011 by Sage Electronic Engineering +Copyright (C) 2016 by Philipp Deppenwiese This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -749,12 +876,12 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:,urls,nocolor -o Vhcd:bp:l:P:j:D:tSys:un -- "$@") + args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:,generate_checksums,urls,nocolor -o Vhcd:bp:l:P:j:D:tSys:gun -- "$@") getopt_ret=$? eval set -- "$args" else # Detected non-GNU getopt - args=$(getopt Vhcd:bp:l:P:j:D:tSys:un $*) + args=$(getopt Vhcd:bp:l:P:j:D:tSys:gun $*) getopt_ret=$? set -- $args fi @@ -782,7 +909,8 @@ while true ; do -s|--supported) shift; PRINTSTABLE="$1"; shift;; -u|--urls) shift; printf "%s\n" "$ALL_ARCHIVES"; exit 0;; -n|--nocolor) shift; \ - unset red RED green GREEN blue BLUE cyan CYAN NC;; + unset red RED green GREEN blue BLUE cyan CYAN yellow YELLOW NC;; + -g|--generate-checksums) shift; GENERATE_CHECKSUMS=1;; --) shift; break;; *) break;; esac @@ -848,6 +976,10 @@ case "$PACKAGE" in NAME="GNU Make" PACKAGES=MAKE ;; + ALL|all) + NAME="All packages" + PACKAGES="GMP MPFR MPC LIBELF BINUTILS GCC EXPAT PYTHON GDB LLVM CFE CRT CTE IASL MAKE" + ;; *) printf "${red}ERROR: Unsupported package $PACKAGE. (Supported packages are GCC, GDB, CLANG, IASL, MAKE)${NC}\n\n"; exit 1 @@ -856,15 +988,14 @@ esac # Find all the required tools: -TAR=$(searchtool tar) || exit $? -PATCH=$(searchtool patch) || exit $? -MAKE=$(searchtool make) || exit $? -SHA1SUM=$(searchtool sha1sum) -#SHA512SUM=$(searchtool sha512sum) -#MD5SUM=$(searchtool md5sum) -CHECKSUM=$SHA1SUM -LBZIP2=$(searchtool lbzip2 "" nofail) -PIGZ=$(searchtool pigz "" nofail) +TAR=$(searchtool tar "tar") +PATCH=$(searchtool patch "patch") +MAKE=$(searchtool make "Make") +LBZIP2=$(searchtool lbzip2 "bzip2" nofail) +PIGZ=$(searchtool pigz "pigz" nofail) +GPG=$(searchtool gpg "gpg" nofail) +OPENSSL=$(searchtool openssl "openssl") +AWK=$(searchtool awk "Awk") searchtool m4 > /dev/null searchtool bison > /dev/null @@ -946,6 +1077,15 @@ if [ "$USECCACHE" = 1 ]; then CC="ccache $CC" fi +if [ "$GENERATE_CHECKSUMS" = 1 ]; then + mkdir -p tarballs + for P in $PACKAGES; do + generate_checksums $P + done + + exit 0 +fi + # Prepare target directory for building GCC # (dependencies must be in the PATH) mkdir -p $DESTDIR$TARGETDIR/bin @@ -977,7 +1117,7 @@ printf "Packages built ... ${green}ok${NC}\n" # for reproducibility PROGNAME=$(basename "$0") rm -f "$DESTDIR$TARGETDIR/share/$PROGNAME-*" -cp "$PROGNAME" "$DESTDIR$TARGETDIR/share/$PROGNAME-$CROSSGCC_VERSION-$CROSGCC_COMMIT" +cp "$PROGNAME" "$DESTDIR$TARGETDIR/share/$PROGNAME-$CROSSGCC_VERSION-$CROSSGCC_COMMIT" cleanup diff --git a/util/crossgcc/gpg.keyring b/util/crossgcc/gpg.keyring new file mode 100644 index 0000000..8cbce7e Binary files /dev/null and b/util/crossgcc/gpg.keyring differ diff --git a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum index 58affb0..46f43a3 100644 --- a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum +++ b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum @@ -1 +1 @@ -0186da436db76776196612b98bb9c2f76acfe90e tarballs/Python-3.5.1.tar.xz +SHA384(tarballs/Python-3.5.1.tar.xz)= 9aca49d2cde4760035f4fff23e8a446f6451e8effb6e6fab3f259645a631593acb2ce3412aadf810f103f3f6b561abe7 diff --git a/util/crossgcc/sum/acpica-unix2-20160831.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20160831.tar.gz.cksum index d7e538b..6b39768 100644 --- a/util/crossgcc/sum/acpica-unix2-20160831.tar.gz.cksum +++ b/util/crossgcc/sum/acpica-unix2-20160831.tar.gz.cksum @@ -1 +1 @@ -7e7449f15a195fefd72b65b1671df18e4dccf665 tarballs/acpica-unix2-20160831.tar.gz +SHA384(tarballs/acpica-unix2-20160831.tar.gz)= 171f914bbfc71a69011494cd3484bc87e5ce6b28558699585c8719c250094140357793ead18d2432573a61a1ea5afc6c diff --git a/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum b/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum index 4bd0bce..b3a7126 100644 --- a/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum +++ b/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum @@ -1 +1 @@ -624cd377e3a8eef3db83a56ce289a60f556b3ec2 tarballs/binutils-2.26.1.tar.bz2 +SHA384(tarballs/binutils-2.26.1.tar.bz2)= 30cc8be8c230d69b966b80268223b823b3d301c83472317a4b6ff3aa9dd528a31cb1af33640097854e0e34743b1339b7 diff --git a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum index 7ba8c8c..48ccfbf 100644 --- a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -2230ef962f2df3c13ec93f5b04b0e3cdff94b2ce tarballs/cfe-3.8.0.src.tar.xz +SHA384(tarballs/cfe-3.8.0.src.tar.xz)= 3edbe3cafc58ad6fc3d3a133156a656ea7756e8a36176b29bba63434d6f073cef63241cc6df8337fcab3832dd5b5c485 diff --git a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum index e9d8d72..2c4154c 100644 --- a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -a99d8b6fc5e593c4671424b327779318a1856acf tarballs/clang-tools-extra-3.8.0.src.tar.xz +SHA384(tarballs/clang-tools-extra-3.8.0.src.tar.xz)= abd447239f09295f8592225bb7e07ba57cedc3d19a4972b45cd7d70a2db82106d1874a5be03656f8209a0e8a1308fb31 diff --git a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum index 081705d..8637b48 100644 --- a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -480ea09e369dac6de1f3759b27fa19417b26b69e tarballs/compiler-rt-3.8.0.src.tar.xz +SHA384(tarballs/compiler-rt-3.8.0.src.tar.xz)= 4560d512f3c3a0dbcc5c29ab7754b07d91ffa1ddc1c06a5215f3d325bc3f138ebf483e2a37abb10fc36cd125e6bf559e diff --git a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum b/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum index 882e501..e3a94fa 100644 --- a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum +++ b/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum @@ -1 +1 @@ -ff91419882ac52151050dad0ee8190645fbeee08 tarballs/expat-2.1.1.tar.bz2 +SHA384(tarballs/expat-2.1.1.tar.bz2)= 816e8ca9ac57b6aac76e9979d11714313246492a49c228bb0a16d349174be45cd780d760524eb45acf12ff371e8b96a3 diff --git a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum index bb05e39..073390b 100644 --- a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum +++ b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum @@ -1 +1 @@ -0612270b103941da08376df4d0ef4e5662a2e9eb tarballs/gcc-5.3.0.tar.bz2 +SHA384(tarballs/gcc-5.3.0.tar.bz2)= 4184972f66dc929686c30936cf8f5085829d8584118ebc3e2ec53a40754afbefc351cfd2c211c09dd3b6eb4ab4759820 diff --git a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum index ffe5a1c..f3082e7 100644 --- a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum +++ b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum @@ -1 +1 @@ -466208d771d97d3dfcf965d5c835a669cff8d847 tarballs/gdb-7.11.tar.xz +SHA384(tarballs/gdb-7.11.tar.xz)= 82f89ef35ea1916d5faa67b7fefa2ac3627894d245c43fb4e20828274566cbbb5d7f83899baad77a3cf7fe9fec6f8c7b diff --git a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum index 348b80f..e0ebab2 100644 --- a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum +++ b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum @@ -1 +1 @@ -99d691607613e749aa5d7c0c2a89aeab38fec070 tarballs/gmp-6.1.0.tar.xz +SHA384(tarballs/gmp-6.1.0.tar.xz)= ec69b394cbcf887ab0717473b04bb70ce30102abf24869eca5acb781de405d3a5670fabb776ba68cfe6e117631522d9f diff --git a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum index daa27c6..46f991d 100644 --- a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum +++ b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum @@ -1 +1 @@ -c1d6ac5f182d19dd685c4dfd74eedbfe3992425d tarballs/libelf-0.8.13.tar.gz +SHA384(tarballs/libelf-0.8.13.tar.gz)= 07fc0b1a40ba3d2b003899df199d1043bb5d44cf7d913e6460c985582e5275b634edb6af6779255d770010fd7d09580e diff --git a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum index 2f0af53..e407716 100644 --- a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -723ac918979255706434a05f5af34b71c49c9971 tarballs/llvm-3.8.0.src.tar.xz +SHA384(tarballs/llvm-3.8.0.src.tar.xz)= 5d5a012e4d494a4534fcec7643ad28bab7467b96029b6d497e1d523357ae7c9e8bd86400dc90e261d791d6391a369b30 diff --git a/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum b/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum index 34af72c..5c8a69c9 100644 --- a/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum +++ b/util/crossgcc/sum/make-4.2.1.tar.bz2.cksum @@ -1 +1 @@ -7d9d11eb36cfb752da1fb11bb3e521d2a3cc8830 tarballs/make-4.2.1.tar.bz2 +SHA384(tarballs/make-4.2.1.tar.bz2)= 07fed67f907c8139cd27d606069ce20f219ccf1d047d2ebb2a2b3242d4332957a64b7ff8c3b5db4b28dcbbfdb2ad1e01 diff --git a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum index c7ca1ac..50c2c67 100644 --- a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum +++ b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum @@ -1 +1 @@ -b8be66396c726fdc36ebb0f692ed8a8cca3bcc66 tarballs/mpc-1.0.3.tar.gz +SHA384(tarballs/mpc-1.0.3.tar.gz)= dceeb2566d6145fa771641d22de3bef866fa601fe1fa964bc680a275919080bd12bc1abab4f68cecdbaef71d295b7397 diff --git a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum index 90f90eb..88cd06c 100644 --- a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum +++ b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum @@ -1 +1 @@ -cedc0055d55b6ee4cd17e1e6119ed412520ff81a tarballs/mpfr-3.1.4.tar.xz +SHA384(tarballs/mpfr-3.1.4.tar.xz)= 30a2807378f578544538810b24bb65d44268015e5d2390d8ae6383fe3939b3bba1e85279789400a226b365010de4bbcd diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 3dbd473..144cda1 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -15,5 +15,5 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.keyring$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

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Patch set updated for coreboot: nb/i945/raminit.h: Fix fsb_frequency's comment
by HAOUAS Elyes 01 Dec '16

01 Dec '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17686 -gerrit commit e0b6f5281f3989d04a3eb5024688a9ec3669f693 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Dec 1 19:59:12 2016 +0100 nb/i945/raminit.h: Fix fsb_frequency's comment Change-Id: Ie1c28b73bd2d34070173838d341cc6b8f65f50ef Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 6c7ae96..0554900 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -25,7 +25,7 @@ struct sys_info { u16 memory_frequency; /* 400, 533 or 667 */ - u16 fsb_frequency; /* 400, 533 or 667 */ + u16 fsb_frequency; /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */ u8 trp; /* calculated by sdram_detect_smallest_tRP() */ u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */

1 0

New patch to review for coreboot: nb/i945/raminit.h: Fix fsb_frequency's comment
by HAOUAS Elyes 01 Dec '16

01 Dec '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17686 -gerrit commit 9bfcb9673b92760774dacb36374c2a15b953cae5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Dec 1 19:59:12 2016 +0100 nb/i945/raminit.h: Fix fsb_frequency's comment Change-Id: Ie1c28b73bd2d34070173838d341cc6b8f65f50ef Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/raminit.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 6c7ae96..51d5275 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -25,7 +25,7 @@ struct sys_info { u16 memory_frequency; /* 400, 533 or 667 */ - u16 fsb_frequency; /* 400, 533 or 667 */ + u16 fsb_frequency; /* 945: GM400, 533 or 667 / 945GC: 533, 800, or 1066 */ u8 trp; /* calculated by sdram_detect_smallest_tRP() */ u8 trcd; /* calculated by sdram_detect_smallest_tRCD() */

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coreboot-gerrit December 2016