coreboot-gerrit December 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit 187543c90da824198a7da2b531665f4d2dece243 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 11:03:13 2016 +0200 AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17534 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17534 for details. -gerrit

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Patch merged into coreboot/master: AMD binaryPI: Use explicit PCI IO config access in bootblock
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit cc37bbd7acaaa060fa272115aa077baabac402c4 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 08:24:12 2016 +0200 AMD binaryPI: Use explicit PCI IO config access in bootblock This allows us to set MMCONF_SUPPORT_DEFAULT since we enable MMCONF early in romstage. Change-Id: I380cf483bfe4e2d64969110ae6d5d04c3ced2418 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17532 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17532 for details. -gerrit

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Patch merged into coreboot/master: AGESA: Disable PCI_CFG_EXT_IO
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit b995f436b355ec357788d3a8c11c70bf5ec437df Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 17:31:58 2016 +0200 AGESA: Disable PCI_CFG_EXT_IO We don't need to do explicit pci_io_read/write operations, as we can use MMCONF everywhere. AGESA code still enables extended cf8/cfc should it be required by payload or OS. Change-Id: I278e5e26eb9a247f67927cbc67e04f081ca50f7b Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17535 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17535 for details. -gerrit

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Patch set updated for coreboot: util/superiotool/fintek.c: Add support for F71889A
by Marty Plummer 01 Dec '16

01 Dec '16

Marty Plummer (ntzrmtthihu777(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17442 -gerrit commit 6124d2b9b05247f55090ad98a93ee8479da96aab Author: Marty Plummer <ntzrmtthihu777(a)gmail.com> Date: Wed Nov 16 13:37:28 2016 -0600 util/superiotool/fintek.c: Add support for F71889A Datasheet: F71889A rev V0.21P Basic implementation, did the best I could in deciphering the datasheet. Portions I could not understand as of this moment are marked NANA. Change-Id: Ifc5035ebe2c1c66213069567da757886923e5596 Signed-off-by: Marty Plummer <ntzrmtthihu777(a)gmail.com> --- util/superiotool/fintek.c | 53 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) diff --git a/util/superiotool/fintek.c b/util/superiotool/fintek.c index 5a30652..138f193 100644 --- a/util/superiotool/fintek.c +++ b/util/superiotool/fintek.c @@ -423,6 +423,59 @@ static const struct superio_registers reg_table[] = { {0x30,0x60,0x61,0x70,0xf0,0xf2,0xf4,0xf5,EOT}, {NANA,0x00,0x00,NANA,NANA,NANA,0x00,0x00,EOT}}, {EOT}}}, + {0x0510, "F71889A", { + {NOLDN, NULL, + {0x02, 0x07, 0x20, 0x21, 0x23, 0x24, 0x25, 0x26, 0x27, + 0x28, 0x29, 0x2a, 0x2b, 0x2c, 0x2d, EOT}, + {NANA, 0x00, 0x10, 0x05, 0x19, 0x34, NANA, NANA, NANA, + NANA, 0x00, 0xf0, 0x30, 0x00, 0x08, EOT} }, + {0x01, "UART1", + {0x30, 0x60, 0x61, 0x70, 0xf0, EOT}, + {0x01, 0x03, 0xf8, NANA, NANA, EOT} }, + {0x02, "UART2", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf1, EOT}, + {0x01, 0x02, 0xf8, NANA, NANA, NANA, EOT} }, + {0x03, "LPT", + {0x30, 0x60, 0x61, 0x70, 0x74, 0xf0, EOT}, + {0x01, 0x03, 0x78, NANA, NANA, NANA, EOT} }, + {0x04, "HWMON", + {0x30, 0x60, 0x61, 0x70, EOT}, + {0x01, 0x02, 0x95, NANA, EOT} }, + {0x05, "KBC", + {0x30, 0x60, 0x61, 0x70, 0x72, 0xfe, 0xff, EOT}, + {0x01, 0x00, 0x60, 0x01, 0x0c, NANA, 0x29, EOT} }, + {0x06, "GPIO", + {0xf0, 0xf1, 0xf2, 0xf3, 0xfe, 0xff, 0xe0, 0xe1, 0xe2, + 0xe3, 0xd0, 0xd1, 0xd2, 0xd3, 0xc0, 0xc1, 0xc2, 0xc3, + 0xb0, 0xb1, 0xb2, 0xa0, 0xa1, 0xa2, 0xa4, 0xa5, 0xa6, + 0xab, 0xac, 0xad, 0xae, 0xaf, 0x90, 0x91, 0x92, 0x93, + 0x80, 0x81, 0x82, 0x83, EOT}, + {NANA, NANA, NANA, NANA, NANA, 0x00, 0x00, NANA, NANA, + NANA, NANA, NANA, NANA, NANA, 0x00, 0xff, NANA, 0x00, + 0x00, 0xff, NANA, NANA, NANA, NANA, NANA, NANA, NANA, + 0x00, 0x00, 0x00, 0xe0, 0x00, 0x00, 0x00, NANA, 0x00, + 0x00, 0xff, NANA, 0x00, EOT} }, + {0x07, "WDT", + {0x30, 0x60, 0x61, 0xf0, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, + 0xf7, 0xf8, 0xf9, 0xfa, 0xfb, 0xfc, 0xfd, 0xfe, EOT}, + {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0e, EOT} }, + {0x08, "CIR", + {0x30, 0x60, 0x61, 0x70, 0xf0, 0xf1, 0xf8, 0xf9, 0xfa, + 0xfb, 0xfc, 0xfd, 0xfe, EOT}, + {0x00, 0x00, 0x00, 0x00, NANA, NANA, 0x00, 0x00, 0x80, + 0x3b, 0x00, 0x00, 0x00, EOT} }, + {0x0a, "PME, ACPI, and ERP", + {0x30, 0xf0, 0xf1, 0xf2, 0xf3, 0xf4, 0xf5, 0xf6, 0xf7, + 0xfa, 0xfc, 0xfe, 0xe0, 0xe1, 0xe2, 0xe3, 0xe4, 0xe5, + 0xe6, 0xe7, 0xe8, 0xe9, 0xec, 0xed, 0xee, EOT}, + {NANA, NANA, NANA, NANA, NANA, 0x26, 0x04, NANA, NANA, + NANA, NANA, NANA, NANA, 0xcc, NANA, 0x13, 0x09, 0xc7, + 0x09, 0x63, 0x10, 0xff, NANA, NANA, 0x00, EOT} }, + {0x0b, "VREF", + {0xf0, 0xf1, 0xf2, 0xf3, 0xff, EOT}, + {0x64, 0x64, 0x64, 0x00, 0x00, EOT} }, + {EOT} } }, {EOT} };

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Patch merged into coreboot/master: AGESA: Switch to MMCONF_SUPPORT_DEFAULT
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit 59e03342076ea79cb7c0ed2fdbd199947c8c5212 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 11:03:13 2016 +0200 AGESA: Switch to MMCONF_SUPPORT_DEFAULT Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17533 for details. -gerrit

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Patch merged into coreboot/master: AGESA: Use explicit PCI IO config access in bootblock
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit 7d09cfcf749c1c0fd1c3791585065b39ec1a3433 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 08:24:12 2016 +0200 AGESA: Use explicit PCI IO config access in bootblock This allows us to set MMCONF_SUPPORT_DEFAULT since we enable MMCONF early in romstage. Change-Id: I994bb257db96300c2eb8872be6fae2a92bbabab4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17531 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17531 for details. -gerrit

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Patch merged into coreboot/master: asus/f2a85-m msi/ms7721: Enable MMCONF early
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit de43dd631402e326bbfb3fa6fa3bd92cb497871c Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Nov 22 08:37:15 2016 +0200 asus/f2a85-m msi/ms7721: Enable MMCONF early PCI MMCONF access only works after amd_initmmio() call. Change-Id: I5765604e178d09abdd6bb6ce7cc220bc5b35ed03 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17565 for details. -gerrit

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Patch merged into coreboot/master: AGESA f14: Consolidate early P-states setting
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit 7d25651ed3eb78228a00b479454d0ab2417f3f2a Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 08:03:49 2016 +0200 AGESA f14: Consolidate early P-states setting Change-Id: I3feed296b6ff9908e783c1221a8f61d9c548fef4 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17564 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17564 for details. -gerrit

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Patch merged into coreboot/master: AGESA f14: Consolidate XIP cache
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit 036a581b8fa9478d4dba1bf9e576ee9cc0bead24 Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Sun Nov 20 07:45:17 2016 +0200 AGESA f14: Consolidate XIP cache Do this like fam15tn to reduce code duplication. Change-Id: I064fd27b85be7fb0c9d6918a84fc6f9b17065534 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Reviewed-on: https://review.coreboot.org/17563 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17563 for details. -gerrit

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Patch set updated for coreboot: intel MMA: Enable MMA with FSP2.0
by Pratikkumar V Prajapati 01 Dec '16

01 Dec '16

Pratikkumar V Prajapati (pratikkumar.v.prajapati(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17496 -gerrit commit 5dedd2ddd03f02493d0a92ed1c74289b2ea87e64 Author: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Date: Fri Nov 18 14:36:34 2016 -0800 intel MMA: Enable MMA with FSP2.0 - Separate mma code for fsp1.1 and fsp2.0 and restructuring the code - common code is placed in mma.c and mma.h - mma_fsp<ver>.h and fsp<ver>/mma_core.c contains fsp version specific code. - whole MMA feature is guarded by CONFIG_MMA flag. Change-Id: I12c9a1122ea7a52f050b852738fb95d03ce44800 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- src/drivers/intel/common/Kconfig | 19 ++ src/drivers/intel/common/Makefile.inc | 19 ++ src/drivers/intel/common/include/mma.h | 55 +++++ src/drivers/intel/common/mma.c | 236 ++++++++++++++++++++ src/drivers/intel/fsp1_1/Kconfig | 6 + src/drivers/intel/fsp1_1/Makefile.inc | 2 + src/drivers/intel/fsp1_1/include/fsp/mma_fsp11.h | 25 +++ src/drivers/intel/fsp1_1/mma_core.c | 41 ++++ src/drivers/intel/fsp1_1/raminit.c | 17 +- src/drivers/intel/fsp2_0/Kconfig | 6 + src/drivers/intel/fsp2_0/Makefile.inc | 2 + src/drivers/intel/fsp2_0/include/fsp/mma_fsp20.h | 25 +++ src/drivers/intel/fsp2_0/memory_init.c | 15 ++ src/drivers/intel/fsp2_0/mma_core.c | 38 ++++ src/soc/intel/common/Kconfig | 11 - src/soc/intel/common/Makefile.inc | 2 - src/soc/intel/common/mma.c | 273 ----------------------- src/soc/intel/common/mma.h | 23 -- 18 files changed, 503 insertions(+), 312 deletions(-) diff --git a/src/drivers/intel/common/Kconfig b/src/drivers/intel/common/Kconfig new file mode 100644 index 0000000..4a57264 --- /dev/null +++ b/src/drivers/intel/common/Kconfig @@ -0,0 +1,19 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Intel Corp. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +config MMA_BLOBS_PATH + string "Path to MMA blobs" + depends on MMA && ( PLATFORM_USES_FSP2_0 || PLATFORM_USES_FSP1_1 ) + default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma" diff --git a/src/drivers/intel/common/Makefile.inc b/src/drivers/intel/common/Makefile.inc new file mode 100644 index 0000000..e704dcc --- /dev/null +++ b/src/drivers/intel/common/Makefile.inc @@ -0,0 +1,19 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Intel Corporation. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; version 2 of the License. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +ramstage-$(CONFIG_MMA) += mma.c +romstage-$(CONFIG_MMA) += mma.c + +CPPFLAGS_common += -I$(src)/drivers/intel/common/include diff --git a/src/drivers/intel/common/include/mma.h b/src/drivers/intel/common/include/mma.h new file mode 100644 index 0000000..9e9c96e --- /dev/null +++ b/src/drivers/intel/common/include/mma.h @@ -0,0 +1,55 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMA_H_ +#define _SOC_MMA_H_ + +#pragma pack(push, 1) + +typedef struct mma_config_param MMA_CONFIG_PARAM; +typedef struct mma_data_container MMA_DATA_CONTAINER; + +#if IS_ENABLED(CONFIG_PLATFORM_USES_FSP2_0) +#include <fsp/mma_fsp20.h> +#elif IS_ENABLED(CONFIG_PLATFORM_USES_FSP1_1) +#include <fsp/mma_fsp11.h> +#else +#error "error FSP version not defined or unsupported for MMA" +#endif + +struct mma_data_container { + u32 mma_signature; // "MMAD" + u8 mma_data[0]; // Variable size, platform/run time dependent. +}; + +struct mma_config_param { + u32 MmaTestContentPtr; + u32 MmaTestContentSize; + u32 MmaTestConfigPtr; + u32 MmaTestConfigSize; + u8 MrcFastBoot; + u8 SaGv; +}; + +int find_label(const char *haystack, size_t haystack_sz, + const char *label); +int label_value(const char *haystack, size_t haystack_sz, + const char *label, char *dest, size_t dest_sz); +int setup_mma(MMA_CONFIG_PARAM *mma_cfg); +void fsp_locate_mma_results(const void *mma_hob, u32 *mma_hob_size); + +#pragma pack(pop) + +#endif diff --git a/src/drivers/intel/common/mma.c b/src/drivers/intel/common/mma.c new file mode 100644 index 0000000..c7bcd84 --- /dev/null +++ b/src/drivers/intel/common/mma.c @@ -0,0 +1,236 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootstate.h> +#include <cbfs.h> +#include <cbmem.h> +#include <console/console.h> +#include <fsp/util.h> +#include <mma.h> + +#define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin" +#define MMA_TEST_NAME_TAG "MMA_TEST_NAME" +#define MMA_TEST_PARAM_TAG "MMA_TEST_PARAM" +#define TEST_NAME_MAX_SIZE 30 +#define TEST_PARAM_MAX_SIZE 100 +#define MMA_DATA_SIGNATURE (('M' << 0) | ('M' << 8) | \ + ('A' << 16) | ('D' << 24)) +#define MMA_CBFS_REGION "COREBOOT" + +/* + * Format of the MMA test metadata file, stored under CBFS + * MMA_TEST_NAME=xxxxxx.efi;MMA_TEST_PARAM=xxxxxx.bin; + */ + +/* Returns index in haystack after 'LABEL=' + * string is found, < 0 on error. + */ +int find_label(const char *haystack, size_t haystack_sz, + const char *label) +{ + size_t label_sz; + size_t i; + size_t search_sz; + + label_sz = strlen(label); + + if (label_sz + 1 >= haystack_sz) + return -1; + + /* Handle '=' follow label. i.e. LABEL= */ + search_sz = haystack_sz - label_sz - 1; + for (i = 0; i < search_sz; i++) { + if (!strncmp(&haystack[i], label, label_sz)) + break; + } + + if (i == search_sz) + return -1; + + if (haystack[i + label_sz] != '=') + return -1; + + return i + label_sz + 1; +} + +/* + * Fill in value in dest field located by LABEL=. + * Returns 0 on success, < 0 on error. + */ +int label_value(const char *haystack, size_t haystack_sz, + const char *label, char *dest, size_t dest_sz) +{ + size_t val_begin; + size_t val_end; + size_t val_sz; + int val_index; + + memset(dest, 0, dest_sz); + + /* Allow for NULL termination. */ + dest_sz--; + val_index = find_label(haystack, haystack_sz, label); + if (val_index < 0) + return -1; + + val_begin = val_index; + val_end = val_begin; + val_sz = 0; + + for (val_end = val_begin; val_end < haystack_sz; val_end++) { + if (haystack[val_end] == ';') { + val_sz = val_end - val_begin; + break; + } + } + + if (val_end == haystack_sz) + return -1; + + if (dest_sz < val_sz) + return -1; + + memcpy(dest, &haystack[val_begin], val_sz); + + return 0; +} + +int setup_mma(MMA_CONFIG_PARAM *mma_cfg) +{ + void *mma_test_metadata, *mma_test_content, *mma_test_param; + size_t mma_test_metadata_file_len, mma_test_content_file_len, + mma_test_param_file_len; + char test_filename[TEST_NAME_MAX_SIZE], + test_param_filename[TEST_PARAM_MAX_SIZE]; + + printk(BIOS_DEBUG, "Entry %s\n", __func__); + + memset(&mma_cfg, 0, sizeof(mma_cfg)); + + mma_test_metadata = cbfs_locate_file_in_region(MMA_CBFS_REGION, + MMA_TEST_METADATA_FILENAME, CBFS_TYPE_MMA, + &mma_test_metadata_file_len); + + if (!mma_test_metadata) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to read %s\n", + MMA_TEST_METADATA_FILENAME); + return -1; + } + + if (label_value(mma_test_metadata, mma_test_metadata_file_len, + MMA_TEST_NAME_TAG, test_filename, TEST_NAME_MAX_SIZE)) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to get %s", + MMA_TEST_NAME_TAG); + return -1; + } + + if (label_value(mma_test_metadata, mma_test_metadata_file_len, + MMA_TEST_PARAM_TAG, test_param_filename, + TEST_PARAM_MAX_SIZE)) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to get %s", + MMA_TEST_PARAM_TAG); + return -1; + } + + printk(BIOS_DEBUG, "Got MMA_TEST_NAME=%s MMA_TEST_PARAM=%s\n", + test_filename, test_param_filename); + + mma_test_content = cbfs_locate_file_in_region(MMA_CBFS_REGION, + test_filename, CBFS_TYPE_EFI, + &mma_test_content_file_len); + if (!mma_test_content) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to read %s.\n", + test_filename); + return -1; + } + + mma_test_param = cbfs_locate_file_in_region(MMA_CBFS_REGION, + test_param_filename, CBFS_TYPE_MMA, + &mma_test_param_file_len); + if (!mma_test_param) { + printk(BIOS_DEBUG, "MMA set up failed: Failed to read %s.\n", + test_param_filename); + return -1; + } + + mma_cfg->MmaTestContentPtr = (uintptr_t) &mma_test_content; + mma_cfg->MmaTestContentSize = mma_test_content_file_len; + mma_cfg->MmaTestConfigPtr = (uintptr_t) &mma_test_param; + mma_cfg->MmaTestConfigSize = mma_test_param_file_len; + mma_cfg->MrcFastBoot = 0x00; + mma_cfg->SaGv = 0x02; + + printk(BIOS_DEBUG, "MMA Test name %s\n", test_filename); + printk(BIOS_DEBUG, "MMA Test Config name %s\n", test_param_filename); + printk(BIOS_DEBUG, "MMA passing following mma_cfg\n"); + printk(BIOS_DEBUG, "mma_cfg->MmaTestContentPtr = %0x\n", + mma_cfg->MmaTestContentPtr); + printk(BIOS_DEBUG, "mma_cfg->MmaTestContentSize = %d\n", + mma_cfg->MmaTestContentSize); + printk(BIOS_DEBUG, "mma_cfg->MmaTestConfigPtr = %0x\n", + mma_cfg->MmaTestConfigPtr); + printk(BIOS_DEBUG, "mma_cfg->MmaTestConfigSize = %d\n", + mma_cfg->MmaTestConfigSize); + printk(BIOS_DEBUG, "mma_cfg->MrcFastBoot = %d\n", + mma_cfg->MrcFastBoot); + printk(BIOS_DEBUG, "mma_cfg->SaGv = %d\n", + mma_cfg->SaGv); + + return 0; +} + +static void save_mma_results_data(void *unused) +{ + const void *mma_hob = NULL; + u32 mma_hob_size; + MMA_DATA_CONTAINER *mma_data; + u32 mma_data_size = 0; + + printk(BIOS_DEBUG, "Entry %s\n", __func__); + + fsp_locate_mma_results(mma_hob, &mma_hob_size); + + if (mma_hob == NULL) { + printk(BIOS_DEBUG, + "MMA results data Hob not present\n"); + return; + } + + mma_data_size = ALIGN(mma_hob_size, 16) + + sizeof(MMA_DATA_CONTAINER); + + mma_data = cbmem_add(CBMEM_ID_MMA_DATA, mma_data_size); + + if (mma_data == NULL) { + printk(BIOS_DEBUG, + "CBMEM was not available to save the MMA data.\n"); + return; + } + + /*clear the mma_data before coping the actual data */ + memset(mma_data, 0, mma_data_size); + + printk(BIOS_DEBUG, + "Copy MMA data to CBMEM(src addr %p, dest addr %p, %u bytes)\n", + mma_hob, mma_data, mma_hob_size); + + mma_data->mma_signature = MMA_DATA_SIGNATURE; + memcpy(mma_data->mma_data, mma_hob, mma_hob_size); + + printk(BIOS_DEBUG, "Write MMA results data to cbmem success\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, + save_mma_results_data, NULL); diff --git a/src/drivers/intel/fsp1_1/Kconfig b/src/drivers/intel/fsp1_1/Kconfig index cc3c0a7..38d6e23 100644 --- a/src/drivers/intel/fsp1_1/Kconfig +++ b/src/drivers/intel/fsp1_1/Kconfig @@ -115,4 +115,10 @@ config RESET_ON_INVALID_RAMSTAGE_CACHE bool "Reset the system on S3 wake when ramstage cache invalid." default n +config MMA + bool "enable MMA (Memory Margin Analysis) support" + default n + help + Set this option to y to enable MMA (Memory Margin Analysis) support + endif #PLATFORM_USES_FSP1_1 diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 4ea23f3..4088293 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -31,6 +31,7 @@ romstage-y += romstage.c romstage-$(CONFIG_SEPARATE_VERSTAGE) += romstage_after_verstage.S romstage-y += stack.c romstage-y += stage_cache.c +romstage-$(CONFIG_MMA) += mma_core.c ramstage-$(CONFIG_GOP_SUPPORT) += fsp_gop.c ramstage-y += fsp_relocate.c @@ -39,6 +40,7 @@ ramstage-y += hob.c ramstage-y += ramstage.c ramstage-y += stage_cache.c ramstage-$(CONFIG_GOP_SUPPORT) += vbt.c +ramstage-$(CONFIG_MMA) += mma_core.c CPPFLAGS_common += -Isrc/drivers/intel/fsp1_1/include diff --git a/src/drivers/intel/fsp1_1/include/fsp/mma_fsp11.h b/src/drivers/intel/fsp1_1/include/fsp/mma_fsp11.h new file mode 100644 index 0000000..df22de7 --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/mma_fsp11.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMA_FSP11_H_ +#define _SOC_MMA_FSP11_H_ + +#include <fsp/soc_binding.h> + +typedef struct mma_config_param MMA_CONFIG_PARAM; + +void update_memory_params_for_mma(MEMORY_INIT_UPD *memory_upd, + MMA_CONFIG_PARAM *mma_cfg); +#endif diff --git a/src/drivers/intel/fsp1_1/mma_core.c b/src/drivers/intel/fsp1_1/mma_core.c new file mode 100644 index 0000000..8e83a00 --- /dev/null +++ b/src/drivers/intel/fsp1_1/mma_core.c @@ -0,0 +1,41 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/util.h> +#include <mma.h> + +#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \ + { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } } + +void fsp_locate_mma_results(const void *mma_hob, u32 *mma_hob_size) +{ + void *mma_hob_start; + const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID; + + mma_hob_start = get_first_guid_hob(&mma_results_guid); + mma_hob = GET_GUID_HOB_DATA(mma_hob_start); + *mma_hob_size = GET_HOB_LENGTH(mma_hob); +} + +void update_memory_params_for_mma(MEMORY_INIT_UPD *memory_upd, + MMA_CONFIG_PARAM *mma_cfg) +{ + memory_upd->MmaTestContentPtr = mma_cfg->MmaTestContentPtr; + memory_upd->MmaTestContentSize = mma_cfg->MmaTestContentSize; + memory_upd->MmaTestConfigPtr = mma_cfg->MmaTestConfigPtr; + memory_upd->MmaTestConfigSize = mma_cfg->MmaTestConfigSize; + memory_upd->MrcFastBoot = 0x00; + memory_upd->SaGv = 0x02; +} diff --git a/src/drivers/intel/fsp1_1/raminit.c b/src/drivers/intel/fsp1_1/raminit.c index eca8934..9b04a5e 100644 --- a/src/drivers/intel/fsp1_1/raminit.c +++ b/src/drivers/intel/fsp1_1/raminit.c @@ -21,7 +21,7 @@ #include <fsp/util.h> #include <lib.h> /* hexdump */ #include <reset.h> -#include <soc/intel/common/mma.h> +#include <mma.h> #include <string.h> #include <timestamp.h> #include <vboot/vboot_common.h> @@ -55,6 +55,9 @@ void raminit(struct romstage_params *params) unsigned long int data; EFI_PEI_HOB_POINTERS hob_ptr; #endif +#if IS_ENABLED(CONFIG_MMA) + MMA_CONFIG_PARAM mma_cfg; +#endif /* * Find and copy the UPD region to the stack so the platform can modify @@ -101,8 +104,16 @@ void raminit(struct romstage_params *params) soc_memory_init_params(params, &memory_init_params); mainboard_memory_init_params(params, &memory_init_params); - if (IS_ENABLED(CONFIG_MMA)) - setup_mma(&memory_init_params); +#if IS_ENABLED(CONFIG_MMA) + if (setup_mma(&mma_cfg)) + printk(BIOS_DEBUG, "%s", + "MMA set up failed, not updating memory param\n"); + else { + update_memory_params_for_mma(&memory_init_params, + &mma_cfg); + printk(BIOS_DEBUG, "MMA set up successfully\n"); + } +#endif post_code(0x36); diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 4f40c3f..2667728 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -100,4 +100,10 @@ config FSP2_0_USES_TPM_MRC_HASH default n select VBOOT_HAS_REC_HASH_SPACE +config MMA + bool "Enable MMA (Memory Margin Analysis) support for Intel Core" + default n + help + Set this option to y to enable MMA (Memory Margin Analysis) support + endif diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index beeec7c..ad654b9 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -24,6 +24,7 @@ romstage-$(CONFIG_VERIFY_HOBS) += hob_verify.c romstage-y += util.c romstage-y += memory_init.c romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +romstage-$(CONFIG_MMA) += mma_core.c ramstage-y += debug.c ramstage-y += graphics.c @@ -36,6 +37,7 @@ ramstage-y += silicon_init.c ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c +ramstage-$(CONFIG_MMA) += mma_core.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c diff --git a/src/drivers/intel/fsp2_0/include/fsp/mma_fsp20.h b/src/drivers/intel/fsp2_0/include/fsp/mma_fsp20.h new file mode 100644 index 0000000..efaedd8 --- /dev/null +++ b/src/drivers/intel/fsp2_0/include/fsp/mma_fsp20.h @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMA_FSP20_H_ +#define _SOC_MMA_FSP20_H_ + +#include <fsp/soc_binding.h> + +typedef struct mma_config_param MMA_CONFIG_PARAM; + +void update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, + MMA_CONFIG_PARAM *mma_cfg); +#endif diff --git a/src/drivers/intel/fsp2_0/memory_init.c b/src/drivers/intel/fsp2_0/memory_init.c index b833561..b9dfe20 100644 --- a/src/drivers/intel/fsp2_0/memory_init.c +++ b/src/drivers/intel/fsp2_0/memory_init.c @@ -22,6 +22,7 @@ #include <fsp/api.h> #include <fsp/util.h> #include <memrange.h> +#include <mma.h> #include <program_loading.h> #include <reset.h> #include <romstage_handoff.h> @@ -293,6 +294,9 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, fsp_memory_init_fn fsp_raminit; FSPM_UPD fspm_upd, *upd; FSPM_ARCH_UPD *arch_upd; +#if IS_ENABLED(CONFIG_MMA) + MMA_CONFIG_PARAM mma_cfg; +#endif post_code(0x34); @@ -318,6 +322,17 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake, /* Give SoC and mainboard a chance to update the UPD */ platform_fsp_memory_init_params_cb(&fspm_upd); +#if IS_ENABLED(CONFIG_MMA) + if (setup_mma(&mma_cfg)) + printk(BIOS_DEBUG, "%s", + "MMA set up failed, not updating memory param\n"); + else { + update_memory_params_for_mma(&(fspm_upd.FspmConfig), + &mma_cfg); + printk(BIOS_DEBUG, "MMA set up successfully\n"); + } +#endif + /* Call FspMemoryInit */ fsp_raminit = (void *)(hdr->image_base + hdr->memory_init_entry_offset); fsp_debug_before_memory_init(fsp_raminit, upd, &fspm_upd); diff --git a/src/drivers/intel/fsp2_0/mma_core.c b/src/drivers/intel/fsp2_0/mma_core.c new file mode 100644 index 0000000..47421a9 --- /dev/null +++ b/src/drivers/intel/fsp2_0/mma_core.c @@ -0,0 +1,38 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <fsp/util.h> +#include <mma.h> + +static const uint8_t mma_results_uuid[16] = { 0x28, 0xe9, 0xf4, 0x08, + 0x5f, 0x0f, 0xd4, 0x46, + 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 }; + +void fsp_locate_mma_results(const void *mma_hob, u32 *mma_hob_size) +{ + mma_hob = fsp_find_extension_hob_by_guid(mma_results_uuid, + mma_hob_size); +} + +void update_memory_params_for_mma(FSP_M_CONFIG *memory_cfg, + MMA_CONFIG_PARAM *mma_cfg) +{ + memory_cfg->MmaTestContentPtr = mma_cfg->MmaTestContentPtr; + memory_cfg->MmaTestContentSize = mma_cfg->MmaTestContentSize; + memory_cfg->MmaTestConfigPtr = mma_cfg->MmaTestConfigPtr; + memory_cfg->MmaTestConfigSize = mma_cfg->MmaTestConfigSize; + memory_cfg->MrcFastBoot = 0x00; + memory_cfg->SaGv = 0x02; +} diff --git a/src/soc/intel/common/Kconfig b/src/soc/intel/common/Kconfig index 5d8bf66..fb4b3d4 100644 --- a/src/soc/intel/common/Kconfig +++ b/src/soc/intel/common/Kconfig @@ -78,17 +78,6 @@ config SOC_INTEL_COMMON_LPSS_I2C_DEBUG Enable debug output for I2C transactions. This can be useful when debugging I2C drivers. -config MMA - bool "enable MMA (Memory Margin Analysis) support" - default n - help - Set this option to y to enable MMA (Memory Margin Analysis) support - -config MMA_BLOBS_PATH - string "Path to MMA blobs" - depends on MMA - default "3rdparty/blobs/mainboard/$(MAINBOARDDIR)/mma" - config ADD_VBT_DATA_FILE bool "Add a Video Bios Table (VBT) binary to CBFS" help diff --git a/src/soc/intel/common/Makefile.inc b/src/soc/intel/common/Makefile.inc index 38903a0..7cf32bf 100644 --- a/src/soc/intel/common/Makefile.inc +++ b/src/soc/intel/common/Makefile.inc @@ -12,7 +12,6 @@ romstage-$(CONFIG_CACHE_MRC_SETTINGS) += mrc_cache.c romstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c romstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c romstage-y += util.c -romstage-$(CONFIG_MMA) += mma.c postcar-y += util.c postcar-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c @@ -24,7 +23,6 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_SPI_PROTECT) += spi.c ramstage-$(CONFIG_SOC_INTEL_COMMON_LPSS_I2C) += lpss_i2c.c ramstage-$(CONFIG_SOC_INTEL_COMMON_RESET) += reset.c ramstage-y += util.c -ramstage-$(CONFIG_MMA) += mma.c ramstage-$(CONFIG_SOC_INTEL_COMMON_ACPI_WAKE_SOURCE) += acpi_wake_source.c ramstage-y += vbt.c ramstage-$(CONFIG_SOC_INTEL_COMMON_GFX_OPREGION) += opregion.c diff --git a/src/soc/intel/common/mma.c b/src/soc/intel/common/mma.c deleted file mode 100644 index 87d8e5c..0000000 --- a/src/soc/intel/common/mma.c +++ /dev/null @@ -1,273 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <boot/coreboot_tables.h> -#include <bootstate.h> -#include <cbfs.h> -#include <cbmem.h> -#include <console/console.h> -#include <lib.h> -#include "mma.h" -#include <soc/romstage.h> -#include <string.h> -#include <fmap.h> - -#define MMA_TEST_METADATA_FILENAME "mma_test_metadata.bin" -#define MMA_TEST_NAME_TAG "MMA_TEST_NAME" -#define MMA_TEST_PARAM_TAG "MMA_TEST_PARAM" -#define MMA_CBFS_REGION "COREBOOT" -#define TEST_NAME_MAX_SIZE 30 -#define TEST_PARAM_MAX_SIZE 100 -#define FSP_MMA_RESULTS_GUID { 0x8f4e928, 0xf5f, 0x46d4, \ - { 0x84, 0x10, 0x47, 0x9f, 0xda, 0x27, 0x9d, 0xb6 } } -#define MMA_DATA_SIGNATURE (('M'<<0)|('M'<<8)|('A'<<16)|('D'<<24)) - -struct mma_data_container { - u32 mma_signature; // "MMAD" - u8 mma_data[0]; // Variable size, platform/run time dependent. -} __attribute__ ((packed)); - -/* -Format of the MMA test metadata file, stored under CBFS -MMA_TEST_NAME=xxxxxx.efi;MMA_TEST_PARAM=xxxxxx.bin; -*/ - -/* Returns index in haystack after 'LABEL=' string is found, < 0 on error. */ -static int find_label(const char *haystack, size_t haystack_sz, - const char *label) -{ - size_t label_sz; - size_t i; - size_t search_sz; - - label_sz = strlen(label); - - if (label_sz + 1 >= haystack_sz) - return -1; - - /* Handle '=' follow label. i.e. LABEL= */ - search_sz = haystack_sz - label_sz - 1; - for (i = 0; i < search_sz; i++) { - if (!strncmp(&haystack[i], label, label_sz)) - break; - } - - if (i == search_sz) - return -1; - - if (haystack[i + label_sz] != '=') - return -1; - - return i + label_sz + 1; -} -/* - * Fill in value in dest field located by LABEL=. - * Returns 0 on success, < 0 on error. - */ -static int label_value(const char *haystack, size_t haystack_sz, - const char *label, char *dest, size_t dest_sz) -{ - size_t val_begin; - size_t val_end; - size_t val_sz; - int val_index; - - memset(dest, 0, dest_sz); - - /* Allow for NULL termination. */ - dest_sz--; - val_index = find_label(haystack, haystack_sz, label); - if (val_index < 0) - return -1; - - val_begin = val_index; - val_end = val_begin; - val_sz = 0; - - for (val_end = val_begin; val_end < haystack_sz; val_end++) { - if (haystack[val_end] == ';') { - val_sz = val_end - val_begin; - break; - } - } - - if (val_end == haystack_sz) - return -1; - - if (dest_sz < val_sz) - return -1; - - memcpy(dest, &haystack[val_begin], val_sz); - - return 0; -} - -static void *cbfs_locate_file_in_region(const char *region_name, const char *file_name, - uint32_t file_type, uint32_t *file_size) -{ - struct region_device rdev; - struct cbfsf fh; - - if (file_size != NULL) - *file_size = 0; - - if (fmap_locate_area_as_rdev(region_name, &rdev) == 0) { - if (cbfs_locate(&fh, &rdev, file_name, &file_type) == 0) { - if (file_size != NULL) - *file_size = region_device_sz(&fh.data); - return rdev_mmap_full(&fh.data); - } else - printk(BIOS_DEBUG, "%s file not found in %s region\n", - file_name, region_name); - } else - printk(BIOS_DEBUG,"%s region not found while looking for %s\n", region_name, - file_name); - - return NULL; -} - -void setup_mma(MEMORY_INIT_UPD *memory_params) -{ - void *mma_test_metadata, *mma_test_content, *mma_test_param; - size_t mma_test_metadata_file_len, mma_test_content_file_len, - mma_test_param_file_len; - char test_filename[TEST_NAME_MAX_SIZE], - test_param_filename[TEST_PARAM_MAX_SIZE]; - - printk(BIOS_DEBUG, "Entry setup_mma\n"); - - memory_params->MmaTestContentPtr = 0; - memory_params->MmaTestContentSize = 0; - memory_params->MmaTestConfigPtr = 0; - memory_params->MmaTestConfigSize = 0; - - mma_test_metadata = cbfs_locate_file_in_region(MMA_CBFS_REGION, - MMA_TEST_METADATA_FILENAME, CBFS_TYPE_MMA, - &mma_test_metadata_file_len); - - if (!mma_test_metadata) { - printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s\n", - MMA_TEST_METADATA_FILENAME); - return; - } - - if (label_value(mma_test_metadata, mma_test_metadata_file_len, - MMA_TEST_NAME_TAG, test_filename, TEST_NAME_MAX_SIZE)) { - printk(BIOS_DEBUG, "MMA setup failed : Failed to get %s", - MMA_TEST_NAME_TAG); - return; - } - - if (label_value(mma_test_metadata, mma_test_metadata_file_len, - MMA_TEST_PARAM_TAG, test_param_filename, - TEST_PARAM_MAX_SIZE)) { - printk(BIOS_DEBUG, "MMA setup failed : Failed to get %s", - MMA_TEST_PARAM_TAG); - return; - } - - printk(BIOS_DEBUG, "Got MMA_TEST_NAME=%s MMA_TEST_PARAM=%s\n", - test_filename, test_param_filename); - - mma_test_content = cbfs_locate_file_in_region(MMA_CBFS_REGION, - test_filename, CBFS_TYPE_EFI, - &mma_test_content_file_len); - if (!mma_test_content) { - printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s.\n", - test_filename); - return; - } - - mma_test_param = cbfs_locate_file_in_region(MMA_CBFS_REGION, - test_param_filename, CBFS_TYPE_MMA, - &mma_test_param_file_len); - if (!mma_test_param) { - printk(BIOS_DEBUG, "MMA setup failed: Failed to read %s.\n", - test_param_filename); - return; - } - - memory_params->MmaTestContentPtr = (uintptr_t) mma_test_content; - memory_params->MmaTestContentSize = mma_test_content_file_len; - memory_params->MmaTestConfigPtr = (uintptr_t) mma_test_param; - memory_params->MmaTestConfigSize = mma_test_param_file_len; - memory_params->MrcFastBoot = 0x00; - memory_params->SaGv = 0x02; - - printk(BIOS_DEBUG, "MMA Test name %s\n", test_filename); - printk(BIOS_DEBUG, "MMA Test Config name %s\n", test_param_filename); - printk(BIOS_DEBUG, "MMA passing following memory_params\n"); - printk(BIOS_DEBUG, "memory_params->MmaTestContentPtr = %0x\n", - memory_params->MmaTestContentPtr); - printk(BIOS_DEBUG, "memory_params->MmaTestContentSize = %d\n", - memory_params->MmaTestContentSize); - printk(BIOS_DEBUG, "memory_params->MmaTestConfigPtr = %0x\n", - memory_params->MmaTestConfigPtr); - printk(BIOS_DEBUG, "memory_params->MmaTestConfigSize = %d\n", - memory_params->MmaTestConfigSize); - printk(BIOS_DEBUG, "memory_params->MrcFastBoot = %d\n", - memory_params->MrcFastBoot); - printk(BIOS_DEBUG, "memory_params->SaGv = %d\n", - memory_params->SaGv); - - printk(BIOS_DEBUG, "MMA setup successfully\n"); -} - -static void save_mma_results_data(void *unused) -{ - void *mma_results_hob; - u32 mma_hob_size; - u32 *mma_hob_data; - struct mma_data_container *mma_data; - int cbmem_size; - - const EFI_GUID mma_results_guid = FSP_MMA_RESULTS_GUID; - - printk(BIOS_DEBUG, "Entry save_mma_results_data MMA save data.\n"); - - mma_results_hob = get_first_guid_hob(&mma_results_guid); - if (mma_results_hob == NULL) { - printk(BIOS_DEBUG, - "MMA results data Hob not present\n"); - return; - } - - mma_hob_data = GET_GUID_HOB_DATA(mma_results_hob); - mma_hob_size = GET_HOB_LENGTH(mma_results_hob); - cbmem_size = ALIGN(mma_hob_size, 16) + - sizeof(struct mma_data_container); - mma_data = cbmem_add(CBMEM_ID_MMA_DATA, cbmem_size); - - if (mma_data == NULL) { - printk(BIOS_DEBUG, - "CBMEM was not available to save the MMA data.\n"); - return; - } - - /*clear the mma_data before coping the actual data */ - memset(mma_data, 0, cbmem_size); - - printk(BIOS_DEBUG, - "Copy MMA DATA to HOB(src addr %p, dest addr %p, %u bytes)\n", - mma_hob_data, mma_data, mma_hob_size); - - mma_data->mma_signature = MMA_DATA_SIGNATURE; - memcpy(mma_data->mma_data, mma_hob_data, mma_hob_size); - - printk(BIOS_DEBUG, "write MMA results data to cbmem success\n"); -} - -BOOT_STATE_INIT_ENTRY(BS_WRITE_TABLES, BS_ON_ENTRY, - save_mma_results_data, NULL); diff --git a/src/soc/intel/common/mma.h b/src/soc/intel/common/mma.h deleted file mode 100644 index f1c91e2..0000000 --- a/src/soc/intel/common/mma.h +++ /dev/null @@ -1,23 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SOC_MMA_H_ -#define _SOC_MMA_H_ - -#include <fsp/soc_binding.h> - -void setup_mma(MEMORY_INIT_UPD *memory_params); - -#endif

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coreboot-gerrit December 2016