coreboot-gerrit December 2016

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Patch set updated for coreboot: nb/x4x: Move checkreset before SPD reading
by Arthur Heymans 01 Dec '16

01 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17661 -gerrit commit 54d1e45a1da0a7445d72a42dcee8618e84d552a5 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Nov 30 20:37:29 2016 +0100 nb/x4x: Move checkreset before SPD reading It makes no sense to read SPDs if the system will reset anyway. Change-Id: Id2ad9b04860b3e4939a149eef6b619a496179ff8 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit.c | 33 +++++++++++++++++++++++++++++++ src/northbridge/intel/x4x/raminit_ddr2.c | 34 -------------------------------- 2 files changed, 33 insertions(+), 34 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 122cab5..436815a 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -316,6 +316,37 @@ static void sdram_detect_ram_speed(struct sysinfo *s) } } +static void checkreset_ddr2(void) +{ + u8 pmcon2; + u8 reset = 0; + + if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE)) { + printk(BIOS_DEBUG, "Waiting for disks to timeout...\n"); + mdelay(2000); + reset = 1; + } + + pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); + reset = 1; + + /* do magic 0xf0 thing. */ + u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); + reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); + pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); + } + if (reset) { + printk(BIOS_DEBUG, "Reset...\n"); + outb(0xe, 0xcf9); + asm ("hlt"); + } + pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); +} + /** * @param boot_path: 0 = normal, 1 = reset, 2 = resume from s3 */ @@ -328,6 +359,8 @@ void sdram_initialize(int boot_path, const u8 *spd_map) pci_write_config8(PCI_DEV(0,0,0), 0xdf, 0xff); + checkreset_ddr2(); + memset(&s, 0, sizeof(struct sysinfo)); s.boot_path = boot_path; diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index bfc918e..41701ff 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -254,37 +254,6 @@ static void clkcross_ddr2(struct sysinfo *s) MCHBAR32(0x70c) = clkxtab[i][j][12]; } -static void checkreset_ddr2(struct sysinfo *s) -{ - u8 pmcon2; - u8 reset = 0; - - if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE)) { - printk(BIOS_DEBUG, "Waiting for disks to timeout...\n"); - mdelay(2000); - reset = 1; - } - - pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (pmcon2 & 0x80) { - pmcon2 &= ~0x80; - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); - reset = 1; - - /* do magic 0xf0 thing. */ - u8 reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 & ~(1 << 2)); - reg8 = pci_read_config8(PCI_DEV(0, 0, 0), 0xf0); - pci_write_config8(PCI_DEV(0, 0, 0), 0xf0, reg8 | (1 << 2)); - } - if (reset) { - printk(BIOS_DEBUG, "Reset...\n"); - outb(0xe, 0xcf9); - asm ("hlt"); - } - pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2 | 0x80); -} - static void setioclk_ddr2(struct sysinfo *s) { MCHBAR32(0x1bc) = 0x08060402; @@ -1862,9 +1831,6 @@ void raminit_ddr2(struct sysinfo *s) // Select timings based on SPD info sdram_detect_smallest_params2(s); - // Reset if required - checkreset_ddr2(s); - // Clear self refresh MCHBAR32(0xf14) = MCHBAR32(0xf14) | 0x3;

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New patch to review for coreboot: drivers/r8168: Read default MAC address from CBFS
by Damien Zammit 01 Dec '16

01 Dec '16

Damien Zammit (damien(a)zamaudio.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17672 -gerrit commit f2bd9f182e88d1dfeadf93cd84b8782fb6a782b4 Author: Damien Zammit <damien(a)zamaudio.com> Date: Thu Dec 1 23:29:34 2016 +1100 drivers/r8168: Read default MAC address from CBFS This driver applies to 10ec:8168 Previously, this driver resetted the nic and set a hardcoded MAC address. Now the driver reads a default MAC address from CBFS in the form of a string: echo -n "xx:xx:xx:xx:xx:xx" > macaddress and store the macaddress file in CBFS with the same name. Change-Id: If1af91120fa3efca3f1406334a83ed1e59fbdaf9 Signed-off-by: Damien Zammit <damien(a)zamaudio.com> --- src/drivers/net/r8168.c | 115 ++++++++++++++++++++++++++++++++++++------------ 1 file changed, 88 insertions(+), 27 deletions(-) diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 1e6db57..4768b86 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -1,6 +1,7 @@ /* * This file is part of the coreboot project. * + * Copyright (C) 2012 Google Inc. * Copyright (C) 2016 Damien Zammit <damien(a)zamaudio.com> * * This program is free software; you can redistribute it and/or modify @@ -14,11 +15,14 @@ */ /* - * This driver forces the 10ec:8168 device to reset so that it goes - * into a proper power state, also programs a default MAC address - * so that if the EEPROM/efuse is unconfigured it still has a default MAC. + * This driver resets the 10ec:8168 NIC then tries to read + * "macaddress" string XX:XX:XX:XX:XX:XX from CBFS. + * If no MAC is found, it programs a default MAC address in the device + * so that if the EEPROM/efuse is unconfigured it still has a default MAC */ +#include <cbfs.h> +#include <string.h> #include <arch/io.h> #include <device/device.h> #include <device/pci.h> @@ -36,26 +40,64 @@ #define CFG_9346_LOCK 0x00 #define CFG_9346_UNLOCK 0xc0 -static void r8168_init(struct device *dev) +static unsigned char get_hex_digit(u8 *offset) { - u32 i; - const u8 mac[6] = { 0x00, 0xe0, 0x4c, 0x00, 0xc0, 0xb0 }; + unsigned char retval = 0; - /* Get the resource of the NIC mmio */ - struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0); - u16 nic_port = (u16)nic_res->base; + retval = *offset - '0'; + if (retval > 0x09) { + retval = *offset - 'A' + 0x0A; + if (retval > 0x0F) + retval = *offset - 'a' + 0x0a; + } + if (retval > 0x0F) { + printk(BIOS_DEBUG, "Error: Invalid Hex digit found: %c - 0x%02x\n", + *offset, *offset); + retval = 0; + } - /* Ensble but do not set bus master. That's dangerous on a NIC. */ - pci_write_config16(dev, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + return retval; +} + +static void get_mac_address(u8 *macaddr, u8 *cbfs_address) +{ + unsigned int offset = 0; + int i; + + for (i = 0; i < 6; i++) { + macaddr[i] = 0; + macaddr[i] |= (get_hex_digit(cbfs_address + offset) + << (4 + (i * 8))); + macaddr[i] |= (get_hex_digit(cbfs_address + offset + 1) + << (i * 8)); + offset += 3; + } +} + +static void program_mac_address(struct device *dev, u16 io_base) +{ + void *cbfs_address = NULL; + size_t search_length = -1; + int i = 0; + u8 mac[6] = { 0x00, 0xe0, 0x4c, 0x00, 0xc0, 0xb0 }; + + cbfs_address = cbfs_boot_map_with_leak("macaddress", + CBFS_TYPE_RAW, + &search_length); + + if (cbfs_address == NULL) { + printk(BIOS_ERR, "r8168: `macaddress` not found in CBFS, " + "using default 00:e0:4c:00:c0:b0\n"); + } else { + get_mac_address(mac, cbfs_address); + } /* Reset NIC */ printk(BIOS_DEBUG, "r8168: Resetting NIC..."); - outb(CMD_REG_RESET, nic_port + CMD_REG); + outb(CMD_REG_RESET, io_base + CMD_REG); - i = 0; - /* Poll for reset, with 1s timeout */ - while (i < NIC_TIMEOUT && (inb(nic_port + CMD_REG) & CMD_REG_RESET)) { + /* Poll for reset, with 1sec timeout */ + while (i < NIC_TIMEOUT && (inb(io_base + CMD_REG) & CMD_REG_RESET)) { udelay(1000); if (++i >= NIC_TIMEOUT) printk(BIOS_DEBUG, "timeout waiting for nic to reset\n"); @@ -63,20 +105,39 @@ static void r8168_init(struct device *dev) if (i < NIC_TIMEOUT) printk(BIOS_DEBUG, "done\n"); - /* Unlock config regs */ - outb(CFG_9346_UNLOCK, nic_port + CFG_9346); - - /* Set MAC address 00:e0:4c:00:c0:b0 - * NB: only 4-byte write accesses allowed - */ - outl(mac[4] | mac[5] << 8, nic_port + 4); - inl(nic_port + 4); + printk(BIOS_DEBUG, "r8168: Programming MAC Address..."); - outl(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, nic_port); - inl(nic_port); + /* Disable register protection */ + outb(CFG_9346_UNLOCK, io_base + CFG_9346); + /* Set MAC address: only 4-byte write accesses allowed */ + outl(mac[4] | mac[5] << 8, io_base + 4); + inl(io_base + 4); + outl(mac[0] | mac[1] << 8 | mac[2] << 16 | mac[3] << 24, + io_base); + inl(io_base); /* Lock config regs */ - outb(CFG_9346_LOCK, nic_port + CFG_9346); + outb(CFG_9346_LOCK, io_base + CFG_9346); + + printk(BIOS_DEBUG, "done\n"); +} + +static void r8168_init(struct device *dev) +{ + /* Get the resource of the NIC mmio */ + struct resource *nic_res = find_resource(dev, PCI_BASE_ADDRESS_0); + u16 io_base = (u16)nic_res->base; + + /* Enable but do not set bus master. That's dangerous on a NIC. */ + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_IO); + + /* Program MAC address based on CBFS "macaddress" containing + * a string AA:BB:CC:DD:EE:FF */ + if (io_base) + program_mac_address(dev, io_base); + else + printk(BIOS_DEBUG, "r8168: Error cant find MMIO resource\n"); } static struct device_operations r8168_ops = {

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New patch to review for coreboot: mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missing
by Werner Zeh 01 Dec '16

01 Dec '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17671 -gerrit commit 266d6ee65e2a67b8692a81b1d3cafdaaeeb17147 Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Dec 1 10:57:34 2016 +0100 mc_tcu3: Do not abort initialization of PTN3460 when HW-ID is missing Do not abort the initialization of PTN3460 if HW-ID could not be retrieved and just assume that the HW-ID does not match 7.9.2.0. In this case PTN3460 will be setup to a working condition even if this field is missing. This makes this driver more robust with faulty blocks. Change-Id: I301fb165a7924768e44182d92be820294beb0280 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/mainboard/siemens/mc_tcu3/ptn3460.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/src/mainboard/siemens/mc_tcu3/ptn3460.c b/src/mainboard/siemens/mc_tcu3/ptn3460.c index cd59492..347bc9c 100644 --- a/src/mainboard/siemens/mc_tcu3/ptn3460.c +++ b/src/mainboard/siemens/mc_tcu3/ptn3460.c @@ -58,11 +58,6 @@ int ptn3460_init(char *hwi_block) hwi_block); return 1; } - if (hwilib_get_field(HWID, hwid, sizeof(hwid)) != sizeof(hwid)) { - printk(BIOS_ERR, "LCD: Missing HW-ID from %s\n", - hwi_block); - return 1; - } /* Here, all the desired information for setting up DP2LVDS converter*/ /* are present. Inside the converter, table 6 will be used for */ /* the timings. */ @@ -85,10 +80,12 @@ int ptn3460_init(char *hwi_block) cfg.lvds_interface_ctrl1 |= 0x20; /* Use 18 bits per pixel */ cfg.lvds_interface_ctrl2 = 0x03; /* no clock spreading, 300 mV LVDS swing */ - if (memcmp(hwid, tcu31_hwid, sizeof(hwid))) - cfg.lvds_interface_ctrl3 = 0x00; /* no LVDS signal swap */ - else + /* Swap LVDS even and odd lanes for HW-ID 7.9.2.0 only. */ + if (hwilib_get_field(HWID, hwid, sizeof(hwid)) == sizeof(hwid) && + !(memcmp(hwid, tcu31_hwid, sizeof(hwid)))) { cfg.lvds_interface_ctrl3 = 0x01; /* swap LVDS even and odd */ + } else + cfg.lvds_interface_ctrl3 = 0x00; /* no LVDS signal swap */ cfg.t2_delay = 1; /* Delay T2 (VDD to LVDS active) by 16 ms */ cfg.t3_timing = 10; /* 500 ms from LVDS to backlight active */ cfg.t12_timing = 20; /* 1 second re-power delay */

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New patch to review for coreboot: vendorcode/siemens: Ensure a given info block is available for a field
by Werner Zeh 01 Dec '16

01 Dec '16

Werner Zeh (werner.zeh(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17670 -gerrit commit ccf30b5f264e24ed6d190cb348fc685d306875ca Author: Werner Zeh <werner.zeh(a)siemens.com> Date: Thu Dec 1 10:53:14 2016 +0100 vendorcode/siemens: Ensure a given info block is available for a field While searching for a field in all blocks ensure that the checked block is available and can be used. In this way a field can be retrieved from every block and not just the first one. Change-Id: Idbd7656ab0664763cb065f5e817193ad1d9e0871 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- src/vendorcode/siemens/hwilib/hwilib.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/siemens/hwilib/hwilib.c b/src/vendorcode/siemens/hwilib/hwilib.c index 18880ff..df9bd22 100644 --- a/src/vendorcode/siemens/hwilib/hwilib.c +++ b/src/vendorcode/siemens/hwilib/hwilib.c @@ -396,7 +396,8 @@ static uint32_t hwilib_read_bytes (const struct param_info *param, uint8_t *dst, return 0; /* Take the first valid block to get the parameter from */ do { - if ((param->pos[i].len) && (param->pos[i].offset)) { + if ((param->pos[i].len) && (param->pos[i].offset) && + (blk_ptr[param->pos[i].blk_type])) { blk = blk_ptr[param->pos[i].blk_type]; break; }

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Patch set updated for coreboot: nb/x4x: Fix raminit unconditionally resetting
by Arthur Heymans 01 Dec '16

01 Dec '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17659 -gerrit commit 092e1740526d27f3f6c293731a8abf7f113e0849 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Nov 30 18:40:38 2016 +0100 nb/x4x: Fix raminit unconditionally resetting The raminit only succeeds when it starts from a cold boot. To achieve this it unconditionally did a cold reset. This patch uses the sticky scratchpad MCHBAR to issue a cold reset only when not started from a cold boot. This sticky scratchpad register is only empty on cold boot or on cold reset (outb(0xe, 0xcf9)). It also adds a 2s delay before reset because some disk drives expect a warm reboot when the OS wants to reboot and therefore are not shut down properly / in time. If the drive is unexpectedly powered off which happens during a cold reset, it can cause data loss. Giving the drive 2 extra seconds can work around this issue. (A proper fix would be to fix the raminit such that it works on a hot reset) Change-Id: I6063dd6aed908558155d2523f35d7241ff1f4fde Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/raminit_ddr2.c | 11 +++++++++-- src/northbridge/intel/x4x/x4x.h | 4 +--- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/x4x/raminit_ddr2.c b/src/northbridge/intel/x4x/raminit_ddr2.c index b3ee34a..bfc918e 100644 --- a/src/northbridge/intel/x4x/raminit_ddr2.c +++ b/src/northbridge/intel/x4x/raminit_ddr2.c @@ -259,9 +259,15 @@ static void checkreset_ddr2(struct sysinfo *s) u8 pmcon2; u8 reset = 0; + if ((MCHBAR16(SSKPD_MCHBAR) == 0xCAFE)) { + printk(BIOS_DEBUG, "Waiting for disks to timeout...\n"); + mdelay(2000); + reset = 1; + } + pmcon2 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xa2); - if (!(pmcon2 & 0x80)) { - pmcon2 |= 0x80; + if (pmcon2 & 0x80) { + pmcon2 &= ~0x80; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xa2, pmcon2); reset = 1; @@ -2058,4 +2064,5 @@ void raminit_ddr2(struct sysinfo *s) MCHBAR32(0xa30) = MCHBAR32(0xa30) | (1 << 26); printk(BIOS_DEBUG, "Done ddr2\n"); + MCHBAR16(SSKPD_MCHBAR) = 0xCAFE; } diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index e4eb8dd..ab9ba80 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -97,9 +97,7 @@ #define CLKCFG_MEMCLK_MASK (7 << CLKCFG_MEMCLK_SHIFT) #define CLKCFG_UPDATE (1 << 12) -#define SSKPD_MCHBAR 0x0c1c -#define SSKPD_CLK_SHIFT 0 -#define SSKPD_CLK_MASK (7 << SSKPD_CLK_SHIFT) +#define SSKPD_MCHBAR 0x0c20 /* 64bit */ /* * DMIBAR

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New patch to review for coreboot: superio/fintek: Add support for Fintek F71889A.
by Marty Plummer 01 Dec '16

01 Dec '16

Marty Plummer (ntzrmtthihu777(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17669 -gerrit commit d0d0730d1c454cb7b98206370786fcc20f9338ef Author: Marty Plummer <ntzrmtthihu777(a)gmail.com> Date: Thu Dec 1 02:14:39 2016 -0600 superio/fintek: Add support for Fintek F71889A. Datasheet: F71889A rev V0.21P Change-Id: I91c60a3b48cd4872ae7a27de8f49faa40e877a27 Signed-off-by: Marty Plummer <ntzrmtthihu777(a)gmail.com> --- src/superio/fintek/Makefile.inc | 1 + src/superio/fintek/f71889a/Kconfig | 20 ++++++++++ src/superio/fintek/f71889a/Makefile.inc | 18 +++++++++ src/superio/fintek/f71889a/f71889a.h | 31 ++++++++++++++ src/superio/fintek/f71889a/superio.c | 71 +++++++++++++++++++++++++++++++++ 5 files changed, 141 insertions(+) diff --git a/src/superio/fintek/Makefile.inc b/src/superio/fintek/Makefile.inc index 0d0ae66..5d117e2 100644 --- a/src/superio/fintek/Makefile.inc +++ b/src/superio/fintek/Makefile.inc @@ -24,3 +24,4 @@ subdirs-y += f71872 subdirs-y += f81216h subdirs-y += f81865f subdirs-y += f81866d +supdirs-y += f71889a diff --git a/src/superio/fintek/f71889a/Kconfig b/src/superio/fintek/f71889a/Kconfig new file mode 100644 index 0000000..641621e --- /dev/null +++ b/src/superio/fintek/f71889a/Kconfig @@ -0,0 +1,20 @@ +# +# This file is part of the coreboot project. +# +# Copyright (C) 2016 Marty Plummer <netz.kernel(a)gmail.com> +# +# This program is free software: you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation, either version 3 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# + +config SUPERIO_FINTEK_F71889A + bool + select SUPERIO_FINTEK_COMMON_ROMSTAGE + diff --git a/src/superio/fintek/f71889a/Makefile.inc b/src/superio/fintek/f71889a/Makefile.inc new file mode 100644 index 0000000..4642c46 --- /dev/null +++ b/src/superio/fintek/f71889a/Makefile.inc @@ -0,0 +1,18 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2016 Marty Plummer <netz.kernel(a)gmail.com> +## +## This program is free software: you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation, either version 3 of the License, or +## (at your option) any later version. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## + +ramstage-$(CONFIG_SUPERIO_FINTEK_F71889A) += superio.c + diff --git a/src/superio/fintek/f71889a/f71889a.h b/src/superio/fintek/f71889a/f71889a.h new file mode 100644 index 0000000..a129e41 --- /dev/null +++ b/src/superio/fintek/f71889a/f71889a.h @@ -0,0 +1,31 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marty Plummer <netz.kernel(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef SUPERIO_FINTEK_F71889A_H +#define SUPERIO_FINTEK_F71889A_H + +/* Logical Device Numbers (LDN). */ +#define F71889A_SP1 0x01 /* UART1 */ +#define F71889A_SP2 0x02 /* UART2 */ +#define F71889A_PP 0x03 /* Parallel Port */ +#define F71889A_HWM 0x04 /* Hardware Monitor */ +#define F71889A_KBC 0x05 /* Keyboard/Mouse */ +#define F71889A_GPIO 0x06 /* GPIO */ +#define F71889A_VID 0x07 /* VID */ +#define F71889A_PM 0x0a /* ACPI/PME */ + +#endif /* SUPERIO_FINTEK_F71889A_H */ + diff --git a/src/superio/fintek/f71889a/superio.c b/src/superio/fintek/f71889a/superio.c new file mode 100644 index 0000000..34d4806 --- /dev/null +++ b/src/superio/fintek/f71889a/superio.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Marty Plummer <netz.kernel(a)gmail.com> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 3 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <device/device.h> +#include <device/pnp.h> +#include <superio/conf_mode.h> +#include <console/console.h> +#include <stdlib.h> +#include <pc80/keyboard.h> +#include "f71889a.h" + +static void f71889a_init(struct device *dev) +{ + if (!dev->enabled) + return; + + switch (dev->path.pnp.device) { + + case F71889A_KBC: + pc_keyboard_init(NO_AUX_DEVICE); + break; + } +} + +static struct device_operations ops = { + .read_resources = pnp_read_resources, + .set_resources = pnp_set_resources, + .enable_resources = pnp_enable_resources, + .enable = pnp_alt_enable, + .init = f71889a_init, + .ops_pnp_mode = &pnp_conf_mode_8787_aa, +}; + +static struct pnp_info pnp_dev_info[] = { + /* TODO: Some of the 0x07f8 etc. values may not be correct. + * double check bitmasks + */ + { &ops, F71889A_SP1, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_SP2, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_PP, PNP_IO0 | PNP_IRQ0 | PNP_DRQ0, {0x07f8, 0}, }, + { &ops, F71889A_HWM, PNP_IO0 | PNP_IRQ0, {0x07f8, 0}, }, + { &ops, F71889A_KBC, PNP_IO0 | PNP_IRQ0 | PNP_IRQ1, {0x07ff, 0}, }, + { &ops, F71889A_GPIO, PNP_IRQ0, }, + { &ops, F71889A_VID, PNP_IO0, {0x0ff8, 0}, }, + { &ops, F71889A_PM, }, +}; + +static void enable_dev(struct device *dev) +{ + pnp_enable_devices(dev, &ops, ARRAY_SIZE(pnp_dev_info), pnp_dev_info); +} + +struct chip_operations superio_fintek_f71889a_ops = { + CHIP_NAME("Fintek F71889A Super I/O") + .enable_Dev = enable_dev +}; +

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New patch to review for coreboot: src/cpu/amd: Add socket AM3+ support
by Marty Plummer 01 Dec '16

01 Dec '16

Marty Plummer (ntzrmtthihu777(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17668 -gerrit commit d86864f3b79e5c4fb65fee22d1b40cd66270affd Author: Marty Plummer <ntzrmtthihu777(a)gmail.com> Date: Thu Dec 1 01:58:47 2016 -0600 src/cpu/amd: Add socket AM3+ support Pretty much a clone of src/cpu/amd/socket_AM3 for the sake of explicit distinction between AM3/AM3+ mobos. Checked against src/cpu/amd/agesa/family15/Kconfig for accuracy. Change-Id: I421728d1d69bd52fbf1fbc8f8780d7b1dd2a79a5 Signed-off-by: Marty Plummer <ntzrmtthihu777(a)gmail.com> --- src/cpu/amd/Kconfig | 1 + src/cpu/amd/Makefile.inc | 1 + src/cpu/amd/socket_AM3r2/Kconfig | 30 ++++++++++++++++++++++++++++++ src/cpu/amd/socket_AM3r2/Makefile.inc | 13 +++++++++++++ 4 files changed, 45 insertions(+) diff --git a/src/cpu/amd/Kconfig b/src/cpu/amd/Kconfig index 23e4deb..e51ddf9 100644 --- a/src/cpu/amd/Kconfig +++ b/src/cpu/amd/Kconfig @@ -4,6 +4,7 @@ source src/cpu/amd/socket_940/Kconfig source src/cpu/amd/socket_AM2/Kconfig source src/cpu/amd/socket_AM2r2/Kconfig source src/cpu/amd/socket_AM3/Kconfig +source src/cpu/amd/socket_AM3r2/Kconfig source src/cpu/amd/socket_C32/Kconfig source src/cpu/amd/socket_FM2/Kconfig source src/cpu/amd/socket_G34/Kconfig diff --git a/src/cpu/amd/Makefile.inc b/src/cpu/amd/Makefile.inc index da6862d..5bfaad4 100644 --- a/src/cpu/amd/Makefile.inc +++ b/src/cpu/amd/Makefile.inc @@ -6,6 +6,7 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_940) += socket_940 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2) += socket_AM2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2 subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3 +subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3R2) += socket_AM3r2 subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2 subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32 subdirs-$(CONFIG_CPU_AMD_SOCKET_FM2_NON_AGESA) += socket_FM2 diff --git a/src/cpu/amd/socket_AM3r2/Kconfig b/src/cpu/amd/socket_AM3r2/Kconfig new file mode 100644 index 0000000..41590ce --- /dev/null +++ b/src/cpu/amd/socket_AM3r2/Kconfig @@ -0,0 +1,30 @@ +config CPU_AMD_SOCKET_AM3R2 + bool + select CPU_AMD_MODEL_10XXX + select PCI_IO_CFG_EXT + select X86_AMD_FIXED_MTRRS + +if CPU_AMD_SOCKET_AM3R2 + +config CPU_SOCKET_TYPE + hex + default 0x11 + +config EXT_RT_TBL_SUPPORT + bool + default n + +config CBB + hex + default 0x0 + +config CDB + hex + default 0x18 + +config XIP_ROM_SIZE + hex + default 0x80000 + +endif + diff --git a/src/cpu/amd/socket_AM3r2/Makefile.inc b/src/cpu/amd/socket_AM3r2/Makefile.inc new file mode 100644 index 0000000..6917441 --- /dev/null +++ b/src/cpu/amd/socket_AM3r2/Makefile.inc @@ -0,0 +1,13 @@ +subdirs-y += ../family_10h-family_15h +subdirs-y += ../quadcore +subdirs-y += ../mtrr +subdirs-y += ../microcode +subdirs-y += ../../x86/tsc +subdirs-y += ../../x86/lapic +subdirs-y += ../../x86/cache +subdirs-y += ../../x86/pae +subdirs-y += ../../x86/mtrr +subdirs-y += ../../x86/smm +subdirs-y += ../smm + +cpu_incs-y += $(src)/cpu/amd/car/cache_as_ram.inc

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Patch merged into coreboot/master: mainboard/google/reef: allow variants to modify nhlt oem revision
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit d0a648e18a7162f7361a13296beb0c1293acb16e Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 23:20:07 2016 -0600 mainboard/google/reef: allow variants to modify nhlt oem revision In order to mirror the full flexibility of the NHLT library that allows a caller to set the OEM revision field in the ACPI header modify the variant callback to override the value. Change-Id: I16e539b350a50e3c163be1439c8637b82e53a759 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17651 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17651 for details. -gerrit

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Patch merged into coreboot/master: lib/nhlt: add support for setting the oem_revision
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit b4afe3c19747758412c734132e5e342a9b3572b1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 23:14:25 2016 -0600 lib/nhlt: add support for setting the oem_revision In the ACPI header there's an OEM revision field that was previously just being implicitly set to 0. Allow for a board to provide a non-zero value for this field. Change-Id: Icd40c1c162c2645b3990a6f3361c592706251f82 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17650 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17650 for details. -gerrit

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Patch merged into coreboot/master: arch/x86: cache postcar in stage cache
by gerrit＠coreboot.org 01 Dec '16

01 Dec '16

the following patch was just integrated into master: commit d008413a3c46d4346f3cc398bbfd60b875ff3084 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Nov 29 15:52:08 2016 -0600 arch/x86: cache postcar in stage cache Stash and reload postcar stage in the stage cache for increased S3 resume speed. It's impact is small (2 ms or so), but there's no need to go to the boot media on resume to reload something that was already loaded. This aligns with the same paths we take on ramstage as well. Change-Id: I4313794826120853163c7366e81346858747ed0a Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: https://review.coreboot.org/17649 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan(a)google.com> See https://review.coreboot.org/17649 for details. -gerrit

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coreboot-gerrit December 2016