coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: ec/lenovo/h8: don't load configuration when booting from s3
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 83df672d2ce481686c5c4e04625bc1b97d7a4a8b Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Oct 16 07:30:34 2016 +0200 ec/lenovo/h8: don't load configuration when booting from s3 Some user might change some devices. After a suspend this reset to the (nvram) defaults which breaks the user expectation. Change-Id: Ifacca35210474ec3db41a53d2ad18f3798b14077 Signed-off-by: Alexander Couzens <… [View More]

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Patch merged into coreboot/master: ec/lenovo/h8: move charge priority into own function
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit c5a6fb805265f53917eef9748dfa8e39f0697b8c Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Oct 16 06:55:19 2016 +0200 ec/lenovo/h8: move charge priority into own function Change-Id: I53c7cffd0f32f9babc5fb70d5a2440a7d3377602 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/17035 Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> … [View More]

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Patch merged into coreboot/master: nb/i945/gma.c: use an if else statement for use of native init
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit f3f4bea6b53cd21823a196096cca4bcb31be4b73 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 20 20:44:54 2016 +0200 nb/i945/gma.c: use an if else statement for use of native init Change-Id: I1e964ed939ca5282008253e3fbdd1d2fa5cbf278 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17076 Reviewed-by: Nico Huber <nico.h(a)gmx.de> … [View More]

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Patch merged into coreboot/master: nb/i945/gma.c: Do not try to load vbios when selecting native init
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit d0e0118be888604e6d7e462ccf703115f655de39 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 20 20:18:12 2016 +0200 nb/i945/gma.c: Do not try to load vbios when selecting native init This fixes a typo introduced in 9c5fc62f: "nb/i945/gma.c: use IS_ENABLED instead of #if, #endif". Change-Id: I2c9ca796767a507483c32867f9b7f172842a1ab3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz&… [View More]

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Patch set updated for coreboot: nb/intel/i945: make pci_mmio_size a devicetree parameter
by Arthur Heymans 02 Nov '16

02 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit 3a7372d5fcfa87fcbe5de1b963aac8d3e269bfeb Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: make pci_mmio_size a devicetree parameter Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. Change-Id: … [View More]If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 ++ src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/raminit.c | 21 ++++++++++++++++++--- 5 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 4bbe28d..f37e768 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 2dc9f45..f66455b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e2a24c1..0ac9273 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 446af72..c6d80e6 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -8,6 +8,7 @@ struct northbridge_intel_i945_config { u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c..f6af0b2 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <device/pci_def.h> +#include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> @@ -25,6 +27,7 @@ #include <lib.h> #include "raminit.h" #include "i945.h" +#include "chip.h" #include <cbmem.h> /* Debugging macros. */ @@ -48,6 +51,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +#define DEFAULT_PCI_MMIO_SIZE 768 static int get_dimm_spd_address(struct sys_info *sysinfo, int device) { if (sysinfo->spd_addresses) @@ -1503,7 +1507,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; - int cum0, cum1, tolud, tom; + int cum0, cum1, tolud, tom, pci_mmio_size; + const struct device *dev; + const struct northbridge_intel_i945_config *cfg = NULL; printk(BIOS_DEBUG, "Setting RAM size...\n"); @@ -1542,8 +1548,17 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + pci_mmio_size = DEFAULT_PCI_MMIO_SIZE; + else + pci_mmio_size = cfg->pci_mmio_size; + + tolud = MIN(((4096 - pci_mmio_size) / 128) << 3, tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud); [View Less]

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Patch merged into coreboot/master: rockchip/rk3399: display: Do not allocate framebuffer in coreboot
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 152e675fd952bbb0e7d786fbaa7711b8d0d454f2 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Oct 20 14:22:11 2016 -0700 rockchip/rk3399: display: Do not allocate framebuffer in coreboot framebuffer address is dynamically chosen by libpayload now, so there's no need to configure it in coreboot. CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, dev screen is … [View More]

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Patch merged into coreboot/master: rockchip/rk3399: sdram: Reset system if switch to index1 fails
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 13acd35d6fa2623dce970acae9296b80a75ed2a3 Author: Lin Huang <hl(a)rock-chips.com> Date: Sun Oct 16 13:24:08 2016 -0700 rockchip/rk3399: sdram: Reset system if switch to index1 fails Near the end of DDR initialization, the system switches to the index1 configuration. Sometimes this failed and a status bit that coreboot was waiting for was never set, hanging the system. Instead, give the system 100ms … [View More]

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Patch merged into coreboot/master: rockchip/rk3399: sdram: Fix data training function
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit f435f92654a18860814187a029657755f1c1d187 Author: Lin Huang <hl(a)rock-chips.com> Date: Sun Oct 9 09:37:10 2016 +0800 rockchip/rk3399: sdram: Fix data training function 1. Update write leveling value to 0x200. When the wrdqs slave delay is changed to 0x200, the phase between the dqs and the clock is 0 degrees. The pcb layout can make sure the tDQSS timing is smaller than 0.25tck, so this value is useful … [View More]

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Patch merged into coreboot/master: rockchip/rk3399: sdram: also prepare the index1 configuration
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 883f5cbdcea6e8e4dbca57ff0a430338c9159ed2 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Sep 15 22:59:55 2016 +0800 rockchip/rk3399: sdram: also prepare the index1 configuration To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to train alternative configurations first, so do the training and store the values. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: … [View More]

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Patch merged into coreboot/master: intel/{skylake, apollolake}: Enable signalling of error condition
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 84164603188175abd2a3d8eeab1adc5efc33330f Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Jul 29 18:37:56 2016 +0200 intel/{skylake,apollolake}: Enable signalling of error condition Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn returns an int (with -1 for "error"), so use int for devfn. Adapt Change-Id I7d1cdb6af4140f7dc322141c0c018d8418627434 to fix more … [View More]

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coreboot-gerrit November 2016