coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: northbridge/amd: Update all names and IDs for 00670F00
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit aa31f999e9835945f3603c778248dcf67276906d Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:30:17 2016 -0600 northbridge/amd: Update all names and IDs for 00670F00 Modify the new Stoney support files to match the APU's IDs and codename. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit de626730758def76e558294762a06d8ec9950cb9) Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17143 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17143 for details. -gerrit

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Patch set updated for coreboot: northbridge/amd: Update all names and IDs for 00670F00
by Martin Roth 02 Nov '16

02 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17143 -gerrit commit 1238d507828e9832ee5e64b6cbc94554c6db1751 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:30:17 2016 -0600 northbridge/amd: Update all names and IDs for 00670F00 Modify the new Stoney support files to match the APU's IDs and codename. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit de626730758def76e558294762a06d8ec9950cb9) Change-Id: Idc914bc80a27ac13426fdf00fc3f578ce072086f Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00670F00/Kconfig | 10 +++++----- src/northbridge/amd/pi/00670F00/chip.h | 6 +++--- src/northbridge/amd/pi/00670F00/dimmSpd.c | 4 ++-- src/northbridge/amd/pi/00670F00/northbridge.c | 12 ++++++------ src/northbridge/amd/pi/00670F00/northbridge.h | 6 +++--- src/northbridge/amd/pi/Kconfig | 3 ++- src/northbridge/amd/pi/Makefile.inc | 3 ++- 7 files changed, 23 insertions(+), 21 deletions(-) diff --git a/src/northbridge/amd/pi/00670F00/Kconfig b/src/northbridge/amd/pi/00670F00/Kconfig index f5d234d..e349635 100644 --- a/src/northbridge/amd/pi/00670F00/Kconfig +++ b/src/northbridge/amd/pi/00670F00/Kconfig @@ -1,7 +1,7 @@ ## ## This file is part of the coreboot project. ## -## Copyright (C) 2015 Advanced Micro Devices, Inc. +## Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -12,11 +12,11 @@ ## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ## GNU General Public License for more details. ## -config NORTHBRIDGE_AMD_PI_00660F01 +config NORTHBRIDGE_AMD_PI_00670F00 bool select MMCONF_SUPPORT -if NORTHBRIDGE_AMD_PI_00660F01 +if NORTHBRIDGE_AMD_PI_00670F00 config HW_MEM_HOLE_SIZEK hex @@ -36,13 +36,13 @@ config MMCONF_BUS_NUMBER config VGA_BIOS_ID string - default "1002,9870" + default "1002,98e4" help The default VGA BIOS PCI vendor/device ID should be set to the result of the map_oprom_vendev() function in northbridge.c. config VGA_BIOS_FILE string - default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin" + default "3rdparty/blobs/northbridge/amd/00670F00/VBIOS.bin" endif diff --git a/src/northbridge/amd/pi/00670F00/chip.h b/src/northbridge/amd/pi/00670F00/chip.h index ab0e3d2..917bc65 100644 --- a/src/northbridge/amd/pi/00670F00/chip.h +++ b/src/northbridge/amd/pi/00670F00/chip.h @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#ifndef _PI_FAM15CZ_CHIP_H_ -#define _PI_FAM15CZ_CHIP_H_ +#ifndef _PI_FAM15ST_CHIP_H_ +#define _PI_FAM15ST_CHIP_H_ -struct northbridge_amd_pi_00660F01_config +struct northbridge_amd_pi_00670F00_config { u8 spdAddrLookup[2][2][4]; }; diff --git a/src/northbridge/amd/pi/00670F00/dimmSpd.c b/src/northbridge/amd/pi/00670F00/dimmSpd.c index 5c81f36..e0d67d7 100644 --- a/src/northbridge/amd/pi/00670F00/dimmSpd.c +++ b/src/northbridge/amd/pi/00670F00/dimmSpd.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015 - 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -28,7 +28,7 @@ AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PA { int spdAddress; ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2)); - ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info; + ROMSTAGE_CONST struct northbridge_amd_pi_00670F00_config *config = dev->chip_info; if ((dev == 0) || (config == 0)) return AGESA_ERROR; diff --git a/src/northbridge/amd/pi/00670F00/northbridge.c b/src/northbridge/amd/pi/00670F00/northbridge.c index 1caecf9..ce0dde3 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.c +++ b/src/northbridge/amd/pi/00670F00/northbridge.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -582,7 +582,7 @@ static struct device_operations northbridge_operations = { static const struct pci_driver family15_northbridge __pci_driver = { .ops = &northbridge_operations, .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT, + .device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT, }; static void fam15_finalize(void *chip_info) @@ -600,7 +600,7 @@ static void fam15_finalize(void *chip_info) pci_write_config32(dev, 0x60, value); } -struct chip_operations northbridge_amd_pi_00660F01_ops = { +struct chip_operations northbridge_amd_pi_00670F00_ops = { CHIP_NAME("AMD FAM15 Northbridge") .enable_dev = 0, .final = fam15_finalize, @@ -1140,8 +1140,8 @@ static void root_complex_enable_dev(struct device *dev) } } -struct chip_operations northbridge_amd_pi_00660F01_root_complex_ops = { - CHIP_NAME("AMD FAM16 Root Complex") +struct chip_operations northbridge_amd_pi_00670F00_root_complex_ops = { + CHIP_NAME("AMD FAM15 Root Complex") .enable_dev = root_complex_enable_dev, }; @@ -1152,7 +1152,7 @@ u32 map_oprom_vendev(u32 vendev) { u32 new_vendev; new_vendev = - ((0x10029870 <= vendev) && (vendev <= 0x1002987F)) ? 0x10029870 : vendev; + ((0x100298E0 <= vendev) && (vendev <= 0x100298EF)) ? 0x100298E0 : vendev; if (vendev != new_vendev) printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); diff --git a/src/northbridge/amd/pi/00670F00/northbridge.h b/src/northbridge/amd/pi/00670F00/northbridge.h index e095f9a..8ac116c 100644 --- a/src/northbridge/amd/pi/00670F00/northbridge.h +++ b/src/northbridge/amd/pi/00670F00/northbridge.h @@ -13,10 +13,10 @@ * GNU General Public License for more details. */ -#ifndef NORTHBRIDGE_AMD_AGESA_FAM16H_H -#define NORTHBRIDGE_AMD_AGESA_FAM16H_H +#ifndef NORTHBRIDGE_AMD_AGESA_FAM15H_H +#define NORTHBRIDGE_AMD_AGESA_FAM15H_H static struct device_operations pci_domain_ops; static struct device_operations cpu_bus_ops; -#endif /* NORTHBRIDGE_AMD_AGESA_FAM16H_H */ +#endif /* NORTHBRIDGE_AMD_AGESA_FAM15H_H */ diff --git a/src/northbridge/amd/pi/Kconfig b/src/northbridge/amd/pi/Kconfig index cb72416..122b0e6 100644 --- a/src/northbridge/amd/pi/Kconfig +++ b/src/northbridge/amd/pi/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -30,6 +30,7 @@ config S3_VGA_ROM_RUN source src/northbridge/amd/pi/00630F01/Kconfig source src/northbridge/amd/pi/00730F01/Kconfig +source src/northbridge/amd/pi/00670F00/Kconfig source src/northbridge/amd/pi/00660F01/Kconfig config HW_MEM_HOLE_SIZEK diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index 5c2d8e0..09bc2ad 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y) subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 +subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01 romstage-y += agesawrapper.c

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Patch merged into coreboot/master: northbridge/amd: Copy 00660F01 directories to 00670F00
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 2cd67b72746d36186b42f068627e7d2c46e1aecf Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:14:15 2016 -0600 northbridge/amd: Copy 00660F01 directories to 00670F00 Prepare for new 00670FF00 (StoneyRidge) support. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 037cf16883fafd329a15f903ddf97e24a879bcce) Change-Id: I130d4f13beb2c1d71e4e4e9be5011f7993b34660 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17142 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/17142 for details. -gerrit

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Patch merged into coreboot/master: pci_ids.h: Add ID for amd/00670F00 northbridge
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 24901165026731f9fef5e1c91abfca79dd0baa03 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Oct 14 22:30:15 2016 -0400 pci_ids.h: Add ID for amd/00670F00 northbridge Add the D18F0 device ID for the Stoney APU. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit c0fd7f70527c273bcbdce5655a21ca4de4854428) Change-Id: Ib599fc6119a3cef53f4f179c2fcd0e45905d81a4 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17141 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17141 for details. -gerrit

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Patch merged into coreboot/master: cpu/amd: Update files for 00670F00
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit a1ccbf4ec727169fae3a5029e67eba6e727136ae Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:27:46 2016 -0600 cpu/amd: Update files for 00670F00 Add StoneyRidge specific IDs, code, whitespace, and fix Makefles and Kconfig files. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 0bd1dc834792453d8e66216fa9a70afe2f7537d7) Change-Id: Id79f316a89b3baeae95e221fb872dc8a86e7b0f1 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17140 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17140 for details. -gerrit

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Patch set updated for coreboot: cpu/amd: Update files for 00670F00
by Martin Roth 02 Nov '16

02 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17140 -gerrit commit cfe6d0655313fa573fb732d54ba85576cf15c2e8 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:27:46 2016 -0600 cpu/amd: Update files for 00670F00 Add StoneyRidge specific IDs, code, whitespace, and fix Makefles and Kconfig files. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 0bd1dc834792453d8e66216fa9a70afe2f7537d7) Change-Id: Id79f316a89b3baeae95e221fb872dc8a86e7b0f1 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/cpu/amd/pi/00670F00/Kconfig | 6 ++-- src/cpu/amd/pi/00670F00/chip_name.c | 4 +-- src/cpu/amd/pi/00670F00/fixme.c | 50 ++++++++++++++++++--------------- src/cpu/amd/pi/00670F00/model_15_init.c | 20 ++++++------- src/cpu/amd/pi/Kconfig | 4 ++- src/cpu/amd/pi/Makefile.inc | 3 +- 6 files changed, 46 insertions(+), 41 deletions(-) diff --git a/src/cpu/amd/pi/00670F00/Kconfig b/src/cpu/amd/pi/00670F00/Kconfig index de74d3c..d5e3abb 100644 --- a/src/cpu/amd/pi/00670F00/Kconfig +++ b/src/cpu/amd/pi/00670F00/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015 Advanced Micro Devices, Inc. +# Copyright (C) 2015-2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -13,12 +13,12 @@ # GNU General Public License for more details. # -config CPU_AMD_PI_00660F01 +config CPU_AMD_PI_00670F00 bool select PCI_IO_CFG_EXT select X86_AMD_FIXED_MTRRS -if CPU_AMD_PI_00660F01 +if CPU_AMD_PI_00670F00 config CPU_ADDR_BITS int diff --git a/src/cpu/amd/pi/00670F00/chip_name.c b/src/cpu/amd/pi/00670F00/chip_name.c index ff2bc06..3ad62e5 100644 --- a/src/cpu/amd/pi/00670F00/chip_name.c +++ b/src/cpu/amd/pi/00670F00/chip_name.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,6 +15,6 @@ #include <device/device.h> -struct chip_operations cpu_amd_pi_00660F01_ops = { +struct chip_operations cpu_amd_pi_00670F00_ops = { CHIP_NAME("AMD CPU Family 15h") }; diff --git a/src/cpu/amd/pi/00670F00/fixme.c b/src/cpu/amd/pi/00670F00/fixme.c index 9a38bd8..f892af8 100644 --- a/src/cpu/amd/pi/00670F00/fixme.c +++ b/src/cpu/amd/pi/00670F00/fixme.c @@ -25,37 +25,39 @@ void amd_initcpuio(void) AMD_CONFIG_PARAMS StdHeader; /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xF4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); PciData = 1; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. + /* The platform BIOS needs to ensure the memory ranges of SB800 + * legacy devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and + * ACPI) are set to non-posted regions. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x84); - PciData = 0x00FEDF00; /* last address before processor local APIC at FEE00000 */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); + /* last address before processor local APIC at FEE00000 */ + PciData = 0x00FEDF00; PciData |= 1 << 7; /* set NP (non-posted) bit */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x80); - PciData = (0xFED00000 >> 8) | 3; /* lowest NP address is HPET at FED00000 */ + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); + /* lowest NP address is HPET at FED00000 */ + PciData = (0xFED00000 >> 8) | 3; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x8C); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); PciData = 0x00FECF00; /* last address before non-posted range */ LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); LibAmdMsrRead (0xC001001A, &MsrReg, &StdHeader); MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0x88); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); PciData = (UINT32)MsrReg; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC4); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); PciData = 0x0000F000; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x18, 1, 0xC0); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); PciData = 0x00000003; LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); } @@ -68,27 +70,29 @@ void amd_initmmio(void) AMD_CONFIG_PARAMS StdHeader; /* - Set the MMIO Configuration Base Address and Bus Range onto MMIO configuration base - Address MSR register. + Set the MMIO Configuration Base Address and Bus Range onto MMIO + configuration base Address MSR register. */ - MsrReg = CONFIG_MMCONF_BASE_ADDRESS | (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; - LibAmdMsrWrite (0xC0010058, &MsrReg, &StdHeader); + MsrReg = CONFIG_MMCONF_BASE_ADDRESS | \ + (LibAmdBitScanReverse (CONFIG_MMCONF_BUS_NUMBER) << 2) | 1; + LibAmdMsrWrite(0xC0010058, &MsrReg, &StdHeader); /* - Set the NB_CFG MSR register. Enable CF8 extended configuration cycles. + Set the NB_CFG MSR register. Enable CF8 extended config cycles. */ - LibAmdMsrRead (0xC001001F, &MsrReg, &StdHeader); + LibAmdMsrRead(0xC001001F, &MsrReg, &StdHeader); MsrReg = MsrReg | 0x0000400000000000; - LibAmdMsrWrite (0xC001001F, &MsrReg, &StdHeader); + LibAmdMsrWrite(0xC001001F, &MsrReg, &StdHeader); /* For serial port */ PciData = 0xFF03FFD5; - PciAddress.AddressValue = MAKE_SBDFO (0, 0, 0x14, 0x3, 0x44); + PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x14, 0x3, 0x44); LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CACHE_ROM_SIZE) | 5ull; - LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; - LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); + LibAmdMsrWrite(0x20C, &MsrReg, &StdHeader); + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ + 0x800ull; + LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); } diff --git a/src/cpu/amd/pi/00670F00/model_15_init.c b/src/cpu/amd/pi/00670F00/model_15_init.c index e252c3d..dd1c8e3 100644 --- a/src/cpu/amd/pi/00670F00/model_15_init.c +++ b/src/cpu/amd/pi/00670F00/model_15_init.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2015 Advanced Micro Devices, Inc. + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -41,11 +41,11 @@ void PSPProgBar3Msr(void *Buffer) u32 Bar3Addr; u64 Tmp64; /* Get Bar3 Addr */ - Bar3Addr = PspLibPciReadPspConfig (0x20); + Bar3Addr = PspLibPciReadPspConfig(0x20); Tmp64 = Bar3Addr; printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); - LibAmdMsrWrite (0xC00110A2, &Tmp64, NULL); - LibAmdMsrRead (0xC00110A2, &Tmp64, NULL); + LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL); + LibAmdMsrRead(0xC00110A2, &Tmp64, NULL); } static void model_15_init(device_t dev) @@ -59,7 +59,7 @@ static void model_15_init(device_t dev) u32 siblings; #endif - disable_cache (); + disable_cache(); /* Enable access to AMD RdDram and WrDram extension bits */ msr = rdmsr(SYSCFG_MSR); msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; @@ -68,12 +68,12 @@ static void model_15_init(device_t dev) // BSP: make a0000-bffff UC, c0000-fffff WB msr.lo = msr.hi = 0; - wrmsr (0x259, msr); + wrmsr(0x259, msr); msr.lo = msr.hi = 0x1e1e1e1e; wrmsr(0x250, msr); wrmsr(0x258, msr); for (msrno = 0x268; msrno <= 0x26f; msrno++) - wrmsr (msrno, msr); + wrmsr(msrno, msr); msr = rdmsr(SYSCFG_MSR); msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; @@ -89,9 +89,8 @@ static void model_15_init(device_t dev) /* zero the machine check error status registers */ msr.lo = 0; msr.hi = 0; - for (i = 0; i < 6; i++) { + for (i = 0; i < 6; i++) wrmsr(MCI_STATUS + (i * 4), msr); - } /* Enable the local CPU APICs */ @@ -130,8 +129,7 @@ static struct device_operations cpu_dev_ops = { }; static struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x660f00 }, - { X86_VENDOR_AMD, 0x660f01 }, + { X86_VENDOR_AMD, 0x670f00 }, { 0, 0 }, }; diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 3e8d5c7..ed379ea 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -17,6 +17,7 @@ config CPU_AMD_PI bool default y if CPU_AMD_PI_00630F01 default y if CPU_AMD_PI_00730F01 + default y if CPU_AMD_PI_00670F00 default y if CPU_AMD_PI_00660F01 default n select ARCH_BOOTBLOCK_X86_32 @@ -69,4 +70,5 @@ endif # CPU_AMD_PI source src/cpu/amd/pi/00630F01/Kconfig source src/cpu/amd/pi/00730F01/Kconfig +source src/cpu/amd/pi/00670F00/Kconfig source src/cpu/amd/pi/00660F01/Kconfig diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 569c7af..0e31d9f 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2011 - 2012 Advanced Micro Devices, Inc. +# Copyright (C) 2011 - 2016 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -15,6 +15,7 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 +subdirs-$(CONFIG_CPU_AMD_PI_00670F00) += 00670F00 subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 romstage-y += s3_resume.c

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Patch merged into coreboot/master: cpu/amd: Copy 00660F01 to 00670F00
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit a998fbd7cee96780407cacdd4caccbc2560d9985 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:06:43 2016 -0600 cpu/amd: Copy 00660F01 to 00670F00 Prepare for new 00670F00 (StoneyRidge) support. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 87d26e05189247685df0ca6492dc3181a1bad5e8) Change-Id: Ib296ad32a061669b28dae742cac08bb75fdd0de4 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17139 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17139 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Skip FSP initiated core/MP init
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 1a5e32c92966e69399acd154abf9c9e513373ce6 Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Mon Oct 31 17:15:30 2016 -0700 soc/intel/apollolake: Skip FSP initiated core/MP init Enable skip FSP initiated core/MP init as it is implemented in coreboot. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I9417dab3135ca1e0104fc3bde63518288bcfa76a Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Reviewed-on: https://review.coreboot.org/17201 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17201 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Disable Monitor and Mwait feature
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 362180a8a99705caedf9e2843a43d898cb1960af Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Mon Oct 31 17:03:55 2016 -0700 soc/intel/apollolake: Disable Monitor and Mwait feature Monitor/Mwait is broken on APL. So, it needs to be disabled. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I12cd4280de62e0a639b43538171660ee4c0a0265 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Reviewed-on: https://review.coreboot.org/17200 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17200 for details. -gerrit

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Patch merged into coreboot/master: ec/lenovo/h8: move H8_SOUND_REPEAT downwards to it's comment
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 318ed6f8188c3f797fd2fbbc8122f5e2cb8b63d3 Author: Alexander Couzens <lynxis(a)fe80.eu> Date: Sun Oct 16 07:44:26 2016 +0200 ec/lenovo/h8: move H8_SOUND_REPEAT downwards to it's comment Change-Id: Ib147d90c31421c46faf99517fd07d290fd6b90a9 Signed-off-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-on: https://review.coreboot.org/17036 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/17036 for details. -gerrit

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coreboot-gerrit November 2016