coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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1666 discussions

Patch set updated for coreboot: lpss_i2c: Increase transaction timeout
by Duncan Laurie 03 Nov '16

03 Nov '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17213 -gerrit commit 5f73db4eeda585178f11734e91d8b07cb67cd567 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Nov 3 10:43:14 2016 -0700 lpss_i2c: Increase transaction timeout When doing long transcations on an I2C bus at standard speed we saw that long transactions could go over the 4ms limit while waiting for the it to complete on the bus. Increase this so we can use standard speed for testing and debug in firmware. (as there is no way to force standard speed in the kernel) BUG=chrome-os-partner:58666 TEST=boot eve board with cr50 TPM and I2C bus at 100khz Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/common/lpss_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c index 0174792..58d44b8 100644 --- a/src/soc/intel/common/lpss_i2c.c +++ b/src/soc/intel/common/lpss_i2c.c @@ -73,8 +73,8 @@ struct lpss_i2c_regs { uint32_t comp_type; } __attribute__((packed)); -/* Use a ~4ms timeout for various operations */ -#define LPSS_I2C_TIMEOUT_US 4000 +/* Use a ~10ms timeout for various operations */ +#define LPSS_I2C_TIMEOUT_US 10000 /* High and low times in different speed modes (in ns) */ enum {

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New patch to review for coreboot: lpss_i2c: Increase transaction timeout
by Duncan Laurie 03 Nov '16

03 Nov '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17213 -gerrit commit e8facd4e07b5ab41813d37e3980179b602b9fcf7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Nov 3 10:43:14 2016 -0700 lpss_i2c: Increase transaction timeout When doing long transcations on an I2C bus at standard speed we saw that long transactions could go over the 4ms limit while waiting for the it to complete on the bus. Increase this so we can use standard speed for testing and debug in firmware. (as there is no way to force standard speed in the kernel) BUG=chrome-os-partner:58666 TEST=boot eve board with cr50 TPM and I2C bus at 100khz Change-Id: I2987ae6a5aa024b373eb088767194c70b0918b6f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/common/lpss_i2c.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/lpss_i2c.c b/src/soc/intel/common/lpss_i2c.c index 0174792..58d44b8 100644 --- a/src/soc/intel/common/lpss_i2c.c +++ b/src/soc/intel/common/lpss_i2c.c @@ -73,8 +73,8 @@ struct lpss_i2c_regs { uint32_t comp_type; } __attribute__((packed)); -/* Use a ~4ms timeout for various operations */ -#define LPSS_I2C_TIMEOUT_US 4000 +/* Use a ~10ms timeout for various operations */ +#define LPSS_I2C_TIMEOUT_US 10000 /* High and low times in different speed modes (in ns) */ enum {

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New patch to review for coreboot: soc/intel/{sky, apollo}lake: Wait until GPE is clear when reading
by Duncan Laurie 03 Nov '16

03 Nov '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17212 -gerrit commit fb9bf06842c406f01ecbaf9494f31abe806003e1 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Thu Nov 3 10:33:43 2016 -0700 soc/intel/{sky,apollo}lake: Wait until GPE is clear when reading When reading+clearing a GPE for use as an interrupt we need to re-read the status register and keep setting the clear bit until it actually reads back clear. Also add a 1ms timeout in case the status never clears. This is needed if a device sends a longer interrupt pulse and it is still asserted when the "ISR" goes to clear the status. BUG=chrome-os-partner:59299 TEST=test cr50 TPM with 20us pulse to ensure it can successfully communicate with the TPM and does not get confused due to seeing interrupts that it should not. Change-Id: I384f484a1728038d3a355586146deee089b22dd9 Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/soc/intel/apollolake/pmutil.c | 20 +++++++++++++++----- src/soc/intel/skylake/pmutil.c | 23 +++++++++++++++++------ 2 files changed, 32 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 80aaf71..d479b95 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -29,6 +29,7 @@ #include <soc/pm.h> #include <device/device.h> #include <device/pci.h> +#include <timer.h> #include <vboot/vboot_common.h> #include "chip.h" @@ -306,6 +307,8 @@ int acpi_get_gpe(int gpe) { int bank; uint32_t mask, sts; + struct stopwatch sw; + int rc = 0; if (gpe < 0 || gpe > GPE0_DW3_31) return -1; @@ -313,11 +316,18 @@ int acpi_get_gpe(int gpe) bank = gpe / 32; mask = 1 << (gpe % 32); - sts = inl(ACPI_PMIO_BASE + GPE0_STS(bank)); - if (sts & mask) { - outl(mask, ACPI_PMIO_BASE + GPE0_STS(bank)); - return 1; - } + /* Wait up to 1ms for GPE status to clear */ + stopwatch_init_msecs_expire(&sw, 1); + do { + if (stopwatch_expired(&sw)) + return rc; + + sts = inl(ACPI_PMIO_BASE + GPE0_STS(bank)); + if (sts & mask) { + outl(mask, ACPI_PMIO_BASE + GPE0_STS(bank)); + rc = 1; + } + } while (sts & mask); return 0; } diff --git a/src/soc/intel/skylake/pmutil.c b/src/soc/intel/skylake/pmutil.c index 203a430..73dc117 100644 --- a/src/soc/intel/skylake/pmutil.c +++ b/src/soc/intel/skylake/pmutil.c @@ -37,6 +37,7 @@ #include <soc/pm.h> #include <soc/pmc.h> #include <soc/smbus.h> +#include <timer.h> #include "chip.h" /* Print status bits with descriptive names */ @@ -361,6 +362,8 @@ int acpi_get_gpe(int gpe) { int bank; uint32_t mask, sts; + struct stopwatch sw; + int rc = 0; if (gpe < 0 || gpe > GPE0_WADT) return -1; @@ -368,12 +371,20 @@ int acpi_get_gpe(int gpe) bank = gpe / 32; mask = 1 << (gpe % 32); - sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); - if (sts & mask) { - outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); - return 1; - } - return 0; + /* Wait up to 1ms for GPE status to clear */ + stopwatch_init_msecs_expire(&sw, 1); + do { + if (stopwatch_expired(&sw)) + return rc; + + sts = inl(ACPI_BASE_ADDRESS + GPE0_STS(bank)); + if (sts & mask) { + outl(mask, ACPI_BASE_ADDRESS + GPE0_STS(bank)); + rc = 1; + } + } while (sts & mask); + + return rc; } /* Enable all requested GPE */

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Patch set updated for coreboot: drivers/i2c/tpm/cr50: Increase IRQ timeout
by Duncan Laurie 03 Nov '16

03 Nov '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17204 -gerrit commit f577d3dd104d11f0e73353c28158a84b513ffec7 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Nov 1 15:03:13 2016 -0700 drivers/i2c/tpm/cr50: Increase IRQ timeout Increase the IRQ timeout to prevent issues if there is a delay in the TPM responding to a command. Split the no-IRQ case out so it doesn't suffer unnecessarily. BUG=chrome-os-partner:59191 TEST=suspend/resume testing on eve board Change-Id: I1ea7859bc7a056a450b2b0ee32153ae43ee8699f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/i2c/tpm/cr50.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index f7e667b..0877de0 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -48,6 +48,8 @@ #define CR50_MAX_BUFSIZE 63 #define CR50_TIMEOUT_LONG_MS 2000 /* Long timeout while waiting for TPM */ #define CR50_TIMEOUT_SHORT_MS 2 /* Short timeout during transactions */ +#define CR50_TIMEOUT_NOIRQ_MS 20 /* Timeout for TPM ready without IRQ */ +#define CR50_TIMEOUT_IRQ_MS 100 /* Timeout for TPM ready with IRQ */ #define CR50_DID_VID 0x00281ae0L struct tpm_inf_dev { @@ -65,11 +67,11 @@ static int cr50_i2c_wait_tpm_ready(struct tpm_chip *chip) if (!chip->vendor.irq_status) { /* Fixed delay if interrupt not supported */ - mdelay(CR50_TIMEOUT_SHORT_MS); + mdelay(CR50_TIMEOUT_NOIRQ_MS); return 0; } - stopwatch_init_msecs_expire(&sw, 5 * CR50_TIMEOUT_SHORT_MS); + stopwatch_init_msecs_expire(&sw, CR50_TIMEOUT_IRQ_MS); while (!chip->vendor.irq_status(chip->vendor.irq)) if (stopwatch_expired(&sw)) @@ -429,6 +431,11 @@ static void cr50_vendor_init(struct tpm_chip *chip) chip->vendor.irq = -1; #endif } + + if (chip->vendor.irq <= 0) + printk(BIOS_WARNING, + "%s: No IRQ, will use %ums delay for TPM ready\n", + __func__, CR50_TIMEOUT_NOIRQ_MS); } int tpm_vendor_probe(unsigned bus, uint32_t addr)

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Patch merged into coreboot/master: mainboard/intel/kblrvp: Update onboard memory specific configs
by gerrit＠coreboot.org 03 Nov '16

03 Nov '16

the following patch was just integrated into master: commit 46575fb1d4f00e0d1e69e9ad38acb4c1e4b38711 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Thu Oct 27 21:18:25 2016 +0530 mainboard/intel/kblrvp: Update onboard memory specific configs 1. Update dq, dqs map & Rcomp strength & Rcomp target. 2. Fix rvp3.spd.hex byte 2 to 0x0F(JEDEC LPDDR3 memory type). Change-Id: I7efc3499b915d1e414cfe914830232993ef10ba2 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> See https://review.coreboot.org/17162 for details. -gerrit

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Patch merged into coreboot/master: mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.c
by gerrit＠coreboot.org 03 Nov '16

03 Nov '16

the following patch was just integrated into master: commit cebf64592702185be0eba4e4b44f1a9c258751fc Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Thu Oct 27 20:28:23 2016 +0530 mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.c 1. Update gpio.h to set proper pad config for Kaby Lake RVP3. 2. Set spd index to zero. 3. Remove nhlt specific init. Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17161 for details. -gerrit

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Patch set updated for coreboot: intel/apollolake: Enable turbo
by Shaunak Saha 03 Nov '16

03 Nov '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17203 -gerrit commit 0b5aefd533827c2c75a4a33caacc0f592863fc6e Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Mon Oct 10 12:34:28 2016 -0700 intel/apollolake: Enable turbo This patch adds punit initialization code after FspMemoryInit so that turbo can be initialized after that. BUG=chrome-os-partner:58158 BRANCH=None Change-Id: I4939da47da82b9a728cf1b5cf6d5ec54b4f5b31d Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.h | 1 + src/soc/intel/apollolake/include/soc/cpu.h | 2 ++ src/soc/intel/apollolake/include/soc/iomap.h | 6 ++++ src/soc/intel/apollolake/romstage.c | 53 ++++++++++++++++++++++++++++ src/soc/intel/apollolake/tsc_freq.c | 41 +++++++++++++++++++++ 5 files changed, 103 insertions(+) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 6c3bcd8..b5d132d 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -124,4 +124,5 @@ struct soc_intel_apollolake_config { uint16_t prt0_gpio; }; +void set_max_freq(void); #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index e94972d..603d139 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -88,4 +88,6 @@ void apollolake_init_cpus(struct device *dev); /* Common Timer Copy (CTC) frequency - 19.2MHz. */ #define CTC_FREQ 19200000 +#define APL_BURST_MODE_DISABLE 0x0000004000000000 + #endif /* _SOC_APOLLOLAKE_CPU_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index d5d8f87..3c94d1b 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,6 +25,12 @@ #define MCH_BASE_ADDR 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) +#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168 +#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078 +#define PUNIT_THERMAL_DEVICE_IRQ 0x700C +#define PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER 0x18 +#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 + #define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1f6a38f..ffa20f7 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -40,6 +40,8 @@ #include <soc/uart.h> #include <string.h> #include <timestamp.h> +#include <delay.h> +#include "chip.h" static struct chipset_power_state power_state CAR_GLOBAL; @@ -100,6 +102,53 @@ static void migrate_power_state(int is_recovery) } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +/* + * Punit Initialization code.This all isn't documented, but + * this is the recipe . + */ +static void punit_init(void) +{ + uint32_t reg; + uint32_t data; + + /* Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR) */ + write32((void *)(MCH_BASE_ADDR + P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR), + 0x0); + + /* P-Unit bring up */ + reg = read32((void *)(MCH_BASE_ADDR + + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)); + if (reg == 0xffffffff) { + /* P-unit not found */ + printk(BIOS_DEBUG,"Punit MMIO not available \n"); + } else { + /* Set Punit interrupt pin IPIN offset 3D */ + write32((void *)(0xE000103D),0x002); + + /* Set PUINT IRQ to 24 and INTPIN LOCK */ + write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), + PUINT_THERMAL_DEVICE_IRQ_VEC_NUMBER | + PUINT_THERMAL_DEVICE_IRQ_LOCK); + + data = read32((void *)(MCH_BASE_ADDR + 0x7818)); + data &= 0xFFFFE01F; + data |= (0x20 | 0x200); + write32((void *)(MCH_BASE_ADDR + 0x7818), data); + + /* Stage0 BIOS Reset Complete (RST_CPL) */ + write32((void *)(MCH_BASE_ADDR + + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR), 0x1); + + /* Poll for bit 8 in same reg (RST_CPL) */ + data = read32((void *)(MCH_BASE_ADDR + + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)); + while ( !(read32 ((void *)(MCH_BASE_ADDR + + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)) & 0x100) ) { + udelay(100); + } + } +} + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -119,6 +168,10 @@ asmlinkage void car_stage_entry(void) s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + + punit_init(); + set_max_freq(); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c index 9dd1dea..6510c00 100644 --- a/src/soc/intel/apollolake/tsc_freq.c +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -14,12 +14,53 @@ * GNU General Public License for more details. */ +#include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <soc/cpu.h> +#include <console/console.h> +#include <delay.h> +#include "chip.h" unsigned long tsc_freq_mhz(void) { msr_t msr = rdmsr(MSR_PLATFORM_INFO); return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); } + +void set_max_freq(void) +{ + msr_t msr, msr_rd; + unsigned int eax; + + eax = cpuid_eax(6); + + msr = rdmsr(MSR_IA32_MISC_ENABLES); + if ((eax == 0) && ((msr.hi & APL_BURST_MODE_DISABLE) == 0)) { + /* Burst Mode has been factory configured as disabled + * and is not available in this physical processor + * package. + */ + printk(BIOS_DEBUG, "Burst Mode is factory disabled\n"); + return; + } + + /* Enable burst mode */ + msr.hi = 0; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Enable speed step. */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Set P-State ratio */ + msr = rdmsr(IA32_PERL_CTL); + msr.lo &= ~(0xff00); + + /* Read the frequency limit ratio and set it properly in PERF_CTL */ + msr_rd = rdmsr(FREQ_LIMIT_RATIO); + msr.lo |= ((msr_rd.lo & 0xff) << 8); + + wrmsr(IA32_PERL_CTL, msr); +}

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Patch set updated for coreboot: nb/intel/i945: make pci_mmio_size a devicetree parameter
by Arthur Heymans 03 Nov '16

03 Nov '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit 4a9da310e35723058a49ca9f7dce5b16d10ae8db Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: make pci_mmio_size a devicetree parameter Instead of hardcoding pci_mmio_size in the raminit code, this makes it a parameter in the devicetree. Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/devicetree.cb | 2 ++ src/mainboard/lenovo/t60/devicetree.cb | 2 ++ src/mainboard/lenovo/x60/devicetree.cb | 2 ++ src/northbridge/intel/i945/chip.h | 1 + src/northbridge/intel/i945/raminit.c | 21 ++++++++++++++++++--- 5 files changed, 25 insertions(+), 3 deletions(-) diff --git a/src/mainboard/apple/macbook21/devicetree.cb b/src/mainboard/apple/macbook21/devicetree.cb index 4bbe28d..f37e768 100644 --- a/src/mainboard/apple/macbook21/devicetree.cb +++ b/src/mainboard/apple/macbook21/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x8086 0x7270 diff --git a/src/mainboard/lenovo/t60/devicetree.cb b/src/mainboard/lenovo/t60/devicetree.cb index 2dc9f45..f66455b 100644 --- a/src/mainboard/lenovo/t60/devicetree.cb +++ b/src/mainboard/lenovo/t60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2015 diff --git a/src/mainboard/lenovo/x60/devicetree.cb b/src/mainboard/lenovo/x60/devicetree.cb index e2a24c1..0ac9273 100644 --- a/src/mainboard/lenovo/x60/devicetree.cb +++ b/src/mainboard/lenovo/x60/devicetree.cb @@ -30,6 +30,8 @@ chip northbridge/intel/i945 end end + register "pci_mmio_size" = "768" + device domain 0 on device pci 00.0 on # Host bridge subsystemid 0x17aa 0x2017 diff --git a/src/northbridge/intel/i945/chip.h b/src/northbridge/intel/i945/chip.h index 446af72..c6d80e6 100644 --- a/src/northbridge/intel/i945/chip.h +++ b/src/northbridge/intel/i945/chip.h @@ -8,6 +8,7 @@ struct northbridge_intel_i945_config { u32 gpu_backlight; int gpu_lvds_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx; + u16 pci_mmio_size; }; #endif /* NORTHBRIDGE_INTEL_I945_CHIP_H */ diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c..fa70a76 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -16,6 +16,8 @@ #include <console/console.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> +#include <device/pci_def.h> +#include <device/device.h> #include <lib.h> #include <pc80/mc146818rtc.h> #include <spd.h> @@ -25,6 +27,7 @@ #include <lib.h> #include "raminit.h" #include "i945.h" +#include "chip.h" #include <cbmem.h> /* Debugging macros. */ @@ -48,6 +51,7 @@ #define RAM_EMRS_2 (0x1 << 21) #define RAM_EMRS_3 (0x2 << 21) +#define DEFAULT_PCI_MMIO_SIZE 768 static int get_dimm_spd_address(struct sys_info *sysinfo, int device) { if (sysinfo->spd_addresses) @@ -1503,7 +1507,9 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; - int cum0, cum1, tolud, tom; + int cum0, cum1, tolud, tom, pci_mmio_size; + const struct device *dev; + const struct northbridge_intel_i945_config *cfg = NULL; printk(BIOS_DEBUG, "Setting RAM size...\n"); @@ -1542,8 +1548,17 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) tom = tolud >> 3; /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + dev = dev_find_slot(0, PCI_DEVFN(0, 0)); + if (dev) + cfg = dev->chip_info; + + /* If this is zero, it just means devicetree.cb didn't set it */ + if (!cfg || cfg->pci_mmio_size == 0) + pci_mmio_size = DEFAULT_PCI_MMIO_SIZE; + else + pci_mmio_size = cfg->pci_mmio_size; + + tolud = MIN((ALIGN_DOWN(4096 - pci_mmio_size, 128) / 128) << 3, tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);

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Patch merged into coreboot/master: google/veyron*: change .ddrconfig from 14 to 3
by gerrit＠coreboot.org 03 Nov '16

03 Nov '16

the following patch was just integrated into master: commit f4401eb997dab0690261e0e42eab52131815d949 Author: ZhengShunQian <zhengsq(a)rock-chips.com> Date: Fri Oct 28 16:16:04 2016 +0800 google/veyron*: change .ddrconfig from 14 to 3 There are two configs, sdram-lpddr3-hynix-2GB.inc and sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14. Changing .ddrconfig from 14 to 3 improves performance especially on contiguous memory accesses. Comparing the .ddrconfig: - if .ddrconfig = 3, C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C--- - if .ddrconfig = 14, C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C--- where - R: indicates Row bits - B: indicates Bank bits - C: indicates Column bits - D: indicates Chip selects bits .ddrconfig = 3 has multiple banks switching which improves DDR timing. BUG=chrome-os-partner:57321 TEST=Boot from fievel and play video BRANCH=veyron Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4 Original-Signed-off-by: ZhengShunQian <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/404691 Original-Commit-Ready: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/17210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17210 for details. -gerrit

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Patch merged into coreboot/master: google/veyron*: add DDR configs for new samsung DDR
by gerrit＠coreboot.org 03 Nov '16

03 Nov '16

the following patch was just integrated into master: commit 8859afdb44194cacf0bc1c694b09eb94d568dab9 Author: ZhengShunQian <zhengsq(a)rock-chips.com> Date: Fri Oct 28 15:58:51 2016 +0800 google/veyron*: add DDR configs for new samsung DDR Add the new samsung DDR configs for all veyron except veyron_rialto: * K4E6E304EB-EGCE, ramid = 0010, 4GB * K4E8E324EB-EGCF, ramid = 1100, 2GB BRANCH=veyron BUG=none TEST=boot fievel board Change-Id: I747aa86f8c93174651a28face63b3386e22b23b3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5f55462e71bd481eda85af3d582cfe5b9873cc9c Original-Change-Id: I19123634c994f685683323f7d85cc4d35814e2ab Original-Signed-off-by: ZhengShunQian <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345748 Original-Commit-Queue: Ren Kuo <ren.kuo(a)quantatw.com> Original-Reviewed-by: Philip Chen <philipchen(a)chromium.org> Original-(cherry-pick from cc990f27024255a326fd9fa9644deb28b01a31a7) Original-Reviewed-on: https://chromium-review.googlesource.com/404690 Original-Commit-Ready: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/17209 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17209 for details. -gerrit

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coreboot-gerrit November 2016