coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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1666 discussions

Patch merged into coreboot/master: rockchip/rk3399: sdram.c: Fix msch ddrconfig register error
by gerrit＠coreboot.org 03 Nov '16

03 Nov '16

the following patch was just integrated into master: commit 60687b52076ec6d4da3587859adcb0d49a05aca0 Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Oct 17 10:31:30 2016 +0800 rockchip/rk3399: sdram.c: Fix msch ddrconfig register error Fix msch ddrconfig register write error. Also make sure that the row number configured in msch is equal to the row number configured in the DDR controller. This would not affect systems with 4GB of memory, but is needed for 2GB configurations. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: Ic95b3371faec5b31c32b011c50e55e83d949e74d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: dfa43d3d44839d9685b6393157f51b646e9996de Original-Change-Id: I0c95378bf937a245b7cdc0583c5d2ed1347f2a3e Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399563 Original-Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/17208 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17208 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Implement SPI flash status register read
by gerrit＠coreboot.org 03 Nov '16

03 Nov '16

the following patch was just integrated into master: commit d36ed272b2d2d082889a7f21414904badc2c2936 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Nov 1 21:33:12 2016 -0700 soc/intel/apollolake: Implement SPI flash status register read This was a dummy implementation until now which returned -1 always. Add support for reading SPI flash status register (srp0). BUG=chrome-os-partner:59267 BRANCH=None TEST=Verified by enabling and disabling write-protect on reef that the value of SRP0 changes accordingly in status register read. Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17205 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17205 for details. -gerrit

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Patch set updated for coreboot: arch/x86/acpigen: Add OperationRegion & Field method
by Naresh Solanki 03 Nov '16

03 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17113 -gerrit commit 0f9cbe244a48a47a087b9127b911e80be64f2d12 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Oct 25 00:51:24 2016 +0530 arch/x86/acpigen: Add OperationRegion & Field method Add acpigen_write_opregion that generates ACPI AML code for OperationRegion, region name, region space, region length & region size are inputs. Add acpigen_write_field that generates ACPI AML code for Field. Operation region name & field list are inputs. Change-Id: I578834217d39aa3b0d409eb8ba4b5f7a31969fa8 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/arch/x86/acpigen.c | 116 ++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 72 ++++++++++++++++++++++ 2 files changed, 188 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 42d4204..0c5a10c 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -351,6 +351,122 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) acpigen_emit_byte(pblock_len); } +/* + * Generate ACPI AML code for OperationRegion + * Arg0: Pointer to struct opregion opreg = OPREGION(rname, space, offset, len) + * where rname is region name, space is region space, offset is region offset & + * len is region length. + * OperationRegion(regionname, regionspace, regionoffset, regionlength) + */ +void acpigen_write_opregion(struct opregion *opreg) +{ + /* OpregionOp */ + acpigen_emit_ext_op(OPREGION_OP); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(opreg->name); + /* RegionSpace */ + acpigen_emit_byte(opreg->regionspace); + /* RegionOffset & RegionLen, it can be byte word or double word */ + acpigen_write_integer(opreg->regionoffset); + acpigen_write_integer(opreg->regionlen); +} + +static void acpigen_write_field_offset(uint32_t offset, + uint32_t current_bit_pos) +{ + uint32_t diff_bits; + uint8_t i, j; + uint8_t emit[4]; + + if (offset < current_bit_pos) { + printk(BIOS_WARNING, "%s: Cannot move offset backward", + __func__); + return; + } + + diff_bits = offset - current_bit_pos; + /* Upper limit */ + if (diff_bits > 0xFFFFFFF) { + printk(BIOS_WARNING, "%s: Offset very large to encode", + __func__); + return; + } + + i = 1; + if (diff_bits < 0x40) { + emit[0] = diff_bits & 0x3F; + } else { + emit[0] = diff_bits & 0xF; + diff_bits >>= 4; + while (diff_bits) { + emit[i] = diff_bits & 0xFF; + i++; + diff_bits >>= 8; + } + } + /* Update bit 7:6 : Number of bytes followed by emit[0] */ + emit[0] |= (i - 1) << 6; + + acpigen_emit_byte(0); + for (j = 0; j < i; j++) + acpigen_emit_byte(emit[j]); +} + +/* + * Generate ACPI AML code for Field + * Arg0: region name + * Arg1: Pointer to struct fieldlist. + * Arg2: no. of entries in Arg1 + * Arg3: flags which indicate filed access type, lock rule & update rule. + * Example with fieldlist + * struct fieldlist l[] = { + * FIELDLIST_OFFSET(0x84), + * FIELDLIST_NAMESTR("PMCS", 2), + * }; + * acpigen_write_field("UART", l ,ARRAY_SIZE(l), FIELD_ANYACC | FIELD_NOLOCK | + * FIELD_PRESERVE); + * Output: + * Field (UART, AnyAcc, NoLock, Preserve) + * { + * Offset (0x84), + * PMCS, 2 + * } + */ +void acpigen_write_field(const char *name, struct fieldlist *l, size_t count, + uint8_t flags) +{ + uint16_t i; + uint32_t current_bit_pos = 0; + + /* FieldOp */ + acpigen_emit_ext_op(FIELD_OP); + /* Package Length */ + acpigen_write_len_f(); + /* NameString 4 chars only */ + acpigen_emit_simple_namestring(name); + /* Field Flag */ + acpigen_emit_byte(flags); + + for (i = 0; i < count; i++) { + switch (l[i].type) { + case NAME_STRING: + acpigen_emit_simple_namestring(l[i].name); + acpigen_emit_byte(l[i].bits); + current_bit_pos += l[i].bits; + break; + case OFFSET: + acpigen_write_field_offset(l[i].bits, current_bit_pos); + current_bit_pos = l[i].bits; + break; + default: + printk(BIOS_ERR, "%s: Invalid field type 0x%X\n" + , __func__, l[i].type); + break; + } + } + acpigen_pop_len(); +} + void acpigen_write_empty_PCT(void) { /* diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 7c15a31..4169fdf 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -53,6 +53,8 @@ enum { EXT_OP_PREFIX = 0x5B, SLEEP_OP = 0x22, DEBUG_OP = 0x31, + OPREGION_OP = 0x80, + FIELD_OP = 0x81, DEVICE_OP = 0x82, PROCESSOR_OP = 0x83, POWER_RES_OP = 0x84, @@ -84,6 +86,64 @@ enum { ONES_OP = 0xFF, }; +#define FIELDLIST_OFFSET(X) { .type = OFFSET, \ + .name = "",\ + .bits = X * 8, \ + } +#define FIELDLIST_NAMESTR(X, Y) { .type = NAME_STRING, \ + .name = X, \ + .bits = Y, \ + } + +#define FIELD_ANYACC 0 +#define FIELD_BYTEACC 1 +#define FIELD_WORDACC 2 +#define FIELD_DWORDACC 3 +#define FIELD_QWORDACC 4 +#define FIELD_BUFFERACC 5 +#define FIELD_NOLOCK (0<<4) +#define FIELD_LOCK (1<<4) +#define FIELD_PRESERVE (0<<5) +#define FIELD_WRITEASONES (1<<5) +#define FIELD_WRITEASZEROS (2<<5) + +enum field_type { + OFFSET, + NAME_STRING, + FIELD_TYPE_MAX, +}; + +struct fieldlist { + enum field_type type; + const char *name; + u32 bits; +}; + +#define OPREGION(rname, space, offset, len) {.name = rname, \ + .regionspace = space, \ + .regionoffset = offset, \ + .regionlen = len, \ + } + +enum region_space { + SYSTEMMEMORY, + SYSTEMIO, + PCI_CONFIG, + EMBEDDEDCONTROL, + SMBUS, + CMOS, + PCIBARTARGET, + IPMI, + REGION_SPACE_MAX, +}; + +struct opregion { + const char *name; + enum region_space regionspace; + unsigned long regionoffset; + unsigned long regionlen; +}; + void acpigen_write_len_f(void); void acpigen_pop_len(void); void acpigen_set_current(char *curr); @@ -175,6 +235,18 @@ void acpigen_write_return_byte(uint8_t arg); */ void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), size_t count, void *arg); +/* + * Generate ACPI AML code for OperationRegion + * This function takes input region name, region space, region offset & region + * length. + */ +void acpigen_write_opregion(struct opregion *opreg); +/* + * Generate ACPI AML code for Field + * This function takes input region name, fieldlist, count & flags. + */ +void acpigen_write_field(const char *name, struct fieldlist *l, size_t count, + uint8_t flags); int get_cst_entries(acpi_cstate_t **);

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Patch set updated for coreboot: soc/intel: Add MSR to support enabling turbo frequency
by Shaunak Saha 02 Nov '16

02 Nov '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17211 -gerrit commit e064a13fc19b5f2eeec4d210080af2b4a0336943 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Wed Nov 2 10:52:23 2016 -0700 soc/intel: Add MSR to support enabling turbo frequency This patch adds definition for IA32_PERF_CTL and FREQ_LIMIT_RATIO MSR's. FREQ_LIMIT_RATIO register allows determines the ratio limits to be used to limit frequency. PERF_CTL is Performance Control MSR. BIOS makes request for a new Performance state (P-state) by writing this MSR. BUG=chrome-os-partner:58158 BRANCH=None Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/include/cpu/intel/turbo.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 6626cb1..cfa859a 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -26,6 +26,9 @@ #define H_MISC_DISABLE_TURBO (1 << 6) +#define IA32_PERL_CTL 0x199 +#define FREQ_LIMIT_RATIO 0x1AD + enum { TURBO_UNKNOWN, TURBO_UNAVAILABLE,

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Patch merged into coreboot/master: nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)"
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 6372a0eef14dd97f2743d7d1820e2446cc997bd2 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 30 18:39:53 2016 +0100 nb/intel/i945/early_init.c: Use "IS_ENABLED(CONFIG_ ....)" Change-Id: I230b5425ac9e916a5ee10a49eeaf5d6d44fd49e6 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/17192 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h(a)gmx.de> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17192 for details. -gerrit

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Patch set updated for coreboot: drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support
by Brenton Dong 02 Nov '16

02 Nov '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17062 -gerrit commit 89212006b5def0a482f6dd221b2cf581e148b03d Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Tue Oct 18 11:35:15 2016 -0700 drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/arch/x86/postcar.c | 5 +++ src/drivers/intel/fsp2_0/Kconfig | 17 ++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 9 ++++ src/drivers/intel/fsp2_0/include/fsp/api.h | 1 + src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 + src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/temp_ram_exit.c | 48 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/util.c | 2 + 8 files changed, 85 insertions(+) diff --git a/src/arch/x86/postcar.c b/src/arch/x86/postcar.c old mode 100644 new mode 100755 index b6ae09a..c4c9cda --- a/src/arch/x86/postcar.c +++ b/src/arch/x86/postcar.c @@ -18,6 +18,7 @@ #include <main_decl.h> #include <program_loading.h> #include <soc/intel/common/util.h> +#include <fsp/util.h> void main(void) { @@ -26,6 +27,10 @@ void main(void) /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); + /* Call TempRamExit FSP API if enabled. */ + if (IS_ENABLED(CONFIG_FSP_CAR)) + fsp_temp_ram_exit(); + /* Display the MTRRs */ if (IS_ENABLED(CONFIG_DISPLAY_MTRRS)) soc_display_mtrrs(); diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3ffb402..62bdd50 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -53,6 +53,11 @@ config DISPLAY_UPD_DATA Display the user specified product data prior to memory initialization. +config FSP_T_CBFS + string "Name of FSP-T in CBFS" + depends on FSP_CAR + default "fspt.bin" + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" @@ -61,6 +66,12 @@ config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" +config FSP_T_FILE + string "Intel FSP-T (temp ram init) binary path and filename" + depends on FSP_CAR + help + The path and filename of the Intel FSP-M binary for this platform. + config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES @@ -73,6 +84,12 @@ config FSP_S_FILE help The path and filename of the Intel FSP-S binary for this platform. +config FSP_CAR + bool "Use FSP TempRamInit & TempRamExit APIs" + default n + help + Use FSP APIs to initialize & Tear Down the Cache-As-Ram + config FSP_M_XIP bool "Is FSP-M XIP" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index beeec7c..d222e4c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -38,11 +38,20 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c +postcar-$(CONFIG_FSP_CAR) += util.c +postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +ifeq ($(CONFIG_FSP_CAR),y) +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_T_CBFS) +$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) +$(CONFIG_FSP_T_CBFS)-type := fsp +endif # CONFIG_FSP_CAR + cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h old mode 100644 new mode 100755 index 553fc52..14c92fd --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -39,6 +39,7 @@ enum fsp_notify_phase { /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); +uint32_t fsp_temp_ram_exit(void); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 6351b32..c84c33e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -34,6 +34,8 @@ struct fsp_header { uint16_t component_attribute; size_t cfg_region_offset; size_t cfg_region_size; + size_t temp_ram_init_entry; + size_t temp_ram_exit_entry; size_t notify_phase_entry_offset; size_t memory_init_entry_offset; size_t silicon_init_entry_offset; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 04f8c00..13c6ab2 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -101,6 +101,7 @@ void fsp_handle_reset(uint32_t status); /* SoC/chipset must provide this to handle platform-specific reset codes */ void chipset_handle_reset(uint32_t status); +typedef asmlinkage uint32_t (*temp_ram_exit_fn)(void *param); typedef asmlinkage uint32_t (*fsp_memory_init_fn) (void *raminit_upd, void **hob_list); typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c new file mode 100755 index 0000000..38a6098 --- /dev/null +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -0,0 +1,48 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> + +#include <cbfs.h> + +uint32_t fsp_temp_ram_exit(void) +{ + struct fsp_header hdr; + uint32_t status; + temp_ram_exit_fn temp_ram_exit; + struct cbfsf file_desc; + struct region_device file_data; + const char *name = CONFIG_FSP_M_CBFS; + + if (cbfs_boot_locate(&file_desc, name, NULL)) { + printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); + die("FSPM not available for CAR Exit!\n"); + } + + cbfs_file_data(&file_data, &file_desc); + + if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS) + return CB_ERR; + + temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); + printk(BIOS_DEBUG, "Calling TempRamExit: 0x%p\n", temp_ram_exit); + status = temp_ram_exit(NULL); + printk(BIOS_DEBUG, "TempRamExit returned 0x%08x\n", status); + + return status; +} diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index e7e4f16..7453b59 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -52,6 +52,8 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) hdr->component_attribute = read16(raw_hdr + 34); hdr->cfg_region_offset = read32(raw_hdr + 36); hdr->cfg_region_size = read32(raw_hdr + 40); + hdr->temp_ram_init_entry = read32(raw_hdr + 48); + hdr->temp_ram_exit_entry = read32(raw_hdr + 64); hdr->notify_phase_entry_offset = read32(raw_hdr + 56); hdr->memory_init_entry_offset = read32(raw_hdr + 60); hdr->silicon_init_entry_offset = read32(raw_hdr + 68);

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Patch set updated for coreboot: soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
by Brenton Dong 02 Nov '16

02 Nov '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17063 -gerrit commit a217e34cf2f1e4f3a7264c900b5ba2938c9a0866 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Tue Oct 18 13:57:54 2016 -0700 soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 15 +++- .../intel/apollolake/bootblock/cache_as_ram_fsp.S | 98 ++++++++++++++++++++++ src/soc/intel/apollolake/exit_car_fsp.S | 45 ++++++++++ src/soc/intel/apollolake/include/soc/postcar.h | 26 ++++++ src/soc/intel/apollolake/postcar.c | 34 ++++++++ 5 files changed, 216 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4f867e1..b4a79f0 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += gpio.c @@ -22,6 +21,12 @@ bootblock-y += spi.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ifeq ($(CONFIG_FSP_CAR),y) +bootblock-y += bootblock/cache_as_ram_fsp.S +else +bootblock-y += bootblock/cache_as_ram.S +endif + romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c @@ -75,13 +80,19 @@ ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c -postcar-y += exit_car.S postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +ifeq ($(CONFIG_FSP_CAR),y) +postcar-y += exit_car_fsp.S +postcar-y += postcar.c +else +postcar-y += exit_car.S +endif + verstage-y += car.c verstage-y += i2c_early.c verstage-y += heci.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S new file mode 100644 index 0000000..1fad8cb --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/cpu.h> + +#include <../../../arch/x86/walkcbfs.S> + +#define FSP_HDR_OFFSET 0x94 + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add FSP_HDR_OFFSET, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntryOffset */ + add 0x1c(%ebx), %eax /* add the FSP ImageBase */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + nop + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0 /* Microcode Location */ + .long 0 /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_IBBL_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_IBBL_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "blobs/fspt.bin\x00" diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/apollolake/exit_car_fsp.S new file mode 100755 index 0000000..4e3011c --- /dev/null +++ b/src/soc/intel/apollolake/exit_car_fsp.S @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +#include <soc/cpu.h> + +/* + * This path for CAR teardown is taken when CONFIG_FSP_CAR is employed. + * This version of chipset_teardown_car sets up the stack, then bypasses + * the rest of arch/x86/exit_car.S and calls main() itself instead of + * returning to _start. In main(), the TempRamExit FSP API is called + * to tear down the CAR and set up caching as seen in the table below but + * can be overwritten after the API call. More info can be found in the + * Apollo Lake FSP Integration Guide included with the FSP binary. + * + * TempRamExit MTRR Settings: + * 0x00000000 - 0x0009FFFF | Write Back + * 0x000C0000 - Top of Low Memory | Write Back + * 0xFF800000 - 0xFFFFFFFF Flash Reg | Write Protect + * 0x100000000 - Top of High Memory | Write Back + */ + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov $CONFIG_RAMTOP, %esp + + /* Call C code */ + call main diff --git a/src/soc/intel/apollolake/include/soc/postcar.h b/src/soc/intel/apollolake/include/soc/postcar.h new file mode 100644 index 0000000..7e31def --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/postcar.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_POSTCAR_H_ +#define _SOC_APOLLOLAKE_POSTCAR_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +void post_car_main(void); + +#endif /* _SOC_APOLLOLAKE_POSTCAR_H_ */ diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c new file mode 100644 index 0000000..0b0e4ca --- /dev/null +++ b/src/soc/intel/apollolake/postcar.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <string.h> +#include <cbmem.h> +#include <arch/cpu.h> +#include <arch/stages.h> +#include <fsp/util.h> +#include <soc/postcar.h> +#include <boot_device.h> + +void post_car_main(void) +{ + temp_ram_exit(); + + /* Recover cbmem so infrastruture using it is functional. */ + cbmem_initialize(); + + copy_and_run(); +}

1 0

Patch set updated for coreboot: soc/intel/apollolake: add Multiple FMAP build
by Brenton Dong 02 Nov '16

02 Nov '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17064 -gerrit commit 227d4c32abf9906f6e74feba453dc32f10ed13c8 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:21:12 2016 -0700 soc/intel/apollolake: add Multiple FMAP build Multiple coreboot binaries with separate FMAPs and separate CBFSs allow coreboot to run separate stages from different regions (SRAM, CAR, Mem). When enabling Multiple FMAP, 3 Coreboot Images will be created. IBBL: Contains bootblock, CAR init (FSP-T) and hands off to IBBM. IBBM: Contains romstage, mem init (FSP-M) and postcar. OBB: Contains ramstage, silicon init (FSP-S), and the rest of the components in the original single coreboot.rom file. This is the same image as the original coreboot.rom minus the components moved to the IBBL and IBBM. Add functions to select which region cbfs files will be loaded from. Verified on Intel Leaf Hill CRB and confirmed that the coreboot builds 3 separate coreboot files which can be loaded and booted. Verified that other ApolloLake projects can build correctly with this option disabled. Change-Id: Iab3c353b65e1e0fc9d04fcee6a82a330927db41e Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- Makefile.inc | 47 ++++++++++ src/arch/x86/Makefile.inc | 2 + src/drivers/intel/fsp2_0/Makefile.inc | 5 + src/soc/intel/apollolake/Kconfig | 6 ++ src/soc/intel/apollolake/Makefile.inc | 4 + src/soc/intel/apollolake/bootblock/bootblock.c | 57 ++++++++++++ src/soc/intel/apollolake/chip.c | 9 +- src/soc/intel/apollolake/include/soc/bootregion.h | 28 ++++++ src/soc/intel/apollolake/include/soc/cse.h | 30 ++++++ src/soc/intel/apollolake/include/soc/mmio.h | 35 +++++++ src/soc/intel/apollolake/mmap_boot.c | 2 + src/soc/intel/apollolake/mmap_boot_cse.c | 53 +++++++++++ src/soc/intel/apollolake/postcar.c | 10 ++ src/soc/intel/apollolake/romstage.c | 108 ++++++++++++++++++++++ 14 files changed, 395 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 127f372..9e25883 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -826,11 +826,13 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) ifeq ($(CONFIG_ARCH_X86),y) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) $(CBFSTOOL) $@.tmp add \ -f $(objcbfs)/bootblock.bin \ -n bootblock \ -t bootblock \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) +endif # ifeq ($(CONFIG_MULTIPLE_FMAP),y) else # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ @@ -865,6 +867,49 @@ $(REFCODE_BLOB): $(RMODTOOL) $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ endif + +ifeq ($(CONFIG_MULTIPLE_FMAP),y) + +.PHONY:$(obj)/coreboot_ibbl.rom +$(obj)/coreboot_ibbl.rom: $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(obj)/ibbl_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbl_fmap.fmap -r $(shell cat $(obj)/ibbl_fmap.desc) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_T_FILE)) \ + -n blobs/fspt.bin -t fsp -y -b 0xC0 + mv $@.tmp $@ + @printf "\ncoreboot IBBL image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +.PHONY:$(obj)/coreboot_ibbm.rom +$(obj)/coreboot_ibbm.rom: $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(objcbfs)/romstage.elf \ + $(objcbfs)/postcar.elf \ + $(obj)/ibbm_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbm_fmap.fmap -r $(shell cat $(obj)/ibbm_fmap.desc) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/romstage.elf \ + -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ + $(CBFSTOOL_PRE_OPTS) -b 0 + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_M_FILE)) \ + -n blobs/fspm.bin -t fsp -y + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/postcar.elf \ + -n $(CONFIG_CBFS_PREFIX)/postcar + mv $@.tmp $@ + @printf "\ncoreboot IBBM image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +coreboot: $(obj)/coreboot_ibbl.rom $(obj)/coreboot_ibbm.rom + +endif # ifneq ($(CONFIG_MULTIPLE_FMAP),y) + $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty @@ -892,6 +937,7 @@ endif @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage-type := stage @@ -924,6 +970,7 @@ endif # CONFIG_NO_FIXED_XIP_ROM_SIZE endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 +endif # CONFIG_MULTIPLE_FMAP cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 782ca63..fc7eb5c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -300,10 +300,12 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ # Add postcar to CBFS +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage $(CONFIG_CBFS_PREFIX)/postcar-compression := none +endif #CONFIG_MULTIPLE_FMAP ############################################################################### # ramstage diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index d222e4c..d06e99c 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -46,6 +46,8 @@ CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +ifneq ($(CONFIG_MULTIPLE_FMAP),y) + ifeq ($(CONFIG_FSP_CAR),y) cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_T_CBFS) $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) @@ -55,6 +57,9 @@ endif # CONFIG_FSP_CAR cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp + +endif #CONFIG_MULTIPLE_FMAP + ifeq ($(CONFIG_FSP_M_XIP),y) $(CONFIG_FSP_M_CBFS)-options := --xip endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 6c178c3..eeba42a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -81,6 +81,12 @@ config TPM_ON_FAST_SPI TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. +config MULTIPLE_FMAP + depends on FSP_CAR + bool + help + Enable build with mulitple coreboot images and each will has its own fmap. + config SOC_INTEL_COMMON_RESET bool default y diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b4a79f0..fdbc903 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -15,6 +15,7 @@ bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += itss.c bootblock-y += lpc_lib.c +bootblock-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c bootblock-y += mmap_boot.c bootblock-y += pmutil.c bootblock-y += spi.c @@ -37,6 +38,7 @@ romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c romstage-y += memmap.c romstage-y += meminit.c +romstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c romstage-y += mmap_boot.c romstage-y += tsc_freq.c romstage-y += pmutil.c @@ -65,6 +67,7 @@ ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += lpc.c ramstage-y += lpc_lib.c ramstage-y += memmap.c +ramstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c ramstage-y += mmap_boot.c ramstage-y += p2sb.c ramstage-y += uart.c @@ -81,6 +84,7 @@ ramstage-y += spi.c ramstage-y += xhci.c postcar-y += memmap.c +postcar-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 28a9128..22a4d44 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -14,6 +14,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include <string.h> #include <arch/cpu.h> #include <bootblock_common.h> #include <cpu/x86/mtrr.h> @@ -31,6 +32,53 @@ #include <spi-generic.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm0(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_num; + uint32_t state; + msr_t msr; + + /* Request data from CSE */ + host_to_cse = (ibbm_size << 4) | 0xC0000000; + CSE_HOST2CSE = host_to_cse; + + /* Wait for response */ + do { + cse_to_host = CSE_CSE2HOST; + chunk_num = (cse_to_host >> 28) & 3; + } while (!chunk_num); + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* + * The 1st 128K should have been loaded into SRAM now + * However, since the top 32K IBBL is still cached, we can only read + * (128-32)K at this moment. The remaining will be read in romstage. + */ + memcpy((void *)ibbm_base, (void *)(~CSE_IBB_SRAM_SIZE + 1), + CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE); + + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + the temporary memory */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + static const struct pad_config tpm_spi_configs[] = { PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ }; @@ -92,6 +140,15 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp) enable_cmos_upper_bank(); +#if CONFIG_MULTIPLE_FMAP + /* Loading IBBM into CAR */ + load_ibbm0(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE, CONFIG_IBBM_ROM_SIZE); + + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); +#endif //CONFIG_MULTIPLE_FMAP + /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(base_timestamp); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d722992..0a184eb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -35,9 +35,12 @@ #include <soc/pm.h> #include <soc/p2sb.h> #include <soc/northbridge.h> - #include "chip.h" +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif /* CONFIG_MULTIPLE_FMAP */ + static void *vbt; static struct region_device vbt_rdev; @@ -267,6 +270,10 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_OBB); +#endif //CONFIG_MULTIPLE_FMAP + fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ diff --git a/src/soc/intel/apollolake/include/soc/bootregion.h b/src/soc/intel/apollolake/include/soc/bootregion.h new file mode 100644 index 0000000..dde562a --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootregion.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_BOOT_RGN_H_ +#define _SOC_LEAFHILL_BOOT_RGN_H_ + +#define BOOT_REGION_IBBL 0 +#define BOOT_REGION_IBBM 1 +#define BOOT_REGION_OBB 2 + +/* Set current active boot region */ +void set_boot_region(int region_id); + +#endif /* _SOC_LEAFHILL_BOOT_RGN_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/cse.h b/src/soc/intel/apollolake/include/soc/cse.h new file mode 100644 index 0000000..ed2b136 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cse.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_CSE_H_ +#define _SOC_LEAFHILL_CSE_H_ + +#define HOST2CSE 0x70 +#define CSE2HOST 0x60 +#define CSE_IBB_SRAM_SIZE 0x20000 + +#define CSE_CFG_BASE (CONFIG_MMCONF_BASE_ADDRESS + 0x78000) +#define CSE_VIDDID (*(volatile int32_t *)CSE_CFG_BASE) +#define CSE_HOST2CSE (*(volatile int32_t *)(CSE_CFG_BASE + HOST2CSE)) +#define CSE_CSE2HOST (*(volatile int32_t *)(CSE_CFG_BASE + CSE2HOST)) + +#endif /* _SOC_LEAFHILL_CSE_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/mmio.h b/src/soc/intel/apollolake/include/soc/mmio.h new file mode 100644 index 0000000..674e071 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/mmio.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMIO_H_ +#define _SOC_MMIO_H_ + + +#define MmioRead32(x) (*(volatile uint32_t *)(unsigned int)(x)) +#define MmioWrite32(x, y) (*(volatile uint32_t *)(unsigned int)(x) = y) +#define MmioRead16(x) (*(volatile uint16_t *)(unsigned int)(x)) +#define MmioWrite16(x, y) (*(volatile uint16_t *)(unsigned int)(x) = y) +#define MmioRead8(x) (*(volatile uint8_t *)(unsigned int)(x)) +#define MmioWrite8(x, y) (*(volatile uint8_t *)(unsigned int)(x) = y) + +#define PCIE_MMIO(Bus, Device, Function, Register) \ + ((unsigned int)CONFIG_MMCONF_BASE_ADDRESS + \ + (unsigned int)(Bus << 20) + \ + (unsigned int)(Device << 15) + \ + (unsigned int)(Function << 12) + \ + (unsigned int)(Register) \ + ) + +#endif diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index bf2e5b9..994f7b8 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -113,6 +113,7 @@ static void bios_mmap_init(void) car_set_var(bios_size, size); } +#if !CONFIG_MULTIPLE_FMAP const struct region_device *boot_device_ro(void) { bios_mmap_init(); @@ -122,6 +123,7 @@ const struct region_device *boot_device_ro(void) return &real_dev_ptr->rdev; } +#endif //CONFIG_MULTIPLE_FMAP static int iafw_boot_region_properties(struct cbfs_props *props) { diff --git a/src/soc/intel/apollolake/mmap_boot_cse.c b/src/soc/intel/apollolake/mmap_boot_cse.c new file mode 100644 index 0000000..d5b4526 --- /dev/null +++ b/src/soc/intel/apollolake/mmap_boot_cse.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> +#include <soc/bootregion.h> +#include <soc/intel/common/nvm.h> +#include <arch/early_variables.h> + +/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ +#define rom_base(x) (void *)(uintptr_t)(-(int32_t)(x)) +#define IBBL_ROM_BASE rom_base(CONFIG_IBBL_ROM_SIZE) +#define IBBM_ROM_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ + - CONFIG_IBBM_ROM_SIZE) + +static int curr_boot_region CAR_GLOBAL; + +static const struct mem_region_device boot_dev[] = { + MEM_REGION_DEV_RO_INIT(IBBL_ROM_BASE, CONFIG_IBBL_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(IBBM_ROM_BASE, CONFIG_IBBM_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(CONFIG_RAMTOP, CONFIG_ROM_SIZE) +}; + +#if CONFIG_MULTIPLE_FMAP +const struct region_device *boot_device_ro(void) +{ + return &boot_dev[car_get_var(curr_boot_region)].rdev; +} +#endif //CONFIG_MULTIPLE_FMAP + +void set_boot_region(int rgn_idx) +{ + if (rgn_idx < sizeof(boot_dev)/sizeof(boot_dev[0])) + car_set_var(curr_boot_region, rgn_idx); +} diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c index 0b0e4ca..7c24fe9 100644 --- a/src/soc/intel/apollolake/postcar.c +++ b/src/soc/intel/apollolake/postcar.c @@ -23,9 +23,19 @@ #include <soc/postcar.h> #include <boot_device.h> +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif + void post_car_main(void) { +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_IBBM); + temp_ram_exit(); + set_boot_region(BOOT_REGION_OBB); +#else temp_ram_exit(); +#endif /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1f6a38f..69d7273 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -41,6 +41,12 @@ #include <string.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <cpu/x86/msr.h> +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + static struct chipset_power_state power_state CAR_GLOBAL; /* High Performance Event Timer Configuration */ @@ -100,6 +106,92 @@ static void migrate_power_state(int is_recovery) } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm1(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t state; + uint32_t size; + uint8_t ring_idx; + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_idx; + uint32_t chunk_size; + uint32_t chunk_num; + uint32_t ibb_remaining; + uint8_t *src; + uint8_t *dst; + uint8_t *ptr; + msr_t msr; + + /* Set IBBL cache to UC */ + msr = rdmsr(0x202); + msr.lo &= ~0x0f; + wrmsr(0x202, msr); + + /* Init variables */ + size = CONFIG_IBBL_ROM_SIZE; + dst = (uint8_t *)ibbm_base; + src = (uint8_t *)(~CONFIG_IBBL_ROM_SIZE + 1); + memcpy(dst, src, size); + + cse_to_host = CSE_CSE2HOST; + host_to_cse = CSE_HOST2CSE; + chunk_num = (cse_to_host >> 28) & 3; + if (chunk_num == 3) + chunk_num = 4; + chunk_size = CSE_IBB_SRAM_SIZE / chunk_num; + chunk_idx = chunk_num; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~0x0f) | (cse_to_host & 0x0f); + CSE_HOST2CSE = host_to_cse; + + ibb_remaining = ibbm_size - size; + while (ibb_remaining > 0) { + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* Calculate ring index */ + ring_idx = (uint8_t)(chunk_idx % chunk_num); + if (state & (1 << ring_idx)) { + /* Calculate source and dest. address in ring buffer */ + src += chunk_size; + dst += chunk_size; + if (src == 0) + src = (uint8_t *)(~CSE_IBB_SRAM_SIZE + 1); + if (ibb_remaining < chunk_size) + size = ibb_remaining; + else + size = chunk_size; + + /* Move data from SRAM into temporary memory */ + memcpy(dst, src, size); + ibb_remaining -= size; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~(1 << ring_idx)) | + (cse_to_host & (1 << ring_idx)); + CSE_HOST2CSE = host_to_cse; + + chunk_idx++; + } + } + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + * the temporary memory + */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -109,6 +201,10 @@ asmlinkage void car_stage_entry(void) void *smm_base; size_t smm_size; uintptr_t tseg_base; +#if CONFIG_MULTIPLE_FMAP + uint32_t ibbm_base; + uint32_t ibbm_loaded; +#endif //CONFIG_MULTIPLE_FMAP timestamp_add_now(TS_START_ROMSTAGE); @@ -117,6 +213,18 @@ asmlinkage void car_stage_entry(void) console_init(); +#if CONFIG_MULTIPLE_FMAP + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); + + /* load the remaining IBBM */ + ibbm_loaded = CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE; + ibbm_base = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE; + load_ibbm1(ibbm_base + ibbm_loaded, + CONFIG_IBBM_ROM_SIZE - ibbm_loaded); +#endif //CONFIG_MULTIPLE_FMAP + s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1*KiB))

1 0

Patch set updated for coreboot: mainboard/intel/leafhill: add LeafHill CRB (Apollo Lake)
by Brenton Dong 02 Nov '16

02 Nov '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17065 -gerrit commit 6bca6f7b576c529fd469c95267522a182e016d6c Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:40:39 2016 -0700 mainboard/intel/leafhill: add LeafHill CRB (Apollo Lake) Leaf Hill CRB is an Intel Customer Reference Board with ApolloLake silicon and LPDDR4 Down. Verified on Intel Leaf Hill CRB and confirmed to boot using Intel UEFI Payload and Yocto Linux. Change-Id: Ieeed6a7e5e9b6f02e4dd7e15cbcb58894c3c4eac Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/mainboard/intel/leafhill/Kconfig | 45 ++++++++++ src/mainboard/intel/leafhill/Kconfig.name | 3 + src/mainboard/intel/leafhill/Makefile.inc | 64 ++++++++++++++ src/mainboard/intel/leafhill/acpi_tables.c | 14 +++ src/mainboard/intel/leafhill/board.h | 36 ++++++++ src/mainboard/intel/leafhill/board_info.txt | 6 ++ src/mainboard/intel/leafhill/brd_gpio.h | 65 ++++++++++++++ src/mainboard/intel/leafhill/devicetree.cb | 56 ++++++++++++ src/mainboard/intel/leafhill/dsdt.asl | 37 ++++++++ src/mainboard/intel/leafhill/ibb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/obb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/romstage.c | 128 ++++++++++++++++++++++++++++ 12 files changed, 466 insertions(+) diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig new file mode 100644 index 0000000..462e458 --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_LEAFHILL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default intel/leafhill + +config MAINBOARD_PART_NUMBER + string + default "LeafHill" + +config MAINBOARD_VENDOR + string + default "Intel" + +config IFD_BIOS_END + hex + default 0x6FF000 + +config IFD_BIOS_START + hex + default 0x1000 + +config IBBL_ROM_SIZE + hex + default 0x10000 + +config IBBM_ROM_SIZE + hex + default 0x62000 + +config OBB_ROM_SIZE + hex + default 0x100000 + +config OBB_ROM_BASE + hex + default 0x200000 + +endif diff --git a/src/mainboard/intel/leafhill/Kconfig.name b/src/mainboard/intel/leafhill/Kconfig.name new file mode 100644 index 0000000..72664cd --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_INTEL_LEAFHILL + bool "LeafHill" + diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc new file mode 100644 index 0000000..271b20a --- /dev/null +++ b/src/mainboard/intel/leafhill/Makefile.inc @@ -0,0 +1,64 @@ +#Nothing here yet + +MAINBOARD_PATH := $(src)/mainboard/$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) +IBB_FLASHMAP := $(MAINBOARD_PATH)/ibb_fmap.fmd + +IBBL_FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_IBBL_ROM_SIZE)) +IBBL_FMAP_ROM_SIZE := $(CONFIG_IBBL_ROM_SIZE) +IBBL_FMAP_BIOS_BASE := 0 +IBBL_FMAP_BIOS_SIZE := $(IBBL_FMAP_ROM_SIZE) +IBBL_FMAP_FMAP_BASE := 0 +IBBL_FMAP_FMAP_SIZE := 0x100 +IBBL_FMAP_CBFS_BASE := $(IBBL_FMAP_FMAP_SIZE) +IBBL_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBL_FMAP_BIOS_SIZE) $(IBBL_FMAP_FMAP_SIZE)) + +$(obj)/ibbl_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBL_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBL_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBL_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBL_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBL_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBL_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBL_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBL_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbl_fmap.fmap +$(obj)/ibbl_fmap_config.h: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.desc: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.fmap: $(obj)/ibbl_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h -R $(obj)/ibbl_fmap.desc $< $@ + + +IBBM_FMAP_CAR_TOP := $(call int-add, $(CONFIG_DCACHE_RAM_BASE) $(CONFIG_DCACHE_RAM_SIZE)) +IBBM_FMAP_ROM_ADDR := $(call int-subtract, $(IBBM_FMAP_CAR_TOP) $(CONFIG_IBBM_ROM_SIZE)) +IBBM_FMAP_ROM_SIZE := $(CONFIG_IBBM_ROM_SIZE) +IBBM_FMAP_BIOS_BASE := 0 +IBBM_FMAP_BIOS_SIZE := $(IBBM_FMAP_ROM_SIZE) +IBBM_FMAP_FMAP_BASE := 0 +IBBM_FMAP_FMAP_SIZE := 0x100 +IBBM_FMAP_CBFS_BASE := $(IBBM_FMAP_FMAP_SIZE) +IBBM_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBM_FMAP_BIOS_SIZE) $(IBBM_FMAP_FMAP_SIZE)) + +$(obj)/ibbm_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBM_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBM_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBM_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBM_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBM_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBM_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBM_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBM_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbm_fmap.fmap +$(obj)/ibbm_fmap_config.h: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.desc: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.fmap: $(obj)/ibbm_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h -R $(obj)/ibbm_fmap.desc $< $@ + +# brenton: changed this to headerromstage-y += brd_gpio.c diff --git a/src/mainboard/intel/leafhill/acpi_tables.c b/src/mainboard/intel/leafhill/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/intel/leafhill/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/intel/leafhill/board.h b/src/mainboard/intel/leafhill/board.h new file mode 100644 index 0000000..90e2a10 --- /dev/null +++ b/src/mainboard/intel/leafhill/board.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOARD_H_ +#define _SOC_BOARD_H_ + +typedef struct { + uint32_t VendorDeviceId; //Codec Vendor/Device ID + uint8_t RevisionId; //Coden Revision ID. 0xFF matches any rev + uint8_t SdiNo; //SDI number, 0xFF matches any SDI. + uint16_t DataDwords; //Number of data DWORDs following header + uint8_t FrontPanelSupport; + uint8_t Padding[3]; +} BL_HDA_VERB_TABLE_HEADER; + +typedef struct { + BL_HDA_VERB_TABLE_HEADER VerbTableHeader; + uint32_t VerbTableData[]; +} BL_HDAUDIO_VERB_TABLE; + +void config_board_gpio(void); + + +#endif diff --git a/src/mainboard/intel/leafhill/board_info.txt b/src/mainboard/intel/leafhill/board_info.txt new file mode 100644 index 0000000..eb95944 --- /dev/null +++ b/src/mainboard/intel/leafhill/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Apollolake RVP Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h new file mode 100644 index 0000000..3cd47a7 --- /dev/null +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/mmio.h> +#include <soc/gpio.h> +#include "board.h" + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb new file mode 100644 index 0000000..746aaf3 --- /dev/null +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -0,0 +1,56 @@ +chip soc/intel/apollolake + + register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 + register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot + register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl new file mode 100644 index 0000000..53a7b0f --- /dev/null +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> + +} diff --git a/src/mainboard/intel/leafhill/ibb_fmap.fmd b/src/mainboard/intel/leafhill/ibb_fmap.fmd new file mode 100644 index 0000000..06e905c --- /dev/null +++ b/src/mainboard/intel/leafhill/ibb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/src/mainboard/intel/leafhill/obb_fmap.fmd b/src/mainboard/intel/leafhill/obb_fmap.fmd new file mode 100644 index 0000000..d0d0720 --- /dev/null +++ b/src/mainboard/intel/leafhill/obb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@0x200000 0x100000 { + BIOS@0 0x100000 { + FMAP@0 0x100 + COREBOOT(CBFS)@0x100 1048320 + } +} \ No newline at end of file diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c new file mode 100644 index 0000000..256570a --- /dev/null +++ b/src/mainboard/intel/leafhill/romstage.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/romstage.h> +#include <console/console.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "board.h" +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* DRAM Config settings */ + mupd->FspmConfig.Package = 0x1; + mupd->FspmConfig.Profile = 0xB; + mupd->FspmConfig.MemoryDown = 0x1; + mupd->FspmConfig.DDR3LPageSize = 0x0; + mupd->FspmConfig.DDR3LASR = 0x0; + mupd->FspmConfig.ScramblerSupport = 0x1; + mupd->FspmConfig.ChannelHashMask = 0x36; + mupd->FspmConfig.SliceHashMask = 0x9; + mupd->FspmConfig.InterleavedMode = 0x2; + mupd->FspmConfig.ChannelsSlicesEnable = 0x0; + mupd->FspmConfig.MinRefRate2xEnable = 0x0; + mupd->FspmConfig.DualRankSupportEnable = 0x1; + mupd->FspmConfig.RmtMode = 0x0; + mupd->FspmConfig.MemorySizeLimit = 0x1800; + mupd->FspmConfig.LowMemoryMaxValue = 0x0; + mupd->FspmConfig.DisableFastBoot = 0x0; + mupd->FspmConfig.HighMemoryMaxValue = 0x0; + mupd->FspmConfig.DIMM0SPDAddress = 0x0; + mupd->FspmConfig.DIMM1SPDAddress = 0x0; + mupd->FspmConfig.Ch0_RankEnable = 0x3; + mupd->FspmConfig.Ch0_DeviceWidth = 0x1; + mupd->FspmConfig.Ch0_DramDensity = 0x2; + mupd->FspmConfig.Ch0_Option = 0x3; + mupd->FspmConfig.Ch0_OdtConfig = 0x0; + mupd->FspmConfig.Ch0_TristateClk1 = 0x0; + mupd->FspmConfig.Ch0_Mode2N = 0x0; + mupd->FspmConfig.Ch0_OdtLevels = 0x0; + mupd->FspmConfig.Ch1_RankEnable = 0x3; + mupd->FspmConfig.Ch1_DeviceWidth = 0x1; + mupd->FspmConfig.Ch1_DramDensity = 0x2; + mupd->FspmConfig.Ch1_Option = 0x3; + mupd->FspmConfig.Ch1_OdtConfig = 0x0; + mupd->FspmConfig.Ch1_TristateClk1 = 0x0; + mupd->FspmConfig.Ch1_Mode2N = 0x0; + mupd->FspmConfig.Ch1_OdtLevels = 0x0; + mupd->FspmConfig.Ch2_RankEnable = 0x3; + mupd->FspmConfig.Ch2_DeviceWidth = 0x1; + mupd->FspmConfig.Ch2_DramDensity = 0x2; + mupd->FspmConfig.Ch2_Option = 0x3; + mupd->FspmConfig.Ch2_OdtConfig = 0x0; + mupd->FspmConfig.Ch2_TristateClk1 = 0x0; + mupd->FspmConfig.Ch2_Mode2N = 0x0; + mupd->FspmConfig.Ch2_OdtLevels = 0x0; + mupd->FspmConfig.Ch3_RankEnable = 0x3; + mupd->FspmConfig.Ch3_DeviceWidth = 0x1; + mupd->FspmConfig.Ch3_DramDensity = 0x2; + mupd->FspmConfig.Ch3_Option = 0x3; + mupd->FspmConfig.Ch3_OdtConfig = 0x0; + mupd->FspmConfig.Ch3_TristateClk1 = 0x0; + mupd->FspmConfig.Ch3_Mode2N = 0x0; + mupd->FspmConfig.Ch3_OdtLevels = 0x0; + mupd->FspmConfig.RmtCheckRun = 0x0; + mupd->FspmConfig.MrcDataSaving = 0x1; + mupd->FspmConfig.MrcFastBoot = 0x1; + + memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + mupd->FspmConfig.MsgLevelMask = 0x0; + + /* Request FSP to load the coreboot primary CBFS */ + mupd->FspmConfig.OemLoadingBase = CONFIG_OBB_ROM_BASE; + strcpy((char *)mupd->FspmConfig.OemFileName, "OBB"); + +}

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New patch to review for coreboot: soc/intel: Add MSR to support enabling turbo frequency
by Shaunak Saha 02 Nov '16

02 Nov '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17211 -gerrit commit 66b7220e0e45510b7a70bfb2dd6eadf504266343 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Wed Nov 2 10:52:23 2016 -0700 soc/intel: Add MSR to support enabling turbo frequency This patch adds definition for IA32_PERF_CTL and FREQ_LIMIT_RATIO MSR's. FREQ_LIMIT_RATIO register allows determines the ratio limits to be used to limit frequency. PERF_CTL is Performance Control MSR. BIOS makes request for a new Performance state (P-state) by writing this MSR. BUG=chrome-os-partner:58158 BRANCH=None Change-Id: I50a792accbaab1bff313fd00574814d7dbba1f6b Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/include/cpu/intel/turbo.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 6626cb1..36c8eab 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -23,9 +23,13 @@ #define MSR_IA32_MISC_ENABLES 0x1a0 /* Disable the Monitor Mwait FSM feature */ #define MONITOR_MWAIT_DIS_MASK 0x40000 +#define APL_BURST_MODE_DISABLE 0x0000004000000000ULL #define H_MISC_DISABLE_TURBO (1 << 6) +#define IA32_PERL_CTL 0x199 +#define FREQ_LIMIT_RATIO 0x1AD + enum { TURBO_UNKNOWN, TURBO_UNAVAILABLE,

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coreboot-gerrit November 2016