coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: vendorcode/amd/f14: Fix ignored argument in IDS_HDT_CONSOLE
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 4291e8b6ca0cc62a2d1945422b9eb3a2c9318dac Author: Łukasz Dobrowolski <lukasz(a)dobrowolski.io> Date: Tue Oct 25 00:29:37 2016 +0200 vendorcode/amd/f14: Fix ignored argument in IDS_HDT_CONSOLE String format required two arguments however those were packaged in ( , ) so the left one was ignored. Change-Id: I59698319d5ff4215f296356147b4e22229cc9245 Signed-off-by: Łukasz Dobrowolski <lukasz(a)dobrowolski.io> Reviewed-on: https://review.coreboot.org/17118 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> See https://review.coreboot.org/17118 for details. -gerrit

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Patch merged into coreboot/master: riscv: Add a bandaid for the new toolchain
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 571c2302525206715c2f12bc14fab931e8cdf757 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Fri Oct 28 15:08:59 2016 -0700 riscv: Add a bandaid for the new toolchain After I did a new toolchain build, I found the the mhartid register value is wrong for Spike. The docs seem to agree with Spike, not the code the toolchain produces? Until such time as the bitstreams and toolchain can find a way to agree, just hardcode it. We've been playing this game for two years now so this is hardly a new approach. This is intentionally ugly because we really need the toolchains and emulators and bitstreams to sync up, and that's not happening yet. Lowrisc allegedly implements the v1.9 spec but it's PTEs are clearly 1.7. Once it all settles down we can just use constants supplied by the toolchain. I hope the syncup will have happened by the workshop in November. This gets spike running again. Change-Id: If259bcb6b6320ef01ed29a20ce3d2dcfd0bc7326 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> Reviewed-on: https://review.coreboot.org/17183 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> See https://review.coreboot.org/17183 for details. -gerrit

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Patch merged into coreboot/master: amd/hudson: Add PSP2 build for combo BIOS
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit c98629cd676b41938978f3e108d54755e3c5935b Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 20:50:25 2016 -0600 amd/hudson: Add PSP2 build for combo BIOS The Stoney processor can use multiple directory structures. Turn this feature on in the makefile. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Tested-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit a3334632fd53c07a046c9b23161f6ee67e5cb16e) Change-Id: I40a9ef2e6bed51bc339d3f9ae7c6f316192c4a78 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17149 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Zheng Bao <fishbaozi(a)gmail.com> See https://review.coreboot.org/17149 for details. -gerrit

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Patch merged into coreboot/master: util/amdfwtool: Increase space used for structures
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 350630aefbcebee7edb9941fe2ba1846fca8b793 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 22:55:54 2016 -0600 util/amdfwtool: Increase space used for structures Double the space for psp2dir to 0x200. Based on advice from AMD, increase the region containing the signature to 4K. Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit e03a9402711c3a210816d0aa32865491a0523639) Change-Id: If60132f913928bab0c2fe4aacedf342080929599 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17148 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Zheng Bao <fishbaozi(a)gmail.com> See https://review.coreboot.org/17148 for details. -gerrit

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Patch merged into coreboot/master: util/amdfwtool: Add PSP2 options to optstring
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 90099b68036f89991af7d31f478e9c6b08c7ac93 Author: Marc Jones <marcj303(a)gmail.com> Date: Tue Sep 20 21:05:45 2016 -0600 util/amdfwtool: Add PSP2 options to optstring Original-Signed-off-by: Marc Jones <marcj303(a)gmail.com> Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit 482b65c219b932fd374f2ac469a023db219a66de) Change-Id: I0a24a0aa4c7d9f4a8cc3ee9b7da60ea7704e6f17 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17147 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> Reviewed-by: Zheng Bao <fishbaozi(a)gmail.com> See https://review.coreboot.org/17147 for details. -gerrit

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Patch merged into coreboot/master: util/amdfwtool: Fix duplicate long option name
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit e7d892c651c365b566ce7406ace05f9059df48fa Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 14:49:41 2016 -0600 util/amdfwtool: Fix duplicate long option name Make the PSP2 smufirmware2 name unique so the command-line option gets picked up. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: <marcj303(a)gmail.com> (cherry picked from commit 98cf3880797f72aeb7169c3f8718a10092af9624) Change-Id: I5430cf8b81fb03c95e6ee9d7e53455e6224256ff Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17146 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17146 for details. -gerrit

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Patch merged into coreboot/master: northbridge/amd: Modify 00670F00 chip.h to match DCT
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit c56a558c18c7599d37a0f119b0a51c46cf274c32 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 09:12:27 2016 -0600 northbridge/amd: Modify 00670F00 chip.h to match DCT The Stoney device supports only a single channel of DRAM with two DIMMs. Correct the dimmensions of the SPD lookup array. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: <marcj303(a)gmail.com> (cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8) Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209 Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17145 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/17145 for details. -gerrit

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Patch set updated for coreboot: northbridge/amd: Modify 00670F00 chip.h to match DCT
by Martin Roth 02 Nov '16

02 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17145 -gerrit commit d64c0a7d770212ef829d6599dd3eadfdd6fa62fa Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Sat Oct 8 09:12:27 2016 -0600 northbridge/amd: Modify 00670F00 chip.h to match DCT The Stoney device supports only a single channel of DRAM with two DIMMs. Correct the dimmensions of the SPD lookup array. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: <marcj303(a)gmail.com> (cherry picked from commit 54a5e4a7092b77cca90894e86387f719fa3aa2c8) Change-Id: Ib776133e411d483bb5b7e3c070199befc631d209 Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- src/northbridge/amd/pi/00670F00/chip.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/northbridge/amd/pi/00670F00/chip.h b/src/northbridge/amd/pi/00670F00/chip.h index 917bc65..d11d7a4 100644 --- a/src/northbridge/amd/pi/00670F00/chip.h +++ b/src/northbridge/amd/pi/00670F00/chip.h @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -18,7 +19,7 @@ struct northbridge_amd_pi_00670F00_config { - u8 spdAddrLookup[2][2][4]; + u8 spdAddrLookup[1][1][2]; }; #endif

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Patch merged into coreboot/master: northbridge/amd: Update 00670F00 asl for reduced hardware
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit ade7800ec62ffed51efaaf46dad6cd2cf1148725 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Oct 14 17:57:08 2016 -0400 northbridge/amd: Update 00670F00 asl for reduced hardware Remove the language associated with the Carrizo Gfx PCIe bridges. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit cc32b09b0f0137c11d82f35274ca33e013f73748) Change-Id: I8b67a646f98667d500fcee5da8389c10483488da Signed-off-by: Marc Jones <marcj303(a)gmail.com> Reviewed-on: https://review.coreboot.org/17144 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See https://review.coreboot.org/17144 for details. -gerrit

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Patch set updated for coreboot: northbridge/amd: Update 00670F00 asl for reduced hardware
by Martin Roth 02 Nov '16

02 Nov '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17144 -gerrit commit 78a46637c44c647ef8575d7ae21277c4959faad4 Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Fri Oct 14 17:57:08 2016 -0400 northbridge/amd: Update 00670F00 asl for reduced hardware Remove the language associated with the Carrizo Gfx PCIe bridges. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> (cherry picked from commit cc32b09b0f0137c11d82f35274ca33e013f73748) Change-Id: I8b67a646f98667d500fcee5da8389c10483488da Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- .../amd/pi/00670F00/acpi/northbridge.asl | 36 +--------------------- 1 file changed, 1 insertion(+), 35 deletions(-) diff --git a/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl index cde5182..e5cf34f 100644 --- a/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl +++ b/src/northbridge/amd/pi/00670F00/acpi/northbridge.asl @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2013 Sage Electronic Engineering, LLC + * Copyright (C) 2016 Advanced Micro Devices, Inc. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -94,38 +95,3 @@ Device(PBR8) { Return (PS8) /* PIC Mode */ } /* end _PRT */ } /* end PBR8 */ - -/* GFX 1 */ -Device(PBR9) { - Name(_ADR, 0x00030002) -} /* end PBR8 */ - -/* GFX 2 */ -Device(PBRA) { - Name(_ADR, 0x00030003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSA) } /* APIC mode */ - Return (PSA) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 3 */ -Device(PBRB) { - Name(_ADR, 0x00030004) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSB) } /* APIC mode */ - Return (PSB) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 4 */ -Device(PBRC) { - Name(_ADR, 0x00030005) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD){ Return(APSC) } /* APIC mode */ - Return (PSC) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */

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coreboot-gerrit November 2016