coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: src/mainboard/*/*/spd.h: Correct SPD_DRAM_LPDDR3 type
by HAOUAS Elyes 02 Nov '16

02 Nov '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17206 -gerrit commit 578b9141d5b14780fc5082403bf9ee4f474b22b7 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Nov 2 08:26:37 2016 +0100 src/mainboard/*/*/spd.h: Correct SPD_DRAM_LPDDR3 type Regarding JEDEC Standard No. 21-C, Annex M: Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 1 Annex M: Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 2 (page# 5) Key Byte / DRAM Device Type for LPDDR3 is 0x0f Change-Id: Ic90a1381900b6f6a5b970a14f9490061b1303b5e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/google/auron/spd/spd.h | 2 +- src/mainboard/google/auron_paine/spd/spd.h | 2 +- src/mainboard/google/chell/spd/spd.h | 2 +- src/mainboard/google/eve/spd/spd.h | 2 +- src/mainboard/google/glados/spd/spd.h | 2 +- src/mainboard/google/lars/spd/spd.h | 2 +- src/mainboard/google/samus/spd/spd.h | 2 +- src/mainboard/intel/kunimitsu/spd/spd.h | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/auron/spd/spd.h b/src/mainboard/google/auron/spd/spd.h index cbb463f..44b1e45 100644 --- a/src/mainboard/google/auron/spd/spd.h +++ b/src/mainboard/google/auron/spd/spd.h @@ -20,7 +20,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/auron_paine/spd/spd.h b/src/mainboard/google/auron_paine/spd/spd.h index 09a48fd..7863f7d 100644 --- a/src/mainboard/google/auron_paine/spd/spd.h +++ b/src/mainboard/google/auron_paine/spd/spd.h @@ -20,7 +20,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/chell/spd/spd.h b/src/mainboard/google/chell/spd/spd.h index c8e7b33..6166064 100644 --- a/src/mainboard/google/chell/spd/spd.h +++ b/src/mainboard/google/chell/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h index 9c2b26b..182c4fd 100644 --- a/src/mainboard/google/eve/spd/spd.h +++ b/src/mainboard/google/eve/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h index c8e7b33..6166064 100644 --- a/src/mainboard/google/glados/spd/spd.h +++ b/src/mainboard/google/glados/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/lars/spd/spd.h b/src/mainboard/google/lars/spd/spd.h index d71487b..bb73716 100644 --- a/src/mainboard/google/lars/spd/spd.h +++ b/src/mainboard/google/lars/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index dbfd6a0..dbb0c7f 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -20,7 +20,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index f53c9ec..29d3735 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -25,7 +25,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7

1 0

New patch to review for coreboot: google/veyron*: change .ddrconfig from 14 to 3
by Patrick Georgi 02 Nov '16

02 Nov '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17210 -gerrit commit 0e0988b971e46234198bd6e3945d20e6532ffddf Author: ZhengShunQian <zhengsq(a)rock-chips.com> Date: Fri Oct 28 16:16:04 2016 +0800 google/veyron*: change .ddrconfig from 14 to 3 There are two configs, sdram-lpddr3-hynix-2GB.inc and sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14. Changing .ddrconfig from 14 to 3 improves performance especially on contiguous memory accesses. Comparing the .ddrconfig: - if .ddrconfig = 3, C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C--- - if .ddrconfig = 14, C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C--- where - R: indicates Row bits - B: indicates Bank bits - C: indicates Column bits - D: indicates Chip selects bits .ddrconfig = 3 has multiple banks switching which improves DDR timing. BUG=chrome-os-partner:57321 TEST=Boot from fievel and play video BRANCH=veyron Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4 Original-Signed-off-by: ZhengShunQian <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/404691 Original-Commit-Ready: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc | 2 +- .../google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 2 +- 12 files changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549..1c35c90 100644 --- a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01..c4ce972 100644 --- a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549..1c35c90 100644 --- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01..c4ce972 100644 --- a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549..1c35c90 100644 --- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01..c4ce972 100644 --- a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549..1c35c90 100644 --- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01..c4ce972 100644 --- a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 8573652..8ad3338 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -70,7 +70,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01..c4ce972 100644 --- a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc index 00dc549..1c35c90 100644 --- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-hynix-2GB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc index a4bfb01..c4ce972 100644 --- a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -69,7 +69,7 @@ }, .noc_timing = 0x20D266A4, .noc_activate = 0x5B6, - .ddrconfig = 14, + .ddrconfig = 3, .ddr_freq = 533*MHz, .dramtype = LPDDR3, .num_channels = 2,

1 0

New patch to review for coreboot: google/veyron*: add DDR configs for new samsung DDR
by Patrick Georgi 02 Nov '16

02 Nov '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17209 -gerrit commit adf83d0a1ea70f2f58698e0f9dbd585cc8a93ab0 Author: ZhengShunQian <zhengsq(a)rock-chips.com> Date: Fri Oct 28 15:58:51 2016 +0800 google/veyron*: add DDR configs for new samsung DDR Add the new samsung DDR configs for all veyron except veyron_rialto: * K4E6E304EB-EGCE, ramid = 0010, 4GB * K4E8E324EB-EGCF, ramid = 1100, 2GB BRANCH=veyron BUG=none TEST=boot fievel board Change-Id: I747aa86f8c93174651a28face63b3386e22b23b3 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 5f55462e71bd481eda85af3d582cfe5b9873cc9c Original-Change-Id: I19123634c994f685683323f7d85cc4d35814e2ab Original-Signed-off-by: ZhengShunQian <zhengsq(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345748 Original-Commit-Queue: Ren Kuo <ren.kuo(a)quantatw.com> Original-Reviewed-by: Philip Chen <philipchen(a)chromium.org> Original-(cherry-pick from cc990f27024255a326fd9fa9644deb28b01a31a7) Original-Reviewed-on: https://chromium-review.googlesource.com/404690 Original-Commit-Ready: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq(a)rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/veyron/sdram_configs.c | 4 +- .../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ++++++++++++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_brain/sdram_configs.c | 4 +- .../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ++++++++++++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_danger/sdram_configs.c | 4 +- .../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ++++++++++++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_emile/sdram_configs.c | 4 +- .../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ++++++++++++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_mickey/sdram_configs.c | 4 +- .../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ++++++++++++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ++++++++++++++++++++++ src/mainboard/google/veyron_romy/sdram_configs.c | 4 +- .../sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc | 78 ++++++++++++++++++++++ .../sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc | 78 ++++++++++++++++++++++ 18 files changed, 948 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/veyron/sdram_configs.c b/src/mainboard/google/veyron/sdram_configs.c index aaa0bf3..76e4f76 100644 --- a/src/mainboard/google/veyron/sdram_configs.c +++ b/src/mainboard/google/veyron/sdram_configs.c @@ -23,7 +23,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ @@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ #include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc new file mode 100644 index 0000000..a4bfb01 --- /dev/null +++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E8E324EB-EGCF chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc new file mode 100644 index 0000000..6b6df57 --- /dev/null +++ b/src/mainboard/google/veyron/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E6E304EB-EGCE chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_brain/sdram_configs.c b/src/mainboard/google/veyron_brain/sdram_configs.c index aaa0bf3..76e4f76 100644 --- a/src/mainboard/google/veyron_brain/sdram_configs.c +++ b/src/mainboard/google/veyron_brain/sdram_configs.c @@ -23,7 +23,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ @@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ #include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc new file mode 100644 index 0000000..a4bfb01 --- /dev/null +++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E8E324EB-EGCF chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc new file mode 100644 index 0000000..6b6df57 --- /dev/null +++ b/src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E6E304EB-EGCE chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_danger/sdram_configs.c b/src/mainboard/google/veyron_danger/sdram_configs.c index 8f53088..c7f2055 100644 --- a/src/mainboard/google/veyron_danger/sdram_configs.c +++ b/src/mainboard/google/veyron_danger/sdram_configs.c @@ -23,7 +23,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ @@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ #include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc new file mode 100644 index 0000000..a4bfb01 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E8E324EB-EGCF chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc new file mode 100644 index 0000000..6b6df57 --- /dev/null +++ b/src/mainboard/google/veyron_danger/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E6E304EB-EGCE chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_emile/sdram_configs.c b/src/mainboard/google/veyron_emile/sdram_configs.c index aaa0bf3..76e4f76 100644 --- a/src/mainboard/google/veyron_emile/sdram_configs.c +++ b/src/mainboard/google/veyron_emile/sdram_configs.c @@ -23,7 +23,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ @@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ #include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc new file mode 100644 index 0000000..a4bfb01 --- /dev/null +++ b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E8E324EB-EGCF chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc new file mode 100644 index 0000000..6b6df57 --- /dev/null +++ b/src/mainboard/google/veyron_emile/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E6E304EB-EGCE chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_configs.c b/src/mainboard/google/veyron_mickey/sdram_configs.c index aaa0bf3..76e4f76 100644 --- a/src/mainboard/google/veyron_mickey/sdram_configs.c +++ b/src/mainboard/google/veyron_mickey/sdram_configs.c @@ -23,7 +23,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ @@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ #include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc new file mode 100644 index 0000000..a4bfb01 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E8E324EB-EGCF chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc new file mode 100644 index 0000000..6b6df57 --- /dev/null +++ b/src/mainboard/google/veyron_mickey/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E6E304EB-EGCE chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_romy/sdram_configs.c b/src/mainboard/google/veyron_romy/sdram_configs.c index aaa0bf3..76e4f76 100644 --- a/src/mainboard/google/veyron_romy/sdram_configs.c +++ b/src/mainboard/google/veyron_romy/sdram_configs.c @@ -23,7 +23,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-samsung-2GB.inc" /* ram_code = 0000 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB.inc" /* ram_code = 0001 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 0010 */ +#include "sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc" /* ram_code = 0010 */ #include "sdram_inf/sdram-lpddr3-hynix-2GB-2ranks.inc" /* ram_code = 0011 */ #include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */ @@ -33,7 +33,7 @@ static struct rk3288_sdram_params sdram_configs[] = { #include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */ #include "sdram_inf/sdram-ddr3-nanya-2GB.inc" /* ram_code = 1010 */ #include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */ -#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */ +#include "sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc" /* ram_code = 1100 */ #include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */ #include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */ #include "sdram_inf/sdram-ddr3-hynix-4GB.inc" /* ram_code = 1111 */ diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc new file mode 100644 index 0000000..a4bfb01 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-2GB-24EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E8E324EB-EGCF chips */ + { + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x1, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 14, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 9, + .odt = 0, +}, diff --git a/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc new file mode 100644 index 0000000..6b6df57 --- /dev/null +++ b/src/mainboard/google/veyron_romy/sdram_inf/sdram-lpddr3-samsung-4GB-04EB.inc @@ -0,0 +1,78 @@ +{ + /* 2 Samsung K4E6E304EB-EGCE chips */ + { + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + }, + { + .rank = 0x2, + .col = 0xA, + .bk = 0x3, + .bw = 0x2, + .dbw = 0x2, + .row_3_4 = 0x0, + .cs0_row = 0xF, + .cs1_row = 0xF + } + }, + { + .togcnt1u = 0x215, + .tinit = 0xC8, + .trsth = 0x0, + .togcnt100n = 0x35, + .trefi = 0x26, + .tmrd = 0x2, + .trfc = 0x70, + .trp = 0x2000D, + .trtw = 0x6, + .tal = 0x0, + .tcl = 0x8, + .tcwl = 0x4, + .tras = 0x17, + .trc = 0x24, + .trcd = 0xD, + .trrd = 0x6, + .trtp = 0x4, + .twr = 0x8, + .twtr = 0x4, + .texsr = 0x76, + .txp = 0x4, + .txpdll = 0x0, + .tzqcs = 0x30, + .tzqcsi = 0x0, + .tdqs = 0x1, + .tcksre = 0x2, + .tcksrx = 0x2, + .tcke = 0x4, + .tmod = 0x0, + .trstl = 0x0, + .tzqcl = 0xC0, + .tmrr = 0x4, + .tckesr = 0x8, + .tdpd = 0x1F4 + }, + { + .dtpr0 = 0x48D7DD93, + .dtpr1 = 0x187008D8, + .dtpr2 = 0x121076, + .mr[0] = 0x0, + .mr[1] = 0xC3, + .mr[2] = 0x6, + .mr[3] = 0x1 + }, + .noc_timing = 0x20D266A4, + .noc_activate = 0x5B6, + .ddrconfig = 3, + .ddr_freq = 533*MHz, + .dramtype = LPDDR3, + .num_channels = 2, + .stride = 13, + .odt = 0, +},

1 0

New patch to review for coreboot: rockchip/rk3399: sdram.c: Fix msch ddrconfig register error
by Patrick Georgi 02 Nov '16

02 Nov '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17208 -gerrit commit 87b7efd757e50509dabca2244ca186c6d477135e Author: Lin Huang <hl(a)rock-chips.com> Date: Mon Oct 17 10:31:30 2016 +0800 rockchip/rk3399: sdram.c: Fix msch ddrconfig register error Fix msch ddrconfig register write error. Also make sure that the row number configured in msch is equal to the row number configured in the DDR controller. This would not affect systems with 4GB of memory, but is needed for 2GB configurations. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: Ic95b3371faec5b31c32b011c50e55e83d949e74d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: dfa43d3d44839d9685b6393157f51b646e9996de Original-Change-Id: I0c95378bf937a245b7cdc0583c5d2ed1347f2a3e Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399563 Original-Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/sdram.c | 14 +++++++++++--- 1 file changed, 11 insertions(+), 3 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 9ff1294..4ea31dd 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -153,6 +153,14 @@ static void set_memory_map(u32 channel, u32 *denali_pi = rk3399_ddr_pi[channel]->denali_pi; u32 cs_map; u32 reduc; + u32 row; + + if ((sdram_ch->ddrconfig < 2) || (sdram_ch->ddrconfig == 4)) + row = 16; + else if (sdram_ch->ddrconfig == 3) + row = 14; + else + row = 15; cs_map = (sdram_ch->rank > 1) ? 3 : 1; reduc = (sdram_ch->bw == 2) ? 0 : 1; @@ -160,7 +168,7 @@ static void set_memory_map(u32 channel, clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col)); clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24), ((3 - sdram_ch->bk) << 16) | - ((16 - sdram_ch->cs0_row) << 24)); + ((16 - row) << 24)); clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16), cs_map | (reduc << 16)); @@ -171,7 +179,7 @@ static void set_memory_map(u32 channel, /* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */ clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24), ((3 - sdram_ch->bk) << 16) | - ((16 - sdram_ch->cs0_row) << 24)); + ((16 - row) << 24)); /* PI_41 PI_CS_MAP:RW:24:4 */ clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24); if ((sdram_ch->rank == 1) && (sdram_params->dramtype == DDR3)) @@ -869,7 +877,7 @@ static void set_ddrconfig(const struct rk3399_sdram_params *sdram_params, cs1_cap = cs1_cap * 3 / 4; } - write32(&ddr_msch_regs->ddrconf, ddrconfig | (ddrconfig << 6)); + write32(&ddr_msch_regs->ddrconf, ddrconfig | (ddrconfig << 8)); write32(&ddr_msch_regs->ddrsize, ((cs0_cap / 32) & 0xff) | (((cs1_cap / 32) & 0xff) << 8)); }

1 0

New patch to review for coreboot: soc/rockchip: split edp_enable() function
by Patrick Georgi 02 Nov '16

02 Nov '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17207 -gerrit commit 47ba95e3486d50de733b839b84913b802e4b35aa Author: Lin Huang <hl(a)rock-chips.com> Date: Sun Oct 23 14:17:25 2016 -0700 soc/rockchip: split edp_enable() function To avoid garbage display in firmware on warm reset, we need to enable eDP display in depthcharge instead when the framebuffer is cleared. Therefore limit edp_enable() in coreboot to just configure eDP, and leave enabling the display to depthcharge. CQ-DEPEND=CL:402071 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, and display work Change-Id: I9d937ead33ebba58e33e02fd73b80d6e11bb69aa Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 38b0d18c3fae37dfccb18fe809f763b98703167c Original-Change-Id: Ibbc283a5892b98f4922f02fd67465fe2e1d01b71 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/402095 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/common/edp.c | 15 ++++++++++----- src/soc/rockchip/common/include/soc/edp.h | 1 + src/soc/rockchip/rk3288/display.c | 4 ++++ src/soc/rockchip/rk3399/display.c | 5 +++-- 4 files changed, 18 insertions(+), 7 deletions(-) diff --git a/src/soc/rockchip/common/edp.c b/src/soc/rockchip/common/edp.c index 90bc6e7..5723ccf 100644 --- a/src/soc/rockchip/common/edp.c +++ b/src/soc/rockchip/common/edp.c @@ -921,10 +921,7 @@ static int rk_edp_config_video(struct rk_edp *edp) /* Disable video mute */ clrbits_le32(&edp->regs->video_ctl_1, VIDEO_MUTE); - /* Enable video at next frame */ - setbits_le32(&edp->regs->video_ctl_1, VIDEO_EN); - - return rk_edp_is_video_stream_on(edp); + return 0; } static void rockchip_edp_force_hpd(struct rk_edp *edp) @@ -985,7 +982,7 @@ int rk_edp_get_edid(struct edid *edid) return retval; } -int rk_edp_enable(void) +int rk_edp_prepare(void) { int ret = 0; @@ -1002,6 +999,14 @@ int rk_edp_enable(void) return ret; } +int rk_edp_enable(void) +{ + /* Enable video at next frame */ + setbits_le32(&rk_edp.regs->video_ctl_1, VIDEO_EN); + + return rk_edp_is_video_stream_on(&rk_edp); +} + void rk_edp_init(void) { rk_edp.regs = (struct rk_edp_regs *)EDP_BASE; diff --git a/src/soc/rockchip/common/include/soc/edp.h b/src/soc/rockchip/common/include/soc/edp.h index 1721fc0..a9ebbc5 100644 --- a/src/soc/rockchip/common/include/soc/edp.h +++ b/src/soc/rockchip/common/include/soc/edp.h @@ -651,6 +651,7 @@ struct rk_edp { u8 train_set[4]; }; +int rk_edp_prepare(void); int rk_edp_enable(void); void rk_edp_init(void); int rk_edp_get_edid(struct edid *edid); diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index 30c8ca1..2298d8b 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -128,6 +128,10 @@ void rk_display_init(device_t dev, u32 lcdbase, case VOP_MODE_EDP: default: + if (rk_edp_prepare()) { + printk(BIOS_WARNING, "edp prepare err\n"); + return; + } if (rk_edp_enable()) { printk(BIOS_WARNING, "edp enable err\n"); return; diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 372e115..5b88478 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -99,8 +99,9 @@ void rk_display_init(device_t dev) return; case VOP_MODE_EDP: default: - if (rk_edp_enable()) { - printk(BIOS_WARNING, "edp enable error\n"); + /* will enable edp in depthcharge */ + if (rk_edp_prepare()) { + printk(BIOS_WARNING, "edp prepare error\n"); return; } mainboard_power_on_backlight();

1 0

Patch set updated for coreboot: rockchip/rk3399: sdram: Reset system if switch to index1 fails
by Patrick Georgi 02 Nov '16

02 Nov '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17106 -gerrit commit 7301ba278dd7d2d532148fd76a456690463384c6 Author: Lin Huang <hl(a)rock-chips.com> Date: Sun Oct 16 13:24:08 2016 -0700 rockchip/rk3399: sdram: Reset system if switch to index1 fails Near the end of DDR initialization, the system switches to the index1 configuration. Sometimes this failed and a status bit that coreboot was waiting for was never set, hanging the system. Instead, give the system 100ms to reach the new configuration or reboot it, which generally fixes the issue. Also reset when training the index1 configuration fails. BUG=chrome-os-partner:57988 BRANCH=None TEST=The error condition now leads to a reboot of coreboot which recovers the system, instead of hanging. Change-Id: Icb4270369102ff7a4ce91b0677e04b4eb10f1204 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: ca250d0628ea3b6b39d5131246eaba68637c5140 Original-Change-Id: Id6e8936d90e54b733ac327f8476d744b45639232 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399681 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/soc/rockchip/rk3399/sdram.c | 27 +++++++++++++++++++++------ 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 945c0bc..9ff1294 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -936,23 +936,38 @@ static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) { u32 channel; u32 *denali_phy; + struct stopwatch sw; u32 ch_count = sdram_params->num_channels; + stopwatch_init_msecs_expire(&sw, 100); write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, 1 << 4 | 1 << 2 | 1)); - while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) - ; + while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "index1 frequency change overtime, reset\n"); + hard_reset(); + } + } + stopwatch_init_msecs_expire(&sw, 100); write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(1 << 1, 1 << 1)); - while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) - ; + while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, + "index1 frequency done overtime, reset\n"); + hard_reset(); + } + } for (channel = 0; channel < ch_count; channel++) { denali_phy = rk3399_ddr_publ[channel]->denali_phy; clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); - if (data_training(channel, sdram_params, PI_FULL_TARINING)) - printk(BIOS_DEBUG, "training failed\n"); + if (data_training(channel, sdram_params, PI_FULL_TARINING)) { + printk(BIOS_ERR, "index1 training failed, reset\n"); + hard_reset(); + } } }

1 0

Patch set updated for coreboot: rockchip/rk3399: sdram: Fix data training function
by Patrick Georgi 02 Nov '16

02 Nov '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17105 -gerrit commit b50b68a0fec7953225a6b7c143fc6dfb3c5f70ae Author: Lin Huang <hl(a)rock-chips.com> Date: Sun Oct 9 09:37:10 2016 +0800 rockchip/rk3399: sdram: Fix data training function 1. Update write leveling value to 0x200. When the wrdqs slave delay is changed to 0x200, the phase between the dqs and the clock is 0 degrees. The pcb layout can make sure the tDQSS timing is smaller than 0.25tck, so this value is useful for both higher and lower frequencies. 2. Disable read leveling for LPDDR3. The read leveling result is unreliable - the value is not in the middle of the read eye. To fix this, disable read leveling and fix the read DQSn slave delay setting for DQn to 0x080 (1/4 cycle delay of the input signal). BUG=None BRANCH=None TEST=Boot from kevin; Check by shmoo read eye and stability test, that the updated value of 0x80 is better. Change-Id: Ia72b601d9bf4e34ba1b0b4584b2c5c3ce9dafbd4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 37e8dfe783db3ce71aa026b4609ed0bfa16db06f Original-Change-Id: I2a5d40c0348449b2a7c609c1db65da4ed5f1c09f Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Signed-off-by: Jeff Chen <cym(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/396598 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> --- src/soc/rockchip/rk3399/sdram.c | 83 ++++++++++------------------------------- 1 file changed, 19 insertions(+), 64 deletions(-) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index 688bdeb..945c0bc 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -587,67 +587,14 @@ static void select_per_cs_training_index(u32 channel, u32 rank) } } -/* - * After write leveling for all ranks, check the PHY_CLK_WRDQS_SLAVE_DELAY - * result, if the two ranks in one slice both met - * "0x200-PHY_CLK_WRDQS_SLAVE_DELAY < 0x20 or - * 0x200-PHY_CLK_WRDQS_SLAVE > 0x1E0", - * enable PHY_WRLVL_EARLY_FORCE_ZERO for this slice, and trigger write - * leveling again. Else no additional write leveling is required. - */ -static void check_write_leveling_value(u32 channel, - const struct rk3399_sdram_params - *sdram_params) +static void override_write_leveling_value(u32 channel) { u32 *denali_ctl = rk3399_ddr_pctl[channel]->denali_ctl; u32 *denali_phy = rk3399_ddr_publ[channel]->denali_phy; - u32 i, j; - u32 wl_value[2][4]; - u32 rank = sdram_params->ch[channel].rank; + u32 byte; - for (i = 0; i < rank; i++) { - /* - * PHY_8/136/264/392 - * phy_per_cs_training_index_X 1bit offset_24 - */ - clrsetbits_le32(&denali_phy[8], 0x1 << 24, i << 24); - clrsetbits_le32(&denali_phy[136], 0x1 << 24, i << 24); - clrsetbits_le32(&denali_phy[264], 0x1 << 24, i << 24); - clrsetbits_le32(&denali_phy[392], 0x1 << 24, i << 24); - wl_value[i][0] = (read32(&denali_phy[63]) >> 16) & 0x3ff; - wl_value[i][1] = (read32(&denali_phy[191]) >> 16) & 0x3ff; - wl_value[i][2] = (read32(&denali_phy[319]) >> 16) & 0x3ff; - wl_value[i][3] = (read32(&denali_phy[447]) >> 16) & 0x3ff; - } - - /* - * PHY_8/136/264/392 - * phy_per_cs_training_multicast_en_X 1bit offset_16 - */ - clrsetbits_le32(&denali_phy[8], 0x1 << 16, 0 << 16); - clrsetbits_le32(&denali_phy[136], 0x1 << 16, 0 << 16); - clrsetbits_le32(&denali_phy[264], 0x1 << 16, 0 << 16); - clrsetbits_le32(&denali_phy[392], 0x1 << 16, 0 << 16); - - for (i = 0; i < rank; i++) { - clrsetbits_le32(&denali_phy[8], 0x1 << 24, i << 24); - clrsetbits_le32(&denali_phy[136], 0x1 << 24, i << 24); - clrsetbits_le32(&denali_phy[264], 0x1 << 24, i << 24); - clrsetbits_le32(&denali_phy[392], 0x1 << 24, i << 24); - for (j = 0; j < 4; j++) { - if (wl_value[i][j] < 0x80) - clrsetbits_le32(&denali_phy[63+j*128], - 0x3ff << 16, - (wl_value[i][j]+0x200) << 16); - else if ((wl_value[i][j] >= 0x80) && - (wl_value[i][j] < 0x100)) - clrsetbits_le32(&denali_phy[78+j*128], - 0x7 << 8, 0x1 << 8); - } - } - - /* CTL_200 ctrlupd_req 1bit offset_8 */ - clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); + /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ + setbits_le32(&denali_phy[896], 1); /* * PHY_8/136/264/392 @@ -657,6 +604,16 @@ static void check_write_leveling_value(u32 channel, clrsetbits_le32(&denali_phy[136], 0x1 << 16, 1 << 16); clrsetbits_le32(&denali_phy[264], 0x1 << 16, 1 << 16); clrsetbits_le32(&denali_phy[392], 0x1 << 16, 1 << 16); + + for (byte = 0; byte < 4; byte++) + clrsetbits_le32(&denali_phy[63 + (128 * byte)], 0xffff << 16, + 0x200 << 16); + + /* PHY_896 PHY_FREQ_SEL_MULTICAST_EN 1bit offset_0 */ + clrbits_le32(&denali_phy[896], 1); + + /* CTL_200 ctrlupd_req 1bit offset_8 */ + clrsetbits_le32(&denali_ctl[200], 0x1 << 8, 0x1 << 8); } static int data_training(u32 channel, @@ -679,8 +636,7 @@ static int data_training(u32 channel, PI_READ_LEVELING | PI_WDQ_LEVELING; } else if (sdram_params->dramtype == LPDDR3) { training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING | - PI_READ_GATE_TRAINING | - PI_READ_LEVELING; + PI_READ_GATE_TRAINING; } else if (sdram_params->dramtype == DDR3) { training_flag = PI_WRITE_LEVELING | PI_READ_GATE_TRAINING | @@ -761,18 +717,17 @@ static int data_training(u32 channel, if ((((tmp >> 10) & 0x1) == 0x1) && (((tmp >> 13) & 0x1) == 0x1) && (((tmp >> 4) & 0x1) == 0x0) && - (obs_err == 0)) { - if ((rank == 2) && (i == 1)) - check_write_leveling_value - (channel, sdram_params); + (obs_err == 0)) break; - } else if ((((tmp >> 4) & 0x1) == 0x1) || + else if ((((tmp >> 4) & 0x1) == 0x1) || (obs_err == 1)) return -1; } /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + + override_write_leveling_value(channel); clrbits_le32(&denali_pi[60], 0x3 << 8); }

1 0

Patch set updated for coreboot: rockchip/rk3399: sdram: also prepare the index1 configuration
by Patrick Georgi 02 Nov '16

02 Nov '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17104 -gerrit commit 0baba93aaaddfbd1144abc27b3d26be83d19c4b8 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Sep 15 22:59:55 2016 +0800 rockchip/rk3399: sdram: also prepare the index1 configuration To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to train alternative configurations first, so do the training and store the values. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: I944a4b297a4ed6966893aa09553da88171307a42 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2 Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386596 Original-Commit-Ready: Douglas Anderson <dianders(a)chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c | 82 ++++++------- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c | 134 ++++++++++----------- .../gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c | 6 +- src/soc/rockchip/rk3399/include/soc/addressmap.h | 2 +- src/soc/rockchip/rk3399/include/soc/sdram.h | 12 ++ src/soc/rockchip/rk3399/sdram.c | 32 +++++ 6 files changed, 156 insertions(+), 112 deletions(-) diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c index 4b73cb0..e1a517a 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-666.c @@ -70,10 +70,10 @@ struct rk3399_sdram_params params = { 0x000208d6, /* DENALI_CTL_06_DATA */ 0x0000029b, /* DENALI_CTL_07_DATA */ 0x00001a0b, /* DENALI_CTL_08_DATA */ - 0x00000028, /* DENALI_CTL_09_DATA */ - 0x00013880, /* DENALI_CTL_10_DATA */ - 0x00000190, /* DENALI_CTL_11_DATA */ - 0x00000fa0, /* DENALI_CTL_12_DATA */ + 0x00000043, /* DENALI_CTL_09_DATA */ + 0x000208d6, /* DENALI_CTL_10_DATA */ + 0x0000029b, /* DENALI_CTL_11_DATA */ + 0x00001a0b, /* DENALI_CTL_12_DATA */ 0x00000043, /* DENALI_CTL_13_DATA */ 0x000208d6, /* DENALI_CTL_14_DATA */ 0x0000029b, /* DENALI_CTL_15_DATA */ @@ -89,40 +89,40 @@ struct rk3399_sdram_params params = { 0x04000614, /* DENALI_CTL_25_DATA */ 0x2a070004, /* DENALI_CTL_26_DATA */ 0x220c051c, /* DENALI_CTL_27_DATA */ - 0x111a0400, /* DENALI_CTL_28_DATA */ - 0x00140804, /* DENALI_CTL_29_DATA */ + 0x1c2a0700, /* DENALI_CTL_28_DATA */ + 0x00220c05, /* DENALI_CTL_29_DATA */ 0x051c2a07, /* DENALI_CTL_30_DATA */ 0x0500220c, /* DENALI_CTL_31_DATA */ 0x00000a0a, /* DENALI_CTL_32_DATA */ 0x0500b64a, /* DENALI_CTL_33_DATA */ - 0x0a0a040a, /* DENALI_CTL_34_DATA */ - 0x03006d60, /* DENALI_CTL_35_DATA */ - 0x0a0a0506, /* DENALI_CTL_36_DATA */ + 0x0a0a050a, /* DENALI_CTL_34_DATA */ + 0x0500b64a, /* DENALI_CTL_35_DATA */ + 0x0a0a050a, /* DENALI_CTL_36_DATA */ 0x0500b64a, /* DENALI_CTL_37_DATA */ 0x0203000a, /* DENALI_CTL_38_DATA */ - 0x080a0c00, /* DENALI_CTL_39_DATA */ - 0x040a0c06, /* DENALI_CTL_40_DATA */ + 0x0c0a0c00, /* DENALI_CTL_39_DATA */ + 0x040a0c0a, /* DENALI_CTL_40_DATA */ 0x14000a0a, /* DENALI_CTL_41_DATA */ 0x02020a0a, /* DENALI_CTL_42_DATA */ 0x00010002, /* DENALI_CTL_43_DATA */ - 0x03160e16, /* DENALI_CTL_44_DATA */ - 0x000e090e, /* DENALI_CTL_45_DATA */ + 0x03161616, /* DENALI_CTL_44_DATA */ + 0x000e0e0e, /* DENALI_CTL_45_DATA */ 0x00000000, /* DENALI_CTL_46_DATA */ 0x03010000, /* DENALI_CTL_47_DATA */ 0x0a20008c, /* DENALI_CTL_48_DATA */ - 0x06100054, /* DENALI_CTL_49_DATA */ + 0x0a20008c, /* DENALI_CTL_49_DATA */ 0x0a20008c, /* DENALI_CTL_50_DATA */ 0x00000000, /* DENALI_CTL_51_DATA */ - 0x00030005, /* DENALI_CTL_52_DATA */ + 0x00050005, /* DENALI_CTL_52_DATA */ 0x00100005, /* DENALI_CTL_53_DATA */ - 0x0010000a, /* DENALI_CTL_54_DATA */ - 0x000c080c, /* DENALI_CTL_55_DATA */ + 0x00100010, /* DENALI_CTL_54_DATA */ + 0x000c0c0c, /* DENALI_CTL_55_DATA */ 0x00000000, /* DENALI_CTL_56_DATA */ 0x00000000, /* DENALI_CTL_57_DATA */ 0x00000000, /* DENALI_CTL_58_DATA */ 0x00930000, /* DENALI_CTL_59_DATA */ - 0x00580093, /* DENALI_CTL_60_DATA */ - 0x00930058, /* DENALI_CTL_61_DATA */ + 0x00930093, /* DENALI_CTL_60_DATA */ + 0x00930093, /* DENALI_CTL_61_DATA */ 0x00000093, /* DENALI_CTL_62_DATA */ 0x00000000, /* DENALI_CTL_63_DATA */ 0x00000000, /* DENALI_CTL_64_DATA */ @@ -145,7 +145,7 @@ struct rk3399_sdram_params params = { 0x00040005, /* DENALI_CTL_81_DATA */ 0x28800000, /* DENALI_CTL_82_DATA */ 0x00001440, /* DENALI_CTL_83_DATA */ - 0x0c201840, /* DENALI_CTL_84_DATA */ + 0x14402880, /* DENALI_CTL_84_DATA */ 0x28800000, /* DENALI_CTL_85_DATA */ 0x00001440, /* DENALI_CTL_86_DATA */ 0x00000000, /* DENALI_CTL_87_DATA */ @@ -186,9 +186,9 @@ struct rk3399_sdram_params params = { 0x00860000, /* DENALI_CTL_122_DATA */ 0x00a70043, /* DENALI_CTL_123_DATA */ 0x00a70000, /* DENALI_CTL_124_DATA */ - 0x00280050, /* DENALI_CTL_125_DATA */ - 0x00000064, /* DENALI_CTL_126_DATA */ - 0x00860064, /* DENALI_CTL_127_DATA */ + 0x00430086, /* DENALI_CTL_125_DATA */ + 0x000000a7, /* DENALI_CTL_126_DATA */ + 0x008600a7, /* DENALI_CTL_127_DATA */ 0x00a70043, /* DENALI_CTL_128_DATA */ 0x00a70000, /* DENALI_CTL_129_DATA */ 0x00000000, /* DENALI_CTL_130_DATA */ @@ -196,12 +196,12 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_132_DATA */ 0x00030000, /* DENALI_CTL_133_DATA */ 0x00000018, /* DENALI_CTL_134_DATA */ - 0x00080083, /* DENALI_CTL_135_DATA */ + 0x00180003, /* DENALI_CTL_135_DATA */ 0x00030000, /* DENALI_CTL_136_DATA */ 0x00000018, /* DENALI_CTL_137_DATA */ 0x00010001, /* DENALI_CTL_138_DATA */ 0x06000001, /* DENALI_CTL_139_DATA */ - 0x00000707, /* DENALI_CTL_140_DATA */ + 0x00000706, /* DENALI_CTL_140_DATA */ 0x00000000, /* DENALI_CTL_141_DATA */ 0x00000000, /* DENALI_CTL_142_DATA */ 0x00000000, /* DENALI_CTL_143_DATA */ @@ -210,12 +210,12 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_146_DATA */ 0x00030000, /* DENALI_CTL_147_DATA */ 0x00000018, /* DENALI_CTL_148_DATA */ - 0x00080083, /* DENALI_CTL_149_DATA */ + 0x00180003, /* DENALI_CTL_149_DATA */ 0x00030000, /* DENALI_CTL_150_DATA */ 0x00000018, /* DENALI_CTL_151_DATA */ 0x00010001, /* DENALI_CTL_152_DATA */ 0x06000001, /* DENALI_CTL_153_DATA */ - 0x00000707, /* DENALI_CTL_154_DATA */ + 0x00000706, /* DENALI_CTL_154_DATA */ 0x00000000, /* DENALI_CTL_155_DATA */ 0x00000000, /* DENALI_CTL_156_DATA */ 0x00000000, /* DENALI_CTL_157_DATA */ @@ -243,13 +243,13 @@ struct rk3399_sdram_params params = { 0x00029b03, /* DENALI_CTL_179_DATA */ 0x003c00f0, /* DENALI_CTL_180_DATA */ 0x00000000, /* DENALI_CTL_181_DATA */ - 0x00900190, /* DENALI_CTL_182_DATA */ - 0x00000024, /* DENALI_CTL_183_DATA */ + 0x00f0029b, /* DENALI_CTL_182_DATA */ + 0x0000003c, /* DENALI_CTL_183_DATA */ 0x00029b00, /* DENALI_CTL_184_DATA */ 0x003c00f0, /* DENALI_CTL_185_DATA */ 0x00000000, /* DENALI_CTL_186_DATA */ 0x00220000, /* DENALI_CTL_187_DATA */ - 0x00220014, /* DENALI_CTL_188_DATA */ + 0x00220022, /* DENALI_CTL_188_DATA */ 0x01010100, /* DENALI_CTL_189_DATA */ 0x01000202, /* DENALI_CTL_190_DATA */ 0x0a000002, /* DENALI_CTL_191_DATA */ @@ -273,17 +273,17 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_209_DATA */ 0x00000000, /* DENALI_CTL_210_DATA */ 0x00010000, /* DENALI_CTL_211_DATA */ - 0x03020301, /* DENALI_CTL_212_DATA */ + 0x03030301, /* DENALI_CTL_212_DATA */ 0x01010808, /* DENALI_CTL_213_DATA */ - 0x04030001, /* DENALI_CTL_214_DATA */ + 0x03030001, /* DENALI_CTL_214_DATA */ 0x08080803, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ - 0x02050203, /* DENALI_CTL_217_DATA */ - 0x02050303, /* DENALI_CTL_218_DATA */ + 0x08050203, /* DENALI_CTL_217_DATA */ + 0x02050203, /* DENALI_CTL_218_DATA */ 0x00050203, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ - 0x03020400, /* DENALI_CTL_221_DATA */ - 0x00020401, /* DENALI_CTL_222_DATA */ + 0x04020400, /* DENALI_CTL_221_DATA */ + 0x00020402, /* DENALI_CTL_222_DATA */ 0x00000000, /* DENALI_CTL_223_DATA */ 0x00000000, /* DENALI_CTL_224_DATA */ 0x0d000001, /* DENALI_CTL_225_DATA */ @@ -336,7 +336,7 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_272_DATA */ 0x00000000, /* DENALI_CTL_273_DATA */ 0x00ffff00, /* DENALI_CTL_274_DATA */ - 0x181b0000, /* DENALI_CTL_275_DATA */ + 0x1b1b0000, /* DENALI_CTL_275_DATA */ 0x0800001b, /* DENALI_CTL_276_DATA */ 0x00001440, /* DENALI_CTL_277_DATA */ 0x00000200, /* DENALI_CTL_278_DATA */ @@ -345,13 +345,13 @@ struct rk3399_sdram_params params = { 0x00000200, /* DENALI_CTL_281_DATA */ 0x00001440, /* DENALI_CTL_282_DATA */ 0x0000ca80, /* DENALI_CTL_283_DATA */ - 0x0c200509, /* DENALI_CTL_284_DATA */ + 0x14400509, /* DENALI_CTL_284_DATA */ 0x00000200, /* DENALI_CTL_285_DATA */ 0x00000200, /* DENALI_CTL_286_DATA */ 0x00000200, /* DENALI_CTL_287_DATA */ 0x00000200, /* DENALI_CTL_288_DATA */ - 0x00000c20, /* DENALI_CTL_289_DATA */ - 0x00007940, /* DENALI_CTL_290_DATA */ + 0x00001440, /* DENALI_CTL_289_DATA */ + 0x0000ca80, /* DENALI_CTL_290_DATA */ 0x14400509, /* DENALI_CTL_291_DATA */ 0x00000200, /* DENALI_CTL_292_DATA */ 0x00000200, /* DENALI_CTL_293_DATA */ @@ -370,7 +370,7 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_306_DATA */ 0x00030000, /* DENALI_CTL_307_DATA */ 0x000d001f, /* DENALI_CTL_308_DATA */ - 0x000a001c, /* DENALI_CTL_309_DATA */ + 0x000d001f, /* DENALI_CTL_309_DATA */ 0x000d001f, /* DENALI_CTL_310_DATA */ 0x00000000, /* DENALI_CTL_311_DATA */ 0x00000000, /* DENALI_CTL_312_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c index 3056e55..1035d5d 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-800.c @@ -70,10 +70,10 @@ struct rk3399_sdram_params params = { 0x00027100, /* DENALI_CTL_06_DATA */ 0x00000320, /* DENALI_CTL_07_DATA */ 0x00001f40, /* DENALI_CTL_08_DATA */ - 0x00000028, /* DENALI_CTL_09_DATA */ - 0x00013880, /* DENALI_CTL_10_DATA */ - 0x00000190, /* DENALI_CTL_11_DATA */ - 0x00000fa0, /* DENALI_CTL_12_DATA */ + 0x00000050, /* DENALI_CTL_09_DATA */ + 0x00027100, /* DENALI_CTL_10_DATA */ + 0x00000320, /* DENALI_CTL_11_DATA */ + 0x00001f40, /* DENALI_CTL_12_DATA */ 0x00000050, /* DENALI_CTL_13_DATA */ 0x00027100, /* DENALI_CTL_14_DATA */ 0x00000320, /* DENALI_CTL_15_DATA */ @@ -89,40 +89,40 @@ struct rk3399_sdram_params params = { 0x04000618, /* DENALI_CTL_25_DATA */ 0x33080004, /* DENALI_CTL_26_DATA */ 0x280f0622, /* DENALI_CTL_27_DATA */ - 0x111a0400, /* DENALI_CTL_28_DATA */ - 0x00140804, /* DENALI_CTL_29_DATA */ + 0x22330800, /* DENALI_CTL_28_DATA */ + 0x00280f06, /* DENALI_CTL_29_DATA */ 0x06223308, /* DENALI_CTL_30_DATA */ 0x0600280f, /* DENALI_CTL_31_DATA */ 0x00000a0a, /* DENALI_CTL_32_DATA */ 0x0600dac0, /* DENALI_CTL_33_DATA */ - 0x0a0a040c, /* DENALI_CTL_34_DATA */ - 0x03006d60, /* DENALI_CTL_35_DATA */ - 0x0a0a0606, /* DENALI_CTL_36_DATA */ + 0x0a0a060c, /* DENALI_CTL_34_DATA */ + 0x0600dac0, /* DENALI_CTL_35_DATA */ + 0x0a0a060c, /* DENALI_CTL_36_DATA */ 0x0600dac0, /* DENALI_CTL_37_DATA */ 0x0203000c, /* DENALI_CTL_38_DATA */ - 0x080c0f00, /* DENALI_CTL_39_DATA */ - 0x040c0f06, /* DENALI_CTL_40_DATA */ + 0x0f0c0f00, /* DENALI_CTL_39_DATA */ + 0x040c0f0c, /* DENALI_CTL_40_DATA */ 0x14000a0a, /* DENALI_CTL_41_DATA */ - 0x02030a0a, /* DENALI_CTL_42_DATA */ + 0x03030a0a, /* DENALI_CTL_42_DATA */ 0x00010003, /* DENALI_CTL_43_DATA */ - 0x031b0e1b, /* DENALI_CTL_44_DATA */ - 0x00110911, /* DENALI_CTL_45_DATA */ + 0x031b1b1b, /* DENALI_CTL_44_DATA */ + 0x00111111, /* DENALI_CTL_45_DATA */ 0x00000000, /* DENALI_CTL_46_DATA */ 0x03010000, /* DENALI_CTL_47_DATA */ 0x0c2800a8, /* DENALI_CTL_48_DATA */ - 0x06100054, /* DENALI_CTL_49_DATA */ + 0x0c2800a8, /* DENALI_CTL_49_DATA */ 0x0c2800a8, /* DENALI_CTL_50_DATA */ 0x00000000, /* DENALI_CTL_51_DATA */ - 0x00030006, /* DENALI_CTL_52_DATA */ + 0x00060006, /* DENALI_CTL_52_DATA */ 0x00140006, /* DENALI_CTL_53_DATA */ - 0x0014000a, /* DENALI_CTL_54_DATA */ - 0x000f080f, /* DENALI_CTL_55_DATA */ + 0x00140014, /* DENALI_CTL_54_DATA */ + 0x000f0f0f, /* DENALI_CTL_55_DATA */ 0x00000000, /* DENALI_CTL_56_DATA */ 0x00000000, /* DENALI_CTL_57_DATA */ 0x00000000, /* DENALI_CTL_58_DATA */ 0x00b00000, /* DENALI_CTL_59_DATA */ - 0x005800b0, /* DENALI_CTL_60_DATA */ - 0x00b00058, /* DENALI_CTL_61_DATA */ + 0x00b000b0, /* DENALI_CTL_60_DATA */ + 0x00b000b0, /* DENALI_CTL_61_DATA */ 0x000000b0, /* DENALI_CTL_62_DATA */ 0x00000000, /* DENALI_CTL_63_DATA */ 0x00000000, /* DENALI_CTL_64_DATA */ @@ -145,7 +145,7 @@ struct rk3399_sdram_params params = { 0x00040005, /* DENALI_CTL_81_DATA */ 0x30a00000, /* DENALI_CTL_82_DATA */ 0x00001850, /* DENALI_CTL_83_DATA */ - 0x0c201840, /* DENALI_CTL_84_DATA */ + 0x185030a0, /* DENALI_CTL_84_DATA */ 0x30a00000, /* DENALI_CTL_85_DATA */ 0x00001850, /* DENALI_CTL_86_DATA */ 0x00000000, /* DENALI_CTL_87_DATA */ @@ -186,9 +186,9 @@ struct rk3399_sdram_params params = { 0x00a00000, /* DENALI_CTL_122_DATA */ 0x00c80050, /* DENALI_CTL_123_DATA */ 0x00c80000, /* DENALI_CTL_124_DATA */ - 0x00280050, /* DENALI_CTL_125_DATA */ - 0x00000064, /* DENALI_CTL_126_DATA */ - 0x00a00064, /* DENALI_CTL_127_DATA */ + 0x005000a0, /* DENALI_CTL_125_DATA */ + 0x000000c8, /* DENALI_CTL_126_DATA */ + 0x00a000c8, /* DENALI_CTL_127_DATA */ 0x00c80050, /* DENALI_CTL_128_DATA */ 0x00c80000, /* DENALI_CTL_129_DATA */ 0x00000000, /* DENALI_CTL_130_DATA */ @@ -196,12 +196,12 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_132_DATA */ 0x00430000, /* DENALI_CTL_133_DATA */ 0x0000001a, /* DENALI_CTL_134_DATA */ - 0x000a0083, /* DENALI_CTL_135_DATA */ + 0x001a0043, /* DENALI_CTL_135_DATA */ 0x00430000, /* DENALI_CTL_136_DATA */ 0x0000001a, /* DENALI_CTL_137_DATA */ 0x00010001, /* DENALI_CTL_138_DATA */ 0x06000001, /* DENALI_CTL_139_DATA */ - 0x00000707, /* DENALI_CTL_140_DATA */ + 0x00000706, /* DENALI_CTL_140_DATA */ 0x00000000, /* DENALI_CTL_141_DATA */ 0x00000000, /* DENALI_CTL_142_DATA */ 0x00000000, /* DENALI_CTL_143_DATA */ @@ -210,12 +210,12 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_146_DATA */ 0x00430000, /* DENALI_CTL_147_DATA */ 0x0000001a, /* DENALI_CTL_148_DATA */ - 0x000a0083, /* DENALI_CTL_149_DATA */ + 0x001a0043, /* DENALI_CTL_149_DATA */ 0x00430000, /* DENALI_CTL_150_DATA */ 0x0000001a, /* DENALI_CTL_151_DATA */ 0x00010001, /* DENALI_CTL_152_DATA */ 0x06000001, /* DENALI_CTL_153_DATA */ - 0x00000707, /* DENALI_CTL_154_DATA */ + 0x00000706, /* DENALI_CTL_154_DATA */ 0x00000000, /* DENALI_CTL_155_DATA */ 0x00000000, /* DENALI_CTL_156_DATA */ 0x00000000, /* DENALI_CTL_157_DATA */ @@ -243,13 +243,13 @@ struct rk3399_sdram_params params = { 0x00032003, /* DENALI_CTL_179_DATA */ 0x00480120, /* DENALI_CTL_180_DATA */ 0x00000000, /* DENALI_CTL_181_DATA */ - 0x00900190, /* DENALI_CTL_182_DATA */ - 0x00000024, /* DENALI_CTL_183_DATA */ + 0x01200320, /* DENALI_CTL_182_DATA */ + 0x00000048, /* DENALI_CTL_183_DATA */ 0x00032000, /* DENALI_CTL_184_DATA */ 0x00480120, /* DENALI_CTL_185_DATA */ 0x00000000, /* DENALI_CTL_186_DATA */ 0x00280000, /* DENALI_CTL_187_DATA */ - 0x00280014, /* DENALI_CTL_188_DATA */ + 0x00280028, /* DENALI_CTL_188_DATA */ 0x01010100, /* DENALI_CTL_189_DATA */ 0x01000202, /* DENALI_CTL_190_DATA */ 0x0a000002, /* DENALI_CTL_191_DATA */ @@ -273,17 +273,17 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_209_DATA */ 0x00000000, /* DENALI_CTL_210_DATA */ 0x00010000, /* DENALI_CTL_211_DATA */ - 0x03020301, /* DENALI_CTL_212_DATA */ + 0x03030301, /* DENALI_CTL_212_DATA */ 0x01010808, /* DENALI_CTL_213_DATA */ - 0x04030001, /* DENALI_CTL_214_DATA */ + 0x03030001, /* DENALI_CTL_214_DATA */ 0x0a0a0a03, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ - 0x02050103, /* DENALI_CTL_217_DATA */ + 0x08050103, /* DENALI_CTL_217_DATA */ 0x02050103, /* DENALI_CTL_218_DATA */ 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ - 0x03020500, /* DENALI_CTL_221_DATA */ - 0x00020501, /* DENALI_CTL_222_DATA */ + 0x05020500, /* DENALI_CTL_221_DATA */ + 0x00020502, /* DENALI_CTL_222_DATA */ 0x00000000, /* DENALI_CTL_223_DATA */ 0x00000000, /* DENALI_CTL_224_DATA */ 0x0d000001, /* DENALI_CTL_225_DATA */ @@ -336,7 +336,7 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_272_DATA */ 0x00000000, /* DENALI_CTL_273_DATA */ 0x00ffff00, /* DENALI_CTL_274_DATA */ - 0x181e0000, /* DENALI_CTL_275_DATA */ + 0x1e1e0000, /* DENALI_CTL_275_DATA */ 0x0800001e, /* DENALI_CTL_276_DATA */ 0x00001850, /* DENALI_CTL_277_DATA */ 0x00000200, /* DENALI_CTL_278_DATA */ @@ -345,14 +345,14 @@ struct rk3399_sdram_params params = { 0x00000200, /* DENALI_CTL_281_DATA */ 0x00001850, /* DENALI_CTL_282_DATA */ 0x0000f320, /* DENALI_CTL_283_DATA */ - 0x0c20050a, /* DENALI_CTL_284_DATA */ + 0x1850050a, /* DENALI_CTL_284_DATA */ 0x00000200, /* DENALI_CTL_285_DATA */ 0x00000200, /* DENALI_CTL_286_DATA */ 0x00000200, /* DENALI_CTL_287_DATA */ 0x00000200, /* DENALI_CTL_288_DATA */ - 0x00000c20, /* DENALI_CTL_289_DATA */ - 0x00007940, /* DENALI_CTL_290_DATA */ - 0x1850050b, /* DENALI_CTL_291_DATA */ + 0x00001850, /* DENALI_CTL_289_DATA */ + 0x0000f320, /* DENALI_CTL_290_DATA */ + 0x1850050a, /* DENALI_CTL_291_DATA */ 0x00000200, /* DENALI_CTL_292_DATA */ 0x00000200, /* DENALI_CTL_293_DATA */ 0x00000200, /* DENALI_CTL_294_DATA */ @@ -370,7 +370,7 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_CTL_306_DATA */ 0x00030000, /* DENALI_CTL_307_DATA */ 0x000e0020, /* DENALI_CTL_308_DATA */ - 0x000a001c, /* DENALI_CTL_309_DATA */ + 0x000e0020, /* DENALI_CTL_309_DATA */ 0x000e0020, /* DENALI_CTL_310_DATA */ 0x00000000, /* DENALI_CTL_311_DATA */ 0x00000000, /* DENALI_CTL_312_DATA */ @@ -401,15 +401,15 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_01_DATA */ 0x000030a0, /* DENALI_PI_02_DATA */ 0x00001850, /* DENALI_PI_03_DATA */ - 0x00001840, /* DENALI_PI_04_DATA */ - 0x00000c20, /* DENALI_PI_05_DATA */ + 0x000030a0, /* DENALI_PI_04_DATA */ + 0x00001850, /* DENALI_PI_05_DATA */ 0x000030a0, /* DENALI_PI_06_DATA */ 0x18501850, /* DENALI_PI_07_DATA */ 0x00000200, /* DENALI_PI_08_DATA */ 0x00000200, /* DENALI_PI_09_DATA */ 0x00000200, /* DENALI_PI_10_DATA */ 0x00000200, /* DENALI_PI_11_DATA */ - 0x00000c20, /* DENALI_PI_12_DATA */ + 0x00001850, /* DENALI_PI_12_DATA */ 0x00000200, /* DENALI_PI_13_DATA */ 0x00000200, /* DENALI_PI_14_DATA */ 0x00000200, /* DENALI_PI_15_DATA */ @@ -439,12 +439,12 @@ struct rk3399_sdram_params params = { 0x0f000010, /* DENALI_PI_39_DATA */ 0x377ff000, /* DENALI_PI_40_DATA */ 0x03000101, /* DENALI_PI_41_DATA */ - 0x042e292e, /* DENALI_PI_42_DATA */ + 0x042e2e2e, /* DENALI_PI_42_DATA */ 0x06180006, /* DENALI_PI_43_DATA */ 0x00061800, /* DENALI_PI_44_DATA */ 0x00000018, /* DENALI_PI_45_DATA */ 0x0c2800a8, /* DENALI_PI_46_DATA */ - 0x06100054, /* DENALI_PI_47_DATA */ + 0x0c2800a8, /* DENALI_PI_47_DATA */ 0x0c2800a8, /* DENALI_PI_48_DATA */ 0x00000500, /* DENALI_PI_49_DATA */ 0x00000000, /* DENALI_PI_50_DATA */ @@ -464,12 +464,12 @@ struct rk3399_sdram_params params = { 0x00000000, /* DENALI_PI_64_DATA */ 0x00000000, /* DENALI_PI_65_DATA */ 0x03060002, /* DENALI_PI_66_DATA */ - 0x03010201, /* DENALI_PI_67_DATA */ + 0x03010301, /* DENALI_PI_67_DATA */ 0x01080801, /* DENALI_PI_68_DATA */ 0x04020201, /* DENALI_PI_69_DATA */ 0x01080804, /* DENALI_PI_70_DATA */ 0x00000000, /* DENALI_PI_71_DATA */ - 0x04030000, /* DENALI_PI_72_DATA */ + 0x03030000, /* DENALI_PI_72_DATA */ 0x0a0a0a03, /* DENALI_PI_73_DATA */ 0x00000000, /* DENALI_PI_74_DATA */ 0x00000000, /* DENALI_PI_75_DATA */ @@ -486,21 +486,21 @@ struct rk3399_sdram_params params = { 0x55555a5a, /* DENALI_PI_86_DATA */ 0x55555a5a, /* DENALI_PI_87_DATA */ 0x55555a5a, /* DENALI_PI_88_DATA */ - 0x0b0a0001, /* DENALI_PI_89_DATA */ + 0x0a0a0001, /* DENALI_PI_89_DATA */ 0x0505000a, /* DENALI_PI_90_DATA */ 0x00000005, /* DENALI_PI_91_DATA */ 0x00000100, /* DENALI_PI_92_DATA */ 0x00030000, /* DENALI_PI_93_DATA */ 0x17030000, /* DENALI_PI_94_DATA */ 0x000e0020, /* DENALI_PI_95_DATA */ - 0x000a001c, /* DENALI_PI_96_DATA */ + 0x000e0020, /* DENALI_PI_96_DATA */ 0x000e0020, /* DENALI_PI_97_DATA */ 0x00000000, /* DENALI_PI_98_DATA */ 0x00000000, /* DENALI_PI_99_DATA */ 0x00000100, /* DENALI_PI_100_DATA */ 0x140a0000, /* DENALI_PI_101_DATA */ 0x000a030a, /* DENALI_PI_102_DATA */ - 0x03000a02, /* DENALI_PI_103_DATA */ + 0x03000a03, /* DENALI_PI_103_DATA */ 0x010a000a, /* DENALI_PI_104_DATA */ 0x00000100, /* DENALI_PI_105_DATA */ 0x01000000, /* DENALI_PI_106_DATA */ @@ -508,12 +508,12 @@ struct rk3399_sdram_params params = { 0x00000100, /* DENALI_PI_108_DATA */ 0x1e1a0000, /* DENALI_PI_109_DATA */ 0x10010204, /* DENALI_PI_110_DATA */ - 0x07060705, /* DENALI_PI_111_DATA */ + 0x07070705, /* DENALI_PI_111_DATA */ 0x20000202, /* DENALI_PI_112_DATA */ 0x00201000, /* DENALI_PI_113_DATA */ 0x00201000, /* DENALI_PI_114_DATA */ 0x04041000, /* DENALI_PI_115_DATA */ - 0x0c100100, /* DENALI_PI_116_DATA */ + 0x10100100, /* DENALI_PI_116_DATA */ 0x00010110, /* DENALI_PI_117_DATA */ 0x004b004a, /* DENALI_PI_118_DATA */ 0x1a030000, /* DENALI_PI_119_DATA */ @@ -525,43 +525,43 @@ struct rk3399_sdram_params params = { 0x00004300, /* DENALI_PI_125_DATA */ 0x0001001a, /* DENALI_PI_126_DATA */ 0x004d4d07, /* DENALI_PI_127_DATA */ - 0x000a0083, /* DENALI_PI_128_DATA */ + 0x001a0043, /* DENALI_PI_128_DATA */ 0x4d070001, /* DENALI_PI_129_DATA */ 0x0000434d, /* DENALI_PI_130_DATA */ 0x0001001a, /* DENALI_PI_131_DATA */ 0x004d4d07, /* DENALI_PI_132_DATA */ 0x001a0043, /* DENALI_PI_133_DATA */ 0x4d070001, /* DENALI_PI_134_DATA */ - 0x0000834d, /* DENALI_PI_135_DATA */ - 0x0001000a, /* DENALI_PI_136_DATA */ + 0x0000434d, /* DENALI_PI_135_DATA */ + 0x0001001a, /* DENALI_PI_136_DATA */ 0x004d4d07, /* DENALI_PI_137_DATA */ 0x001a0043, /* DENALI_PI_138_DATA */ 0x4d070001, /* DENALI_PI_139_DATA */ 0x0043004d, /* DENALI_PI_140_DATA */ 0x0001001a, /* DENALI_PI_141_DATA */ 0x004d4d07, /* DENALI_PI_142_DATA */ - 0x000a0083, /* DENALI_PI_143_DATA */ + 0x001a0043, /* DENALI_PI_143_DATA */ 0x4d070001, /* DENALI_PI_144_DATA */ 0x0000434d, /* DENALI_PI_145_DATA */ 0x0001001a, /* DENALI_PI_146_DATA */ 0x004d4d07, /* DENALI_PI_147_DATA */ 0x001a0043, /* DENALI_PI_148_DATA */ 0x4d070001, /* DENALI_PI_149_DATA */ - 0x0000834d, /* DENALI_PI_150_DATA */ - 0x0001000a, /* DENALI_PI_151_DATA */ + 0x0000434d, /* DENALI_PI_150_DATA */ + 0x0001001a, /* DENALI_PI_151_DATA */ 0x004d4d07, /* DENALI_PI_152_DATA */ 0x001a0043, /* DENALI_PI_153_DATA */ 0x4d070001, /* DENALI_PI_154_DATA */ 0x0100004d, /* DENALI_PI_155_DATA */ - 0x006400c8, /* DENALI_PI_156_DATA */ + 0x00c800c8, /* DENALI_PI_156_DATA */ 0x060400c8, /* DENALI_PI_157_DATA */ 0x0c060f11, /* DENALI_PI_158_DATA */ 0x2200d890, /* DENALI_PI_159_DATA */ 0x0a0c2005, /* DENALI_PI_160_DATA */ - 0x0809040a, /* DENALI_PI_161_DATA */ - 0x00000604, /* DENALI_PI_162_DATA */ - 0x11006c48, /* DENALI_PI_163_DATA */ - 0x0a062003, /* DENALI_PI_164_DATA */ + 0x0f11060a, /* DENALI_PI_161_DATA */ + 0x00000c06, /* DENALI_PI_162_DATA */ + 0x2200d890, /* DENALI_PI_163_DATA */ + 0x0a0c2005, /* DENALI_PI_164_DATA */ 0x0f11060a, /* DENALI_PI_165_DATA */ 0x00000c06, /* DENALI_PI_166_DATA */ 0x2200d890, /* DENALI_PI_167_DATA */ @@ -586,8 +586,8 @@ struct rk3399_sdram_params params = { 0x01000300, /* DENALI_PI_186_DATA */ 0x00185000, /* DENALI_PI_187_DATA */ 0x0000f320, /* DENALI_PI_188_DATA */ - 0x00000c20, /* DENALI_PI_189_DATA */ - 0x00007940, /* DENALI_PI_190_DATA */ + 0x00001850, /* DENALI_PI_189_DATA */ + 0x0000f320, /* DENALI_PI_190_DATA */ 0x00001850, /* DENALI_PI_191_DATA */ 0x0000f320, /* DENALI_PI_192_DATA */ 0x08000000, /* DENALI_PI_193_DATA */ diff --git a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c index 3947881..7110748 100644 --- a/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c +++ b/src/mainboard/google/gru/sdram_params/sdram-lpddr3-hynix-4GB-933.c @@ -201,7 +201,7 @@ struct rk3399_sdram_params params = { 0x0000001c, /* DENALI_CTL_137_DATA */ 0x00010001, /* DENALI_CTL_138_DATA */ 0x06000001, /* DENALI_CTL_139_DATA */ - 0x00000707, /* DENALI_CTL_140_DATA */ + 0x00000606, /* DENALI_CTL_140_DATA */ 0x00000000, /* DENALI_CTL_141_DATA */ 0x00000000, /* DENALI_CTL_142_DATA */ 0x00000000, /* DENALI_CTL_143_DATA */ @@ -215,7 +215,7 @@ struct rk3399_sdram_params params = { 0x0000001c, /* DENALI_CTL_151_DATA */ 0x00010001, /* DENALI_CTL_152_DATA */ 0x06000001, /* DENALI_CTL_153_DATA */ - 0x00000707, /* DENALI_CTL_154_DATA */ + 0x00000606, /* DENALI_CTL_154_DATA */ 0x00000000, /* DENALI_CTL_155_DATA */ 0x00000000, /* DENALI_CTL_156_DATA */ 0x00000000, /* DENALI_CTL_157_DATA */ @@ -278,7 +278,7 @@ struct rk3399_sdram_params params = { 0x04040001, /* DENALI_CTL_214_DATA */ 0x0c0c0c04, /* DENALI_CTL_215_DATA */ 0x08080808, /* DENALI_CTL_216_DATA */ - 0x02050103, /* DENALI_CTL_217_DATA */ + 0x08050103, /* DENALI_CTL_217_DATA */ 0x02050103, /* DENALI_CTL_218_DATA */ 0x00050103, /* DENALI_CTL_219_DATA */ 0x00020202, /* DENALI_CTL_220_DATA */ diff --git a/src/soc/rockchip/rk3399/include/soc/addressmap.h b/src/soc/rockchip/rk3399/include/soc/addressmap.h index d316c38..1762a8d 100644 --- a/src/soc/rockchip/rk3399/include/soc/addressmap.h +++ b/src/soc/rockchip/rk3399/include/soc/addressmap.h @@ -17,7 +17,6 @@ #define __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ #define MAX_DRAM_ADDRESS 0xF8000000 - #define PMUGRF_BASE 0xff320000 #define PMUSGRF_BASE 0xff330000 #define PMUCRU_BASE 0xff750000 @@ -69,6 +68,7 @@ #define SERVER_MSCH0_BASE_ADDR 0xffa84000 #define DDRC1_BASE_ADDR 0xffa88000 #define SERVER_MSCH1_BASE_ADDR 0xffa8c000 +#define CIC_BASE_ADDR 0xff620000 #define USB_OTG0_DWC3_BASE 0xfe80c100 #define USB_OTG1_DWC3_BASE 0xfe90c100 diff --git a/src/soc/rockchip/rk3399/include/soc/sdram.h b/src/soc/rockchip/rk3399/include/soc/sdram.h index 1ec6d39..bf99b35 100644 --- a/src/soc/rockchip/rk3399/include/soc/sdram.h +++ b/src/soc/rockchip/rk3399/include/soc/sdram.h @@ -127,6 +127,18 @@ struct rk3399_msch_timings { u32 agingx0; }; +struct rk3399_ddr_cic_regs { + u32 cic_ctrl0; + u32 cic_ctrl1; + u32 cic_idle_th; + u32 cic_cg_wait_th; + u32 cic_status0; + u32 cic_status1; + u32 cic_ctrl2; + u32 cic_ctrl3; + u32 cic_ctrl4; +}; + /* DENALI_CTL_00 */ #define START (1) diff --git a/src/soc/rockchip/rk3399/sdram.c b/src/soc/rockchip/rk3399/sdram.c index ee98033..688bdeb 100644 --- a/src/soc/rockchip/rk3399/sdram.c +++ b/src/soc/rockchip/rk3399/sdram.c @@ -41,6 +41,7 @@ static struct rk3399_ddr_publ_regs * const rk3399_ddr_publ[2] = { (void *)DDRC0_PHY_BASE_ADDR, (void *)DDRC1_PHY_BASE_ADDR }; static struct rk3399_msch_regs * const rk3399_msch[2] = { (void *)SERVER_MSCH0_BASE_ADDR, (void *)SERVER_MSCH1_BASE_ADDR }; +static struct rk3399_ddr_cic_regs *const rk3399_ddr_cic = (void *)CIC_BASE_ADDR; /* * sys_reg bitfield struct @@ -725,6 +726,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[100], 0x3 << 8); } /* write leveling(LPDDR4,LPDDR3,DDR3 support) */ @@ -771,6 +773,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[60], 0x3 << 8); } /* read gate training(LPDDR4,LPDDR3,DDR3 support) */ @@ -817,6 +820,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[80], 0x3 << 24); } /* read leveling(LPDDR4,LPDDR3,DDR3 support) */ @@ -849,6 +853,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[80], 0x3 << 16); } /* wdq leveling(LPDDR4 support) */ @@ -880,6 +885,7 @@ static int data_training(u32 channel, /* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */ write32((&denali_pi[175]), 0x00003f7c); } + clrbits_le32(&denali_pi[124], 0x3 << 16); } /* PHY_927 PHY_PAD_DQS_DRIVE RPULL offset_22 */ @@ -971,6 +977,30 @@ static void dram_all_config(const struct rk3399_sdram_params *sdram_params) clrsetbits_le32(&cru_ptr->glb_rst_con, 0x3, 0x3); } +static void switch_to_phy_index1(const struct rk3399_sdram_params *sdram_params) +{ + u32 channel; + u32 *denali_phy; + u32 ch_count = sdram_params->num_channels; + + write32(&rk3399_ddr_cic->cic_ctrl0, + RK_CLRSETBITS(0x03 << 4 | 1 << 2 | 1, + 1 << 4 | 1 << 2 | 1)); + while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 2))) + ; + + write32(&rk3399_ddr_cic->cic_ctrl0, RK_CLRSETBITS(1 << 1, 1 << 1)); + while (!(read32(&rk3399_ddr_cic->cic_status0) & (1 << 0))) + ; + + for (channel = 0; channel < ch_count; channel++) { + denali_phy = rk3399_ddr_publ[channel]->denali_phy; + clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8); + if (data_training(channel, sdram_params, PI_FULL_TARINING)) + printk(BIOS_DEBUG, "training failed\n"); + } +} + void sdram_init(const struct rk3399_sdram_params *sdram_params) { unsigned char dramtype = sdram_params->dramtype; @@ -1016,6 +1046,8 @@ void sdram_init(const struct rk3399_sdram_params *sdram_params) sdram_params->ch[channel].ddrconfig); } dram_all_config(sdram_params); + switch_to_phy_index1(sdram_params); + printk(BIOS_INFO, "Finish SDRAM initialization...\n"); }

1 0

Patch set updated for coreboot: rockchip/rk3399: display: Do not allocate framebuffer in coreboot
by Patrick Georgi 02 Nov '16

02 Nov '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17109 -gerrit commit a6930e3d0fed37d1ab7c012ea2d634fc1017c4e9 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Oct 20 14:22:11 2016 -0700 rockchip/rk3399: display: Do not allocate framebuffer in coreboot framebuffer address is dynamically chosen by libpayload now, so there's no need to configure it in coreboot. CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, dev screen is visible Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/401401 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/devicetree.cb | 1 - src/soc/rockchip/common/include/soc/vop.h | 3 ++- src/soc/rockchip/common/vop.c | 21 +++++++++++------- src/soc/rockchip/rk3288/display.c | 3 ++- src/soc/rockchip/rk3399/chip.h | 1 - src/soc/rockchip/rk3399/display.c | 28 +++++++++--------------- src/soc/rockchip/rk3399/include/soc/display.h | 3 +-- src/soc/rockchip/rk3399/include/soc/memlayout.ld | 1 - src/soc/rockchip/rk3399/soc.c | 3 +-- 9 files changed, 29 insertions(+), 35 deletions(-) diff --git a/src/mainboard/google/gru/devicetree.cb b/src/mainboard/google/gru/devicetree.cb index 7a421b2..6f177ed 100644 --- a/src/mainboard/google/gru/devicetree.cb +++ b/src/mainboard/google/gru/devicetree.cb @@ -15,7 +15,6 @@ chip soc/rockchip/rk3399 device cpu_cluster 0 on end - register "vop_id" = "0" register "vop_mode" = "VOP_MODE_EDP" register "framebuffer_bits_per_pixel" = "32" end diff --git a/src/soc/rockchip/common/include/soc/vop.h b/src/soc/rockchip/common/include/soc/vop.h index f5ce431..98ad082 100644 --- a/src/soc/rockchip/common/include/soc/vop.h +++ b/src/soc/rockchip/common/include/soc/vop.h @@ -376,5 +376,6 @@ enum vop_modes { #define V_VASP(x) (((x)&0x1fff)<<16) void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode); -void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid); +void rkvop_prepare(u32 vop_id, const struct edid *edid); +void rkvop_enable(u32 vop_id, u32 fbbase); #endif diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 668bee0..629072e 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -30,7 +30,19 @@ static struct rockchip_vop_regs * const vop_regs[] = { (struct rockchip_vop_regs *)VOP_LIT_BASE }; -void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) +void rkvop_enable(u32 vop_id, u32 fbbase) +{ + struct rockchip_vop_regs *preg = vop_regs[vop_id]; + + write32(&preg->win0_yrgb_mst, fbbase); + + /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only, + * but it's fine to write to it + */ + write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */ +} + +void rkvop_prepare(u32 vop_id, const struct edid *edid) { u32 lb_mode; u32 rgb_mode; @@ -85,13 +97,6 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); - - write32(&preg->win0_yrgb_mst, fbbase); - - /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only, - * but it's fine to write to it - */ - write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */ } void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index f3dfac1..30c8ca1 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -108,7 +108,8 @@ void rk_display_init(device_t dev, u32 lcdbase, conf->framebuffer_bits_per_pixel, 0); rkvop_mode_set(conf->vop_id, &edid, detected_mode); - rkvop_enable(conf->vop_id, lcdbase, &edid); + rkvop_prepare(conf->vop_id, &edid); + rkvop_enable(conf->vop_id, lcdbase); switch (detected_mode) { case VOP_MODE_HDMI: diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h index 46baa8c..1f9462a 100644 --- a/src/soc/rockchip/rk3399/chip.h +++ b/src/soc/rockchip/rk3399/chip.h @@ -20,7 +20,6 @@ #include <soc/vop.h> /* for vop_modes enum used in devicetree.cb */ struct soc_rockchip_rk3399_config { - u32 vop_id; gpio_t lcd_bl_pwm_gpio; gpio_t lcd_bl_en_gpio; u32 bl_power_on_udelay; diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 2679860..372e115 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -36,20 +36,14 @@ #include "chip.h" -void rk_display_init(device_t dev, uintptr_t lcdbase, - unsigned long fb_size) +void rk_display_init(device_t dev) { struct edid edid; - uint32_t val; struct soc_rockchip_rk3399_config *conf = dev->chip_info; - uintptr_t lower = ALIGN_DOWN(lcdbase, MiB); - uintptr_t upper = ALIGN_UP(lcdbase + fb_size, MiB); enum vop_modes detected_mode = VOP_MODE_UNKNOWN; - printk(BIOS_DEBUG, "LCD framebuffer @%p\n", (void *)(lcdbase)); - memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ - dcache_clean_invalidate_by_mva((void *)lower, upper - lower); - mmu_config_range((void *)lower, upper - lower, UNCACHED_MEM); + /* let's use vop0 in rk3399 */ + uint32_t vop_id = 0; switch (conf->vop_mode) { case VOP_MODE_NONE: @@ -58,12 +52,10 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, /* try EDP first, then HDMI */ case VOP_MODE_EDP: printk(BIOS_DEBUG, "Attempting to set up EDP display.\n"); - rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); + rkclk_configure_vop_aclk(vop_id, 192 * MHz); - /* select edp signal from vop0(big) or vop1(little) */ - val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) : - RK_CLRBITS(1 << 5); - write32(&rk3399_grf->soc_con20, val); + /* select edp signal from vop0 */ + write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5)); /* select edp clk from SoC internal 24M crystal, otherwise, * it will source from edp's 24M clock (that depends on @@ -89,7 +81,7 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, return; } - if (rkclk_configure_vop_dclk(conf->vop_id, + if (rkclk_configure_vop_dclk(vop_id, edid.mode.pixel_clock * KHz)) { printk(BIOS_WARNING, "config vop err\n"); return; @@ -97,9 +89,9 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, edid_set_framebuffer_bits_per_pixel(&edid, conf->framebuffer_bits_per_pixel, 0); - rkvop_mode_set(conf->vop_id, &edid, detected_mode); + rkvop_mode_set(vop_id, &edid, detected_mode); - rkvop_enable(conf->vop_id, lcdbase, &edid); + rkvop_prepare(vop_id, &edid); switch (detected_mode) { case VOP_MODE_HDMI: @@ -115,5 +107,5 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, break; } - set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); + set_vbe_mode_info_valid(&edid, (uintptr_t)0); } diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h index 7ccde56..c10f1b9 100644 --- a/src/soc/rockchip/rk3399/include/soc/display.h +++ b/src/soc/rockchip/rk3399/include/soc/display.h @@ -18,8 +18,7 @@ #define REF_CLK_24M (0x1 << 0) -void rk_display_init(device_t dev, uintptr_t lcdbase, - unsigned long fb_size); +void rk_display_init(device_t dev); void mainboard_power_on_backlight(void); #endif diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index a441281..f440dfb 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -22,7 +22,6 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00100000, 1M) RAMSTAGE(0x00300000, 256K) DMA_COHERENT(0x10000000, 2M) - FRAMEBUFFER(0x10200000, 16M) /* 8K of special SRAM in PMU power domain. */ SYMBOL(pmu_sram, 0xFF3B0000) diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 12c757f..e34ca09 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -39,8 +39,7 @@ static void soc_init(device_t dev) mmio_resource(dev, 1, (0x10000 / KiB), (0x80000 / KiB)); if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required()) - rk_display_init(dev, (uintptr_t)_framebuffer, - _framebuffer_size); + rk_display_init(dev); else printk(BIOS_INFO, "Display initialization disabled.\n");

1 0

Patch merged into coreboot/master: rockchip/rk3399: Reserve enough framebuffer memory for 32bpp hires panels
by gerrit＠coreboot.org 02 Nov '16

02 Nov '16

the following patch was just integrated into master: commit 1f60007be8d6dc10805aa094682a7890df727663 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 17 17:29:09 2016 -0700 rockchip/rk3399: Reserve enough framebuffer memory for 32bpp hires panels Some of our RK3399 devices have panel resolutions as high as 2400x1600. With 16bpp that barely still fit into an 8MB framebuffer, but then we changed it to 32bpp for better image quality... Note that this is a band-aid. Coreboot-allocated framebuffers shouldn't be used at all on ARM64 devices, since libpayload is perfectly capable to dynamically allocate it with the right size based on EDID-information on this architecture. That will require some more elaborate work to be fixed with later patches. BRANCH=gru BUG=chrome-os-partner:58044 TEST=Warm-reboot Kevin on the dev screen, confirm that you don't see the lower half of the screen that overflowed our allocated framebuffer preserved from the last boot as soon as the backlight turns on. Change-Id: I00a63cfef35a8ee734543abbdb298344fb529283 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d2718efcacb50371624d9f6a3b586c298e8c2fec Original-Change-Id: Ia1fa28971c65d7d0639966e715f742309245172b Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/399966 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> Reviewed-on: https://review.coreboot.org/17108 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17108 for details. -gerrit

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coreboot-gerrit November 2016