coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control
by Sumeet R Pawnikar 02 Nov '16

02 Nov '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17067 -gerrit commit 8fbe1f29acb0cf5512524750756edfb2a73c47da Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Oct 18 10:57:58 2016 +0530 soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control This patch updates below info, [1] Delete the DPTF_CPU_ACTIVE_AC* values because these are not being used. Hence, removing unnecessary defines. [2] Add new DPTF_TSR0_ACTIVE_AC* temperature trip points for TSR0 external thermal sensor. These trip points are being used by _ACx methods to control the fan speed on Skylake-U fan based Lars and Kunimitsu platforms. [3] Follow up patches are using DPTF_CPU_ACTIVE_AC* temperature trip points in board specific acpi/dptf.asl (for lars, kunimitsu, etc) to control the fan speed as per the CPU temperature trip points. [4] Newly added _ACx methods for thermal sensor TSR0 in this patch has nothing to do with DPTF_CPU_ACTIVE_AC*. We can control fan speed using various different thermal sensors. In this patch, we have added new _ACx methods for TSR0 thermal sensor. We run the fan at different speeds to cool down the system at different TSR0 temperatures. Similarly, we considered CPU sensor temperature values and ran the fan at different speeds to cool down the system. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on kunimitsu and lars EVT boards. Verified these _ACx methods with _ART table on these boards with different workloads. Change-Id: Ia7b81e03da936c4a0f69057e43f18efd7c3b9f17 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/332368 --- src/soc/intel/skylake/acpi/dptf/cpu.asl | 20 ---------------- src/soc/intel/skylake/acpi/dptf/thermal.asl | 37 +++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 20 deletions(-) diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl index 32e8863..6278b9f 100644 --- a/src/soc/intel/skylake/acpi/dptf/cpu.asl +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -22,26 +22,6 @@ #define DPTF_CPU_CRITICAL 90 #endif -#ifndef DPTF_CPU_ACTIVE_AC0 -#define DPTF_CPU_ACTIVE_AC0 90 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC1 -#define DPTF_CPU_ACTIVE_AC1 80 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC2 -#define DPTF_CPU_ACTIVE_AC2 70 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC3 -#define DPTF_CPU_ACTIVE_AC3 60 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC4 -#define DPTF_CPU_ACTIVE_AC4 50 -#endif - External (\_PR.CP00._PSS, PkgObj) External (\_PR.CP00._TSS, PkgObj) External (\_PR.CP00._TPC, MethodObj) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 97484e5..a171eb1 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -111,6 +111,43 @@ Device (TSR0) { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0)) + } + + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1)) + } + + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2)) + } + + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3)) + } + + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4)) + } + + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5)) + } + + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6)) + } +#endif } #endif

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Patch set updated for coreboot: src/mainboard/*/*/spd.h: Correct SPD_DRAM_LPDDR3 type
by HAOUAS Elyes 02 Nov '16

02 Nov '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17206 -gerrit commit 0b7e11b2b33592d5b8128995c39cde11bd032bc5 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Nov 2 08:26:37 2016 +0100 src/mainboard/*/*/spd.h: Correct SPD_DRAM_LPDDR3 type Regarding JEDEC Standard No. 21-C, Annex M: Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 1 Key Byte / DRAM Device Type for LPDDR3 is 0x0f Change-Id: Ic90a1381900b6f6a5b970a14f9490061b1303b5e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/google/auron/spd/spd.h | 2 +- src/mainboard/google/auron_paine/spd/spd.h | 2 +- src/mainboard/google/chell/spd/spd.h | 2 +- src/mainboard/google/eve/spd/spd.h | 2 +- src/mainboard/google/glados/spd/spd.h | 2 +- src/mainboard/google/lars/spd/spd.h | 2 +- src/mainboard/google/samus/spd/spd.h | 2 +- src/mainboard/intel/kunimitsu/spd/spd.h | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/google/auron/spd/spd.h b/src/mainboard/google/auron/spd/spd.h index cbb463f..44b1e45 100644 --- a/src/mainboard/google/auron/spd/spd.h +++ b/src/mainboard/google/auron/spd/spd.h @@ -20,7 +20,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/auron_paine/spd/spd.h b/src/mainboard/google/auron_paine/spd/spd.h index 09a48fd..7863f7d 100644 --- a/src/mainboard/google/auron_paine/spd/spd.h +++ b/src/mainboard/google/auron_paine/spd/spd.h @@ -20,7 +20,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/chell/spd/spd.h b/src/mainboard/google/chell/spd/spd.h index c8e7b33..6166064 100644 --- a/src/mainboard/google/chell/spd/spd.h +++ b/src/mainboard/google/chell/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h index 9c2b26b..182c4fd 100644 --- a/src/mainboard/google/eve/spd/spd.h +++ b/src/mainboard/google/eve/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h index c8e7b33..6166064 100644 --- a/src/mainboard/google/glados/spd/spd.h +++ b/src/mainboard/google/glados/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/lars/spd/spd.h b/src/mainboard/google/lars/spd/spd.h index d71487b..bb73716 100644 --- a/src/mainboard/google/lars/spd/spd.h +++ b/src/mainboard/google/lars/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index dbfd6a0..dbb0c7f 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -20,7 +20,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index f53c9ec..29d3735 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -25,7 +25,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7

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New patch to review for coreboot: src/mainboard/*/*/spd.h: Correct SPD_DRAM_LPDDR3 type
by HAOUAS Elyes 02 Nov '16

02 Nov '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17206 -gerrit commit 9996ae2fb77bd12a783fce1a7e192a000b5ce1b0 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Nov 2 08:26:37 2016 +0100 src/mainboard/*/*/spd.h: Correct SPD_DRAM_LPDDR3 type Regarding JEDEC Standard No. 21-C, Annex M: Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 1 Key Byte / DRAM Device Type for LPDDR3 is 0x0f Change-Id: Ic90a1381900b6f6a5b970a14f9490061b1303b5e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/mainboard/google/auron/spd/spd.h | 2 +- src/mainboard/google/auron_paine/spd/spd.h | 2 +- src/mainboard/google/chell/spd/spd.h | 2 +- src/mainboard/google/eve/spd/spd.h | 2 +- src/mainboard/google/glados/spd/spd.h | 2 +- src/mainboard/google/lars/spd/spd.h | 2 +- src/mainboard/google/samus/spd/spd.h | 2 +- src/mainboard/intel/kblrvp/spd/spd.h | 2 +- src/mainboard/intel/kunimitsu/spd/spd.h | 2 +- 9 files changed, 9 insertions(+), 9 deletions(-) diff --git a/src/mainboard/google/auron/spd/spd.h b/src/mainboard/google/auron/spd/spd.h index cbb463f..44b1e45 100644 --- a/src/mainboard/google/auron/spd/spd.h +++ b/src/mainboard/google/auron/spd/spd.h @@ -20,7 +20,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/auron_paine/spd/spd.h b/src/mainboard/google/auron_paine/spd/spd.h index 09a48fd..7863f7d 100644 --- a/src/mainboard/google/auron_paine/spd/spd.h +++ b/src/mainboard/google/auron_paine/spd/spd.h @@ -20,7 +20,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/chell/spd/spd.h b/src/mainboard/google/chell/spd/spd.h index c8e7b33..6166064 100644 --- a/src/mainboard/google/chell/spd/spd.h +++ b/src/mainboard/google/chell/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/eve/spd/spd.h b/src/mainboard/google/eve/spd/spd.h index 9c2b26b..182c4fd 100644 --- a/src/mainboard/google/eve/spd/spd.h +++ b/src/mainboard/google/eve/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/glados/spd/spd.h b/src/mainboard/google/glados/spd/spd.h index c8e7b33..6166064 100644 --- a/src/mainboard/google/glados/spd/spd.h +++ b/src/mainboard/google/glados/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/lars/spd/spd.h b/src/mainboard/google/lars/spd/spd.h index d71487b..bb73716 100644 --- a/src/mainboard/google/lars/spd/spd.h +++ b/src/mainboard/google/lars/spd/spd.h @@ -21,7 +21,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/google/samus/spd/spd.h b/src/mainboard/google/samus/spd/spd.h index dbfd6a0..dbb0c7f 100644 --- a/src/mainboard/google/samus/spd/spd.h +++ b/src/mainboard/google/samus/spd/spd.h @@ -20,7 +20,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index e04d13c..0ae23aa 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -25,7 +25,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 diff --git a/src/mainboard/intel/kunimitsu/spd/spd.h b/src/mainboard/intel/kunimitsu/spd/spd.h index f53c9ec..29d3735 100644 --- a/src/mainboard/intel/kunimitsu/spd/spd.h +++ b/src/mainboard/intel/kunimitsu/spd/spd.h @@ -25,7 +25,7 @@ #define SPD_DRAM_TYPE 2 #define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_LPDDR3 0x0f #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7

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New patch to review for coreboot: soc/intel/apollolake: Implement SPI flash status register read
by Furquan Shaikh 02 Nov '16

02 Nov '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17205 -gerrit commit d242beb6e61e8fcf3c64eedbc9c5b8d4689af225 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Nov 1 21:33:12 2016 -0700 soc/intel/apollolake: Implement SPI flash status register read This was a dummy implementation until now which returned -1 always. Add support for reading SPI flash status register (srp0). BUG=chrome-os-partner:59267 BRANCH=None TEST=Verified by enabling and disabling write-protect on reef that the value of SRP0 changes accordingly in status register read. Change-Id: Ib1349605dd87c4a087e416f52a8256b1eaac4f4c Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/apollolake/spi.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/spi.c b/src/soc/intel/apollolake/spi.c index 85bc0b6..8cb8aa5 100644 --- a/src/soc/intel/apollolake/spi.c +++ b/src/soc/intel/apollolake/spi.c @@ -313,8 +313,16 @@ static int nuclear_spi_write(struct spi_flash *flash, static int nuclear_spi_status(struct spi_flash *flash, uint8_t *reg) { - printk(BIOS_DEBUG, "NOT IMPLEMENTED: %s() !!!\n", __func__); - return E_NOT_IMPLEMENTED; + int ret; + BOILERPLATE_CREATE_CTX(ctx); + + ret = exec_sync_hwseq_xfer(ctx, SPIBAR_HSFSTS_CYCLE_RD_STATUS, 0, + sizeof(*reg)); + if (ret != SUCCESS) + return ret; + + drain_xfer_fifo(ctx, reg, sizeof(*reg)); + return ret; } static struct spi_slave boot_spi CAR_GLOBAL;

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Patch set updated for coreboot: mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.c
by Naresh Solanki 02 Nov '16

02 Nov '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17161 -gerrit commit 0fac98ae252058595ad94929b30b7ffdb35f0310 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Thu Oct 27 20:28:23 2016 +0530 mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.c 1. Update gpio.h to set proper pad config for Kaby Lake RVP3. 2. Set spd index to zero. 3. Remove nhlt specific init. Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kblrvp/gpio.h | 248 +++++++++++++----------------- src/mainboard/intel/kblrvp/mainboard.c | 62 -------- src/mainboard/intel/kblrvp/spd/spd.h | 22 +-- src/mainboard/intel/kblrvp/spd/spd_util.c | 30 +--- 4 files changed, 111 insertions(+), 251 deletions(-) diff --git a/src/mainboard/intel/kblrvp/gpio.h b/src/mainboard/intel/kblrvp/gpio.h index 0e03080..f8ee994 100644 --- a/src/mainboard/intel/kblrvp/gpio.h +++ b/src/mainboard/intel/kblrvp/gpio.h @@ -20,183 +20,148 @@ #include <soc/gpe.h> #include <soc/gpio.h> -/* EC in RW */ -#define GPIO_EC_IN_RW GPP_C6 - -/* BIOS Flash Write Protect */ -#define GPIO_PCH_WP GPP_C23 - -/* Memory configuration board straps */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C13 -#define GPIO_MEM_CONFIG_2 GPP_C14 -#define GPIO_MEM_CONFIG_3 GPP_C15 - /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK -/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */ -#define GPE_WLAN_WAKE GPE0_DW0_16 - -/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */ -#define GPE_TOUCHPAD_WAKE GPE0_DW0_05 - -/* Input device interrupt configuration */ -#define TOUCHPAD_INT_L GPP_B3_IRQ -#define TOUCHSCREEN_INT_L GPP_E7_IRQ -#define MIC_INT_L GPP_F10_IRQ - /* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */ #define EC_SCI_GPI GPE0_DW2_16 #define EC_SMI_GPI GPP_E15 -/* - * GPP_E3 is AUDIO_DB_ID. - * It is a dual purpose GPIO, used for Audio Daughter - * Board Identification & to control the shutdown mode pin - * of the Maxim amp. - */ -#define AUDIO_DB_ID GPP_E3 - -/* SD controller needs additional card detect GPIO to support RTD3 */ -#define GPIO_SD_CARD_DETECT GPP_A7 - #ifndef __ACPI__ /* Pad configuration in ramstage. */ static const struct pad_config gpio_table[] = { -/* EC_PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), -/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1), -/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1), -/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1), -/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1), +/* PCH_RCIN */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), +/* LPC_LAD_0 */ PAD_CFG_NF(GPP_A1, 20K_PD, DEEP, NF1), +/* LPC_LAD_1 */ PAD_CFG_NF(GPP_A2, 20K_PD, DEEP, NF1), +/* LPC_LAD_2 */ PAD_CFG_NF(GPP_A3, 20K_PD, DEEP, NF1), +/* LPC_LAD_3 */ PAD_CFG_NF(GPP_A4, 20K_PD, DEEP, NF1), /* LPC_FRAME */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* LPC_SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -/* SD_CD_WAKE */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), +/* PM_SLP_S0ix_N */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP), /* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), -/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), +/* LPC_CLK */ PAD_CFG_NF(GPP_A9, 20K_PD, DEEP, NF1), /* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10), /* EC_HID_INT */ PAD_CFG_NC(GPP_A11), /* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12), /* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1), /* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14), -/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), +/* SUSACK_R_N */ PAD_CFG_NF(GPP_A15, 20K_PD, DEEP, NF1), /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), /* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), -/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18), +/* ISH_GP0 */ PAD_CFG_NC(GPP_A18), /* ISH_GP1 */ PAD_CFG_NC(GPP_A19), -/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20), -/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21), -/* GYRO_INT */ PAD_CFG_NC(GPP_A22), +/* ISH_GP2 */ PAD_CFG_NC(GPP_A20), +/* ISH_GP3 */ PAD_CFG_NC(GPP_A21), +/* ISH_GP4 */ PAD_CFG_NC(GPP_A22), /* ISH_GP5 */ PAD_CFG_NC(GPP_A23), -/* CORE_VID0 */ PAD_CFG_NC(GPP_B0), -/* CORE_VID1 */ PAD_CFG_NC(GPP_B1), -/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), -/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), -/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4), -/* TOUCHPAD WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), -/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), -/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), -/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES), -/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), -/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10), -/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11), +/* V0.85A_VID0 */ PAD_CFG_NC(GPP_B0), +/* V0.85A_VID1 */ PAD_CFG_NC(GPP_B1), +/* GP_VRALERTB */ PAD_CFG_GPI(GPP_B2, NONE, DEEP), +/* TCH_PAD_INTR */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST), +/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 1, DEEP), +/* CLK_REQ_SLOT0 */ PAD_CFG_NC(GPP_B5), +/* CLK_REQ_SLOT1 */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), +/* CLK_REQ_SLOT2 */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), +/* CLK_REQ_SLOT3 */ PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), +/* CLK_REQ_SLOT4 */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), +/* CLK_REQ_SLOT5 */ PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), +/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), -/* PCH_BUZZER */ PAD_CFG_GPI(GPP_B14, NONE, DEEP), -/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15), +/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_B14, 1, DEEP), +/* GSPI0_CS# */ /* GPP_B15 */ /* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES), -/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17), -/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18), -/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19), -/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20), -/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21), -/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22), -/* SM1ALERT# */ PAD_CFG_NC(GPP_B23), +/* TBT_CIO */ PAD_CFG_NC(GPP_B17), +/* SLOT1_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B18, 20K_PU, DEEP, YES), +/* GSPI1_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), +/* GSPI1_CLK */ PAD_CFG_NF(GPP_B20, 20K_PD, DEEP, NF1), +/* GSPI1_MISO */ PAD_CFG_NF(GPP_B21, 20K_PD, DEEP, NF1), +/* GSPI1_MOSI */ PAD_CFG_NF(GPP_B22, 20K_PD, DEEP, NF1), +/* GNSS_RESET */ PAD_CFG_GPO(GPP_B23, 1, DEEP), /* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), -/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), -/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP), -/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3), -/* SML0DATA */ PAD_CFG_NC(GPP_C4), -/* SML0ALERT# */ PAD_CFG_NC(GPP_C5), -/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP), -/* USB_CTL */ PAD_CFG_NC(GPP_C7), -/* UART0_RXD */ PAD_CFG_NC(GPP_C8), -/* UART0_TXD */ PAD_CFG_NC(GPP_C9), -/* NFC_RST* */ PAD_CFG_NC(GPP_C10), -/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP), -/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), -/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), -/* PCH_MEM_CFG2 */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), -/* PCH_MEM_CFG3 */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), +/* SMB_DATA */ PAD_CFG_NF(GPP_C1, 20K_PD, DEEP, NF1), +/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 1, DEEP), +/* SML0_CLK */ PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), +/* SML0DATA */ PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), +/* SML0ALERT# */ PAD_CFG_GPI_APIC(GPP_C5, 20K_PD, PLTRST), +/* SML1_CLK */ PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), +/* SML1_DATA */ PAD_CFG_NF(GPP_C7, 20K_PD, DEEP, NF1), +/* UART0_RXD */ PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), +/* UART0_TXD */ PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), +/* UART0_RTS */ PAD_CFG_NF(GPP_C10, NONE, DEEP, NF1), +/* UART0_CTS */ PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), +/* UART1_RXD */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), +/* UART1_TXD */ PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1), +/* UART1_RTS */ PAD_CFG_NF(GPP_C14, NONE, DEEP, NF1), +/* UART1_CTS */ PAD_CFG_NF(GPP_C15, NONE, DEEP, NF1), /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, 5K_PU, DEEP, NF1), /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, 5K_PU, DEEP, NF1), /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), -/* GD_UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), -/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), -/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP), -/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), -/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0), -/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1), -/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2), -/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3), -/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4), -/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5), -/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6), -/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7), -/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8), -/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9), -/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 0, DEEP), -/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 0, DEEP), -/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12), -/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13), -/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14), -/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15), -/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16), +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), +/* UART2_RTS */ PAD_CFG_NF(GPP_C22, NONE, DEEP, NF1), +/* UART2_CTS */ PAD_CFG_NF(GPP_C23, NONE, DEEP, NF1), +/* SPI1_CS */ PAD_CFG_NF(GPP_D0, NONE, DEEP, NF1), +/* SPI1_CLK */ PAD_CFG_NF(GPP_D1, NONE, DEEP, NF1), +/* SPI1_MISO */ PAD_CFG_NF(GPP_D2, NONE, DEEP, NF1), +/* SPI1_MOSI */ PAD_CFG_NF(GPP_D3, NONE, DEEP, NF1), +/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1), +/* ISH_I2C0_SDA */ PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), +/* ISH_I2C0_SCL */ PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +/* ISH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), +/* ISH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), +/* HOME_BTN */ PAD_CFG_GPI(GPP_D9, NONE, DEEP), +/* SCREEN_LOCK */ PAD_CFG_GPI(GPP_D10, NONE, DEEP), +/* VOL_UP_PCH */ PAD_CFG_GPI(GPP_D11, NONE, DEEP), +/* VOL_DOWN_PCH */ PAD_CFG_GPI(GPP_D12, NONE, DEEP), +/* ISH_UART0_RXD */ PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), +/* ISH_UART0_TXD */ PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), +/* ISH_UART0_RTS */ PAD_CFG_NF(GPP_D15, NONE, DEEP, NF1), +/* ISH_UART0_CTS */ PAD_CFG_NF(GPP_D16, NONE, DEEP, NF1), /* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), -/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), +/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, 20K_PD, DEEP, NF1), /* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), -/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), -/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21), -/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22), +/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, 20K_PD, DEEP, NF1), +/* SPI1_D2 */ PAD_CFG_NF(GPP_D21, NONE, DEEP, NF1), +/* SPI1_D3 */ PAD_CFG_NF(GPP_D22, NONE, DEEP, NF1), /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1), /* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), -/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1), -/* SSD_PEDET */ PAD_CFG_NC(GPP_E2), -/* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP), -/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4), -/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5), -/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6), +/* SATAXPCIE1 */ PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), +/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP), +/* EINK_SSR_DFU_N */ PAD_CFG_GPO(GPP_E3, 1, DEEP), +/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP), +/* SATA_DEVSLP1 */ PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), +/* SATA_DEVSLP2 */ /* GPP_E6 */ /* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST), -/* SATALED# */ PAD_CFG_NC(GPP_E8), +/* SATALED# */ PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), /* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), -/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), +/* USB2_OC_3 */ PAD_CFG_GPI_APIC(GPP_E12, NONE, PLTRST), /* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES), /* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES), /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), -/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18), -/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), -/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20), -/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), - -/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22), +/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), +/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, 20K_PD, DEEP, NF1), +/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), +/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, 20K_PD, DEEP, NF1), +/* DDPD_CTRLCLK */ PAD_CFG_GPI_APIC(GPP_E22, NONE, DEEP), /* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP), -/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0), -/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1), -/* I2S2_TXD */ PAD_CFG_NC(GPP_F2), -/* I2S2_RXD */ PAD_CFG_NC(GPP_F3), -/* I2C2_SDA */ PAD_CFG_NC(GPP_F4), -/* I2C2_SCL */ PAD_CFG_NC(GPP_F5), -/* I2C3_SDA */ PAD_CFG_NC(GPP_F6), -/* I2C3_SCL */ PAD_CFG_NC(GPP_F7), +/* I2S2_SCLK */ PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), +/* I2S2_SFRM */ PAD_CFG_NF(GPP_F1, NONE, DEEP, NF1), +/* I2S2_TXD */ PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), +/* I2S2_RXD */ PAD_CFG_NF(GPP_F3, NONE, DEEP, NF1), +/* I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F4, NONE, DEEP, NF1), +/* I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F5, NONE, DEEP, NF1), +/* I2C3_SDA */ PAD_CFG_NF_1V8(GPP_F6, NONE, DEEP, NF1), +/* I2C3_SCL */ PAD_CFG_NF_1V8(GPP_F7, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1), /* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1), -/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), -/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES), +/* ISH_I2C2_SDA */ PAD_CFG_NF_1V8(GPP_F10, NONE, DEEP, NF2), +/* ISH_I2C2_SCL */ PAD_CFG_NF_1V8(GPP_F11, NONE, DEEP, NF2), /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), @@ -208,7 +173,7 @@ static const struct pad_config gpio_table[] = { /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), -/* BOOT_BEEP */ PAD_CFG_GPO(GPP_F23, 0, DEEP), +/* UIM_SIM_DET */ PAD_CFG_GPI_APIC(GPP_F23, NONE, DEEP), /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1), /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1), /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1), @@ -218,26 +183,25 @@ static const struct pad_config gpio_table[] = { /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1), /* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1), /* PCH_BATLOW */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1), -/* EC_PCH_ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), -/* EC_PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), -/* EC_PCH_PWRBTN */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1), +/* AC_PRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1), +/* PCH_WAKE */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), +/* PCH_PWRBTN */ PAD_CFG_NF(GPD3, 20K_PD, DEEP, NF1), /* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1), /* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1), /* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1), /* GPD7 */ PAD_CFG_NC(GPD7), /* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1), -/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9), -/* PM_SLP_S5# */ PAD_CFG_NC(GPD10), -/* LANPHYC */ PAD_CFG_NC(GPD11), +/* PCH_SLP_WLAN# */ PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1), +/* LANPHYC */ PAD_CFG_NF(GPD11, NONE, DEEP, NF1), }; /* Early pad configuration in romstage. */ static const struct pad_config early_gpio_table[] = { -/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */ -/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), -/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */ +/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), +/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), }; #endif -#endif +#endif \ No newline at end of file diff --git a/src/mainboard/intel/kblrvp/mainboard.c b/src/mainboard/intel/kblrvp/mainboard.c index fe4fb3a..cd6c3f9 100644 --- a/src/mainboard/intel/kblrvp/mainboard.c +++ b/src/mainboard/intel/kblrvp/mainboard.c @@ -26,73 +26,12 @@ #include "ec.h" #include "gpio.h" -static const char *oem_id_maxim = "INTEL"; -static const char *oem_table_id_maxim = "SCRDMAX"; - static void mainboard_init(device_t dev) { if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC)) mainboard_ec_init(); } -static uint8_t select_audio_codec(void) -{ - int audio_db_sel = gpio_get(AUDIO_DB_ID); - - return audio_db_sel; -} - -static unsigned long mainboard_write_acpi_tables( - device_t device, unsigned long current, acpi_rsdp_t *rsdp) -{ - uintptr_t start_addr; - uintptr_t end_addr; - struct nhlt *nhlt; - const char *oem_id = NULL; - const char *oem_table_id = NULL; - - start_addr = current; - - nhlt = nhlt_init(); - - if (nhlt == NULL) - return start_addr; - - /* 2 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 2)) - printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); - - - /* 4 Channel DMIC array. */ - if (nhlt_soc_add_dmic_array(nhlt, 4)) - printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); - - if (select_audio_codec()) { - /* ADI Smart Amps for left and right. */ - if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0)) - printk(BIOS_ERR, "Couldn't add ssm4567.\n"); - } else { - /* MAXIM Smart Amps for left and right. */ - if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) - printk(BIOS_ERR, "Couldn't add max98357.\n"); - - oem_id = oem_id_maxim; - oem_table_id = oem_table_id_maxim; - } - - /* NAU88l25 Headset codec. */ - if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1)) - printk(BIOS_ERR, "Couldn't add headset codec.\n"); - - end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, - oem_id, oem_table_id); - - if (end_addr != start_addr) - acpi_add_table(rsdp, (void *)start_addr); - - return end_addr; -} - /* * mainboard_enable is executed as first thing after * enumerate_buses(). @@ -100,7 +39,6 @@ static unsigned long mainboard_write_acpi_tables( static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; - dev->ops->write_acpi_tables = mainboard_write_acpi_tables; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; } diff --git a/src/mainboard/intel/kblrvp/spd/spd.h b/src/mainboard/intel/kblrvp/spd/spd.h index e04d13c..6199fb5 100644 --- a/src/mainboard/intel/kblrvp/spd/spd.h +++ b/src/mainboard/intel/kblrvp/spd/spd.h @@ -24,8 +24,8 @@ #define SPD_LEN 256 #define SPD_DRAM_TYPE 2 -#define SPD_DRAM_DDR3 0x0b -#define SPD_DRAM_LPDDR3 0xf1 +#define SPD_DRAM_DDR3 0x0B +#define SPD_DRAM_LPDDR3 0x0F #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 #define SPD_ORGANIZATION 7 @@ -34,26 +34,8 @@ #define SPD_PART_LEN 18 #define SPD_MANU_OFF 148 -#define HYNIX_SINGLE_CHAN 0x1 -#define SAMSUNG_SINGLE_CHAN 0x4 -#define MIC_SINGLE_CHAN 0x5 - -/* PCH_MEM_CFG[3:0] */ -#define MAX_MEMORY_CONFIG 0x10 #define RCOMP_TARGET_PARAMS 0x5 -#define K4E6E304EE_MEM_ID 0x3 -static inline int get_spd_index(void) -{ - /* PCH_MEM_CFG[3:0] */ - gpio_t spd_gpios[] = { - GPIO_MEM_CONFIG_0, - GPIO_MEM_CONFIG_1, - GPIO_MEM_CONFIG_2, - GPIO_MEM_CONFIG_3, - }; - return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); -} void mainboard_fill_dq_map_data(void *dq_map_ptr); void mainboard_fill_dqs_map_data(void *dqs_map_ptr); void mainboard_fill_rcomp_res_data(void *rcomp_ptr); diff --git a/src/mainboard/intel/kblrvp/spd/spd_util.c b/src/mainboard/intel/kblrvp/spd/spd_util.c index fc0581c..68bdb48 100644 --- a/src/mainboard/intel/kblrvp/spd/spd_util.c +++ b/src/mainboard/intel/kblrvp/spd/spd_util.c @@ -52,25 +52,11 @@ void mainboard_fill_rcomp_res_data(void *rcomp_ptr) void mainboard_fill_rcomp_strength_data(void *rcomp_strength_ptr) { - int mem_cfg_id; - - mem_cfg_id = get_spd_index(); /* Rcomp target */ static const u16 RcompTarget[RCOMP_TARGET_PARAMS] = { 100, 40, 40, 23, 40 }; - /* Strengthen the Rcomp Target Ctrl for 8GB K4E6E304EE -EGCF */ - static const u16 StrengthendRcompTarget[RCOMP_TARGET_PARAMS] = { - 100, 40, 40, 21, 40 }; - - - if (mem_cfg_id == K4E6E304EE_MEM_ID) { - memcpy(rcomp_strength_ptr, StrengthendRcompTarget, - sizeof(StrengthendRcompTarget)); - } else { - memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); - } - + memcpy(rcomp_strength_ptr, RcompTarget, sizeof(RcompTarget)); } uintptr_t mainboard_get_spd_data(void) @@ -79,7 +65,7 @@ uintptr_t mainboard_get_spd_data(void) int spd_index, spd_span; size_t spd_file_len; - spd_index = get_spd_index(); + spd_index = 0; printk(BIOS_INFO, "SPD index %d\n", spd_index); /* Load SPD data from CBFS */ @@ -104,15 +90,5 @@ uintptr_t mainboard_get_spd_data(void) int mainboard_has_dual_channel_mem(void) { - int spd_index; - - spd_index = get_spd_index(); - - if (spd_index != HYNIX_SINGLE_CHAN && spd_index != SAMSUNG_SINGLE_CHAN - && spd_index != MIC_SINGLE_CHAN) { - printk(BIOS_INFO, - "Dual channel SPD detected writing second channel\n"); - return 1; - } - return 0; + return 1; }

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New patch to review for coreboot: drivers/i2c/tpm/cr50: Increase IRQ timeout
by Duncan Laurie 01 Nov '16

01 Nov '16

Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17204 -gerrit commit 08eff339f107bf68efbf435c7c20f6c88f6372e2 Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Tue Nov 1 15:03:13 2016 -0700 drivers/i2c/tpm/cr50: Increase IRQ timeout Increase the IRQ timeout to prevent issues if there is a delay in the TPM responding to a command. BUG=chrome-os-partner:59191 TEST=suspend/resume testing on eve board Change-Id: I1ea7859bc7a056a450b2b0ee32153ae43ee8699f Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> --- src/drivers/i2c/tpm/cr50.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/tpm/cr50.c b/src/drivers/i2c/tpm/cr50.c index f7e667b..4b1f03b 100644 --- a/src/drivers/i2c/tpm/cr50.c +++ b/src/drivers/i2c/tpm/cr50.c @@ -48,6 +48,7 @@ #define CR50_MAX_BUFSIZE 63 #define CR50_TIMEOUT_LONG_MS 2000 /* Long timeout while waiting for TPM */ #define CR50_TIMEOUT_SHORT_MS 2 /* Short timeout during transactions */ +#define CR50_TIMEOUT_IRQ_MS 50 /* Timeout waiting for TPM ready */ #define CR50_DID_VID 0x00281ae0L struct tpm_inf_dev { @@ -65,11 +66,11 @@ static int cr50_i2c_wait_tpm_ready(struct tpm_chip *chip) if (!chip->vendor.irq_status) { /* Fixed delay if interrupt not supported */ - mdelay(CR50_TIMEOUT_SHORT_MS); + mdelay(CR50_TIMEOUT_IRQ_MS); return 0; } - stopwatch_init_msecs_expire(&sw, 5 * CR50_TIMEOUT_SHORT_MS); + stopwatch_init_msecs_expire(&sw, CR50_TIMEOUT_IRQ_MS); while (!chip->vendor.irq_status(chip->vendor.irq)) if (stopwatch_expired(&sw)) @@ -429,6 +430,11 @@ static void cr50_vendor_init(struct tpm_chip *chip) chip->vendor.irq = -1; #endif } + + if (chip->vendor.irq <= 0) + printk(BIOS_WARNING, + "%s: No IRQ, will use %ums delay for TPM ready\n", + __func__, CR50_TIMEOUT_IRQ_MS); } int tpm_vendor_probe(unsigned bus, uint32_t addr)

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Patch merged into coreboot/master: google/eve: Add new board
by gerrit＠coreboot.org 01 Nov '16

01 Nov '16

the following patch was just integrated into master: commit 81485d2763f461ce28dad2ffc43441c4bae570dd Author: Duncan Laurie <dlaurie(a)chromium.org> Date: Fri Oct 28 09:13:52 2016 -0700 google/eve: Add new board Add the eve board files using kabylake and FSP 2.0. BUG=chrome-os-partner:58666 TEST=build and boot on eve board Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-on: https://review.coreboot.org/17177 Reviewed-by: Furquan Shaikh <furquan(a)google.com> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17177 for details. -gerrit

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Patch set updated for coreboot: soc/intel/apollolake: Disable Monitor and Mwait feature
by Venkateswarlu V Vinjamuri 01 Nov '16

01 Nov '16

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17200 -gerrit commit d52fa3e0ca4320df6db898dc8591d3e9dea69d07 Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Mon Oct 31 17:03:55 2016 -0700 soc/intel/apollolake: Disable Monitor and Mwait feature Monitor/Mwait is broken on APL. So, it needs to be disabled. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I12cd4280de62e0a639b43538171660ee4c0a0265 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/include/cpu/intel/turbo.h | 3 +++ src/soc/intel/apollolake/cpu.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 8a93b3c..6626cb1 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -21,6 +21,9 @@ #define PM_CAP_TURBO_MODE (1 << 1) #define MSR_IA32_MISC_ENABLES 0x1a0 +/* Disable the Monitor Mwait FSM feature */ +#define MONITOR_MWAIT_DIS_MASK 0x40000 + #define H_MISC_DISABLE_TURBO (1 << 6) enum { diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index bd5cff5..6b5dee2 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -29,6 +29,7 @@ #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/smm.h> +#include <cpu/intel/turbo.h> static const struct reg_script core_msr_script[] = { /* Enable C-state and IO/MWAIT redirect */ @@ -40,6 +41,8 @@ static const struct reg_script core_msr_script[] = { (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + /* Disable support for MONITOR and MWAIT instructions */ + REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), REG_SCRIPT_END };

1 0

Patch set updated for coreboot: soc/intel/apollolake: Disable Monitor and Mwait feature
by Venkateswarlu V Vinjamuri 01 Nov '16

01 Nov '16

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17200 -gerrit commit a03e060cab4446b90fc3f1991b422c2f936b60c0 Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Mon Oct 31 17:03:55 2016 -0700 soc/intel/apollolake: Disable Monitor and Mwait feature Monitor/Mwait is broken on APL. So, it needs to be disabled. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I12cd4280de62e0a639b43538171660ee4c0a0265 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/soc/intel/apollolake/cpu.c | 3 +++ src/soc/intel/apollolake/include/soc/cpu.h | 2 ++ 2 files changed, 5 insertions(+) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index bd5cff5..6b5dee2 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -29,6 +29,7 @@ #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/smm.h> +#include <cpu/intel/turbo.h> static const struct reg_script core_msr_script[] = { /* Enable C-state and IO/MWAIT redirect */ @@ -40,6 +41,8 @@ static const struct reg_script core_msr_script[] = { (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + /* Disable support for MONITOR and MWAIT instructions */ + REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), REG_SCRIPT_END }; diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index e94972d..2ecab7f 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -62,6 +62,8 @@ void apollolake_init_cpus(struct device *dev); #define IO_MWAIT_REDIRECT_MASK 0x400 /* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ #define CST_CFG_LOCK_MASK 0x8000 +/* Disable the Monitor Mwait FSM feature */ +#define MONITOR_MWAIT_DIS_MASK 0x40000 #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4

1 0

Patch set updated for coreboot: soc/intel/apollolake: Disable Monitor and Mwait feature
by Venkateswarlu V Vinjamuri 01 Nov '16

01 Nov '16

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17200 -gerrit commit d075d4692a456ce3b612ad89d34c1b455cb95470 Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Mon Oct 31 17:03:55 2016 -0700 soc/intel/apollolake: Disable Monitor and Mwait feature Monitor/Mwait is broken on APL. So, it needs to be disabled. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I12cd4280de62e0a639b43538171660ee4c0a0265 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/soc/intel/apollolake/cpu.c | 4 ++++ src/soc/intel/apollolake/include/soc/cpu.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index bd5cff5..f6aa3a6 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -29,6 +29,7 @@ #include <soc/cpu.h> #include <soc/iomap.h> #include <soc/smm.h> +#include <cpu/intel/turbo.h> static const struct reg_script core_msr_script[] = { /* Enable C-state and IO/MWAIT redirect */ @@ -40,6 +41,8 @@ static const struct reg_script core_msr_script[] = { (ACPI_PMIO_CST_REG | (PMG_IO_BASE_CST_RNG_BLK_SIZE << 16))), /* Disable C1E */ REG_MSR_RMW(MSR_POWER_CTL, ~0x2, 0), + /* Disable support for MONITOR and MWAIT instructions */ + REG_MSR_RMW(MSR_IA32_MISC_ENABLES, ~MONITOR_MWAIT_DIS_MASK, 0), REG_SCRIPT_END }; @@ -47,6 +50,7 @@ static void soc_core_init(device_t cpu) { /* Set core MSRs */ reg_script_run(core_msr_script); + } static struct device_operations cpu_dev_ops = { diff --git a/src/soc/intel/apollolake/include/soc/cpu.h b/src/soc/intel/apollolake/include/soc/cpu.h index e94972d..2ecab7f 100644 --- a/src/soc/intel/apollolake/include/soc/cpu.h +++ b/src/soc/intel/apollolake/include/soc/cpu.h @@ -62,6 +62,8 @@ void apollolake_init_cpus(struct device *dev); #define IO_MWAIT_REDIRECT_MASK 0x400 /* Set MSR_PMG_CST_CONFIG_CONTROL[15] to lock CST_CFG [0-15] bits */ #define CST_CFG_LOCK_MASK 0x8000 +/* Disable the Monitor Mwait FSM feature */ +#define MONITOR_MWAIT_DIS_MASK 0x40000 #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4

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coreboot-gerrit November 2016