coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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1666 discussions

Patch set updated for coreboot: soc/intel/apollolake: Skip FSP initiated core/MP init
by Venkateswarlu V Vinjamuri 01 Nov '16

01 Nov '16

Venkateswarlu V Vinjamuri (venkateswarlu.v.vinjamuri(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17201 -gerrit commit bb8088865f2b16b84e9f1247af4b1c7e044cc005 Author: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Date: Mon Oct 31 17:15:30 2016 -0700 soc/intel/apollolake: Skip FSP initiated core/MP init Enable skip FSP initiated core/MP init as it is implemented in coreboot. BUG=chrome-os-partner:56922 BRANCH=None Change-Id: I9417dab3135ca1e0104fc3bde63518288bcfa76a Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> --- src/soc/intel/apollolake/chip.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index 181d4d6..12aea77 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -465,6 +465,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* Disable monitor mwait since it is broken due to a hardware bug without a fix */ silconfig->MonitorMwaitEnable = 0; + silconfig->SkipMpInit = 1; + /* Disable setting of EISS bit in FSP. */ silconfig->SpiEiss = 0;

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Patch set updated for coreboot: vendorcode/amd/f14: Fix ignored argument in IDS_HDT_CONSOLE
by Łukasz Dobrowolski 01 Nov '16

01 Nov '16

Łukasz Dobrowolski (lukasz(a)dobrowolski.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17118 -gerrit commit 612e7a2a66d35dfdf27fa21e32d0efbababed7d5 Author: Łukasz Dobrowolski <lukasz(a)dobrowolski.io> Date: Tue Oct 25 00:29:37 2016 +0200 vendorcode/amd/f14: Fix ignored argument in IDS_HDT_CONSOLE String format required two arguments however those were packaged in ( , ) so the left one was ignored. Change-Id: I59698319d5ff4215f296356147b4e22229cc9245 Signed-off-by: Łukasz Dobrowolski <lukasz(a)dobrowolski.io> --- src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c index b7aaf22..8866148 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c @@ -641,7 +641,9 @@ S3SaveDebugPrintHexArray ( break; case AccessWidth64: case AccessS3SaveWidth64: - IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0])); + IDS_HDT_CONSOLE(S3_TRACE, "0x%08x%08x", + ((UINT32 *) ((UINT64 *)Array + Index))[1], + ((UINT32 *) ((UINT64 *)Array + Index))[0]); break; default: IDS_ERROR_TRAP;

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Patch set updated for coreboot: src/apollolake: Enable turbo
by Shaunak Saha 01 Nov '16

01 Nov '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17203 -gerrit commit 0f3898de8337876354523f1fdf1fc718c87591c0 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Mon Oct 10 12:34:28 2016 -0700 src/apollolake: Enable turbo This patch adds punit initilazation code after FspMemoryInit so that turbo can be initialized after that. Change-Id: I4939da47da82b9a728cf1b5cf6d5ec54b4f5b31d Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.h | 2 + src/soc/intel/apollolake/include/soc/iomap.h | 6 +++ src/soc/intel/apollolake/romstage.c | 55 ++++++++++++++++++++++++++++ src/soc/intel/apollolake/tsc_freq.c | 38 +++++++++++++++++++ 4 files changed, 101 insertions(+) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 6c3bcd8..706f810 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -124,4 +124,6 @@ struct soc_intel_apollolake_config { uint16_t prt0_gpio; }; +void get_max_freq(void); +void set_max_freq(void); #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 621b0a6..c15ba95 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,6 +25,12 @@ #define MCH_BASE_ADDR 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) +#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168 +#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078 +#define PUNIT_THERMAL_DEVICE_IRQ 0x700C +#define PUINT_THERMAL_DEVICE_IRQ 0x18 +#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 + #define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1f6a38f..f8bffdc 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -40,6 +40,8 @@ #include <soc/uart.h> #include <string.h> #include <timestamp.h> +#include <delay.h> +#include "chip.h" static struct chipset_power_state power_state CAR_GLOBAL; @@ -100,6 +102,55 @@ static void migrate_power_state(int is_recovery) } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +/* Punit Initialization code */ +/*this is all voodoo that isn't documented, but this is the recipe */ +static void punit_init(void) +{ + uint32_t reg; + uint32_t data, temp; + + /* + * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR)-7168h. + * Enable all cores here. + */ + temp = read32((void *)(MCH_BASE_ADDR + 0x00007168)); + write32((void *)(MCH_BASE_ADDR + P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR), 0x0); + + /* P-Unit bring up */ + reg = read32((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)); + if(reg == 0xffffffff) { + /* P-unit not found */ + printk(BIOS_DEBUG,"Punit MMIO not available \n"); + } + else { + printk(BIOS_DEBUG,"Punit MMIO available \n"); + + /* Set Punit interrupt pin IPIN offset 3D */ + write32((void *)(0xE000103D),0x002); + + /* Set PUINT IRQ to 24 and INTPIN LOCK */ + write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), + PUINT_THERMAL_DEVICE_IRQ | PUINT_THERMAL_DEVICE_IRQ_LOCK); + + data = read32((void *)(MCH_BASE_ADDR + 0x7818)); + data &= 0xFFFFE01F; + data |= (0x20 | 0x200); + write32((void *)(MCH_BASE_ADDR + 0x7818), data); + + /* Stage0 BIOS Reset Complete (RST_CPL): Set by BIOS to + * indicate that all power management configurations as part of reset + * are complete + */ + write32((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR), 0x1); + + /* Poll for bit 8 in same reg (RST_CPL). It will be set once Pcode observes bit 0 being set */ + data = read32((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)); + while ( !(read32 ((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)) & 0x100) ) { + udelay(100); + } + } +} + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -119,6 +170,10 @@ asmlinkage void car_stage_entry(void) s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + + punit_init(); + set_max_freq(); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c index 9dd1dea..c3168dc 100644 --- a/src/soc/intel/apollolake/tsc_freq.c +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -14,12 +14,50 @@ * GNU General Public License for more details. */ +#include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <soc/cpu.h> +#include <console/console.h> +#include <delay.h> +#include "chip.h" unsigned long tsc_freq_mhz(void) { msr_t msr = rdmsr(MSR_PLATFORM_INFO); return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); } + +void set_max_freq(void) +{ + msr_t msr; + unsigned int eax; + + eax = cpuid_eax(6); + + msr = rdmsr(MSR_IA32_MISC_ENABLES); + if((eax == 0 ) && ((msr.hi & 0x4000000000)==0)) { + /* Burst Mode has been factory configured as disabled + * and is not available in this physical processor + * package. + */ + printk(BIOS_DEBUG, "Burst Mode is disabled\n"); + return; + } + else { + /* Enable burst mode */ + msr.hi = 0; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + } + + /* Enable speed step. */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Set P-State ratio */ + msr = rdmsr(0x199); + msr.lo &= ~(0xff00); + msr.lo |= 0x1700; + wrmsr(0x199,msr); +}

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Patch set updated for coreboot: src/apollolake: Enable turbo
by Shaunak Saha 01 Nov '16

01 Nov '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17203 -gerrit commit 8535249ef7f7c8c83864d64bc7eada281d34db25 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Mon Oct 10 12:34:28 2016 -0700 src/apollolake: Enable turbo This patch adds punit initilazation code after FspMemoryInit so that turbo can be initialized after that. Change-Id: I4939da47da82b9a728cf1b5cf6d5ec54b4f5b31d Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.h | 2 + src/soc/intel/apollolake/include/soc/iomap.h | 6 +++ src/soc/intel/apollolake/romstage.c | 55 ++++++++++++++++++++++++++++ src/soc/intel/apollolake/tsc_freq.c | 38 +++++++++++++++++++ 4 files changed, 101 insertions(+) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 6c3bcd8..706f810 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -124,4 +124,6 @@ struct soc_intel_apollolake_config { uint16_t prt0_gpio; }; +void get_max_freq(void); +void set_max_freq(void); #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 621b0a6..c15ba95 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,6 +25,12 @@ #define MCH_BASE_ADDR 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) +#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168 +#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078 +#define PUNIT_THERMAL_DEVICE_IRQ 0x700C +#define PUINT_THERMAL_DEVICE_IRQ 0x18 +#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 + #define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1f6a38f..f8bffdc 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -40,6 +40,8 @@ #include <soc/uart.h> #include <string.h> #include <timestamp.h> +#include <delay.h> +#include "chip.h" static struct chipset_power_state power_state CAR_GLOBAL; @@ -100,6 +102,55 @@ static void migrate_power_state(int is_recovery) } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +/* Punit Initialization code */ +/*this is all voodoo that isn't documented, but this is the recipe */ +static void punit_init(void) +{ + uint32_t reg; + uint32_t data, temp; + + /* + * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR)-7168h. + * Enable all cores here. + */ + temp = read32((void *)(MCH_BASE_ADDR + 0x00007168)); + write32((void *)(MCH_BASE_ADDR + P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR), 0x0); + + /* P-Unit bring up */ + reg = read32((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)); + if(reg == 0xffffffff) { + /* P-unit not found */ + printk(BIOS_DEBUG,"Punit MMIO not available \n"); + } + else { + printk(BIOS_DEBUG,"Punit MMIO available \n"); + + /* Set Punit interrupt pin IPIN offset 3D */ + write32((void *)(0xE000103D),0x002); + + /* Set PUINT IRQ to 24 and INTPIN LOCK */ + write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), + PUINT_THERMAL_DEVICE_IRQ | PUINT_THERMAL_DEVICE_IRQ_LOCK); + + data = read32((void *)(MCH_BASE_ADDR + 0x7818)); + data &= 0xFFFFE01F; + data |= (0x20 | 0x200); + write32((void *)(MCH_BASE_ADDR + 0x7818), data); + + /* Stage0 BIOS Reset Complete (RST_CPL): Set by BIOS to + * indicate that all power management configurations as part of reset + * are complete + */ + write32((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR), 0x1); + + /* Poll for bit 8 in same reg (RST_CPL). It will be set once Pcode observes bit 0 being set */ + data = read32((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)); + while ( !(read32 ((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)) & 0x100) ) { + udelay(100); + } + } +} + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -119,6 +170,10 @@ asmlinkage void car_stage_entry(void) s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + + punit_init(); + set_max_freq(); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c index 9dd1dea..16dbec6 100644 --- a/src/soc/intel/apollolake/tsc_freq.c +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -14,12 +14,50 @@ * GNU General Public License for more details. */ +#include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <soc/cpu.h> +#include <console/console.h> +#include <delay.h> +#include "chip.h" unsigned long tsc_freq_mhz(void) { msr_t msr = rdmsr(MSR_PLATFORM_INFO); return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); } + +void set_max_freq(void) +{ + msr_t msr; + unsigned int eax; + + eax = cpuid_eax(6); + + msr = rdmsr(MSR_IA32_MISC_ENABLES); + if((eax == 0 ) && ((msr.hi & 0x4000000000)==0)) { + /* Burst Mode has been factory configured as disabled + * and is not available in this physical processor + * package. + */ + printk(BIOS_DEBUG, "Burst Mode is disabled\n"); + return; + } + else { + /* Enable burst mode */ + msr.hi = 0; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + } + + /* Enable speed step. */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Set P-State ratio */ + msr = rdmsr(0x199); + msr.lo &= ~(0xff00); + msr.lo |= 0x1700; + wrmsr(0x199,msr); +}

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New patch to review for coreboot: src/apollolake: Enable turbo
by Shaunak Saha 01 Nov '16

01 Nov '16

Shaunak Saha (shaunak.saha(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17203 -gerrit commit 6a81756756945fc0cb3dc1827e8f1b57eb574ea3 Author: Shaunak Saha <shaunak.saha(a)intel.com> Date: Mon Oct 10 12:34:28 2016 -0700 src/apollolake: Enable turbo This patch adds punit initilazation code after FspMemoryInit so that turbo can be initialized after that. Change-Id: I4939da47da82b9a728cf1b5cf6d5ec54b4f5b31d Signed-off-by: Shaunak Saha <shaunak.saha(a)intel.com> --- src/soc/intel/apollolake/chip.h | 2 ++ src/soc/intel/apollolake/include/soc/iomap.h | 6 ++++ src/soc/intel/apollolake/romstage.c | 53 ++++++++++++++++++++++++++++ src/soc/intel/apollolake/tsc_freq.c | 38 ++++++++++++++++++++ 4 files changed, 99 insertions(+) diff --git a/src/soc/intel/apollolake/chip.h b/src/soc/intel/apollolake/chip.h index 6c3bcd8..706f810 100644 --- a/src/soc/intel/apollolake/chip.h +++ b/src/soc/intel/apollolake/chip.h @@ -124,4 +124,6 @@ struct soc_intel_apollolake_config { uint16_t prt0_gpio; }; +void get_max_freq(void); +void set_max_freq(void); #endif /* _SOC_APOLLOLAKE_CHIP_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/iomap.h b/src/soc/intel/apollolake/include/soc/iomap.h index 621b0a6..c15ba95 100644 --- a/src/soc/intel/apollolake/include/soc/iomap.h +++ b/src/soc/intel/apollolake/include/soc/iomap.h @@ -25,6 +25,12 @@ #define MCH_BASE_ADDR 0xfed10000 #define MCH_BASE_SIZE (32 * KiB) +#define P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR 0x7168 +#define P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR 0x7078 +#define PUNIT_THERMAL_DEVICE_IRQ 0x700C +#define PUINT_THERMAL_DEVICE_IRQ 0x18 +#define PUINT_THERMAL_DEVICE_IRQ_LOCK 0x80000000 + #define ACPI_PMIO_BASE 0x400 #define ACPI_PMIO_SIZE 0x100 #define R_ACPI_PM1_TMR 0x8 diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1f6a38f..6c22c9d 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -40,6 +40,8 @@ #include <soc/uart.h> #include <string.h> #include <timestamp.h> +#include <delay.h> +#include "chip.h" static struct chipset_power_state power_state CAR_GLOBAL; @@ -100,6 +102,53 @@ static void migrate_power_state(int is_recovery) } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +static void punit_init(void) +{ + uint32_t reg; + uint32_t data, temp; + + /* + * Software Core Disable Mask (P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR)-7168h. + * Enable all cores here. + */ + temp = read32((void *)(MCH_BASE_ADDR + 0x00007168)); + write32((void *)(MCH_BASE_ADDR + P_CR_CORE_DISABLE_MASK_0_0_0_MCHBAR), 0x0); + + /* P-Unit bring up */ + reg = read32((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)); + if(reg == 0xffffffff) { + /* P-unit not found */ + printk(BIOS_DEBUG,"Punit MMIO not available \n"); + } + else { + printk(BIOS_DEBUG,"Punit MMIO available \n"); + + /* Set Punit interrupt pin IPIN offset 3D */ + write32((void *)(0xE000103D),0x002); + + /* Set PUINT IRQ to 24 and INTPIN LOCK */ + write32((void *)(MCH_BASE_ADDR + PUNIT_THERMAL_DEVICE_IRQ), + PUINT_THERMAL_DEVICE_IRQ | PUINT_THERMAL_DEVICE_IRQ_LOCK); + + data = read32((void *)(MCH_BASE_ADDR + 0x7818)); + data &= 0xFFFFE01F; + data |= (0x20 | 0x200); + write32((void *)(MCH_BASE_ADDR + 0x7818), data); + + /* Stage0 BIOS Reset Complete (RST_CPL): Set by BIOS to + * indicate that all power management configurations as part of reset + * are complete + */ + write32((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR), 0x1); + + /* Poll for bit 8 in same reg (RST_CPL). It will be set once Pcode observes bit 0 being set */ + data = read32((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)); + while ( !(read32 ((void *)(MCH_BASE_ADDR + P_CR_BIOS_RESET_CPL_0_0_0_MCHBAR)) & 0x100) ) { + udelay(100); + } + } +} + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -119,6 +168,10 @@ asmlinkage void car_stage_entry(void) s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); + + punit_init(); + set_max_freq(); + if (postcar_frame_init(&pcf, 1*KiB)) die("Unable to initialize postcar frame.\n"); diff --git a/src/soc/intel/apollolake/tsc_freq.c b/src/soc/intel/apollolake/tsc_freq.c index 9dd1dea..16dbec6 100644 --- a/src/soc/intel/apollolake/tsc_freq.c +++ b/src/soc/intel/apollolake/tsc_freq.c @@ -14,12 +14,50 @@ * GNU General Public License for more details. */ +#include <cpu/intel/turbo.h> #include <cpu/x86/msr.h> #include <cpu/x86/tsc.h> #include <soc/cpu.h> +#include <console/console.h> +#include <delay.h> +#include "chip.h" unsigned long tsc_freq_mhz(void) { msr_t msr = rdmsr(MSR_PLATFORM_INFO); return (BASE_CLOCK_MHZ * ((msr.lo >> 8) & 0xff)); } + +void set_max_freq(void) +{ + msr_t msr; + unsigned int eax; + + eax = cpuid_eax(6); + + msr = rdmsr(MSR_IA32_MISC_ENABLES); + if((eax == 0 ) && ((msr.hi & 0x4000000000)==0)) { + /* Burst Mode has been factory configured as disabled + * and is not available in this physical processor + * package. + */ + printk(BIOS_DEBUG, "Burst Mode is disabled\n"); + return; + } + else { + /* Enable burst mode */ + msr.hi = 0; + wrmsr(MSR_IA32_MISC_ENABLES, msr); + } + + /* Enable speed step. */ + msr = rdmsr(MSR_IA32_MISC_ENABLES); + msr.lo |= (1 << 16); + wrmsr(MSR_IA32_MISC_ENABLES, msr); + + /* Set P-State ratio */ + msr = rdmsr(0x199); + msr.lo &= ~(0xff00); + msr.lo |= 0x1700; + wrmsr(0x199,msr); +}

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Patch set updated for coreboot: Add option to use Ada code in ramstage
by Nico Huber 01 Nov '16

01 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16944 -gerrit commit f2209654a84d49942dd40ba22ec5ebc0609a6610 Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Oct 7 12:58:17 2016 +0200 Add option to use Ada code in ramstage If selected, libgnat will be linked into ramstage. And, to support Ada package intializations, we have to call ramstage_adainit(). Change-Id: I11417db21f16bf3007739a097d63fd592344bce3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/Kconfig | 5 +++++ src/include/adainit.h | 35 +++++++++++++++++++++++++++++++++++ src/lib/gnat/Makefile.inc | 4 ++++ src/lib/hardwaremain.c | 13 +++++++++++++ 4 files changed, 57 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index e337a1a..d6af6eb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1243,3 +1243,8 @@ config CHECKLIST_DATA_FILE_LOCATION symbols contained only in <stage>_complete.dat will be flagged as required and not implemented if a weak implementation is found in the resulting image. + +config RAMSTAGE_ADA + def_bool n + help + Selected by features that use Ada code in ramstage. diff --git a/src/include/adainit.h b/src/include/adainit.h new file mode 100644 index 0000000..34f45cb --- /dev/null +++ b/src/include/adainit.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ADAINIT_H +#define _ADAINIT_H + +/** + * @file adainit.h + * + * Ada supports some complex constructs that result in code for runtime + * initialization. It's also possible to have explicit procedures for + * package level initialization (e.g. you can initialize huge arrays in + * a loop instead of cluttering the binary). + * + * When an Ada main() is in charge, GNAT emmits the call to the initia- + * lizations automatically. When not, we have to call it explicitly. + */ + +#if IS_ENABLED(CONFIG_RAMSTAGE_ADA) +void ramstage_adainit(void); +#else +static inline void ramstage_adainit(void) {} +#endif + +#endif /* _ADAINIT_H */ diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc index 6ba274a..394c838 100644 --- a/src/lib/gnat/Makefile.inc +++ b/src/lib/gnat/Makefile.inc @@ -60,3 +60,7 @@ $(foreach arch,$(standard-archs), \ $(foreach arch,$(standard-archs), \ $(eval $(call libgnat-template,$(arch)))) + +ifeq ($(CONFIG_RAMSTAGE_ADA),y) +ramstage-libs += $$(obj)/libgnat-$(ARCH-ramstage-y)/libgnat.a +endif diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index ab4d9f4..ef78960 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -18,6 +18,7 @@ * C Bootstrap code for the coreboot */ +#include <adainit.h> #include <arch/exception.h> #include <bootstate.h> #include <console/console.h> @@ -429,6 +430,18 @@ static void boot_state_schedule_static_entries(void) void main(void) { + /* + * We can generally jump between C and Ada code back and forth + * without trouble. But since we don't have an Ada main() we + * have to do some Ada package initializations that GNAT would + * do there. This has to be done before calling any Ada code. + * + * The package initializations should not have any dependen- + * cies on C code. So we can call them here early, and don't + * have to worry at which point we can start to use Ada. + */ + ramstage_adainit(); + /* TODO: Understand why this is here and move to arch/platform code. */ /* For MMIO UART this needs to be called before any other printk. */ if (IS_ENABLED(CONFIG_ARCH_X86))

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Patch set updated for coreboot: Add option to use Ada code in ramstage
by Nico Huber 01 Nov '16

01 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16944 -gerrit commit 358af6a4236d1826caf42c301b21e1e783a4a72c Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Oct 7 12:58:17 2016 +0200 Add option to use Ada code in ramstage If selected, libgnat will be linked into ramstage. And, to support Ada package intializations, we have to call ramstage_adainit(). Change-Id: I11417db21f16bf3007739a097d63fd592344bce3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/Kconfig | 5 +++++ src/include/adainit.h | 35 +++++++++++++++++++++++++++++++++++ src/lib/gnat/Makefile.inc | 4 ++++ src/lib/hardwaremain.c | 13 +++++++++++++ 4 files changed, 57 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index e337a1a..d6af6eb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1243,3 +1243,8 @@ config CHECKLIST_DATA_FILE_LOCATION symbols contained only in <stage>_complete.dat will be flagged as required and not implemented if a weak implementation is found in the resulting image. + +config RAMSTAGE_ADA + def_bool n + help + Selected by features that use Ada code in ramstage. diff --git a/src/include/adainit.h b/src/include/adainit.h new file mode 100644 index 0000000..34f45cb --- /dev/null +++ b/src/include/adainit.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ADAINIT_H +#define _ADAINIT_H + +/** + * @file adainit.h + * + * Ada supports some complex constructs that result in code for runtime + * initialization. It's also possible to have explicit procedures for + * package level initialization (e.g. you can initialize huge arrays in + * a loop instead of cluttering the binary). + * + * When an Ada main() is in charge, GNAT emmits the call to the initia- + * lizations automatically. When not, we have to call it explicitly. + */ + +#if IS_ENABLED(CONFIG_RAMSTAGE_ADA) +void ramstage_adainit(void); +#else +static inline void ramstage_adainit(void) {} +#endif + +#endif /* _ADAINIT_H */ diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc index 6ba274a..394c838 100644 --- a/src/lib/gnat/Makefile.inc +++ b/src/lib/gnat/Makefile.inc @@ -60,3 +60,7 @@ $(foreach arch,$(standard-archs), \ $(foreach arch,$(standard-archs), \ $(eval $(call libgnat-template,$(arch)))) + +ifeq ($(CONFIG_RAMSTAGE_ADA),y) +ramstage-libs += $$(obj)/libgnat-$(ARCH-ramstage-y)/libgnat.a +endif diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index ab4d9f4..4a59d78 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -18,6 +18,7 @@ * C Bootstrap code for the coreboot */ +#include <adainit.h> #include <arch/exception.h> #include <bootstate.h> #include <console/console.h> @@ -429,6 +430,18 @@ static void boot_state_schedule_static_entries(void) void main(void) { + /* + * We can generally jump between C and Ada code back and forth + * without trouble. But since we don't have an Ada main() we + * have to do some Ada package initializations that GNAT would + * do there. This has to be done before calling any Ada code. + * + * The package initializations should not have any dependen- + * cies on C code. So we can call them here early, and don't + * have worry at which point we can start to use Ada. + */ + ramstage_adainit(); + /* TODO: Understand why this is here and move to arch/platform code. */ /* For MMIO UART this needs to be called before any other printk. */ if (IS_ENABLED(CONFIG_ARCH_X86))

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Patch merged into coreboot/master: soc/apollolake: Add soc core init
by gerrit＠coreboot.org 01 Nov '16

01 Nov '16

the following patch was just integrated into master: commit ec7293652af797b2595bec396bae8cd625afbf8e Author: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Date: Fri Sep 9 14:08:50 2016 -0700 soc/apollolake: Add soc core init Add soc core init to set up the following feature MSRs: 1. C-states 2. IO/Mwait redirection BUG=chrome-os-partner:56922 BRANCH=None TEST= Check C-state functioning using 'powertop'. Check 0xE2 and 0xE4 MSR to verify IO/Mwait redirection. Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi(a)intel.com> Change-Id: I99b66b02eb790b6b348be7c964d21ec9a6926926 Reviewed-on: https://review.coreboot.org/17168 Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17168 for details. -gerrit

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Patch set updated for coreboot: Add option to use Ada code in ramstage
by Nico Huber 01 Nov '16

01 Nov '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16944 -gerrit commit 2d9255f42ad7770efd80aab60e11059471838d0a Author: Nico Huber <nico.huber(a)secunet.com> Date: Fri Oct 7 12:58:17 2016 +0200 Add option to use Ada code in ramstage If selected, libgnat will be linked into ramstage. And, to support Ada package intializations, we have to call ramstage_adainit(). Change-Id: I11417db21f16bf3007739a097d63fd592344bce3 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/Kconfig | 5 +++++ src/include/adainit.h | 35 +++++++++++++++++++++++++++++++++++ src/lib/gnat/Makefile.inc | 4 ++++ src/lib/hardwaremain.c | 5 +++++ 4 files changed, 49 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index e337a1a..d6af6eb 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1243,3 +1243,8 @@ config CHECKLIST_DATA_FILE_LOCATION symbols contained only in <stage>_complete.dat will be flagged as required and not implemented if a weak implementation is found in the resulting image. + +config RAMSTAGE_ADA + def_bool n + help + Selected by features that use Ada code in ramstage. diff --git a/src/include/adainit.h b/src/include/adainit.h new file mode 100644 index 0000000..34f45cb --- /dev/null +++ b/src/include/adainit.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _ADAINIT_H +#define _ADAINIT_H + +/** + * @file adainit.h + * + * Ada supports some complex constructs that result in code for runtime + * initialization. It's also possible to have explicit procedures for + * package level initialization (e.g. you can initialize huge arrays in + * a loop instead of cluttering the binary). + * + * When an Ada main() is in charge, GNAT emmits the call to the initia- + * lizations automatically. When not, we have to call it explicitly. + */ + +#if IS_ENABLED(CONFIG_RAMSTAGE_ADA) +void ramstage_adainit(void); +#else +static inline void ramstage_adainit(void) {} +#endif + +#endif /* _ADAINIT_H */ diff --git a/src/lib/gnat/Makefile.inc b/src/lib/gnat/Makefile.inc index 6ba274a..394c838 100644 --- a/src/lib/gnat/Makefile.inc +++ b/src/lib/gnat/Makefile.inc @@ -60,3 +60,7 @@ $(foreach arch,$(standard-archs), \ $(foreach arch,$(standard-archs), \ $(eval $(call libgnat-template,$(arch)))) + +ifeq ($(CONFIG_RAMSTAGE_ADA),y) +ramstage-libs += $$(obj)/libgnat-$(ARCH-ramstage-y)/libgnat.a +endif diff --git a/src/lib/hardwaremain.c b/src/lib/hardwaremain.c index ab4d9f4..f30f823 100644 --- a/src/lib/hardwaremain.c +++ b/src/lib/hardwaremain.c @@ -18,6 +18,7 @@ * C Bootstrap code for the coreboot */ +#include <adainit.h> #include <arch/exception.h> #include <bootstate.h> #include <console/console.h> @@ -429,6 +430,10 @@ static void boot_state_schedule_static_entries(void) void main(void) { + /* Since we don't have an Ada main(), initialize Ada packages + explicitly. Has to be done before calling any Ada code. */ + ramstage_adainit(); + /* TODO: Understand why this is here and move to arch/platform code. */ /* For MMIO UART this needs to be called before any other printk. */ if (IS_ENABLED(CONFIG_ARCH_X86))

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Patch set updated for coreboot: vendorcode/amd/f14: Fix ignored argument in IDS_HDT_CONSOLE
by Łukasz Dobrowolski 01 Nov '16

01 Nov '16

Łukasz Dobrowolski (lukasz(a)dobrowolski.io) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17118 -gerrit commit ef5754f5dc3be36c830b39a7ced4f0b3bd0a2c18 Author: Łukasz Dobrowolski <lukasz(a)dobrowolski.io> Date: Tue Oct 25 00:29:37 2016 +0200 vendorcode/amd/f14: Fix ignored argument in IDS_HDT_CONSOLE String format required two arguments however those were packaged in ( , ) so the left one was ignored. Change-Id: I59698319d5ff4215f296356147b4e22229cc9245 Signed-off-by: Łukasz Dobrowolski <lukasz(a)dobrowolski.io> --- src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c index b7aaf22..62af8cc 100644 --- a/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f14/Proc/Common/S3SaveState.c @@ -641,7 +641,9 @@ S3SaveDebugPrintHexArray ( break; case AccessWidth64: case AccessS3SaveWidth64: - IDS_HDT_CONSOLE (S3_TRACE, "0x%08x%08x", ((UINT32*) ((UINT64*)Array + Index)[1], ((UINT32*) ((UINT64*)Array + Index))[0])); + IDS_HDT_CONSOLE(S3_TRACE, "0x%08x%08x", + (UINT32 *) ((UINT64 *)Array + Index)[1], + ((UINT32 *) ((UINT64 *)Array + Index))[0]); break; default: IDS_ERROR_TRAP;

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coreboot-gerrit November 2016