coreboot-gerrit November 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: elog: add sources to reflect full event type namespace usage
by Aaron Durbin 04 Nov '16

04 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17230 -gerrit commit a6cdf65c82840407afe5d0188a8a8b03082a462c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 4 10:53:43 2016 -0500 elog: add sources to reflect full event type namespace usage Some events were added in other places, but coreboot's elog namespace wasn't updated. As such there's a collision with the thermtrip event. This change at least updates the elog information to reflect potential event type uage. BUG=chrome-os-partner:59395 Change-Id: Ib82e2b65ef7d34e260b7d7450174aee7537b69f6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/elog.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/include/elog.h b/src/include/elog.h index e4350f5..bdbafc2 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -142,6 +142,13 @@ struct elog_event_data_me_extended { /* CPU Thermal Trip */ #define ELOG_TYPE_THERM_TRIP 0xa7 +/* ARM/generic versions of sleep/wake - These came from another firmware + * apparently, but not all the firmware sources were updated so that the + * elog namespace was coherent. */ +#define ELOG_TYPE_SLEEP 0xa7 +#define ELOG_TYPE_WAKE 0xa8 +#define ELOG_TYPE_FW_WAKE 0xa9 + #if CONFIG_ELOG /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void);

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Patch set updated for coreboot: soc/intel/common: log event when MRC cache is updated
by Aaron Durbin 04 Nov '16

04 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17231 -gerrit commit 42e971b89a2b7de843f716c2ecbc4e48206bffd9 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 4 10:07:14 2016 -0500 soc/intel/common: log event when MRC cache is updated Log when the MRC cache is attempted to be updated with status of success or failure. Just one slot is supported currently which is deemed 'normal'. This is because there are more slots anticipated in the future. BUG=chrome-os-partner:59395 Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/elog.h | 10 ++++++++++ src/soc/intel/common/mrc_cache.c | 19 +++++++++++++++++++ 2 files changed, 29 insertions(+) diff --git a/src/include/elog.h b/src/include/elog.h index 3df9a4c..0c18ca4 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -149,6 +149,16 @@ struct elog_event_data_me_extended { #define ELOG_TYPE_WAKE 0xa8 #define ELOG_TYPE_FW_WAKE 0xa9 +/* Memory Cache Update */ +#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa +#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 +struct elog_event_mem_cache_update { + u8 slot; + u8 status; +} __attribute__ ((packed)); + #if CONFIG_ELOG /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void); diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index c123da9..bef3ba2 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -17,6 +17,7 @@ #include <bootstate.h> #include <console/console.h> #include <cbmem.h> +#include <elog.h> #include <fmap.h> #include <ip_checksum.h> #include <vboot/vboot_common.h> @@ -281,6 +282,18 @@ static int protect_mrc_cache(const struct mrc_data_region *region) return 0; } +static void log_event_cache_update(uint8_t slot, uint8_t status) +{ + const int type = ELOG_TYPE_MEM_CACHE_UPDATE; + struct elog_event_mem_cache_update event = { + .slot = slot, + .status = status, + }; + + if (elog_add_event_raw(type, &event, sizeof(event)) < 0) + printk(BIOS_ERR, "Failed to log mem cache update event.\n"); +} + static void update_mrc_cache(void *unused) { const struct mrc_saved_data *current_boot; @@ -336,7 +349,13 @@ static void update_mrc_cache(void *unused) current_boot->size + sizeof(*current_boot))) { printk(BIOS_DEBUG, "Failure writing MRC cache to %p.\n", next_slot); + log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, + ELOG_MEM_CACHE_UPDATE_STATUS_FAIL); + } else { + log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, + ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS); } + protect_mrc_cache(&region); }

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New patch to review for coreboot: soc/intel/common: log event when MRC cache is updated
by Aaron Durbin 04 Nov '16

04 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17231 -gerrit commit ab0bc90a3af384355a6c978cd5236ebfad4da8ad Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 4 10:07:14 2016 -0500 soc/intel/common: log event when MRC cache is updated Log when the MRC cache is attempted to be updated with status of success or failure. Just one slot is supported currently which is deemed 'normal'. This is because there are more slots anticipated in the future. BUG=chrome-os-partner:59395 Change-Id: I0f81458325697aff9924cc359a4173e0d35da5da Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/elog.h | 11 +++++++++++ src/soc/intel/common/mrc_cache.c | 19 +++++++++++++++++++ 2 files changed, 30 insertions(+) diff --git a/src/include/elog.h b/src/include/elog.h index 3df9a4c..3d2a563 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -142,6 +142,7 @@ struct elog_event_data_me_extended { /* CPU Thermal Trip */ #define ELOG_TYPE_THERM_TRIP 0xa7 +<<<<<<< HEAD /* ARM/generic versions of sleep/wake - These came from another firmware * apparently, but not all the firmware sources were updated so that the * elog namespace was coherent. */ @@ -149,6 +150,16 @@ struct elog_event_data_me_extended { #define ELOG_TYPE_WAKE 0xa8 #define ELOG_TYPE_FW_WAKE 0xa9 +/* Memory Cache Update */ +#define ELOG_TYPE_MEM_CACHE_UPDATE 0xaa +#define ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS 0 +#define ELOG_MEM_CACHE_UPDATE_STATUS_FAIL 1 +struct elog_event_mem_cache_update { + u8 slot; + u8 status; +} __attribute__ ((packed)); + #if CONFIG_ELOG /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void); diff --git a/src/soc/intel/common/mrc_cache.c b/src/soc/intel/common/mrc_cache.c index c123da9..bef3ba2 100644 --- a/src/soc/intel/common/mrc_cache.c +++ b/src/soc/intel/common/mrc_cache.c @@ -17,6 +17,7 @@ #include <bootstate.h> #include <console/console.h> #include <cbmem.h> +#include <elog.h> #include <fmap.h> #include <ip_checksum.h> #include <vboot/vboot_common.h> @@ -281,6 +282,18 @@ static int protect_mrc_cache(const struct mrc_data_region *region) return 0; } +static void log_event_cache_update(uint8_t slot, uint8_t status) +{ + const int type = ELOG_TYPE_MEM_CACHE_UPDATE; + struct elog_event_mem_cache_update event = { + .slot = slot, + .status = status, + }; + + if (elog_add_event_raw(type, &event, sizeof(event)) < 0) + printk(BIOS_ERR, "Failed to log mem cache update event.\n"); +} + static void update_mrc_cache(void *unused) { const struct mrc_saved_data *current_boot; @@ -336,7 +349,13 @@ static void update_mrc_cache(void *unused) current_boot->size + sizeof(*current_boot))) { printk(BIOS_DEBUG, "Failure writing MRC cache to %p.\n", next_slot); + log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, + ELOG_MEM_CACHE_UPDATE_STATUS_FAIL); + } else { + log_event_cache_update(ELOG_MEM_CACHE_UPDATE_SLOT_NORMAL, + ELOG_MEM_CACHE_UPDATE_STATUS_SUCCESS); } + protect_mrc_cache(&region); }

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New patch to review for coreboot: elog: add sources to reflect full event type namespace usage
by Aaron Durbin 04 Nov '16

04 Nov '16

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17230 -gerrit commit 6f02a7b324fdfebc4349d305e588f2df3dc4703c Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Nov 4 10:53:43 2016 -0500 elog: add sources to reflect full event type namespace usage Some events were added in other places, but coreboot's elog namespace wasn't updated. As such there's a collision with the thermtrip event. This change at least updates the elog information to reflect potential event type uage. BUG=chrome-os-partner:59395 Change-Id: Ib82e2b65ef7d34e260b7d7450174aee7537b69f6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/include/elog.h | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/include/elog.h b/src/include/elog.h index 504c52e..3df9a4c 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -142,6 +142,13 @@ struct elog_event_data_me_extended { /* CPU Thermal Trip */ #define ELOG_TYPE_THERM_TRIP 0xa7 +/* ARM/generic versions of sleep/wake - These came from another firmware + * apparently, but not all the firmware sources were updated so that the + * elog namespace was coherent. */ +#define ELOG_TYPE_SLEEP 0xa7 +#define ELOG_TYPE_WAKE 0xa8 +#define ELOG_TYPE_FW_WAKE 0xa9 + #if CONFIG_ELOG /* Eventlog backing storage must be initialized before calling elog_init(). */ extern int elog_init(void);

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Patch set updated for coreboot: nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GC
by HAOUAS Elyes 04 Nov '16

04 Nov '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17191 -gerrit commit bb773d5c292abfc8f4c91ff77a00fd33a0af1878 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 30 18:30:21 2016 +0100 nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GC 945G-M4 returns : "unknown max. RAM clock (2)", however, it supports up to DDR2-667MHz. i945/raminit.c sdram_capabilities_max_supported_memory_frequency() function returns 667 for case 2. Change-Id: I3d54c88af897a71db757d00288f3968ed2c19151 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/early_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 4373167..e91d590 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -130,6 +130,7 @@ static void i945_detect_chipset(void) reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); switch (reg8) { case 0: + case 2: printk(BIOS_DEBUG, "up to DDR2-667"); break; case 3:

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Patch set updated for coreboot: soc/intel/skylake: Fix SATA booting to OS issue
by Subrata Banik 04 Nov '16

04 Nov '16

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17229 -gerrit commit 2fd53cdd73785d3f5d247529e8beae72892e13ea Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Nov 4 13:26:41 2016 +0530 soc/intel/skylake: Fix SATA booting to OS issue SATA device remains unrecognized if connected at Port 2. Port control and Status register (PCS) is by default set by hardware to the disabled state as a result of an initial power on reset. OS read PCS register during boot causes disabling of SATA ports and can't detect any devices. BRANCH=none BUG=chrome-os-partner:59335 TEST=Build and boot SKL from SATA device connected at Port 2. Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/sata.c | 72 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 32eb708..f02f956 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -73,6 +73,7 @@ ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += sata.c ramstage-y += sd.c ramstage-y += smbus.c ramstage-y += smbus_common.c diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c new file mode 100644 index 0000000..83fddcf --- /dev/null +++ b/src/soc/intel/skylake/sata.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <soc/ramstage.h> + +static void *get_ahci_bar(void) +{ + device_t dev = PCH_DEV_SATA; + uint32_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +/* + * SATA Port control and Status. By default, the SATA ports are set (by HW) + * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial + * power on reset. When enabled by software as per SATA port mapping, + * the ports can transition between the on, partial and slumber states + * and can detect devices. When disabled, the port is in the off state and + * can't detect any devices. + */ +static void sata_final(device_t dev) +{ + void *ahcibar = get_ahci_bar(); + u8 port_impl; + + dev = PCH_DEV_SATA; + /* Read Ports Implemented (GHC_PI) */ + port_impl = read32(ahcibar + 0x0c); + port_impl = ~port_impl & 0x07; + /* Port enable */ + pci_write_config8(dev, 0x92, port_impl); +} + +static struct device_operations sata_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .final = sata_final, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x9d03, /* SKL-U Base */ + 0x9d07, /* SKL-Y Premium, SKL-U Premium */ + 0xa282, /* KBL */ + 0 +}; + +static const struct pci_driver pch_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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Patch set updated for coreboot: soc/intel/skylake: Fix SATA booting to OS issue.
by Subrata Banik 04 Nov '16

04 Nov '16

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17229 -gerrit commit c53766ff727cae2750c74506ae3e624e8e2b573d Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Nov 4 13:26:41 2016 +0530 soc/intel/skylake: Fix SATA booting to OS issue. SATA device remain unrecognized if connected at Port 2. Port control and Status register(PCS) by default set by hardware to the disabled state as a result of an initial power on reset. The same read by OS during booting causes disabling of SATA ports and can't detect any devices. BRANCH=none BUG=chrome-os-partner:59335 TEST=Build and boot SKL from SATA device connected at Port 2. Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/sata.c | 72 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 73 insertions(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 32eb708..f02f956 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -73,6 +73,7 @@ ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += sata.c ramstage-y += sd.c ramstage-y += smbus.c ramstage-y += smbus_common.c diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c new file mode 100644 index 0000000..921932b --- /dev/null +++ b/src/soc/intel/skylake/sata.c @@ -0,0 +1,72 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <soc/ramstage.h> + +static void *get_ahci_bar(void) +{ + device_t dev = PCH_DEV_SATA; + uint32_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +/* + * SATA Port control and Status. By default, the SATA ports are set (by HW) + * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial + * power on reset. When enabled by software as per SATA port mapping, + * the ports can transition between the on, partial and slumber states + * and can detect devices. When disabled, the port is in the off state and + * can't detect any devices. + */ +static void sata_final(device_t dev) +{ + void *ahcibar = get_ahci_bar(); + u8 port_impl; + + dev = PCH_DEV_SATA; + /* Read Ports Implemented (GHC_PI) */ + port_impl = read32(ahcibar + 0x0c); + port_impl = ~port_impl & 0x07; + /* Port enable */ + pci_write_config8(dev, 0x92, port_impl); +} + +static struct device_operations sata_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .final = sata_final, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x9d03, /* SKL-U Base */ + 0x9d07, /* SKL-Y Premium, SKL-U Premium */ + 0xa282, /* KBL */ + 0 +}; + +static const struct pci_driver pch_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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New patch to review for coreboot: soc/intel/skylake: Fix SATA booting to OS issue.
by Subrata Banik 04 Nov '16

04 Nov '16

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17229 -gerrit commit 496b60c93619526ac58332a636cb870f8b7307ff Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Nov 4 13:26:41 2016 +0530 soc/intel/skylake: Fix SATA booting to OS issue. SATA device remain unrecognized if connected at Port 2. Port control and Status register(PCS) by default set by hardware to the disabled state as a result of an initial power on reset. The same read by OS during booting causes disabling of SATA ports and can't detect any devices. BRANCH=none BUG=chrome-os-partner:59335 TEST=Build and boot SKL from SATA device connected at Port 2. Change-Id: I4866ca44567f5024edaca2d48098af5b4c67a7ac Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Makefile.inc | 1 + src/soc/intel/skylake/sata.c | 70 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 32eb708..f02f956 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -73,6 +73,7 @@ ramstage-y += pei_data.c ramstage-y += pmc.c ramstage-y += pmutil.c ramstage-$(CONFIG_PLATFORM_USES_FSP2_0) += reset.c +ramstage-y += sata.c ramstage-y += sd.c ramstage-y += smbus.c ramstage-y += smbus_common.c diff --git a/src/soc/intel/skylake/sata.c b/src/soc/intel/skylake/sata.c new file mode 100644 index 0000000..7269a95 --- /dev/null +++ b/src/soc/intel/skylake/sata.c @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_def.h> +#include <device/pci_ids.h> +#include <soc/ramstage.h> + +static void *get_ahci_bar(void) +{ + device_t dev = PCH_DEV_SATA; + uint32_t bar; + + bar = pci_read_config32(dev, PCI_BASE_ADDRESS_5); + + return (void *)(bar & ~PCI_BASE_ADDRESS_MEM_ATTR_MASK); +} + +/* + * SATA Port control and Status. Byu default, the SATA ports are set (by HW) + * to the disabled state (e.g. bits[3:0] == '0') as a result of an initial + * power on reset. When enabled by software as per SATA port mapping, + * the ports can transition between the on, partial and can detect devices. + */ +static void sata_final(device_t dev) +{ + void *ahcibar = get_ahci_bar(); + u8 port_impl; + + dev = PCH_DEV_SATA; + /* Read Ports Implemented (GHC_PI) */ + port_impl = read32(ahcibar + 0x0c); + port_impl = ~port_impl & 0x07; + /* Port enable */ + pci_write_config8(dev, 0x92, port_impl); +} + +static struct device_operations sata_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .final = sata_final, + .ops_pci = &soc_pci_ops, +}; + +static const unsigned short pci_device_ids[] = { + 0x9d03, /* SKL-U Base */ + 0x9d07, /* SKL-Y Premium, SKL-U Premium */ + 0xa282, /* KBL */ + 0 +}; + +static const struct pci_driver pch_sata __pci_driver = { + .ops = &sata_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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Patch set updated for coreboot: nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GC
by HAOUAS Elyes 04 Nov '16

04 Nov '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17191 -gerrit commit 13b6d7756323b39282df3da0fa44ff4da7d8a4c4 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sun Oct 30 18:30:21 2016 +0100 nb/intel/i945/early_init.c: Add DDR2-667 detection for 945GC 945G-M4 returns : "unknown max. RAM clock (2)", however, it support up to DDR2-667MHz. i945/raminit.c sdram_capabilities_max_supported_memory_frequency() function returns 667 for case 2. Change-Id: I3d54c88af897a71db757d00288f3968ed2c19151 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i945/early_init.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c index 4373167..e91d590 100644 --- a/src/northbridge/intel/i945/early_init.c +++ b/src/northbridge/intel/i945/early_init.c @@ -130,6 +130,7 @@ static void i945_detect_chipset(void) reg8 = (pci_read_config8(PCI_DEV(0, 0x00, 0), 0xe4) & 0x07); switch (reg8) { case 0: + case 2: printk(BIOS_DEBUG, "up to DDR2-667"); break; case 3:

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New patch to review for coreboot: configs/gardenia: Add initial config file
by Marc Jones 04 Nov '16

04 Nov '16

Marc Jones (marc(a)marcjonesconsulting.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17228 -gerrit commit e98bb61095c86a60fd2aba42bbe24b3ee40d0afc Author: Marshall Dawson <marshalldawson3rd(a)gmail.com> Date: Tue Oct 11 18:43:46 2016 -0400 configs/gardenia: Add initial config file This config is for a Gardenia board populated with a Stoney Ridge APU. Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com> (cherry picked from commit 8dd4da5903bbf530899a532297acf345dd4f3842) Change-Id: I9aab0ecca1821935efcaa21ea317795dc290aeab Signed-off-by: Marc Jones <marcj303(a)gmail.com> --- configs/config.gardenia.st | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/config.gardenia.st b/configs/config.gardenia.st new file mode 100644 index 0000000..785a246 --- /dev/null +++ b/configs/config.gardenia.st @@ -0,0 +1,5 @@ +CONFIG_VENDOR_AMD=y +CONFIG_BOARD_AMD_GARDENIA=y +CONFIG_VGA_BIOS=y +CONFIG_HUDSON_UART=y +CONFIG_VGA_ROM_RUN=y

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coreboot-gerrit November 2016