coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: mb/emulation: Select QEMU-i440fx by default
by Martin Roth 19 Oct '16

19 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16987 -gerrit commit f9372c0bad755330d466dd797fbfd809b418b8c9 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Sat Oct 15 00:57:32 2016 +0200 mb/emulation: Select QEMU-i440fx by default It's a better default than QEMU-armv7, which is currently the default board when coreboot is configured for the first time, because most coreboot development targets x86. Change-Id: Ie44a5d95547a55df93f29082c3b5a86fb83aa1e7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 1dc89ca..759b1de 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -2,6 +2,7 @@ if VENDOR_EMULATION choice prompt "Mainboard model" + default BOARD_EMULATION_QEMU_X86_I440FX source "src/mainboard/emulation/*/Kconfig.name"

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Patch merged into coreboot/master: nb/i945/gma.c: use IS_ENABLED instead of #if, #endif
by gerrit＠coreboot.org 19 Oct '16

19 Oct '16

the following patch was just integrated into master: commit 9c5fc62f96f3f98f5434216c5531722ef97ca03f Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Tue Oct 18 02:15:44 2016 +0200 nb/i945/gma.c: use IS_ENABLED instead of #if, #endif Change-Id: Ib58126e1c9001ed679e161d6d06241fac762bdb3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17049 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17049 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/skylake: Allow selecting FSP driver in Kconfig
by gerrit＠coreboot.org 19 Oct '16

19 Oct '16

the following patch was just integrated into master: commit fe517f635b85de64a7eff85bc9daf932ed211f6c Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Mon Oct 17 17:21:08 2016 +0530 soc/intel/skylake: Allow selecting FSP driver in Kconfig Enable mainboard Kconfig to select between FSP 2.0 & 1.1 driver to be used. If mainboard Kconfig selects MAINBOARD_USES_FSP2_0 the FSP2_0 driver is used else FSP1_1. Change-Id: I724aaa87c2b0b8f6ddb18f61af9c37176ef632f2 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Reviewed-on: https://review.coreboot.org/17044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17044 for details. -gerrit

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Patch merged into coreboot/master: winbond/w83627ehg: Remove unnecessary value
by gerrit＠coreboot.org 19 Oct '16

19 Oct '16

the following patch was just integrated into master: commit 09ec9e74a99521b4b4caab7a53b591db52be588b Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Mon Oct 17 21:51:12 2016 +0200 winbond/w83627ehg: Remove unnecessary value Change-Id: I5f88f34d1c040ac6ed413cfaf8ceb45a358c117c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/17048 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17048 for details. -gerrit

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Patch set updated for coreboot: payloads/external/Makefile.inc: Clean up makefile
by Martin Roth 19 Oct '16

19 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17046 -gerrit commit b770f7cd541e4b6aa69f12492d58245a0cb84e4a Author: Martin Roth <martinroth(a)google.com> Date: Mon Oct 17 10:11:10 2016 -0600 payloads/external/Makefile.inc: Clean up makefile - Add comments dividing the payload sections. - Move separate TINT and Memtest sections that were intermingled. Change-Id: If0bbd6e182359c5186a8b958dd2c9ab9f0e0a3f3 Signed-off-by: Martin Roth <martinroth(a)google.com> --- payloads/external/Makefile.inc | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 98ed4d2..e4d3e12 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -60,6 +60,8 @@ cbfs-files-$(CONFIG_INCLUDE_CONFIG_FILE) += payload_revision payload_revision-file := $(PAYLOAD_VERSION) payload_revision-type := raw +# SeaBIOS + SEABIOS_CC_OFFSET=$(if $(filter %ccache,$(HOSTCC)),2,1) payloads/external/SeaBIOS/seabios/out/bios.bin.elf seabios: $(DOTCONFIG) $(MAKE) -C payloads/external/SeaBIOS \ @@ -92,11 +94,16 @@ bootorder-file := $(strip $(CONFIG_SEABIOS_BOOTORDER_FILE)) bootorder-type := raw endif +# Depthcharge + payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(DOTCONFIG) $(CBFSTOOL) + $(MAKE) -C payloads/external/depthcharge \ BOARD=$(call ws_to_under,$(call strip_quotes,$(call tolower,$(CONFIG_MAINBOARD_PART_NUMBER)))) \ MFLAGS= MAKEFLAGS= +# FILO + filo: $(MAKE) -C payloads/external/FILO \ HOSTCC="$(HOSTCC)" \ @@ -109,6 +116,8 @@ payloads/external/FILO/filo/build/filo.elf: filo payloads/external/FILO/filo/.config: filo payloads/external/FILO/filo/build/version.h: filo +# Grub + grub2: $(MAKE) -C payloads/external/GRUB2 \ HOSTCC="$(HOSTCC)" \ @@ -119,14 +128,24 @@ grub2: payloads/external/GRUB2/grub2/build/default_payload.elf: grub2 +# U-Boot + payloads/external/U-Boot/u-boot/u-boot-dtb.bin u-boot: $(DOTCONFIG) $(MAKE) -C payloads/external/U-Boot \ CONFIG_UBOOT_MASTER=$(CONFIG_UBOOT_MASTER) \ CONFIG_UBOOT_STABLE=$(CONFIG_UBOOT_STABLE) +# TINT + payloads/external/tint/tint/tint.elf tint: $(MAKE) -C payloads/external/tint +cbfs-files-$(CONFIG_TINT_SECONDARY_PAYLOAD) += img/tint +img/tint-file := payloads/external/tint/tint/tint.elf +img/tint-type := payload + +# Memtest86+ + cbfs-files-$(CONFIG_MEMTEST_SECONDARY_PAYLOAD) += img/memtest img/memtest-file := payloads/external/Memtest86Plus/memtest86plus/memtest img/memtest-type := payload @@ -137,10 +156,6 @@ ifeq ($(CONFIG_CONSOLE_SERIAL)$(CONFIG_DRIVERS_UART_8250IO),yy) SERIAL_BAUD_RATE=$(CONFIG_TTYS0_BAUD) endif -cbfs-files-$(CONFIG_TINT_SECONDARY_PAYLOAD) += img/tint -img/tint-file := payloads/external/tint/tint/tint.elf -img/tint-type := payload - payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG) $(MAKE) -C payloads/external/Memtest86Plus all \ CC="$(CC_x86_32)" \ @@ -152,6 +167,8 @@ payloads/external/Memtest86Plus/memtest86plus/memtest: $(DOTCONFIG) $(MEMTEST_SERIAL_OPTIONS) \ MFLAGS= MAKEFLAGS= +# iPXE + PXE_ROM_PCI_ID:=$(subst $(comma),,$(CONFIG_PXE_ROM_ID)) ifeq ($(CONFIG_PXE_ROM),y)

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Patch set updated for coreboot: RISCV: architecture cleanup.
by Ronald G. Minnich 19 Oct '16

19 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17058 -gerrit commit e5d11c122d232150eedf46e236a63d701e089c05 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Oct 19 08:07:13 2016 -0700 RISCV: architecture cleanup. This includes changes that will make the lowrisc fpga implementation work. We provide a standard payload that makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 1 + src/arch/riscv/boot.c | 4 ++++ src/arch/riscv/include/vm.h | 10 ---------- src/arch/riscv/payload.S | 35 +++++++++++++++++++++++++++++++++++ src/arch/riscv/trap_handler.c | 1 + src/arch/riscv/virtual_memory.c | 40 +++++++++++++++++++++++++++++----------- 6 files changed, 70 insertions(+), 21 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 4bab459..cf6ce99 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -96,6 +96,7 @@ ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += sbi.S +ramstage-y += payload.S ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 7435490..35a9123 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <lib.h> #include <program_loading.h> #include <vm.h> #include <arch/encoding.h> @@ -21,9 +22,12 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); + void riscvpayload(void); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { + hexdump((void *)0x81000000, 128); initVirtualMemory(); + riscvpayload(); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index bee2ed4..6472cad 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -37,16 +37,6 @@ #define VA_BITS 39 #define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) -#define PROT_READ 1 -#define PROT_WRITE 2 -#define PROT_EXEC 4 - -#define MAP_PRIVATE 0x2 -#define MAP_FIXED 0x10 -#define MAP_ANONYMOUS 0x20 -#define MAP_POPULATE 0x8000 -#define MREMAP_FIXED 0x2 - #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S new file mode 100644 index 0000000..bc9654a --- /dev/null +++ b/src/arch/riscv/payload.S @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .global riscvpayload +riscvpayload: + /* Jump to 0xffffffff81000000 in S-mode */ + li t0, 0xffffffff81000000 + csrw mepc, t0 + csrr t0, mstatus + li t1, ~(3<<11) + and t0, t0, t1 + li t2, (1<<11) + or t0, t0, t2 + csrw mstatus, t0 + +#if 0 // remove for testing. +.L2: + li a5,1107296256 + li a4,48 + sw a4,0(a5) + j .L2 +#endif + // We're still in toolchain no mans land. + .word 0x30200073 + //mret diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ad49928..d2b05bd 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -163,6 +163,7 @@ void trap_handler(trapframe *tf) { break; } + //print_page_table(); die("Can't recover from trap. Halting.\n"); } diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index be8b488..fe4ac40 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -94,7 +94,7 @@ static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level) /* Print the page table structures to the console */ void print_page_table(void) { - print_page_table_at(root_page_table, 0, 0); + print_page_table_at((void *)(read_csr(sptbr)<<12), 0, 0); } void flush_tlb(void) @@ -115,9 +115,9 @@ pte_t ptd_create(uintptr_t ppn) pte_t pte_create(uintptr_t ppn, int prot, int user) { pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_R | PTE_V; - if (prot & PROT_WRITE) + if (prot & PTE_W) pte |= PTE_W; - if (prot & PROT_EXEC) + if (prot & PTE_X) pte |= PTE_X; if (user) pte |= PTE_U; @@ -147,21 +147,31 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); l2_idx += ((vaddr - virtMemStart) >> l2_shift); - middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, PROT_READ|PROT_WRITE|PROT_EXEC, 0); + middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, + PTE_R|PTE_W|PTE_X, 0); } // map SBI at top of vaddr space - uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface + // only need to map a single page for sbi interface + uintptr_t num_sbi_pages = 1; uintptr_t sbiStartAddress = (uintptr_t) &sbi_page; uintptr_t sbiAddr = sbiStartAddress; for (uintptr_t i = 0; i < num_sbi_pages; i++) { uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; - sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, PROT_READ|PROT_EXEC, 0); + sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, + PTE_W|PTE_R|PTE_X, 0); sbiAddr += RISCV_PGSIZE; } pte_t* sbi_pte = middle_pt + ((num_middle_pts << RISCV_PGLEVEL_BITS)-1); *sbi_pte = ptd_create((uintptr_t)sbi_pt >> RISCV_PGSHIFT); + // IO space. + + root_pt[0] = pte_create(0, PTE_W|PTE_R|PTE_X, 0); + root_pt[1] = pte_create(0x40000000>>RISCV_PGSHIFT, + PTE_W|PTE_R|PTE_X, 0); + root_pt[2] = pte_create(0x80000000>>RISCV_PGSHIFT, + PTE_W|PTE_R|PTE_X, 0); mb(); root_page_table = root_pt; uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT; @@ -185,12 +195,14 @@ void initVirtualMemory(void) { printk(BIOS_DEBUG, "-----------------------------\n"); } + // TODO: Figure out how to grab this from cbfs printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x90000000; // TODO: Figure out how to grab this from cbfs - uintptr_t virtualStart = 0xffffffff80000000; - uintptr_t pageTableStart = 0x91400000; + uintptr_t physicalStart = 0x81000000; + uintptr_t virtualStart = 0xffffffff81000000; + uintptr_t pageTableStart = 0x80800000; init_vm(virtualStart, physicalStart, pageTableStart); mb(); + flush_tlb(); #if IS_ENABLED(CONFIG_DEBUG_PRINT_PAGE_TABLES) printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); @@ -211,6 +223,7 @@ void mstatus_init(void) set_csr(mie, MIP_MSIP); /* Configure which exception causes are delegated to supervisor mode */ +/* set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH) | (1 << CAUSE_FAULT_FETCH) | (1 << CAUSE_ILLEGAL_INSTRUCTION) @@ -220,7 +233,12 @@ void mstatus_init(void) | (1 << CAUSE_USER_ECALL) ); +*/ /* Enable all user/supervisor-mode counters */ - write_csr(mscounteren, 0b111); - write_csr(mucounteren, 0b111); + /* We'll turn these on once lowrisc gets their bitstream up to + * 1.9. Right now there's no agreement on the values for these + * architectural registers. + */ + //write_csr(mscounteren, 0b111); + //write_csr(mucounteren, 0b111); }

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New patch to review for coreboot: RISCV: architecture cleanup.
by Ronald G. Minnich 19 Oct '16

19 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17058 -gerrit commit a563eb964aaae784fbcd3b6125fa976fb5d5efe3 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Oct 19 08:07:13 2016 -0700 RISCV: architecture cleanup. This includes changes that will make the lowrisc fpga implementation work. We provide a standard payload that makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 1 + src/arch/riscv/boot.c | 4 ++++ src/arch/riscv/include/vm.h | 10 ---------- src/arch/riscv/payload.S | 35 ++++++++++++++++++++++++++++++++++ src/arch/riscv/trap_handler.c | 1 + src/arch/riscv/virtual_memory.c | 42 +++++++++++++++++++++++++++++------------ 6 files changed, 71 insertions(+), 22 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 4bab459..cf6ce99 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -96,6 +96,7 @@ ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += sbi.S +ramstage-y += payload.S ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 7435490..35a9123 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <lib.h> #include <program_loading.h> #include <vm.h> #include <arch/encoding.h> @@ -21,9 +22,12 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); + void riscvpayload(void); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { + hexdump((void *)0x81000000, 128); initVirtualMemory(); + riscvpayload(); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index bee2ed4..6472cad 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -37,16 +37,6 @@ #define VA_BITS 39 #define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) -#define PROT_READ 1 -#define PROT_WRITE 2 -#define PROT_EXEC 4 - -#define MAP_PRIVATE 0x2 -#define MAP_FIXED 0x10 -#define MAP_ANONYMOUS 0x20 -#define MAP_POPULATE 0x8000 -#define MREMAP_FIXED 0x2 - #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S new file mode 100644 index 0000000..bc9654a --- /dev/null +++ b/src/arch/riscv/payload.S @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .global riscvpayload +riscvpayload: + /* Jump to 0xffffffff81000000 in S-mode */ + li t0, 0xffffffff81000000 + csrw mepc, t0 + csrr t0, mstatus + li t1, ~(3<<11) + and t0, t0, t1 + li t2, (1<<11) + or t0, t0, t2 + csrw mstatus, t0 + +#if 0 // remove for testing. +.L2: + li a5,1107296256 + li a4,48 + sw a4,0(a5) + j .L2 +#endif + // We're still in toolchain no mans land. + .word 0x30200073 + //mret diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ad49928..d2b05bd 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -163,6 +163,7 @@ void trap_handler(trapframe *tf) { break; } + //print_page_table(); die("Can't recover from trap. Halting.\n"); } diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index be8b488..6865e39 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -94,7 +94,7 @@ static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level) /* Print the page table structures to the console */ void print_page_table(void) { - print_page_table_at(root_page_table, 0, 0); + print_page_table_at((void *)(read_csr(sptbr)<<12), 0, 0); } void flush_tlb(void) @@ -115,13 +115,13 @@ pte_t ptd_create(uintptr_t ppn) pte_t pte_create(uintptr_t ppn, int prot, int user) { pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_R | PTE_V; - if (prot & PROT_WRITE) + if (prot & PTE_W) pte |= PTE_W; - if (prot & PROT_EXEC) + if (prot & PTE_X) pte |= PTE_X; if (user) pte |= PTE_U; - return pte; + return pte | 0x1f; } void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart) { @@ -147,21 +147,31 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); l2_idx += ((vaddr - virtMemStart) >> l2_shift); - middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, PROT_READ|PROT_WRITE|PROT_EXEC, 0); + middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, + PTE_R|PTE_W|PTE_X, 0); } // map SBI at top of vaddr space - uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface + // only need to map a single page for sbi interface + uintptr_t num_sbi_pages = 1; uintptr_t sbiStartAddress = (uintptr_t) &sbi_page; uintptr_t sbiAddr = sbiStartAddress; for (uintptr_t i = 0; i < num_sbi_pages; i++) { uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; - sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, PROT_READ|PROT_EXEC, 0); + sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, + PTE_W|PTE_R|PTE_X, 0); sbiAddr += RISCV_PGSIZE; } pte_t* sbi_pte = middle_pt + ((num_middle_pts << RISCV_PGLEVEL_BITS)-1); *sbi_pte = ptd_create((uintptr_t)sbi_pt >> RISCV_PGSHIFT); + // IO space. + + root_pt[0] = pte_create(0, PTE_W|PTE_R|PTE_X, 0); + root_pt[1] = pte_create(0x40000000>>RISCV_PGSHIFT, + PTE_W|PTE_R|PTE_X, 0); + root_pt[2] = pte_create(0x80000000>>RISCV_PGSHIFT, + PTE_W|PTE_R|PTE_X, 0); mb(); root_page_table = root_pt; uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT; @@ -185,12 +195,14 @@ void initVirtualMemory(void) { printk(BIOS_DEBUG, "-----------------------------\n"); } + // TODO: Figure out how to grab this from cbfs printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x90000000; // TODO: Figure out how to grab this from cbfs - uintptr_t virtualStart = 0xffffffff80000000; - uintptr_t pageTableStart = 0x91400000; + uintptr_t physicalStart = 0x81000000; + uintptr_t virtualStart = 0xffffffff81000000; + uintptr_t pageTableStart = 0x80800000; init_vm(virtualStart, physicalStart, pageTableStart); mb(); + flush_tlb(); #if IS_ENABLED(CONFIG_DEBUG_PRINT_PAGE_TABLES) printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); @@ -211,6 +223,7 @@ void mstatus_init(void) set_csr(mie, MIP_MSIP); /* Configure which exception causes are delegated to supervisor mode */ +/* set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH) | (1 << CAUSE_FAULT_FETCH) | (1 << CAUSE_ILLEGAL_INSTRUCTION) @@ -220,7 +233,12 @@ void mstatus_init(void) | (1 << CAUSE_USER_ECALL) ); +*/ /* Enable all user/supervisor-mode counters */ - write_csr(mscounteren, 0b111); - write_csr(mucounteren, 0b111); + /* We'll turn these on once lowrisc gets their bitstream up to + * 1.9. Right now there's no agreement on the values for these + * architectural registers. + */ + //write_csr(mscounteren, 0b111); + //write_csr(mucounteren, 0b111); }

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Patch merged into coreboot/master: nb/i945/raminit: Add fix for clock crossing for 800MHz FSB CPU
by gerrit＠coreboot.org 19 Oct '16

19 Oct '16

the following patch was just integrated into master: commit 8b6df62fc21dc167979c03aa88cfe9cf03a115a8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sun Oct 16 10:58:01 2016 +0200 nb/i945/raminit: Add fix for clock crossing for 800MHz FSB CPU The cross clocking of 800MHz FSB CPU with 667MHz RAM was incorrect. The result is that 800MHz FSB CPUs now properly work with 667MHz RAM. Value taken from vendor bios on ga-945gcm-s2l and suggested by Haouas Elyes. Change-Id: I56c12af50c75a735af0150a4e7bce4faacc93648 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17038 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17038 for details. -gerrit

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Patch merged into coreboot/master: nb/i945/raminit: Add fix for 1067MHz FSB CPUs
by gerrit＠coreboot.org 19 Oct '16

19 Oct '16

the following patch was just integrated into master: commit e1897616038f78015633134fc38e351c33a46975 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Oct 15 23:29:18 2016 +0200 nb/i945/raminit: Add fix for 1067MHz FSB CPUs Previously the 945gc raminit only worked for 533MHz FSB CPUs. This extends the tRD_Mclks in drt0_table for other FSB speeds. The values are taken from the vendor bios of Gigabyte ga-945gcm-s2l. The result is that 1067MHz FSB CPUs now boot without problems. 800MHz FSB cpus still don't get past romstage. Change-Id: I13a6b97d2e580512155edf66c48405a153121957 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Reviewed-on: https://review.coreboot.org/17034 Tested-by: build bot (Jenkins) Reviewed-by: HAOUAS Elyes <ehaouas(a)noos.fr> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17034 for details. -gerrit

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Patch merged into coreboot/master: util/msrtool: Use tabs for indents
by gerrit＠coreboot.org 19 Oct '16

19 Oct '16

the following patch was just integrated into master: commit 3baa7e707388306d81beac7cc34634e4d831da6d Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Sat Oct 15 10:01:21 2016 +0200 util/msrtool: Use tabs for indents Change-Id: Ib1aa4ad04dc8a584a751677aac5652cfa2e457df Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/17031 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> Reviewed-by: Anton Kochkov <anton.kochkov(a)gmail.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17031 for details. -gerrit

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coreboot-gerrit October 2016