coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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1281 discussions

Patch set updated for coreboot: [DON'T MERGE] Investigating CL #16987
by Jonathan Neuschäfer 19 Oct '16

19 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17060 -gerrit commit d6316837105d4818354b5a6ad262ab7989b08eb0 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Oct 19 02:18:54 2016 +0200 [DON'T MERGE] Investigating CL #16987 https://review.coreboot.org/#/c/16987/ results in a crash in AMDFWTOOL for some boards, on jenkins. With this patch, I try to figure out what's going on. Change-Id: Ic36b8be2b0ee458311dcc8e9139df2b4d113b4ba Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/Kconfig | 1 + src/southbridge/amd/agesa/hudson/Makefile.inc | 2 +- src/southbridge/amd/pi/hudson/Makefile.inc | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 1dc89ca..759b1de 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -2,6 +2,7 @@ if VENDOR_EMULATION choice prompt "Mainboard model" + default BOARD_EMULATION_QEMU_X86_I440FX source "src/mainboard/emulation/*/Kconfig.name" diff --git a/src/southbridge/amd/agesa/hudson/Makefile.inc b/src/southbridge/amd/agesa/hudson/Makefile.inc index 3877e60..bb96e22 100644 --- a/src/southbridge/amd/agesa/hudson/Makefile.inc +++ b/src/southbridge/amd/agesa/hudson/Makefile.inc @@ -58,7 +58,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ + valgrind $(AMDFWTOOL) \ $(OPT_HUDSON_XHCI_FWM_FILE) \ $(OPT_HUDSON_IMC_FWM_FILE) \ $(OPT_HUDSON_GEC_FWM_FILE) \ diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 291e25f..9c790c6 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -206,7 +206,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" - $(AMDFWTOOL) \ + valgrind $(AMDFWTOOL) \ $(OPT_HUDSON_XHCI_FWM_FILE) \ $(OPT_HUDSON_IMC_FWM_FILE) \ $(OPT_HUDSON_GEC_FWM_FILE) \

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Patch set updated for coreboot: marvell/mvmap2315: Compose BOOTBLOCK region
by Martin Roth 19 Oct '16

19 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16747 -gerrit commit f1b5972796859a958de3d657b78b78e2ec5f0b4f Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Sep 23 17:40:15 2016 -0700 marvell/mvmap2315: Compose BOOTBLOCK region This patch adds a Makefile rule for mvmap2315 to install a BDB and bootblock code in the BOOTBLOCK region. The resulting BDB has a header and data both signed by a RSA-4096 key. BUG=chrome-os-partner:57889 BRANCH=none TEST=emerge-rotor coreboot and examined the output binary. Booted coreboot.rom on Palladium. Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- 3rdparty/blobs | 2 +- src/soc/marvell/mvmap2315/Makefile.inc | 75 +++++++++++++++++++++++++++++++++- 2 files changed, 75 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8ad2d63..9ba0703 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8ad2d6385652e14b6f0d35ab9b474c31ddeb1773 +Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1 diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index d30ab68..c6426f1 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -63,4 +63,77 @@ romstage-y += wdt.c CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ -endif +# +# Common Boot Flow parameters +# +BOOTBLOCK_REGION_SIZE = 131072 +BOOTBLOCK_TYPE = 1 +BOOTBLOCK_PARTITION = 1 +BOOTBLOCK_LOAD_ADDRESS = 0xe000c000 +BDB = $(obj)/bdb.bin +BDB_LOAD_ADDRESS = 0xe0000000 +DATA_VERSION = 2 + +# +# Keys used to create BDB +# +KEYDIR = $(VBOOT_SOURCE)/tests/testkeys +BDBKEY_PUB = $(KEYDIR)/bdbkey.keyb +BDBKEY_PRI = $(KEYDIR)/bdbkey.pem +BDBKEY_DIGEST = $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin +# Use bdbkeys because mvmap2315's bootROM doesn't support RSA3072b with +# exponent 3 and the algorithms for BDB key and data key have to match. +DATAKEY_PUB = $(KEYDIR)/bdbkey.keyb +DATAKEY_PRI = $(KEYDIR)/bdbkey.pem + +# Calculate bootblock.raw.bin's size and offset +.PHONY: bootblock_offset +bootblock_offset: $(objcbfs)/bootblock.raw.bin + $(eval BOOTBLOCK_SIZE = $(call file-size, $<)) + $(eval BOOTBLOCK_OFFSET = $(call int-subtract, \ + $(BOOTBLOCK_REGION_SIZE) $(BOOTBLOCK_SIZE))) + +# +# Create BDB +# +# TODO: Verify sign algorithms of the BDB key and data key are supported +$(BDB): $(objcbfs)/bootblock.raw.bin $(FUTILITY) bootblock_offset \ + $(BDBKEY_PRI) $(BDBKEY_PUB) $(DATAKEY_PRI) $(DATAKEY_PUB) \ + $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin + $(FUTILITY) bdb --create $@.tmp \ + --bdbkey_pri $(BDBKEY_PRI) --bdbkey_pub $(BDBKEY_PUB) \ + --datakey_pri $(DATAKEY_PRI) --datakey_pub $(DATAKEY_PUB) \ + --load_address $(BDB_LOAD_ADDRESS) + $(FUTILITY) bdb --add $@.tmp \ + --data $< \ + --offset $(BOOTBLOCK_OFFSET) \ + --partition $(BOOTBLOCK_PARTITION) \ + --type $(BOOTBLOCK_TYPE) \ + --load_address $(BOOTBLOCK_LOAD_ADDRESS) + $(FUTILITY) bdb --resign $@.tmp \ + --datakey_pri $(DATAKEY_PRI) \ + --data_version $(DATA_VERSION) + $(FUTILITY) bdb --verify $@.tmp --key_digest $(BDBKEY_DIGEST) + mv $@.tmp $@ + +# +# Create custom bootblock.bin +# +# This overrides generic pattern rule *.raw.bin -> *.bin for bootblock.bin. +# bootblock.bin is structured as follows: +# +------------------+ +# | BDB | +# +------------------+ +# | 000............0 | +# +------------------+ +# |bootblock.raw.bin | +# +------------------+ +# And this will be placed in BOOTBLOCK region. +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BDB) bootblock_offset + dd if=/dev/zero bs=1 count=$(BOOTBLOCK_REGION_SIZE) of=$@.tmp + dd if=$(BDB) bs=1 count=$(call file-size, $(BDB)) conv=notrunc of=$@.tmp + dd if=$(objcbfs)/bootblock.raw.bin bs=1 count=$(BOOTBLOCK_SIZE) \ + seek=$(BOOTBLOCK_OFFSET) conv=notrunc of=$@.tmp + mv $@.tmp $@ + +endif \ No newline at end of file

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New patch to review for coreboot: 3rdparty/vboot: update to latest master for rotor support
by Martin Roth 19 Oct '16

19 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17061 -gerrit commit 0291dd982c964a2819d420f78a389864d721b33e Author: Martin Roth <martinroth(a)google.com> Date: Wed Oct 19 13:39:57 2016 -0600 3rdparty/vboot: update to latest master for rotor support This pulls in the bdb support for futility so that rotor can build. Change-Id: Icfa432fb840bea3e1616933ed02cf34a681fa3ce Signed-off-by: Martin Roth <martinroth(a)google.com> --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 46b77fb..3875e61 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 46b77fb2f04941c869c3a98cd17e9209c36b2917 +Subproject commit 3875e6191f24ceb83415f553ca91dcac7b71073b

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Patch set updated for coreboot: [DON'T MERGE] Investigating CL #16987
by Jonathan Neuschäfer 19 Oct '16

19 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17060 -gerrit commit ec703a95dc8ef0aee543bff501ad34d4477398a4 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Oct 19 02:18:54 2016 +0200 [DON'T MERGE] Investigating CL #16987 https://review.coreboot.org/#/c/16987/ results in a crash in AMDFWTOOL for some boards, on jenkins. With this patch, I try to figure out what's going on. Change-Id: Ic36b8be2b0ee458311dcc8e9139df2b4d113b4ba Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- Makefile.inc | 2 +- src/mainboard/emulation/Kconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 127f372..1eb4b02 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -487,7 +487,7 @@ $(IFDFAKE): $(top)/util/ifdfake/ifdfake.c AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< + $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -fsanitize=address -o $@ $< CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 1dc89ca..759b1de 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -2,6 +2,7 @@ if VENDOR_EMULATION choice prompt "Mainboard model" + default BOARD_EMULATION_QEMU_X86_I440FX source "src/mainboard/emulation/*/Kconfig.name"

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Patch set updated for coreboot: [DON'T MERGE] Investigating CL #16987
by Jonathan Neuschäfer 19 Oct '16

19 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17060 -gerrit commit 1cd2d1ea10b5f350fbb692523e7dab90586d1c23 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Oct 19 02:18:54 2016 +0200 [DON'T MERGE] Investigating CL #16987 https://review.coreboot.org/#/c/16987/ results in a crash in AMDFWTOOL for some tools, on jenkins. With this patch, I try to figure out what's going on. Change-Id: Ic36b8be2b0ee458311dcc8e9139df2b4d113b4ba Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- Makefile.inc | 2 +- src/mainboard/emulation/Kconfig | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 127f372..1eb4b02 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -487,7 +487,7 @@ $(IFDFAKE): $(top)/util/ifdfake/ifdfake.c AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< + $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -fsanitize=address -o $@ $< CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 1dc89ca..759b1de 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -2,6 +2,7 @@ if VENDOR_EMULATION choice prompt "Mainboard model" + default BOARD_EMULATION_QEMU_X86_I440FX source "src/mainboard/emulation/*/Kconfig.name"

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Patch set updated for coreboot: [DON'T MERGE] Investigating CL #16987
by Jonathan Neuschäfer 19 Oct '16

19 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17060 -gerrit commit 25670c8a59e53b253c899e60e28b517995fae172 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Oct 19 02:18:54 2016 +0200 [DON'T MERGE] Investigating CL #16987 https://review.coreboot.org/#/c/16987/ results in a crash in AMDFWTOOL for some tools, on jenkins. With this patch, I try to figure out what's going on. Change-Id: Ic36b8be2b0ee458311dcc8e9139df2b4d113b4ba Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- Makefile.inc | 3 ++- src/mainboard/emulation/Kconfig | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 127f372..8c2705b 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -487,7 +487,8 @@ $(IFDFAKE): $(top)/util/ifdfake/ifdfake.c AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< + @$(HOSTCC) --version + $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -fsanitize=address -o $@ $< CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 1dc89ca..759b1de 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -2,6 +2,7 @@ if VENDOR_EMULATION choice prompt "Mainboard model" + default BOARD_EMULATION_QEMU_X86_I440FX source "src/mainboard/emulation/*/Kconfig.name"

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Patch merged into coreboot/master: intel/broadwell: "free" memory after use
by gerrit＠coreboot.org 19 Oct '16

19 Oct '16

the following patch was just integrated into master: commit b753eeb7afe0f51a07725b13a2f53ed10d7930bc Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Oct 18 19:46:33 2016 +0200 intel/broadwell: "free" memory after use While we stub out free(), tools like coverity scan have no idea, and it might change in the future. So free it. Change-Id: I1d93a6f45b64445662daa95b51128140ad0a87e2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1260716 Reviewed-on: https://review.coreboot.org/17055 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> See https://review.coreboot.org/17055 for details. -gerrit

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New patch to review for coreboot: [DON'T MERGE] Investigating CL #16987
by Jonathan Neuschäfer 19 Oct '16

19 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17060 -gerrit commit 87aeecdb98290436b865aa2b022893a1e0468e99 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Oct 19 02:18:54 2016 +0200 [DON'T MERGE] Investigating CL #16987 https://review.coreboot.org/#/c/16987/ results in a crash in AMDFWTOOL for some tools, on jenkins. With this patch, I try to figure out what's going on. Change-Id: Ic36b8be2b0ee458311dcc8e9139df2b4d113b4ba Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 1dc89ca..759b1de 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -2,6 +2,7 @@ if VENDOR_EMULATION choice prompt "Mainboard model" + default BOARD_EMULATION_QEMU_X86_I440FX source "src/mainboard/emulation/*/Kconfig.name"

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New patch to review for coreboot: util/inteltool: Remove unnecessary whitespace
by HAOUAS Elyes 19 Oct '16

19 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17059 -gerrit commit 4cbb45093e9060291dcafeaa2ffcc9f46124c440 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 19 18:13:55 2016 +0200 util/inteltool: Remove unnecessary whitespace Change-Id: Id42a2901cf76e6b867f62a752a38bbd6f6e5f54e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- util/inteltool/ivy_memory.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 92e61ac..f0e473f 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -124,9 +124,9 @@ void ivybridge_dump_timings(const char *dump_spd_file) mad_dimm[channel] = read_mchbar32(0x5004 + 4 * channel); } - printf(".rankmap = { 0x%x, 0x%x }, \n", rankmap[0], rankmap[1]); + printf(".rankmap = { 0x%x, 0x%x },\n", rankmap[0], rankmap[1]); - printf(".mad_dimm = { 0x%x, 0x%x }, \n", mad_dimm[0], mad_dimm[1]); + printf(".mad_dimm = { 0x%x, 0x%x },\n", mad_dimm[0], mad_dimm[1]); for (channel = 0; channel < 2; channel++) if (rankmap[channel]) {

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Patch set updated for coreboot: util/inteltool: Use tabs for indents
by HAOUAS Elyes 19 Oct '16

19 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17025 -gerrit commit 9899bbec7defa71c53fcb3e9d80eb08adc8a614e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 19 17:59:10 2016 +0200 util/inteltool: Use tabs for indents Change-Id: I9d27c276053c51021166f4b22d150060e415d08f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- util/inteltool/cpu.c | 136 ++++++++++++++++++++++----------------------- util/inteltool/inteltool.h | 6 +- util/inteltool/pcie.c | 90 +++++++++++++++--------------- 3 files changed, 116 insertions(+), 116 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 9bdc1eb..afafc63 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -815,74 +815,74 @@ int print_intel_core_msrs(void) */ }; - static const msr_entry_t model6_atom_per_core_msrs[] = { - { 0x0006, "IA32_MONITOR_FILTER_SIZE" }, - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, - { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, - { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, - { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, - { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, - { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, - { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, - { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, - { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, - { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, - { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, - { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, - { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, - { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, - { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, - { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, - /* Write register */ - /* - { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - */ - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00c1, "IA32_PMC0" }, - { 0x00c2, "IA32_PMC1" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0186, "IA32_PERF_EVNTSEL0" }, - { 0x0187, "IA32_PERF_EVNTSEL1" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01c9, "MSR_LASTBRANCH_TOS" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x01dd, "MSR_LER_FROM_LIP" }, - { 0x01de, "MSR_LER_TO_LIP" }, - { 0x0277, "IA32_PAT" }, - { 0x0309, "IA32_FIXED_CTR0" }, - { 0x030a, "IA32_FIXED_CTR1" }, - { 0x030b, "IA32_FIXED_CTR2" }, - { 0x038d, "IA32_FIXED_CTR_CTRL" }, - { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, - { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, - { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, - { 0x03f1, "MSR_PEBS_ENABLE" }, - { 0x0480, "IA32_VMX_BASIC" }, - { 0x0481, "IA32_VMX_PINBASED_CTLS" }, - { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, - { 0x0483, "IA32_VMX_EXIT_CTLS" }, - { 0x0484, "IA32_VMX_ENTRY_CTLS" }, - { 0x0485, "IA32_VMX_MISC" }, - { 0x0486, "IA32_VMX_CR0_FIXED0" }, - { 0x0487, "IA32_VMX_CR0_FIXED1" }, - { 0x0488, "IA32_VMX_CR4_FIXED0" }, - { 0x0489, "IA32_VMX_CR4_FIXED1" }, - { 0x048a, "IA32_VMX_VMCS_ENUM" }, - { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, - { 0x0600, "IA32_DS_AREA" }, - }; + static const msr_entry_t model6_atom_per_core_msrs[] = { + { 0x0006, "IA32_MONITOR_FILTER_SIZE" }, + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, + { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, + { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, + { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, + { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, + { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, + { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, + { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, + { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, + { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, + { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, + { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, + { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, + { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, + { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, + { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, + /* Write register */ + /* + { 0x0079, "IA32_BIOS_UPDT_TRIG" }, + */ + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00c1, "IA32_PMC0" }, + { 0x00c2, "IA32_PMC1" }, + { 0x00e7, "IA32_MPERF" }, + { 0x00e8, "IA32_APERF" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0186, "IA32_PERF_EVNTSEL0" }, + { 0x0187, "IA32_PERF_EVNTSEL1" }, + { 0x0199, "IA32_PERF_CONTROL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x01a0, "IA32_MISC_ENABLES" }, + { 0x01c9, "MSR_LASTBRANCH_TOS" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x01dd, "MSR_LER_FROM_LIP" }, + { 0x01de, "MSR_LER_TO_LIP" }, + { 0x0277, "IA32_PAT" }, + { 0x0309, "IA32_FIXED_CTR0" }, + { 0x030a, "IA32_FIXED_CTR1" }, + { 0x030b, "IA32_FIXED_CTR2" }, + { 0x038d, "IA32_FIXED_CTR_CTRL" }, + { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, + { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, + { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, + { 0x03f1, "MSR_PEBS_ENABLE" }, + { 0x0480, "IA32_VMX_BASIC" }, + { 0x0481, "IA32_VMX_PINBASED_CTLS" }, + { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, + { 0x0483, "IA32_VMX_EXIT_CTLS" }, + { 0x0484, "IA32_VMX_ENTRY_CTLS" }, + { 0x0485, "IA32_VMX_MISC" }, + { 0x0486, "IA32_VMX_CR0_FIXED0" }, + { 0x0487, "IA32_VMX_CR0_FIXED1" }, + { 0x0488, "IA32_VMX_CR4_FIXED0" }, + { 0x0489, "IA32_VMX_CR4_FIXED1" }, + { 0x048a, "IA32_VMX_VMCS_ENUM" }, + { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, + { 0x0600, "IA32_DS_AREA" }, + }; static const msr_entry_t model20650_global_msrs[] = { { 0x0000, "IA32_P5_MC_ADDR" }, diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index c6f486f..5931cb0 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -44,9 +44,9 @@ static inline uint8_t inb(unsigned port) } static inline uint16_t inw(unsigned port) { - uint16_t data; - __asm volatile("inw %w1,%0": "=a" (data) : "d" (port)); - return data; + uint16_t data; + __asm volatile("inw %w1,%0": "=a" (data) : "d" (port)); + return data; } static inline uint32_t inl(unsigned port) { diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index de70e6d..67b0e19 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -123,51 +123,51 @@ static const io_register_t sandybridge_dmi_registers[] = { * 329002-002 */ static const io_register_t haswell_ult_dmi_registers[] = { - { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability - { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 - { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 - { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control -/* { 0x0E, 2, "RSVD" }, // Reserved */ - { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability - { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control -/* { 0x18, 2, "RSVD" }, // Reserved */ - { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status - { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability - { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control -/* { 0x24, 2, "RSVD" }, // Reserved */ - { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status - { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability - { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control -/* { 0x30, 2, "RSVD" }, // Reserved */ - { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status - { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability - { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control -/* { 0x3C, 2, "RSVD" }, // Reserved */ - { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status - { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ - { 0x44, 4, "DMIESD" }, // DMI Element Self Description -/* { 0x48, 4, "RSVD" }, // Reserved */ -/* { 0x4C, 4, "RSVD" }, // Reserved */ - { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description -/* { 0x54, 4, "RSVD" }, // Reserved */ - { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address - { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address - { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description -/* { 0x64, 4, "RSVD" }, // Reserved */ - { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address -/* { 0x6C, 4, "RSVD" }, // Reserved */ -/* { 0x70, 4, "RSVD" }, // Reserved */ -/* { 0x74, 4, "RSVD" }, // Reserved */ -/* { 0x78, 4, "RSVD" }, // Reserved */ -/* { 0x7C, 4, "RSVD" }, // Reserved */ -/* { 0x80, 4, "RSVD" }, // Reserved */ -/* { 0x84, 4, "RSVD" }, // Reserved */ - { 0x88, 2, "LCTL" }, // Link Control - /* ... - Reserved */ - { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status - { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask - { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status - { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask + { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control +/* { 0x0E, 2, "RSVD" }, // Reserved */ + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control +/* { 0x18, 2, "RSVD" }, // Reserved */ + { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control +/* { 0x24, 2, "RSVD" }, // Reserved */ + { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status + { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability + { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control +/* { 0x30, 2, "RSVD" }, // Reserved */ + { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status + { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability + { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control +/* { 0x3C, 2, "RSVD" }, // Reserved */ + { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status + { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ + { 0x44, 4, "DMIESD" }, // DMI Element Self Description +/* { 0x48, 4, "RSVD" }, // Reserved */ +/* { 0x4C, 4, "RSVD" }, // Reserved */ + { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description +/* { 0x54, 4, "RSVD" }, // Reserved */ + { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address + { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address + { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description +/* { 0x64, 4, "RSVD" }, // Reserved */ + { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address +/* { 0x6C, 4, "RSVD" }, // Reserved */ +/* { 0x70, 4, "RSVD" }, // Reserved */ +/* { 0x74, 4, "RSVD" }, // Reserved */ +/* { 0x78, 4, "RSVD" }, // Reserved */ +/* { 0x7C, 4, "RSVD" }, // Reserved */ +/* { 0x80, 4, "RSVD" }, // Reserved */ +/* { 0x84, 4, "RSVD" }, // Reserved */ + { 0x88, 2, "LCTL" }, // Link Control + /* ... - Reserved */ + { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status + { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask + { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status + { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask /* ... - Reserved */ };

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coreboot-gerrit October 2016