coreboot-gerrit October 2016

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Patch set updated for coreboot: northbridge/intel/i5000: Convert 'for(; ; )' to 'die'
by HAOUAS Elyes 19 Oct '16

19 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17006 -gerrit commit 0ccb05d521df3cc5da8cf0d8e16ee73498f80b56 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 12 19:57:38 2016 +0200 northbridge/intel/i5000: Convert 'for(;;)' to 'die' Change-Id: I1ceea759a40d740503bde725ad6d72fab4aa7971 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- src/northbridge/intel/i5000/raminit.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/northbridge/intel/i5000/raminit.c b/src/northbridge/intel/i5000/raminit.c index 1a802b0..3b06a49 100644 --- a/src/northbridge/intel/i5000/raminit.c +++ b/src/northbridge/intel/i5000/raminit.c @@ -351,9 +351,8 @@ static int i5000_amb_smbus_write(struct i5000_fbdimm *d, int byte1, int byte2) if (status & I5000_SPD_WOD && timeout) return 0; - printk(BIOS_ERR, "SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n", + die("SMBus write failed: %d/%d/%d, byte1 %02x, byte2 %02x status %04x\n", d->branch->num, d->channel->num, d->num, byte1, byte2, status); - for (;;); return -1; }

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Patch set updated for coreboot: util/inteltool: Use tabs for indents
by HAOUAS Elyes 19 Oct '16

19 Oct '16

HAOUAS Elyes (ehaouas(a)noos.fr) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17025 -gerrit commit 071f53d79f35e405705458e252a27bb39992fe81 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Thu Oct 13 21:55:08 2016 +0200 util/inteltool: Use tabs for indents Change-Id: I9d27c276053c51021166f4b22d150060e415d08f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- util/inteltool/cpu.c | 2098 ++++++++++++++++++++++---------------------- util/inteltool/inteltool.h | 6 +- util/inteltool/pcie.c | 90 +- 3 files changed, 1095 insertions(+), 1099 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 9bdc1eb..61c2927 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -98,908 +98,907 @@ int print_intel_core_msrs(void) char *name; } msr_entry_t; - /* Pentium III */ - static const msr_entry_t model67x_global_msrs[] = { - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x0033, "TEST_CTL" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x0088, "BBL_CR_D0" }, - { 0x0089, "BBL_CR_D1" }, - { 0x008a, "BBL_CR_D2" }, - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00c1, "PERFCTR0" }, - { 0x00c2, "PERFCTR1" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0116, "BBL_CR_ADDR" }, - { 0x0118, "BBL_CR_DECC" }, - { 0x0119, "BBL_CR_CTL" }, - //{ 0x011a, "BBL_CR_TRIG" }, - { 0x011b, "BBL_CR_BUSY" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x017b, "IA32_MCG_CTL" }, - { 0x0186, "IA32_PERF_EVNTSEL0" }, - { 0x0187, "IA32_PERF_EVNTSEL1" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x01db, "MSR_LASTBRANCHFROMIP" }, - { 0x01dc, "MSR_LASTBRANCHTOIP" }, - { 0x01dd, "MSR_LASTINTFROMIP" }, - { 0x01de, "MSR_LASTINTTOIP" }, - { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x0404, "IA32_MC1_CTL" }, - { 0x0405, "IA32_MC1_STATUS" }, - { 0x0406, "IA32_MC1_ADDR" }, - //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO - { 0x0408, "IA32_MC2_CTL" }, - { 0x0409, "IA32_MC2_STATUS" }, - { 0x040a, "IA32_MC2_ADDR" }, - //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - { 0x0410, "IA32_MC3_CTL" }, - { 0x0411, "IA32_MC3_STATUS" }, - { 0x0412, "IA32_MC3_ADDR" }, - //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO - }; +/* Pentium III */ +static const msr_entry_t model67x_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x002a, "EBL_CR_POWERON" }, + { 0x0033, "TEST_CTL" }, + //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO + { 0x0088, "BBL_CR_D0" }, + { 0x0089, "BBL_CR_D1" }, + { 0x008a, "BBL_CR_D2" }, + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00c1, "PERFCTR0" }, + { 0x00c2, "PERFCTR1" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0116, "BBL_CR_ADDR" }, + { 0x0118, "BBL_CR_DECC" }, + { 0x0119, "BBL_CR_CTL" }, + //{ 0x011a, "BBL_CR_TRIG" }, + { 0x011b, "BBL_CR_BUSY" }, + { 0x011e, "BBL_CR_CTL3" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x017b, "IA32_MCG_CTL" }, + { 0x0186, "IA32_PERF_EVNTSEL0" }, + { 0x0187, "IA32_PERF_EVNTSEL1" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x01db, "MSR_LASTBRANCHFROMIP" }, + { 0x01dc, "MSR_LASTBRANCHTOIP" }, + { 0x01dd, "MSR_LASTINTFROMIP" }, + { 0x01de, "MSR_LASTINTTOIP" }, + { 0x01e0, "MSR_ROB_CR_BKUPTMPDR6" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO + { 0x0404, "IA32_MC1_CTL" }, + { 0x0405, "IA32_MC1_STATUS" }, + { 0x0406, "IA32_MC1_ADDR" }, + //{ 0x0407, "IA32_MC1_MISC" }, // Seems to be RO + { 0x0408, "IA32_MC2_CTL" }, + { 0x0409, "IA32_MC2_STATUS" }, + { 0x040a, "IA32_MC2_ADDR" }, + //{ 0x040b, "IA32_MC2_MISC" }, // Seems to be RO + { 0x040c, "IA32_MC4_CTL" }, + { 0x040d, "IA32_MC4_STATUS" }, + { 0x040e, "IA32_MC4_ADDR" }, + //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO + { 0x0410, "IA32_MC3_CTL" }, + { 0x0411, "IA32_MC3_STATUS" }, + { 0x0412, "IA32_MC3_ADDR" }, + //{ 0x0413, "IA32_MC3_MISC" }, // Seems to be RO +}; - static const msr_entry_t model6bx_global_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x0033, "TEST_CTL" }, - { 0x003f, "THERM_DIODE_OFFSET" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00c1, "PERFCTR0" }, - { 0x00c2, "PERFCTR1" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - }; +static const msr_entry_t model6bx_global_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x002a, "EBL_CR_POWERON" }, + { 0x0033, "TEST_CTL" }, + { 0x003f, "THERM_DIODE_OFFSET" }, + //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00c1, "PERFCTR0" }, + { 0x00c2, "PERFCTR1" }, + { 0x011e, "BBL_CR_CTL3" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x0199, "IA32_PERF_CONTROL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x01a0, "IA32_MISC_ENABLES" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO + { 0x040c, "IA32_MC4_CTL" }, + { 0x040d, "IA32_MC4_STATUS" }, + { 0x040e, "IA32_MC4_ADDR" }, + //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO +}; - static const msr_entry_t model6ex_global_msrs[] = { - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x00cd, "FSB_CLOCK_STS" }, - { 0x00ce, "FSB_CLOCK_VCC" }, - { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" }, - { 0x00e3, "PMG_IO_BASE_ADDR" }, - { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, - { 0x00ee, "EXT_CONFIG" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0194, "CLOCK_FLEX_MAX" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01aa, "PIC_SENS_CFG" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - }; +static const msr_entry_t model6ex_global_msrs[] = { + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "EBL_CR_POWERON" }, + { 0x00cd, "FSB_CLOCK_STS" }, + { 0x00ce, "FSB_CLOCK_VCC" }, + { 0x00e2, "CLOCK_CST_CONFIG_CONTROL" }, + { 0x00e3, "PMG_IO_BASE_ADDR" }, + { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, + { 0x00ee, "EXT_CONFIG" }, + { 0x011e, "BBL_CR_CTL3" }, + { 0x0194, "CLOCK_FLEX_MAX" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x01a0, "IA32_MISC_ENABLES" }, + { 0x01aa, "PIC_SENS_CFG" }, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO + { 0x040c, "IA32_MC4_CTL" }, + { 0x040d, "IA32_MC4_STATUS" }, + { 0x040e, "IA32_MC4_ADDR" }, + //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO +}; - static const msr_entry_t model6ex_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x003f, "IA32_TEMPERATURE_OFFSET" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x015f, "DTS_CAL_CTRL" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x019d, "GV_THERM" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO - }; +static const msr_entry_t model6ex_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x003f, "IA32_TEMPERATURE_OFFSET" }, + //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00e7, "IA32_MPERF" }, + { 0x00e8, "IA32_APERF" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x015f, "DTS_CAL_CTRL" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0199, "IA32_PERF_CONTROL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x019d, "GV_THERM" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO +}; - static const msr_entry_t model6fx_global_msrs[] = { - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "EBL_CR_POWERON" }, - { 0x003f, "IA32_TEMPERATURE_OFFSET" }, - { 0x00a8, "EMTTM_CR_TABLE0" }, - { 0x00a9, "EMTTM_CR_TABLE1" }, - { 0x00aa, "EMTTM_CR_TABLE2" }, - { 0x00ab, "EMTTM_CR_TABLE3" }, - { 0x00ac, "EMTTM_CR_TABLE4" }, - { 0x00ad, "EMTTM_CR_TABLE5" }, - { 0x00cd, "FSB_CLOCK_STS" }, - { 0x00e2, "PMG_CST_CONFIG_CONTROL" }, - { 0x00e3, "PMG_IO_BASE_ADDR" }, - { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, - { 0x00ee, "EXT_CONFIG" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0194, "CLOCK_FLEX_MAX" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01aa, "PIC_SENS_CFG" }, - { 0x0400, "IA32_MC0_CTL" }, - { 0x0401, "IA32_MC0_STATUS" }, - { 0x0402, "IA32_MC0_ADDR" }, - //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO - { 0x040c, "IA32_MC4_CTL" }, - { 0x040d, "IA32_MC4_STATUS" }, - { 0x040e, "IA32_MC4_ADDR" }, - //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO - }; +static const msr_entry_t model6fx_global_msrs[] = { + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "EBL_CR_POWERON" }, + { 0x003f, "IA32_TEMPERATURE_OFFSET" }, + { 0x00a8, "EMTTM_CR_TABLE0" }, + { 0x00a9, "EMTTM_CR_TABLE1" }, + { 0x00aa, "EMTTM_CR_TABLE2" }, + { 0x00ab, "EMTTM_CR_TABLE3" }, + { 0x00ac, "EMTTM_CR_TABLE4" }, + { 0x00ad, "EMTTM_CR_TABLE5" }, + { 0x00cd, "FSB_CLOCK_STS" }, + { 0x00e2, "PMG_CST_CONFIG_CONTROL" }, + { 0x00e3, "PMG_IO_BASE_ADDR" }, + { 0x00e4, "PMG_IO_CAPTURE_ADDR" }, + { 0x00ee, "EXT_CONFIG" }, + { 0x011e, "BBL_CR_CTL3" }, + { 0x0194, "CLOCK_FLEX_MAX" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x01a0, "IA32_MISC_ENABLES" }, + { 0x01aa, "PIC_SENS_CFG" }, + { 0x0400, "IA32_MC0_CTL" }, + { 0x0401, "IA32_MC0_STATUS" }, + { 0x0402, "IA32_MC0_ADDR" }, + //{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO + { 0x040c, "IA32_MC4_CTL" }, + { 0x040d, "IA32_MC4_STATUS" }, + { 0x040e, "IA32_MC4_ADDR" }, + //{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO +}; - static const msr_entry_t model6fx_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00e1, "SMM_CST_MISC_INFO" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_THERM_CTL" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x019d, "MSR_THERM2_CTL" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO - }; +static const msr_entry_t model6fx_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + //{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00e1, "SMM_CST_MISC_INFO" }, + { 0x00e7, "IA32_MPERF" }, + { 0x00e8, "IA32_APERF" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0199, "IA32_PERF_CONTROL" }, + { 0x019a, "IA32_THERM_CTL" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x019d, "MSR_THERM2_CTL" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + //{ 0x00c000080, "IA32_CR_EFER" }, // Seems to be RO +}; - /* Pentium 4 and XEON */ - /* - * All MSRs per - * - * Intel 64 and IA-32 Architectures Software Developer's Manual - * Volume 3B: System Programming Guide, Part 2 - * - * Table B-5, B-7 - */ - static const msr_entry_t modelf2x_global_msrs[] = { - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - /* 0x6: Not available in model 2. */ - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "MSR_EBC_HARD_POWERON" }, - { 0x002b, "MSR_EBC_SOFT_POWERON" }, - /* 0x2c: Not available in model 2. */ +/* Pentium 4 and XEON */ +/* + * All MSRs per + * + * Intel 64 and IA-32 Architectures Software Developer's Manual + * Volume 3B: System Programming Guide, Part 2 + * + * Table B-5, B-7 + */ +static const msr_entry_t modelf2x_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + /* 0x6: Not available in model 2. */ + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, + { 0x002b, "MSR_EBC_SOFT_POWERON" }, + /* 0x2c: Not available in model 2. */ // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - { 0x019c, "IA32_THERM_STATUS" }, - /* 0x19d: Not available in model 2. */ - { 0x01a0, "IA32_MISC_ENABLE" }, - /* 0x1a1: Not available in model 2. */ - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x0300, "MSR_BPU_COUNTER0" }, - { 0x0301, "MSR_BPU_COUNTER1" }, - { 0x0302, "MSR_BPU_COUNTER2" }, - { 0x0303, "MSR_BPU_COUNTER3" }, - { 0x0304, "MSR_MS_COUNTER0" }, - { 0x0305, "MSR_MS_COUNTER1" }, - { 0x0306, "MSR_MS_COUNTER2" }, - { 0x0307, "MSR_MS_COUNTER3" }, - { 0x0308, "MSR_FLAME_COUNTER0" }, - { 0x0309, "MSR_FLAME_COUNTER1" }, - { 0x030a, "MSR_FLAME_COUNTER2" }, - { 0x030b, "MSR_FLAME_COUNTER3" }, - { 0x030c, "MSR_IQ_COUNTER0" }, - { 0x030d, "MSR_IQ_COUNTER1" }, - { 0x030e, "MSR_IQ_COUNTER2" }, - { 0x030f, "MSR_IQ_COUNTER3" }, - { 0x0310, "MSR_IQ_COUNTER4" }, - { 0x0311, "MSR_IQ_COUNTER5" }, - { 0x0360, "MSR_BPU_CCCR0" }, - { 0x0361, "MSR_BPU_CCCR1" }, - { 0x0362, "MSR_BPU_CCCR2" }, - { 0x0363, "MSR_BPU_CCCR3" }, - { 0x0364, "MSR_MS_CCCR0" }, - { 0x0365, "MSR_MS_CCCR1" }, - { 0x0366, "MSR_MS_CCCR2" }, - { 0x0367, "MSR_MS_CCCR3" }, - { 0x0368, "MSR_FLAME_CCCR0" }, - { 0x0369, "MSR_FLAME_CCCR1" }, - { 0x036a, "MSR_FLAME_CCCR2" }, - { 0x036b, "MSR_FLAME_CCCR3" }, - { 0x036c, "MSR_IQ_CCCR0" }, - { 0x036d, "MSR_IQ_CCCR1" }, - { 0x036e, "MSR_IQ_CCCR2" }, - { 0x036f, "MSR_IQ_CCCR3" }, - { 0x0370, "MSR_IQ_CCCR4" }, - { 0x0371, "MSR_IQ_CCCR5" }, - { 0x03a0, "MSR_BSU_ESCR0" }, - { 0x03a1, "MSR_BSU_ESCR1" }, - { 0x03a2, "MSR_FSB_ESCR0" }, - { 0x03a3, "MSR_FSB_ESCR1" }, - { 0x03a4, "MSR_FIRM_ESCR0" }, - { 0x03a5, "MSR_FIRM_ESCR1" }, - { 0x03a6, "MSR_FLAME_ESCR0" }, - { 0x03a7, "MSR_FLAME_ESCR1" }, - { 0x03a8, "MSR_DAC_ESCR0" }, - { 0x03a9, "MSR_DAC_ESCR1" }, - { 0x03aa, "MSR_MOB_ESCR0" }, - { 0x03ab, "MSR_MOB_ESCR1" }, - { 0x03ac, "MSR_PMH_ESCR0" }, - { 0x03ad, "MSR_PMH_ESCR1" }, - { 0x03ae, "MSR_SAAT_ESCR0" }, - { 0x03af, "MSR_SAAT_ESCR1" }, - { 0x03b0, "MSR_U2L_ESCR0" }, - { 0x03b1, "MSR_U2L_ESCR1" }, - { 0x03b2, "MSR_BPU_ESCR0" }, - { 0x03b3, "MSR_BPU_ESCR1" }, - { 0x03b4, "MSR_IS_ESCR0" }, - { 0x03b5, "MSR_BPU_ESCR1" }, - { 0x03b6, "MSR_ITLB_ESCR0" }, - { 0x03b7, "MSR_ITLB_ESCR1" }, - { 0x03b8, "MSR_CRU_ESCR0" }, - { 0x03b9, "MSR_CRU_ESCR1" }, - { 0x03ba, "MSR_IQ_ESCR0" }, - { 0x03bb, "MSR_IQ_ESCR1" }, - { 0x03bc, "MSR_RAT_ESCR0" }, - { 0x03bd, "MSR_RAT_ESCR1" }, - { 0x03be, "MSR_SSU_ESCR0" }, - { 0x03c0, "MSR_MS_ESCR0" }, - { 0x03c1, "MSR_MS_ESCR1" }, - { 0x03c2, "MSR_TBPU_ESCR0" }, - { 0x03c3, "MSR_TBPU_ESCR1" }, - { 0x03c4, "MSR_TC_ESCR0" }, - { 0x03c5, "MSR_TC_ESCR1" }, - { 0x03c8, "MSR_IX_ESCR0" }, - { 0x03c9, "MSR_IX_ESCR1" }, - { 0x03ca, "MSR_ALF_ESCR0" }, - { 0x03cb, "MSR_ALF_ESCR1" }, - { 0x03cc, "MSR_CRU_ESCR2" }, - { 0x03cd, "MSR_CRU_ESCR3" }, - { 0x03e0, "MSR_CRU_ESCR4" }, - { 0x03e1, "MSR_CRU_ESCR5" }, - { 0x03f0, "MSR_TC_PRECISE_EVENT" }, - { 0x03f1, "MSR_PEBS_ENABLE" }, - { 0x03f2, "MSR_PEBS_MATRIX_VERT" }, + { 0x019c, "IA32_THERM_STATUS" }, + /* 0x19d: Not available in model 2. */ + { 0x01a0, "IA32_MISC_ENABLE" }, + /* 0x1a1: Not available in model 2. */ + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0300, "MSR_BPU_COUNTER0" }, + { 0x0301, "MSR_BPU_COUNTER1" }, + { 0x0302, "MSR_BPU_COUNTER2" }, + { 0x0303, "MSR_BPU_COUNTER3" }, + { 0x0304, "MSR_MS_COUNTER0" }, + { 0x0305, "MSR_MS_COUNTER1" }, + { 0x0306, "MSR_MS_COUNTER2" }, + { 0x0307, "MSR_MS_COUNTER3" }, + { 0x0308, "MSR_FLAME_COUNTER0" }, + { 0x0309, "MSR_FLAME_COUNTER1" }, + { 0x030a, "MSR_FLAME_COUNTER2" }, + { 0x030b, "MSR_FLAME_COUNTER3" }, + { 0x030c, "MSR_IQ_COUNTER0" }, + { 0x030d, "MSR_IQ_COUNTER1" }, + { 0x030e, "MSR_IQ_COUNTER2" }, + { 0x030f, "MSR_IQ_COUNTER3" }, + { 0x0310, "MSR_IQ_COUNTER4" }, + { 0x0311, "MSR_IQ_COUNTER5" }, + { 0x0360, "MSR_BPU_CCCR0" }, + { 0x0361, "MSR_BPU_CCCR1" }, + { 0x0362, "MSR_BPU_CCCR2" }, + { 0x0363, "MSR_BPU_CCCR3" }, + { 0x0364, "MSR_MS_CCCR0" }, + { 0x0365, "MSR_MS_CCCR1" }, + { 0x0366, "MSR_MS_CCCR2" }, + { 0x0367, "MSR_MS_CCCR3" }, + { 0x0368, "MSR_FLAME_CCCR0" }, + { 0x0369, "MSR_FLAME_CCCR1" }, + { 0x036a, "MSR_FLAME_CCCR2" }, + { 0x036b, "MSR_FLAME_CCCR3" }, + { 0x036c, "MSR_IQ_CCCR0" }, + { 0x036d, "MSR_IQ_CCCR1" }, + { 0x036e, "MSR_IQ_CCCR2" }, + { 0x036f, "MSR_IQ_CCCR3" }, + { 0x0370, "MSR_IQ_CCCR4" }, + { 0x0371, "MSR_IQ_CCCR5" }, + { 0x03a0, "MSR_BSU_ESCR0" }, + { 0x03a1, "MSR_BSU_ESCR1" }, + { 0x03a2, "MSR_FSB_ESCR0" }, + { 0x03a3, "MSR_FSB_ESCR1" }, + { 0x03a4, "MSR_FIRM_ESCR0" }, + { 0x03a5, "MSR_FIRM_ESCR1" }, + { 0x03a6, "MSR_FLAME_ESCR0" }, + { 0x03a7, "MSR_FLAME_ESCR1" }, + { 0x03a8, "MSR_DAC_ESCR0" }, + { 0x03a9, "MSR_DAC_ESCR1" }, + { 0x03aa, "MSR_MOB_ESCR0" }, + { 0x03ab, "MSR_MOB_ESCR1" }, + { 0x03ac, "MSR_PMH_ESCR0" }, + { 0x03ad, "MSR_PMH_ESCR1" }, + { 0x03ae, "MSR_SAAT_ESCR0" }, + { 0x03af, "MSR_SAAT_ESCR1" }, + { 0x03b0, "MSR_U2L_ESCR0" }, + { 0x03b1, "MSR_U2L_ESCR1" }, + { 0x03b2, "MSR_BPU_ESCR0" }, + { 0x03b3, "MSR_BPU_ESCR1" }, + { 0x03b4, "MSR_IS_ESCR0" }, + { 0x03b5, "MSR_BPU_ESCR1" }, + { 0x03b6, "MSR_ITLB_ESCR0" }, + { 0x03b7, "MSR_ITLB_ESCR1" }, + { 0x03b8, "MSR_CRU_ESCR0" }, + { 0x03b9, "MSR_CRU_ESCR1" }, + { 0x03ba, "MSR_IQ_ESCR0" }, + { 0x03bb, "MSR_IQ_ESCR1" }, + { 0x03bc, "MSR_RAT_ESCR0" }, + { 0x03bd, "MSR_RAT_ESCR1" }, + { 0x03be, "MSR_SSU_ESCR0" }, + { 0x03c0, "MSR_MS_ESCR0" }, + { 0x03c1, "MSR_MS_ESCR1" }, + { 0x03c2, "MSR_TBPU_ESCR0" }, + { 0x03c3, "MSR_TBPU_ESCR1" }, + { 0x03c4, "MSR_TC_ESCR0" }, + { 0x03c5, "MSR_TC_ESCR1" }, + { 0x03c8, "MSR_IX_ESCR0" }, + { 0x03c9, "MSR_IX_ESCR1" }, + { 0x03ca, "MSR_ALF_ESCR0" }, + { 0x03cb, "MSR_ALF_ESCR1" }, + { 0x03cc, "MSR_CRU_ESCR2" }, + { 0x03cd, "MSR_CRU_ESCR3" }, + { 0x03e0, "MSR_CRU_ESCR4" }, + { 0x03e1, "MSR_CRU_ESCR5" }, + { 0x03f0, "MSR_TC_PRECISE_EVENT" }, + { 0x03f1, "MSR_PEBS_ENABLE" }, + { 0x03f2, "MSR_PEBS_MATRIX_VERT" }, - /* - * All MCX_ADDR and MCX_MISC MSRs depend on a bit being - * set in MCX_STATUS. - */ - { 0x400, "IA32_MC0_CTL" }, - { 0x401, "IA32_MC0_STATUS" }, - { 0x402, "IA32_MC0_ADDR" }, - { 0x403, "IA32_MC0_MISC" }, - { 0x404, "IA32_MC1_CTL" }, - { 0x405, "IA32_MC1_STATUS" }, - { 0x406, "IA32_MC1_ADDR" }, - { 0x407, "IA32_MC1_MISC" }, - { 0x408, "IA32_MC2_CTL" }, - { 0x409, "IA32_MC2_STATUS" }, - { 0x40a, "IA32_MC2_ADDR" }, - { 0x40b, "IA32_MC2_MISC" }, - { 0x40c, "IA32_MC3_CTL" }, - { 0x40d, "IA32_MC3_STATUS" }, - { 0x40e, "IA32_MC3_ADDR" }, - { 0x40f, "IA32_MC3_MISC" }, - { 0x410, "IA32_MC4_CTL" }, - { 0x411, "IA32_MC4_STATUS" }, - { 0x412, "IA32_MC4_ADDR" }, - { 0x413, "IA32_MC4_MISC" }, - }; +/* + * All MCX_ADDR and MCX_MISC MSRs depend on a bit being + * set in MCX_STATUS. + */ + { 0x400, "IA32_MC0_CTL" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x402, "IA32_MC0_ADDR" }, + { 0x403, "IA32_MC0_MISC" }, + { 0x404, "IA32_MC1_CTL" }, + { 0x405, "IA32_MC1_STATUS" }, + { 0x406, "IA32_MC1_ADDR" }, + { 0x407, "IA32_MC1_MISC" }, + { 0x408, "IA32_MC2_CTL" }, + { 0x409, "IA32_MC2_STATUS" }, + { 0x40a, "IA32_MC2_ADDR" }, + { 0x40b, "IA32_MC2_MISC" }, + { 0x40c, "IA32_MC3_CTL" }, + { 0x40d, "IA32_MC3_STATUS" }, + { 0x40e, "IA32_MC3_ADDR" }, + { 0x40f, "IA32_MC3_MISC" }, + { 0x410, "IA32_MC4_CTL" }, + { 0x411, "IA32_MC4_STATUS" }, + { 0x412, "IA32_MC4_ADDR" }, + { 0x413, "IA32_MC4_MISC" }, +}; - static const msr_entry_t modelf2x_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - /* 0x3a: Not available in model 2. */ - { 0x008b, "IA32_BIOS_SIGN_ID" }, - /* 0x9b: Not available in model 2. */ - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x017b, "IA32_MCG_CTL" }, - { 0x0180, "MSR_MCG_RAX" }, - { 0x0181, "MSR_MCG_RBX" }, - { 0x0182, "MSR_MCG_RCX" }, - { 0x0183, "MSR_MCG_RDX" }, - { 0x0184, "MSR_MCG_RSI" }, - { 0x0185, "MSR_MCG_RDI" }, - { 0x0186, "MSR_MCG_RBP" }, - { 0x0187, "MSR_MCG_RSP" }, - { 0x0188, "MSR_MCG_RFLAGS" }, - { 0x0189, "MSR_MCG_RIP" }, - { 0x018a, "MSR_MCG_MISC" }, - /* 0x18b-0x18f: Reserved */ - { 0x0190, "MSR_MCG_R8" }, - { 0x0191, "MSR_MCG_R9" }, - { 0x0192, "MSR_MCG_R10" }, - { 0x0193, "MSR_MCG_R11" }, - { 0x0194, "MSR_MCG_R12" }, - { 0x0195, "MSR_MCG_R13" }, - { 0x0196, "MSR_MCG_R14" }, - { 0x0197, "MSR_MCG_R15" }, - /* 0x198: Not available in model 2. */ - /* 0x199: Not available in model 2. */ - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x01a0, "IA32_MISC_ENABLE" }, - { 0x01d7, "MSR_LER_FROM_LIP" }, - { 0x01d8, "MSR_LER_TO_LIP" }, - { 0x01d9, "MSR_DEBUGCTLA" }, - { 0x01da, "MSR_LASTBRANCH_TOS" }, - { 0x01db, "MSR_LASTBRANCH_0" }, - { 0x01dd, "MSR_LASTBRANCH_2" }, - { 0x01de, "MSR_LASTBRANCH_3" }, - { 0x0277, "IA32_PAT" }, - /* 0x480-0x48b : Not available in model 2. */ - { 0x0600, "IA32_DS_AREA" }, - /* 0x0680 - 0x06cf Branch Records Skipped */ - }; +static const msr_entry_t modelf2x_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + /* 0x3a: Not available in model 2. */ + { 0x008b, "IA32_BIOS_SIGN_ID" }, + /* 0x9b: Not available in model 2. */ + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x017b, "IA32_MCG_CTL" }, + { 0x0180, "MSR_MCG_RAX" }, + { 0x0181, "MSR_MCG_RBX" }, + { 0x0182, "MSR_MCG_RCX" }, + { 0x0183, "MSR_MCG_RDX" }, + { 0x0184, "MSR_MCG_RSI" }, + { 0x0185, "MSR_MCG_RDI" }, + { 0x0186, "MSR_MCG_RBP" }, + { 0x0187, "MSR_MCG_RSP" }, + { 0x0188, "MSR_MCG_RFLAGS" }, + { 0x0189, "MSR_MCG_RIP" }, + { 0x018a, "MSR_MCG_MISC" }, + /* 0x18b-0x18f: Reserved */ + { 0x0190, "MSR_MCG_R8" }, + { 0x0191, "MSR_MCG_R9" }, + { 0x0192, "MSR_MCG_R10" }, + { 0x0193, "MSR_MCG_R11" }, + { 0x0194, "MSR_MCG_R12" }, + { 0x0195, "MSR_MCG_R13" }, + { 0x0196, "MSR_MCG_R14" }, + { 0x0197, "MSR_MCG_R15" }, + /* 0x198: Not available in model 2. */ + /* 0x199: Not available in model 2. */ + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x01a0, "IA32_MISC_ENABLE" }, + { 0x01d7, "MSR_LER_FROM_LIP" }, + { 0x01d8, "MSR_LER_TO_LIP" }, + { 0x01d9, "MSR_DEBUGCTLA" }, + { 0x01da, "MSR_LASTBRANCH_TOS" }, + { 0x01db, "MSR_LASTBRANCH_0" }, + { 0x01dd, "MSR_LASTBRANCH_2" }, + { 0x01de, "MSR_LASTBRANCH_3" }, + { 0x0277, "IA32_PAT" }, + /* 0x480-0x48b : Not available in model 2. */ + { 0x0600, "IA32_DS_AREA" }, + /* 0x0680 - 0x06cf Branch Records Skipped */ +}; - static const msr_entry_t modelf4x_global_msrs[] = { - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "MSR_EBC_HARD_POWERON" }, - { 0x002b, "MSR_EBC_SOFT_POWERON" }, - { 0x002c, "MSR_EBC_FREQUENCY_ID" }, +static const msr_entry_t modelf4x_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, + { 0x002b, "MSR_EBC_SOFT_POWERON" }, + { 0x002c, "MSR_EBC_FREQUENCY_ID" }, // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x019d, "MSR_THERM2_CTL" }, - { 0x01a0, "IA32_MISC_ENABLE" }, - { 0x01a1, "MSR_PLATFORM_BRV" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x0300, "MSR_BPU_COUNTER0" }, - { 0x0301, "MSR_BPU_COUNTER1" }, - { 0x0302, "MSR_BPU_COUNTER2" }, - { 0x0303, "MSR_BPU_COUNTER3" }, - /* Skipped through 0x3ff for now*/ - + { 0x019c, "IA32_THERM_STATUS" }, + { 0x019d, "MSR_THERM2_CTL" }, + { 0x01a0, "IA32_MISC_ENABLE" }, + { 0x01a1, "MSR_PLATFORM_BRV" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0300, "MSR_BPU_COUNTER0" }, + { 0x0301, "MSR_BPU_COUNTER1" }, + { 0x0302, "MSR_BPU_COUNTER2" }, + { 0x0303, "MSR_BPU_COUNTER3" }, + /* Skipped through 0x3ff for now*/ /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being * set in MCX_STATUS */ - { 0x400, "IA32_MC0_CTL" }, - { 0x401, "IA32_MC0_STATUS" }, - { 0x402, "IA32_MC0_ADDR" }, - { 0x403, "IA32_MC0_MISC" }, - { 0x404, "IA32_MC1_CTL" }, - { 0x405, "IA32_MC1_STATUS" }, - { 0x406, "IA32_MC1_ADDR" }, - { 0x407, "IA32_MC1_MISC" }, - { 0x408, "IA32_MC2_CTL" }, - { 0x409, "IA32_MC2_STATUS" }, - { 0x40a, "IA32_MC2_ADDR" }, - { 0x40b, "IA32_MC2_MISC" }, - { 0x40c, "IA32_MC3_CTL" }, - { 0x40d, "IA32_MC3_STATUS" }, - { 0x40e, "IA32_MC3_ADDR" }, - { 0x40f, "IA32_MC3_MISC" }, - { 0x410, "IA32_MC4_CTL" }, - { 0x411, "IA32_MC4_STATUS" }, - { 0x412, "IA32_MC4_ADDR" }, - { 0x413, "IA32_MC4_MISC" }, - }; + { 0x400, "IA32_MC0_CTL" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x402, "IA32_MC0_ADDR" }, + { 0x403, "IA32_MC0_MISC" }, + { 0x404, "IA32_MC1_CTL" }, + { 0x405, "IA32_MC1_STATUS" }, + { 0x406, "IA32_MC1_ADDR" }, + { 0x407, "IA32_MC1_MISC" }, + { 0x408, "IA32_MC2_CTL" }, + { 0x409, "IA32_MC2_STATUS" }, + { 0x40a, "IA32_MC2_ADDR" }, + { 0x40b, "IA32_MC2_MISC" }, + { 0x40c, "IA32_MC3_CTL" }, + { 0x40d, "IA32_MC3_STATUS" }, + { 0x40e, "IA32_MC3_ADDR" }, + { 0x40f, "IA32_MC3_MISC" }, + { 0x410, "IA32_MC4_CTL" }, + { 0x411, "IA32_MC4_STATUS" }, + { 0x412, "IA32_MC4_ADDR" }, + { 0x413, "IA32_MC4_MISC" }, +}; - static const msr_entry_t modelf4x_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x009b, "IA32_SMM_MONITOR_CTL" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0180, "MSR_MCG_RAX" }, - { 0x0181, "MSR_MCG_RBX" }, - { 0x0182, "MSR_MCG_RCX" }, - { 0x0183, "MSR_MCG_RDX" }, - { 0x0184, "MSR_MCG_RSI" }, - { 0x0185, "MSR_MCG_RDI" }, - { 0x0186, "MSR_MCG_RBP" }, - { 0x0187, "MSR_MCG_RSP" }, - { 0x0188, "MSR_MCG_RFLAGS" }, - { 0x0189, "MSR_MCG_RIP" }, - { 0x018a, "MSR_MCG_MISC" }, - // 0x18b-f Reserved - { 0x0190, "MSR_MCG_R8" }, - { 0x0191, "MSR_MCG_R9" }, - { 0x0192, "MSR_MCG_R10" }, - { 0x0193, "MSR_MCG_R11" }, - { 0x0194, "MSR_MCG_R12" }, - { 0x0195, "MSR_MCG_R13" }, - { 0x0196, "MSR_MCG_R14" }, - { 0x0197, "MSR_MCG_R15" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x0199, "IA32_PERF_CTL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific - { 0x01d7, "MSR_LER_FROM_LIP" }, - { 0x01d8, "MSR_LER_TO_LIP" }, - { 0x01d9, "MSR_DEBUGCTLA" }, - { 0x01da, "MSR_LASTBRANCH_TOS" }, - { 0x0277, "IA32_PAT" }, - /** Virtualization - { 0x480, "IA32_VMX_BASIC" }, - through - { 0x48b, "IA32_VMX_PROCBASED_CTLS2" }, - Not implemented in my CPU - */ - { 0x0600, "IA32_DS_AREA" }, - /* 0x0680 - 0x06cf Branch Records Skipped */ +static const msr_entry_t modelf4x_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x009b, "IA32_SMM_MONITOR_CTL" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0180, "MSR_MCG_RAX" }, + { 0x0181, "MSR_MCG_RBX" }, + { 0x0182, "MSR_MCG_RCX" }, + { 0x0183, "MSR_MCG_RDX" }, + { 0x0184, "MSR_MCG_RSI" }, + { 0x0185, "MSR_MCG_RDI" }, + { 0x0186, "MSR_MCG_RBP" }, + { 0x0187, "MSR_MCG_RSP" }, + { 0x0188, "MSR_MCG_RFLAGS" }, + { 0x0189, "MSR_MCG_RIP" }, + { 0x018a, "MSR_MCG_MISC" }, + // 0x18b-f Reserved + { 0x0190, "MSR_MCG_R8" }, + { 0x0191, "MSR_MCG_R9" }, + { 0x0192, "MSR_MCG_R10" }, + { 0x0193, "MSR_MCG_R11" }, + { 0x0194, "MSR_MCG_R12" }, + { 0x0195, "MSR_MCG_R13" }, + { 0x0196, "MSR_MCG_R14" }, + { 0x0197, "MSR_MCG_R15" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x0199, "IA32_PERF_CTL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific + { 0x01d7, "MSR_LER_FROM_LIP" }, + { 0x01d8, "MSR_LER_TO_LIP" }, + { 0x01d9, "MSR_DEBUGCTLA" }, + { 0x01da, "MSR_LASTBRANCH_TOS" }, + { 0x0277, "IA32_PAT" }, + /** Virtualization + { 0x480, "IA32_VMX_BASIC" }, + through + { 0x48b, "IA32_VMX_PROCBASED_CTLS2" }, + Not implemented in my CPU + */ + { 0x0600, "IA32_DS_AREA" }, + /* 0x0680 - 0x06cf Branch Records Skipped */ - }; +}; - /* Atom N455 - * - * This should apply to the following processors: - * 06_1CH - * 06_26H - * 06_27H - * 06_35 - * 06_36 +/* Atom N455 + * + * This should apply to the following processors: + * 06_1CH + * 06_26H + * 06_27H + * 06_35 + * 06_36 + */ +/* + * All MSRs per + * + * Intel 64 and IA-32 Architectures Software Developer's Manual + * Volume 3C: System Programming Guide, Part 3 + * Order Number 326019 + * January 2013 + * + * Table 35-4, 35-5 + * + * For now it has only been tested with 06_1CH. + */ +static const msr_entry_t model6_atom_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, + { 0x00cd, "MSR_FSB_FREQ" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x011e, "MSR_BBL_CR_CTL3" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x019d, "MSR_THERM2_CTL" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x0345, "IA32_PERF_CAPABILITIES" }, + { 0x400, "IA32_MC0_CTL" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x402, "IA32_MC0_ADDR" }, + { 0x404, "IA32_MC1_CTL" }, + { 0x405, "IA32_MC1_STATUS" }, + { 0x408, "IA32_MC2_CTL" }, + { 0x409, "IA32_MC2_STATUS" }, + { 0x40a, "IA32_MC2_ADDR" }, + { 0x40c, "IA32_MC3_CTL" }, + { 0x40d, "IA32_MC3_STATUS" }, + { 0x40e, "IA32_MC3_ADDR" }, + { 0x410, "IA32_MC4_CTL" }, + { 0x411, "IA32_MC4_STATUS" }, + { 0x412, "IA32_MC4_ADDR" }, + /* + * Only 06_27C has the following MSRs */ /* - * All MSRs per - * - * Intel 64 and IA-32 Architectures Software Developer's Manual - * Volume 3C: System Programming Guide, Part 3 - * Order Number 326019 - * January 2013 - * - * Table 35-4, 35-5 - * - * For now it has only been tested with 06_1CH. + { 0x03f8, "MSR_PKG_C2_RESIDENCY" }, + { 0x03f9, "MSR_PKG_C4_RESIDENCY" }, + { 0x03fa, "MSR_PKG_C6_RESIDENCY" }, */ - static const msr_entry_t model6_atom_global_msrs[] = { - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "MSR_EBC_HARD_POWERON" }, - { 0x00cd, "MSR_FSB_FREQ" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x011e, "MSR_BBL_CR_CTL3" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x019d, "MSR_THERM2_CTL" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x0345, "IA32_PERF_CAPABILITIES" }, - { 0x400, "IA32_MC0_CTL" }, - { 0x401, "IA32_MC0_STATUS" }, - { 0x402, "IA32_MC0_ADDR" }, - { 0x404, "IA32_MC1_CTL" }, - { 0x405, "IA32_MC1_STATUS" }, - { 0x408, "IA32_MC2_CTL" }, - { 0x409, "IA32_MC2_STATUS" }, - { 0x40a, "IA32_MC2_ADDR" }, - { 0x40c, "IA32_MC3_CTL" }, - { 0x40d, "IA32_MC3_STATUS" }, - { 0x40e, "IA32_MC3_ADDR" }, - { 0x410, "IA32_MC4_CTL" }, - { 0x411, "IA32_MC4_STATUS" }, - { 0x412, "IA32_MC4_ADDR" }, - /* - * Only 06_27C has the following MSRs - */ - /* - { 0x03f8, "MSR_PKG_C2_RESIDENCY" }, - { 0x03f9, "MSR_PKG_C4_RESIDENCY" }, - { 0x03fa, "MSR_PKG_C6_RESIDENCY" }, - */ - }; +}; - static const msr_entry_t model6_atom_per_core_msrs[] = { - { 0x0006, "IA32_MONITOR_FILTER_SIZE" }, - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, - { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, - { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, - { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, - { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, - { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, - { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, - { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, - { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, - { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, - { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, - { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, - { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, - { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, - { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, - { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, - /* Write register */ - /* - { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - */ - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00c1, "IA32_PMC0" }, - { 0x00c2, "IA32_PMC1" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0186, "IA32_PERF_EVNTSEL0" }, - { 0x0187, "IA32_PERF_EVNTSEL1" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01c9, "MSR_LASTBRANCH_TOS" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x01dd, "MSR_LER_FROM_LIP" }, - { 0x01de, "MSR_LER_TO_LIP" }, - { 0x0277, "IA32_PAT" }, - { 0x0309, "IA32_FIXED_CTR0" }, - { 0x030a, "IA32_FIXED_CTR1" }, - { 0x030b, "IA32_FIXED_CTR2" }, - { 0x038d, "IA32_FIXED_CTR_CTRL" }, - { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, - { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, - { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, - { 0x03f1, "MSR_PEBS_ENABLE" }, - { 0x0480, "IA32_VMX_BASIC" }, - { 0x0481, "IA32_VMX_PINBASED_CTLS" }, - { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, - { 0x0483, "IA32_VMX_EXIT_CTLS" }, - { 0x0484, "IA32_VMX_ENTRY_CTLS" }, - { 0x0485, "IA32_VMX_MISC" }, - { 0x0486, "IA32_VMX_CR0_FIXED0" }, - { 0x0487, "IA32_VMX_CR0_FIXED1" }, - { 0x0488, "IA32_VMX_CR4_FIXED0" }, - { 0x0489, "IA32_VMX_CR4_FIXED1" }, - { 0x048a, "IA32_VMX_VMCS_ENUM" }, - { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, - { 0x0600, "IA32_DS_AREA" }, - }; +static const msr_entry_t model6_atom_per_core_msrs[] = { + { 0x0006, "IA32_MONITOR_FILTER_SIZE" }, + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, + { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, + { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, + { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, + { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, + { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, + { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, + { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, + { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, + { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, + { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, + { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, + { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, + { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, + { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, + { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, + /* Write register */ + /* + { 0x0079, "IA32_BIOS_UPDT_TRIG" }, + */ + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00c1, "IA32_PMC0" }, + { 0x00c2, "IA32_PMC1" }, + { 0x00e7, "IA32_MPERF" }, + { 0x00e8, "IA32_APERF" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0186, "IA32_PERF_EVNTSEL0" }, + { 0x0187, "IA32_PERF_EVNTSEL1" }, + { 0x0199, "IA32_PERF_CONTROL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x01a0, "IA32_MISC_ENABLES" }, + { 0x01c9, "MSR_LASTBRANCH_TOS" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x01dd, "MSR_LER_FROM_LIP" }, + { 0x01de, "MSR_LER_TO_LIP" }, + { 0x0277, "IA32_PAT" }, + { 0x0309, "IA32_FIXED_CTR0" }, + { 0x030a, "IA32_FIXED_CTR1" }, + { 0x030b, "IA32_FIXED_CTR2" }, + { 0x038d, "IA32_FIXED_CTR_CTRL" }, + { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, + { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, + { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, + { 0x03f1, "MSR_PEBS_ENABLE" }, + { 0x0480, "IA32_VMX_BASIC" }, + { 0x0481, "IA32_VMX_PINBASED_CTLS" }, + { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, + { 0x0483, "IA32_VMX_EXIT_CTLS" }, + { 0x0484, "IA32_VMX_ENTRY_CTLS" }, + { 0x0485, "IA32_VMX_MISC" }, + { 0x0486, "IA32_VMX_CR0_FIXED0" }, + { 0x0487, "IA32_VMX_CR0_FIXED1" }, + { 0x0488, "IA32_VMX_CR4_FIXED0" }, + { 0x0489, "IA32_VMX_CR4_FIXED1" }, + { 0x048a, "IA32_VMX_VMCS_ENUM" }, + { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, + { 0x0600, "IA32_DS_AREA" }, +}; - static const msr_entry_t model20650_global_msrs[] = { - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "MSR_EBC_HARD_POWERON" }, +static const msr_entry_t model20650_global_msrs[] = { + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, // WRITE ONLY { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - { 0x00ce, "IA32_MSR_PLATFORM_INFO" }, - { 0x00e2, "IA32_MSR_PMG_CST_CONFIG" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x019d, "MSR_THERM2_CTL" }, - { 0x01a0, "IA32_MISC_ENABLE" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x02ff, "IA32_MTRR_DEF_TYPE" }, - { 0x0300, "MSR_BPU_COUNTER0" }, - { 0x0301, "MSR_BPU_COUNTER1" }, - /* Skipped through 0x3ff for now*/ + { 0x00ce, "IA32_MSR_PLATFORM_INFO" }, + { 0x00e2, "IA32_MSR_PMG_CST_CONFIG" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x019d, "MSR_THERM2_CTL" }, + { 0x01a0, "IA32_MISC_ENABLE" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x02ff, "IA32_MTRR_DEF_TYPE" }, + { 0x0300, "MSR_BPU_COUNTER0" }, + { 0x0301, "MSR_BPU_COUNTER1" }, + /* Skipped through 0x3ff for now*/ - /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being - * set in MCX_STATUS */ - { 0x400, "IA32_MC0_CTL" }, - { 0x401, "IA32_MC0_STATUS" }, - { 0x402, "IA32_MC0_ADDR" }, - { 0x403, "IA32_MC0_MISC" }, - { 0x404, "IA32_MC1_CTL" }, - { 0x405, "IA32_MC1_STATUS" }, - { 0x406, "IA32_MC1_ADDR" }, - { 0x407, "IA32_MC1_MISC" }, - { 0x408, "IA32_MC2_CTL" }, - { 0x409, "IA32_MC2_STATUS" }, - { 0x40a, "IA32_MC2_ADDR" }, - { 0x40c, "IA32_MC3_CTL" }, - { 0x40d, "IA32_MC3_STATUS" }, - { 0x40e, "IA32_MC3_ADDR" }, - { 0x410, "IA32_MC4_CTL" }, - { 0x411, "IA32_MC4_STATUS" }, - }; + /* All MCX_ADDR AND MCX_MISC MSRs depend on a bit being + * set in MCX_STATUS */ + { 0x400, "IA32_MC0_CTL" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x402, "IA32_MC0_ADDR" }, + { 0x403, "IA32_MC0_MISC" }, + { 0x404, "IA32_MC1_CTL" }, + { 0x405, "IA32_MC1_STATUS" }, + { 0x406, "IA32_MC1_ADDR" }, + { 0x407, "IA32_MC1_MISC" }, + { 0x408, "IA32_MC2_CTL" }, + { 0x409, "IA32_MC2_STATUS" }, + { 0x40a, "IA32_MC2_ADDR" }, + { 0x40c, "IA32_MC3_CTL" }, + { 0x40d, "IA32_MC3_STATUS" }, + { 0x40e, "IA32_MC3_ADDR" }, + { 0x410, "IA32_MC4_CTL" }, + { 0x411, "IA32_MC4_STATUS" }, +}; - static const msr_entry_t model20650_per_core_msrs[] = { - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x009b, "IA32_SMM_MONITOR_CTL" }, - { 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0186, "MSR_MCG_RBP" }, - { 0x0187, "MSR_MCG_RSP" }, - { 0x0188, "MSR_MCG_RFLAGS" }, - { 0x0189, "MSR_MCG_RIP" }, - { 0x0194, "MSR_MCG_R12" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x0199, "IA32_PERF_CTL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific - { 0x01aa, "IA32_MISC_PWR_MGMT" }, - { 0x01d9, "MSR_DEBUGCTLA" }, - { 0x01fc, "MSR_POWER_CTL" }, - { 0x0277, "IA32_PAT" }, - /** Virtualization - { 0x480, "IA32_VMX_BASIC" }, - through - { 0x48b, "IA32_VMX_PROCBASED_CTLS2" }, - Not implemented in my CPU - */ - { 0x0600, "IA32_DS_AREA" }, - /* 0x0680 - 0x06cf Branch Records Skipped */ +static const msr_entry_t model20650_per_core_msrs[] = { + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x009b, "IA32_SMM_MONITOR_CTL" }, + { 0x00e4, "IA32_PMG_IO_CAPTURE_BASE" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0186, "MSR_MCG_RBP" }, + { 0x0187, "MSR_MCG_RSP" }, + { 0x0188, "MSR_MCG_RFLAGS" }, + { 0x0189, "MSR_MCG_RIP" }, + { 0x0194, "MSR_MCG_R12" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x0199, "IA32_PERF_CTL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x01a0, "IA32_MISC_ENABLE" }, // Bit 34 is Core Specific + { 0x01aa, "IA32_MISC_PWR_MGMT" }, + { 0x01d9, "MSR_DEBUGCTLA" }, + { 0x01fc, "MSR_POWER_CTL" }, + { 0x0277, "IA32_PAT" }, + /** Virtualization + { 0x480, "IA32_VMX_BASIC" }, + through + { 0x48b, "IA32_VMX_PROCBASED_CTLS2" }, + Not implemented in my CPU + */ + { 0x0600, "IA32_DS_AREA" }, + /* 0x0680 - 0x06cf Branch Records Skipped */ - { 0x3a, "IA32_FEATURE_CONTROL" }, - { 0x13c, "MSR_FEATURE_CONFIG" }, - { 0x194, "MSR_FLEX_RATIO" }, - { 0x1a0, "IA32_MISC_ENABLE" }, - { 0x1a2, "MSR_TEMPERATURE_TARGET" }, - { 0x199, "IA32_PERF_CTL" }, - { 0x19b, "IA32_THERM_INTERRUPT" }, - { 0x401, "IA32_MC0_STATUS" }, - { 0x2e, "MSR_PIC_MSG_CONTROL" }, - { 0xce, "MSR_PLATFORM_INFO" }, - { 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" }, - { 0xe4, "MSR_PMG_IO_CAPTURE_BASE" }, - { 0x1aa, "MSR_MISC_PWR_MGMT" }, - { 0x1ad, "MSR_TURBO_RATIO_LIMIT" }, - { 0x1fc, "MSR_POWER_CTL" }, - }; + { 0x3a, "IA32_FEATURE_CONTROL" }, + { 0x13c, "MSR_FEATURE_CONFIG" }, + { 0x194, "MSR_FLEX_RATIO" }, + { 0x1a0, "IA32_MISC_ENABLE" }, + { 0x1a2, "MSR_TEMPERATURE_TARGET" }, + { 0x199, "IA32_PERF_CTL" }, + { 0x19b, "IA32_THERM_INTERRUPT" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x2e, "MSR_PIC_MSG_CONTROL" }, + { 0xce, "MSR_PLATFORM_INFO" }, + { 0xe2, "MSR_PMG_CST_CONFIG_CONTROL" }, + { 0xe4, "MSR_PMG_IO_CAPTURE_BASE" }, + { 0x1aa, "MSR_MISC_PWR_MGMT" }, + { 0x1ad, "MSR_TURBO_RATIO_LIMIT" }, + { 0x1fc, "MSR_POWER_CTL" }, +}; /* * The following two tables are the Silvermont registers listed in Table 35-6 @@ -1007,185 +1006,182 @@ int print_intel_core_msrs(void) * September 2014 * Vol. 3C 35-59 */ - static const msr_entry_t silvermont_per_core_msrs[] = { - /* - * Per core MSRs in Intel Processors Based on the Silvermont Microarchitecture - * These are MSRs marked as "core" - * - */ - { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, - { 0x0010, "IA32_TIME_STAMP_COUNTER" }, - { 0x001b, "IA32_APIC_BASE" }, - { 0x0034, "MSR_SMI_COUNT" }, - { 0x003a, "IA32_FEATURE_CONTROL" }, - { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, - { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, - { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, - { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, - { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, - { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, - { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, - { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, - { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, - { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, - { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, - { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, - { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, - { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, - { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, - { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, - /* Write register - { 0x0079, "IA32_BIOS_UPDT_TRIG" }, - */ - { 0x008b, "IA32_BIOS_SIGN_ID" }, - { 0x00c1, "IA32_PMC0" }, - { 0x00c2, "IA32_PMC1" }, - { 0x00e7, "IA32_MPERF" }, - { 0x00e8, "IA32_APERF" }, - { 0x00fe, "IA32_MTRRCAP" }, - { 0x0174, "IA32_SYSENTER_CS" }, - { 0x0175, "IA32_SYSENTER_ESP" }, - { 0x0176, "IA32_SYSENTER_EIP" }, - { 0x0179, "IA32_MCG_CAP" }, - { 0x017a, "IA32_MCG_STATUS" }, - { 0x0186, "IA32_PERF_EVNTSEL0" }, - { 0x0187, "IA32_PERF_EVNTSEL1" }, - { 0x0199, "IA32_PERF_CONTROL" }, - { 0x019a, "IA32_CLOCK_MODULATION" }, - { 0x019b, "IA32_THERM_INTERRUPT" }, - { 0x019c, "IA32_THERM_STATUS" }, - { 0x01a0, "IA32_MISC_ENABLES" }, - { 0x01b0, "IA32_ENERGY_PERF_BIAS" }, - { 0x01c9, "MSR_LASTBRANCH_TOS" }, - { 0x01d9, "IA32_DEBUGCTL" }, - { 0x01dd, "MSR_LER_FROM_LIP" }, - { 0x01de, "MSR_LER_TO_LIP" }, - { 0x01f2, "IA32_SMRR_PHYSBASE" }, - { 0x01f3, "IA32_SMRR_PHYSMASK" }, - { 0x0200, "IA32_MTRR_PHYSBASE0" }, - { 0x0201, "IA32_MTRR_PHYSMASK0" }, - { 0x0202, "IA32_MTRR_PHYSBASE1" }, - { 0x0203, "IA32_MTRR_PHYSMASK1" }, - { 0x0204, "IA32_MTRR_PHYSBASE2" }, - { 0x0205, "IA32_MTRR_PHYSMASK2" }, - { 0x0206, "IA32_MTRR_PHYSBASE3" }, - { 0x0207, "IA32_MTRR_PHYSMASK3" }, - { 0x0208, "IA32_MTRR_PHYSBASE4" }, - { 0x0209, "IA32_MTRR_PHYSMASK4" }, - { 0x020a, "IA32_MTRR_PHYSBASE5" }, - { 0x020b, "IA32_MTRR_PHYSMASK5" }, - { 0x020c, "IA32_MTRR_PHYSBASE6" }, - { 0x020d, "IA32_MTRR_PHYSMASK6" }, - { 0x020e, "IA32_MTRR_PHYSBASE7" }, - { 0x020f, "IA32_MTRR_PHYSMASK7" }, - { 0x0250, "IA32_MTRR_FIX64K_00000" }, - { 0x0258, "IA32_MTRR_FIX16K_80000" }, - { 0x0259, "IA32_MTRR_FIX16K_A0000" }, - { 0x0268, "IA32_MTRR_FIX4K_C0000" }, - { 0x0269, "IA32_MTRR_FIX4K_C8000" }, - { 0x026a, "IA32_MTRR_FIX4K_D0000" }, - { 0x026b, "IA32_MTRR_FIX4K_D8000" }, - { 0x026c, "IA32_MTRR_FIX4K_E0000" }, - { 0x026d, "IA32_MTRR_FIX4K_E8000" }, - { 0x026e, "IA32_MTRR_FIX4K_F0000" }, - { 0x026f, "IA32_MTRR_FIX4K_F8000" }, - { 0x0277, "IA32_PAT" }, - { 0x02FF, "IA32_MTRR_DEF_TYPE" }, - { 0x0309, "IA32_FIXED_CTR0" }, - { 0x030a, "IA32_FIXED_CTR1" }, - { 0x030b, "IA32_FIXED_CTR2" }, - { 0x0345, "IA32_PERF_CAPABILITIES" }, - { 0x038d, "IA32_FIXED_CTR_CTRL" }, - { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, - { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, - { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, - { 0x03f1, "MSR_PEBS_ENABLE" }, - { 0x03fd, "MSR_CORE_C6_RESIDENCY" }, - { 0x40c, "IA32_MC3_CTL" }, - { 0x40d, "IA32_MC3_STATUS" }, - { 0x40e, "IA32_MC3_ADDR" }, - { 0x410, "IA32_MC4_CTL" }, - { 0x411, "IA32_MC4_STATUS" }, - { 0x412, "IA32_MC4_ADDR" }, - { 0x0480, "IA32_VMX_BASIC" }, - { 0x0481, "IA32_VMX_PINBASED_CTLS" }, - { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, - { 0x0483, "IA32_VMX_EXIT_CTLS" }, - { 0x0484, "IA32_VMX_ENTRY_CTLS" }, - { 0x0485, "IA32_VMX_MISC" }, - { 0x0486, "IA32_VMX_CR0_FIXED0" }, - { 0x0487, "IA32_VMX_CR0_FIXED1" }, - { 0x0488, "IA32_VMX_CR4_FIXED0" }, - { 0x0489, "IA32_VMX_CR4_FIXED1" }, - { 0x048a, "IA32_VMX_VMCS_ENUM" }, - { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, - { 0x048c, "IA32_VMX_EPT_VPID_ENUM" }, - { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" }, - { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" }, - { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" }, - { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" }, - { 0x0491, "IA32_VMX_FMFUNC" }, - { 0x04c1, "IA32_A_PMC0" }, - { 0x04c2, "IA32_A_PMC1" }, - { 0x0600, "IA32_DS_AREA" }, - { 0x0660, "MSR_CORE_C1_RESIDENCY" }, - { 0x06e0, "IA32_TSC_DEADLINE" }, - }; - - static const msr_entry_t silvermont_global_msrs[] = { - /* - * Common MSRs in Intel Processors Based on the Silvermont Microarchitecture - * These are MSRs marked as "shared" or "package" - */ - { 0x0000, "IA32_P5_MC_ADDR" }, - { 0x0001, "IA32_P5_MC_TYPE" }, - { 0x0017, "IA32_PLATFORM_ID" }, - { 0x002a, "MSR_EBC_HARD_POWERON" }, - { 0x00cd, "MSR_FSB_FREQ" }, - { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" }, - { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" }, - { 0x011e, "BBL_CR_CTL3" }, - { 0x0198, "IA32_PERF_STATUS" }, - { 0x01A2, "MSR_TEMPERATURE_TARGET" }, - { 0x01A6, "MSR_OFFCORE_RSP_0" }, - { 0x01A7, "MSR_OFFCORE_RSP_1" }, - { 0x01AD, "MSR_TURBO_RATIO_LIMIT" }, - { 0x03fa, "MSR_PKG_C6_RESIDENCY" }, - { 0x400, "IA32_MC0_CTL" }, - { 0x401, "IA32_MC0_STATUS" }, - { 0x402, "IA32_MC0_ADDR" }, - { 0x404, "IA32_MC1_CTL" }, - { 0x405, "IA32_MC1_STATUS" }, - { 0x408, "IA32_MC2_CTL" }, - { 0x409, "IA32_MC2_STATUS" }, - { 0x40a, "IA32_MC2_ADDR" }, - { 0x414, "MSR_MC5_CTL" }, - { 0x415, "MSR_MC5_STATUS" }, - { 0x416, "MSR_MC5_ADDR" }, - }; +static const msr_entry_t silvermont_per_core_msrs[] = { + /* + * Per core MSRs in Intel Processors Based on the Silvermont Microarchitecture + * These are MSRs marked as "core" + * + */ + { 0x0006, "IA32_MONITOR_FILTER_LINE_SIZE" }, + { 0x0010, "IA32_TIME_STAMP_COUNTER" }, + { 0x001b, "IA32_APIC_BASE" }, + { 0x0034, "MSR_SMI_COUNT" }, + { 0x003a, "IA32_FEATURE_CONTROL" }, + { 0x0040, "MSR_LASTBRANCH_0_FROM_IP" }, + { 0x0041, "MSR_LASTBRANCH_1_FROM_IP" }, + { 0x0042, "MSR_LASTBRANCH_2_FROM_IP" }, + { 0x0043, "MSR_LASTBRANCH_3_FROM_IP" }, + { 0x0044, "MSR_LASTBRANCH_4_FROM_IP" }, + { 0x0045, "MSR_LASTBRANCH_5_FROM_IP" }, + { 0x0046, "MSR_LASTBRANCH_6_FROM_IP" }, + { 0x0047, "MSR_LASTBRANCH_7_FROM_IP" }, + { 0x0060, "MSR_LASTBRANCH_0_TO_IP" }, + { 0x0061, "MSR_LASTBRANCH_1_TO_IP" }, + { 0x0062, "MSR_LASTBRANCH_2_TO_IP" }, + { 0x0063, "MSR_LASTBRANCH_3_TO_IP" }, + { 0x0064, "MSR_LASTBRANCH_4_TO_IP" }, + { 0x0065, "MSR_LASTBRANCH_5_TO_IP" }, + { 0x0066, "MSR_LASTBRANCH_6_TO_IP" }, + { 0x0067, "MSR_LASTBRANCH_7_TO_IP" }, + /* Write register + { 0x0079, "IA32_BIOS_UPDT_TRIG" }, + */ + { 0x008b, "IA32_BIOS_SIGN_ID" }, + { 0x00c1, "IA32_PMC0" }, + { 0x00c2, "IA32_PMC1" }, + { 0x00e7, "IA32_MPERF" }, + { 0x00e8, "IA32_APERF" }, + { 0x00fe, "IA32_MTRRCAP" }, + { 0x0174, "IA32_SYSENTER_CS" }, + { 0x0175, "IA32_SYSENTER_ESP" }, + { 0x0176, "IA32_SYSENTER_EIP" }, + { 0x0179, "IA32_MCG_CAP" }, + { 0x017a, "IA32_MCG_STATUS" }, + { 0x0186, "IA32_PERF_EVNTSEL0" }, + { 0x0187, "IA32_PERF_EVNTSEL1" }, + { 0x0199, "IA32_PERF_CONTROL" }, + { 0x019a, "IA32_CLOCK_MODULATION" }, + { 0x019b, "IA32_THERM_INTERRUPT" }, + { 0x019c, "IA32_THERM_STATUS" }, + { 0x01a0, "IA32_MISC_ENABLES" }, + { 0x01b0, "IA32_ENERGY_PERF_BIAS" }, + { 0x01c9, "MSR_LASTBRANCH_TOS" }, + { 0x01d9, "IA32_DEBUGCTL" }, + { 0x01dd, "MSR_LER_FROM_LIP" }, + { 0x01de, "MSR_LER_TO_LIP" }, + { 0x01f2, "IA32_SMRR_PHYSBASE" }, + { 0x01f3, "IA32_SMRR_PHYSMASK" }, + { 0x0200, "IA32_MTRR_PHYSBASE0" }, + { 0x0201, "IA32_MTRR_PHYSMASK0" }, + { 0x0202, "IA32_MTRR_PHYSBASE1" }, + { 0x0203, "IA32_MTRR_PHYSMASK1" }, + { 0x0204, "IA32_MTRR_PHYSBASE2" }, + { 0x0205, "IA32_MTRR_PHYSMASK2" }, + { 0x0206, "IA32_MTRR_PHYSBASE3" }, + { 0x0207, "IA32_MTRR_PHYSMASK3" }, + { 0x0208, "IA32_MTRR_PHYSBASE4" }, + { 0x0209, "IA32_MTRR_PHYSMASK4" }, + { 0x020a, "IA32_MTRR_PHYSBASE5" }, + { 0x020b, "IA32_MTRR_PHYSMASK5" }, + { 0x020c, "IA32_MTRR_PHYSBASE6" }, + { 0x020d, "IA32_MTRR_PHYSMASK6" }, + { 0x020e, "IA32_MTRR_PHYSBASE7" }, + { 0x020f, "IA32_MTRR_PHYSMASK7" }, + { 0x0250, "IA32_MTRR_FIX64K_00000" }, + { 0x0258, "IA32_MTRR_FIX16K_80000" }, + { 0x0259, "IA32_MTRR_FIX16K_A0000" }, + { 0x0268, "IA32_MTRR_FIX4K_C0000" }, + { 0x0269, "IA32_MTRR_FIX4K_C8000" }, + { 0x026a, "IA32_MTRR_FIX4K_D0000" }, + { 0x026b, "IA32_MTRR_FIX4K_D8000" }, + { 0x026c, "IA32_MTRR_FIX4K_E0000" }, + { 0x026d, "IA32_MTRR_FIX4K_E8000" }, + { 0x026e, "IA32_MTRR_FIX4K_F0000" }, + { 0x026f, "IA32_MTRR_FIX4K_F8000" }, + { 0x0277, "IA32_PAT" }, + { 0x02FF, "IA32_MTRR_DEF_TYPE" }, + { 0x0309, "IA32_FIXED_CTR0" }, + { 0x030a, "IA32_FIXED_CTR1" }, + { 0x030b, "IA32_FIXED_CTR2" }, + { 0x0345, "IA32_PERF_CAPABILITIES" }, + { 0x038d, "IA32_FIXED_CTR_CTRL" }, + { 0x038e, "IA32_PERF_GLOBAL_STATUS" }, + { 0x038f, "IA32_PERF_GLOBAL_CTRL" }, + { 0x0390, "IA32_PERF_GLOBAL_OVF_CTRL" }, + { 0x03f1, "MSR_PEBS_ENABLE" }, + { 0x03fd, "MSR_CORE_C6_RESIDENCY" }, + { 0x40c, "IA32_MC3_CTL" }, + { 0x40d, "IA32_MC3_STATUS" }, + { 0x40e, "IA32_MC3_ADDR" }, + { 0x410, "IA32_MC4_CTL" }, + { 0x411, "IA32_MC4_STATUS" }, + { 0x412, "IA32_MC4_ADDR" }, + { 0x0480, "IA32_VMX_BASIC" }, + { 0x0481, "IA32_VMX_PINBASED_CTLS" }, + { 0x0482, "IA32_VMX_PROCBASED_CTLS" }, + { 0x0483, "IA32_VMX_EXIT_CTLS" }, + { 0x0484, "IA32_VMX_ENTRY_CTLS" }, + { 0x0485, "IA32_VMX_MISC" }, + { 0x0486, "IA32_VMX_CR0_FIXED0" }, + { 0x0487, "IA32_VMX_CR0_FIXED1" }, + { 0x0488, "IA32_VMX_CR4_FIXED0" }, + { 0x0489, "IA32_VMX_CR4_FIXED1" }, + { 0x048a, "IA32_VMX_VMCS_ENUM" }, + { 0x048b, "IA32_VMX_PROCBASED_CTLS2" }, + { 0x048c, "IA32_VMX_EPT_VPID_ENUM" }, + { 0x048d, "IA32_VMX_TRUE_PINBASED_CTLS" }, + { 0x048e, "IA32_VMX_TRUE_PROCBASED_CTLS" }, + { 0x048f, "IA32_VMX_TRUE_EXIT_CTLS" }, + { 0x0490, "IA32_VMX_TRUE_ENTRY_CTLS" }, + { 0x0491, "IA32_VMX_FMFUNC" }, + { 0x04c1, "IA32_A_PMC0" }, + { 0x04c2, "IA32_A_PMC1" }, + { 0x0600, "IA32_DS_AREA" }, + { 0x0660, "MSR_CORE_C1_RESIDENCY" }, + { 0x06e0, "IA32_TSC_DEADLINE" }, +}; - typedef struct { - unsigned int model; - const msr_entry_t *global_msrs; - unsigned int num_global_msrs; - const msr_entry_t *per_core_msrs; - unsigned int num_per_core_msrs; - } cpu_t; +static const msr_entry_t silvermont_global_msrs[] = { + /* + * Common MSRs in Intel Processors Based on the Silvermont Microarchitecture + * These are MSRs marked as "shared" or "package" + */ + { 0x0000, "IA32_P5_MC_ADDR" }, + { 0x0001, "IA32_P5_MC_TYPE" }, + { 0x0017, "IA32_PLATFORM_ID" }, + { 0x002a, "MSR_EBC_HARD_POWERON" }, + { 0x00cd, "MSR_FSB_FREQ" }, + { 0x00e2, "MSR_PKG_CST_CONFIG_CONTROL" }, + { 0x00e4, "MSR_PMG_IO_CAPTURE_BASE" }, + { 0x011e, "BBL_CR_CTL3" }, + { 0x0198, "IA32_PERF_STATUS" }, + { 0x01A2, "MSR_TEMPERATURE_TARGET" }, + { 0x01A6, "MSR_OFFCORE_RSP_0" }, + { 0x01A7, "MSR_OFFCORE_RSP_1" }, + { 0x01AD, "MSR_TURBO_RATIO_LIMIT" }, + { 0x03fa, "MSR_PKG_C6_RESIDENCY" }, + { 0x400, "IA32_MC0_CTL" }, + { 0x401, "IA32_MC0_STATUS" }, + { 0x402, "IA32_MC0_ADDR" }, + { 0x404, "IA32_MC1_CTL" }, + { 0x405, "IA32_MC1_STATUS" }, + { 0x408, "IA32_MC2_CTL" }, + { 0x409, "IA32_MC2_STATUS" }, + { 0x40a, "IA32_MC2_ADDR" }, + { 0x414, "MSR_MC5_CTL" }, + { 0x415, "MSR_MC5_STATUS" }, + { 0x416, "MSR_MC5_ADDR" }, +}; - cpu_t cpulist[] = { - { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 }, - { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 }, - { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, - { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, - { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) }, - { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, - { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, - { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, +typedef struct { + unsigned int model; + const msr_entry_t *global_msrs; + unsigned int num_global_msrs; + const msr_entry_t *per_core_msrs; + unsigned int num_per_core_msrs; +} cpu_t; +cpu_t cpulist[] = { + { 0x00670, model67x_global_msrs, ARRAY_SIZE(model67x_global_msrs), NULL, 0 }, + { 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 }, + { 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) }, + { 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) }, + { 0x00f20, modelf2x_global_msrs, ARRAY_SIZE(modelf2x_global_msrs), modelf2x_per_core_msrs, ARRAY_SIZE(modelf2x_per_core_msrs) }, + { 0x00f40, modelf4x_global_msrs, ARRAY_SIZE(modelf4x_global_msrs), modelf4x_per_core_msrs, ARRAY_SIZE(modelf4x_per_core_msrs) }, + { 0x106c0, model6_atom_global_msrs, ARRAY_SIZE(model6_atom_global_msrs), model6_atom_per_core_msrs, ARRAY_SIZE(model6_atom_per_core_msrs) }, + { 0x20650, model20650_global_msrs, ARRAY_SIZE(model20650_global_msrs), model20650_per_core_msrs, ARRAY_SIZE(model20650_per_core_msrs) }, { CPUID_BAYTRAIL, silvermont_global_msrs, ARRAY_SIZE(silvermont_global_msrs), silvermont_per_core_msrs, ARRAY_SIZE(silvermont_per_core_msrs) }, /* Baytrail */ - }; - cpu_t *cpu = NULL; /* Get CPU family and model, not the stepping diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index c6f486f..5931cb0 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -44,9 +44,9 @@ static inline uint8_t inb(unsigned port) } static inline uint16_t inw(unsigned port) { - uint16_t data; - __asm volatile("inw %w1,%0": "=a" (data) : "d" (port)); - return data; + uint16_t data; + __asm volatile("inw %w1,%0": "=a" (data) : "d" (port)); + return data; } static inline uint32_t inl(unsigned port) { diff --git a/util/inteltool/pcie.c b/util/inteltool/pcie.c index de70e6d..67b0e19 100644 --- a/util/inteltool/pcie.c +++ b/util/inteltool/pcie.c @@ -123,51 +123,51 @@ static const io_register_t sandybridge_dmi_registers[] = { * 329002-002 */ static const io_register_t haswell_ult_dmi_registers[] = { - { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability - { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 - { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 - { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control -/* { 0x0E, 2, "RSVD" }, // Reserved */ - { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability - { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control -/* { 0x18, 2, "RSVD" }, // Reserved */ - { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status - { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability - { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control -/* { 0x24, 2, "RSVD" }, // Reserved */ - { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status - { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability - { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control -/* { 0x30, 2, "RSVD" }, // Reserved */ - { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status - { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability - { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control -/* { 0x3C, 2, "RSVD" }, // Reserved */ - { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status - { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ - { 0x44, 4, "DMIESD" }, // DMI Element Self Description -/* { 0x48, 4, "RSVD" }, // Reserved */ -/* { 0x4C, 4, "RSVD" }, // Reserved */ - { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description -/* { 0x54, 4, "RSVD" }, // Reserved */ - { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address - { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address - { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description -/* { 0x64, 4, "RSVD" }, // Reserved */ - { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address -/* { 0x6C, 4, "RSVD" }, // Reserved */ -/* { 0x70, 4, "RSVD" }, // Reserved */ -/* { 0x74, 4, "RSVD" }, // Reserved */ -/* { 0x78, 4, "RSVD" }, // Reserved */ -/* { 0x7C, 4, "RSVD" }, // Reserved */ -/* { 0x80, 4, "RSVD" }, // Reserved */ -/* { 0x84, 4, "RSVD" }, // Reserved */ - { 0x88, 2, "LCTL" }, // Link Control - /* ... - Reserved */ - { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status - { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask - { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status - { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask + { 0x00, 4, "DMIVCECH" }, // DMI Virtual Channel Enhanced Capability + { 0x04, 4, "DMIPVCCAP1" }, // DMI Port VC Capability Register 1 + { 0x08, 4, "DMIPVCCAP2" }, // DMI Port VC Capability Register 2 + { 0x0C, 2, "DMI PVCCTL" }, // DMI Port VC Control +/* { 0x0E, 2, "RSVD" }, // Reserved */ + { 0x10, 4, "DMIVC0RCAP" }, // DMI VC0 Resource Capability + { 0x14, 4, "DMIVC0RCTL" }, // DMI VC0 Resource Control +/* { 0x18, 2, "RSVD" }, // Reserved */ + { 0x1A, 2, "DMIVC0RSTS" }, // DMI VC0 Resource Status + { 0x1C, 4, "DMIVC1RCAP" }, // DMI VC1 Resource Capability + { 0x20, 4, "DMIVC1RCTL" }, // DMI VC1 Resource Control +/* { 0x24, 2, "RSVD" }, // Reserved */ + { 0x26, 2, "DMIVC1RSTS" }, // DMI VC1 Resource Status + { 0x28, 4, "DMIVCPRCAP" }, // DMI VCp Resource Capability + { 0x2C, 4, "DMIVCPRCTL" }, // DMI VCp Resource Control +/* { 0x30, 2, "RSVD" }, // Reserved */ + { 0x32, 2, "DMIVCPRSTS" }, // DMI VCp Resource Status + { 0x34, 4, "DMIVCMRCAP" }, // DMI VCm Resource Capability + { 0x38, 4, "DMIVCMRCTL" }, // DMI VCm Resource Control +/* { 0x3C, 2, "RSVD" }, // Reserved */ + { 0x3E, 2, "DMIVCMRSTS" }, // DMI VCm Resource Status + { 0x40, 4, "DMIRCLDECH" }, // DMI Root Complex Link Declaration */ + { 0x44, 4, "DMIESD" }, // DMI Element Self Description +/* { 0x48, 4, "RSVD" }, // Reserved */ +/* { 0x4C, 4, "RSVD" }, // Reserved */ + { 0x50, 4, "DMILE1D" }, // DMI Link Entry 1 Description +/* { 0x54, 4, "RSVD" }, // Reserved */ + { 0x58, 4, "DMILE1A" }, // DMI Link Entry 1 Address + { 0x5C, 4, "DMILUE1A" }, // DMI Link Upper Entry 1 Address + { 0x60, 4, "DMILE2D" }, // DMI Link Entry 2 Description +/* { 0x64, 4, "RSVD" }, // Reserved */ + { 0x68, 4, "DMILE2A" }, // DMI Link Entry 2 Address +/* { 0x6C, 4, "RSVD" }, // Reserved */ +/* { 0x70, 4, "RSVD" }, // Reserved */ +/* { 0x74, 4, "RSVD" }, // Reserved */ +/* { 0x78, 4, "RSVD" }, // Reserved */ +/* { 0x7C, 4, "RSVD" }, // Reserved */ +/* { 0x80, 4, "RSVD" }, // Reserved */ +/* { 0x84, 4, "RSVD" }, // Reserved */ + { 0x88, 2, "LCTL" }, // Link Control + /* ... - Reserved */ + { 0x1C4, 4, "DMIUESTS" }, // DMI Uncorrectable Error Status + { 0x1C8, 4, "DMIUEMSK" }, // DMI Uncorrectable Error Mask + { 0x1D0, 4, "DMICESTS" }, // DMI Correctable Error Status + { 0x1D4, 4, "DMICEMSK" }, // DMI Correctable Error Mask /* ... - Reserved */ };

1 0

Patch set updated for coreboot: intel/skylake: Add support to enable wake-on-usb attach/detach
by Furquan Shaikh 18 Oct '16

18 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17056 -gerrit commit d6ba0c232d59fd935e252b96271d00ba2eb9cb66 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Oct 18 14:25:25 2016 -0700 intel/skylake: Add support to enable wake-on-usb attach/detach Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 4 +++ src/soc/intel/skylake/acpi/globalnvs.asl | 2 ++ src/soc/intel/skylake/acpi/xhci.asl | 51 ++++++++++++++++++++++++++++++++ src/soc/intel/skylake/chip.h | 6 ++++ src/soc/intel/skylake/include/soc/nvs.h | 4 ++- src/soc/intel/skylake/include/soc/usb.h | 7 +++++ 6 files changed, 73 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 28a0a6e..d83c74b 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -198,6 +198,10 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* Fill in the Wifi Region id */ gnvs->cid1 = wifi_regulatory_domain(); + + /* Set USB2/USB3 wake enable bitmaps. */ + gnvs->u2we = config->usb2_wake_enable_bitmap; + gnvs->u3we = config->usb3_wake_enable_bitmap; } unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 2bff7d3..ab3c63c 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -64,6 +64,8 @@ Field (GNVS, ByteAcc, NoLock, Preserve) NHLA, 64, // 0x31 - NHLT Address NHLL, 32, // 0x39 - NHLT Length CID1, 16, // 0x3d - Wifi Country Identifier + U2WE, 16, // 0x3f - USB2 Wake Enable Bitmap + U3WE, 8, // 0x41 - USB3 Wake Enable Bitmap /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 1a1c6e3..96f3b6a 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -15,6 +15,55 @@ * GNU General Public License for more details. */ +/* + * USB Port Wake Enable (UPWE) on usb attach/detach + * Arg0 - Port Number + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UPWE, 3, Serialized) +{ + /* Local0 = Arg1 + ((Arg0 - 1) * 0x10) */ + Add (Arg1, Multiply (Subtract (Arg0, 1), 0x10), Local0) + + /* Map ((XMEM << 16) + Local0 in PSCR */ + OperationRegion (PSCR, SystemMemory, + Add (ShiftLeft (Arg2, 16), Local0), 0x10) + Field (PSCR, AnyAcc, NoLock, Preserve) + { + , 25, + UPCE, 1, + UPDE, 1, + } + Store (One, UPCE) + Store (One, UPDE) +} + +/* + * USB Wake Enable Setup (UWES) + * Arg0 - Port enable bitmap + * Arg1 - Port 1 Status and control offset + * Arg2 - xHCI Memory-mapped address + */ +Method (UWES, 3, Serialized) +{ + Store (Arg0, Local0) + + While (One) { + FindSetRightBit (Local0, Local1) + If (LEqual (Local1, Zero)) { + Break + } + UPWE (Local1, Arg1, Arg2) + /* + * Clear the lowest set bit in Local0 since it was + * processed. + * Local0 = Local0 & (Local0 - 1) + */ + And (Local0, Subtract (Local0, 1), Local0) + } +} + /* XHCI Controller 0:14.0 */ Device (XHCI) @@ -26,6 +75,8 @@ Device (XHCI) Method (_DSW, 3) { Store (Arg0, PMEE) + UWES (And (\U2WE, 0x3FF), 0x480, XMEM) + UWES (And (\U3WE, 0x3F), 0x540, XMEM) } Name (_S3D, 3) /* D3 supported in S3 */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 00393b2..5a4e85b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -395,6 +395,12 @@ struct soc_intel_skylake_config { /* Use custom SD card detect GPIO configuration */ struct acpi_gpio sdcard_cd_gpio; + + /* Wake Enable Bitmap for USB2 ports */ + u16 usb2_wake_enable_bitmap; + + /* Wake Enable Bitmap for USB3 ports */ + u8 usb3_wake_enable_bitmap; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index f9d5b71..cb3b2c6 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -54,7 +54,9 @@ typedef struct { u64 nhla; /* 0x31 - NHLT Address */ u32 nhll; /* 0x39 - NHLT Length */ u16 cid1; /* 0x3d - Wifi Country Identifier */ - u8 unused[193]; + u16 u2we; /* 0x3f - USB2 Wake Enable Bitmap */ + u8 u3we; /* 0x41 - USB3 Wake Enable Bitmap */ + u8 unused[190]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index e5b0495..a18e79c 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -169,4 +169,11 @@ struct usb3_port_config { .tx_downscale_amp = 0x00, \ } +/* + * Set bit corresponding to USB port in wake enable bitmap. Bit 0 corresponds + * to Port 1, Bit n corresponds to Port (n+1). This bitmap is later used to + * decide what ports need to set PORTSCN/PORTSCXUSB3 register bits. + */ +#define USB_PORT_WAKE_ENABLE(x) (1 << (x - 1)) + #endif

1 0

New patch to review for coreboot: riscv: Move SBI call implementations under arch/riscv/
by Jonathan Neuschäfer 18 Oct '16

18 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17057 -gerrit commit e479645f0c95789b011179929d6842e39b8c0afd Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Oct 19 02:18:53 2016 +0200 riscv: Move SBI call implementations under arch/riscv/ Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/arch/riscv/Makefile.inc | 2 + src/arch/riscv/include/mcall.h | 70 ++++++++++++++++ src/arch/riscv/include/spike_util.h | 70 ---------------- src/arch/riscv/mcall.c | 100 +++++++++++++++++++++++ src/arch/riscv/trap_handler.c | 2 +- src/mainboard/emulation/qemu-riscv/Makefile.inc | 3 - src/mainboard/emulation/qemu-riscv/qemu_util.c | 100 ----------------------- src/mainboard/emulation/spike-riscv/Makefile.inc | 3 - src/mainboard/emulation/spike-riscv/spike_util.c | 100 ----------------------- src/mainboard/emulation/spike-riscv/uart.c | 1 - 10 files changed, 173 insertions(+), 278 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 4bab459..1ddfe19 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -34,6 +34,7 @@ $(call src-to-obj,bootblock,$(dir)/id.S): $(obj)/build.h bootblock-y = bootblock.S stages.c bootblock-y += trap_util.S bootblock-y += trap_handler.c +bootblock-y += mcall.c bootblock-y += virtual_memory.c bootblock-y += boot.c bootblock-y += misc.c @@ -90,6 +91,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y) ramstage-y = ramstage-y += trap_handler.c +ramstage-y += mcall.c ramstage-y += virtual_memory.c ramstage-y += stages.c ramstage-y += misc.c diff --git a/src/arch/riscv/include/mcall.h b/src/arch/riscv/include/mcall.h new file mode 100644 index 0000000..a43b9cf --- /dev/null +++ b/src/arch/riscv/include/mcall.h @@ -0,0 +1,70 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2013 The ChromiumOS Authors + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _MCALL_H +#define _MCALL_H + +#include <arch/encoding.h> +#include <atomic.h> +#include <stdint.h> + +#define HLS_SIZE 64 +#define MENTRY_FRAME_SIZE HLS_SIZE + +typedef struct { + unsigned long base; + unsigned long size; + unsigned long node_id; +} memory_block_info; + +typedef struct { + unsigned long dev; + unsigned long cmd; + unsigned long data; + unsigned long sbi_private_data; +} sbi_device_message; + + +typedef struct { + sbi_device_message* device_request_queue_head; + unsigned long device_request_queue_size; + sbi_device_message* device_response_queue_head; + sbi_device_message* device_response_queue_tail; + + int hart_id; + int ipi_pending; +} hls_t; + +#define MACHINE_STACK_TOP() ({ \ + register uintptr_t sp asm ("sp"); \ + (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) + +// hart-local storage, at top of stack +#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) +#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) + +#define MACHINE_STACK_SIZE RISCV_PGSIZE + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p); +uintptr_t mcall_console_putchar(uint8_t ch); +uintptr_t mcall_dev_req(sbi_device_message *m); +uintptr_t mcall_dev_resp(void); +uintptr_t mcall_set_timer(unsigned long long when); +uintptr_t mcall_clear_ipi(void); +uintptr_t mcall_send_ipi(uintptr_t recipient); +uintptr_t mcall_shutdown(void); +void hls_init(uint32_t hart_id); // need to call this before launching linux + +#endif diff --git a/src/arch/riscv/include/spike_util.h b/src/arch/riscv/include/spike_util.h deleted file mode 100644 index 175ee6c..0000000 --- a/src/arch/riscv/include/spike_util.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 The ChromiumOS Authors - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SPIKE_UTIL_H -#define _SPIKE_UTIL_H - -#include <arch/encoding.h> -#include <atomic.h> -#include <stdint.h> - -#define HLS_SIZE 64 -#define MENTRY_FRAME_SIZE HLS_SIZE - -typedef struct { - unsigned long base; - unsigned long size; - unsigned long node_id; -} memory_block_info; - -typedef struct { - unsigned long dev; - unsigned long cmd; - unsigned long data; - unsigned long sbi_private_data; -} sbi_device_message; - - -typedef struct { - sbi_device_message* device_request_queue_head; - unsigned long device_request_queue_size; - sbi_device_message* device_response_queue_head; - sbi_device_message* device_response_queue_tail; - - int hart_id; - int ipi_pending; -} hls_t; - -#define MACHINE_STACK_TOP() ({ \ - register uintptr_t sp asm ("sp"); \ - (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); }) - -// hart-local storage, at top of stack -#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE)) -#define OTHER_HLS(id) ((hls_t*)((void*)HLS() + RISCV_PGSIZE * ((id) - HLS()->hart_id))) - -#define MACHINE_STACK_SIZE RISCV_PGSIZE - -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *p); -uintptr_t mcall_console_putchar(uint8_t ch); -uintptr_t mcall_dev_req(sbi_device_message *m); -uintptr_t mcall_dev_resp(void); -uintptr_t mcall_set_timer(unsigned long long when); -uintptr_t mcall_clear_ipi(void); -uintptr_t mcall_send_ipi(uintptr_t recipient); -uintptr_t mcall_shutdown(void); -void hls_init(uint32_t hart_id); // need to call this before launching linux - -#endif diff --git a/src/arch/riscv/mcall.c b/src/arch/riscv/mcall.c new file mode 100644 index 0000000..b571fbc --- /dev/null +++ b/src/arch/riscv/mcall.c @@ -0,0 +1,100 @@ +/* + * Copyright (c) 2013, The Regents of the University of California (Regents). + * All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. Neither the name of the Regents nor the + * names of its contributors may be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, + * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING + * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS + * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED + * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE + * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. + */ + +#include <arch/barrier.h> +#include <arch/errno.h> +#include <atomic.h> +#include <console/console.h> +#include <mcall.h> +#include <string.h> +#include <vm.h> + +uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) +{ + if (id == 0) { + mprv_write_ulong(&info->base, 2U*GiB); + + /* TODO: Return the correct value */ + mprv_write_ulong(&info->size, 1*GiB); + return 0; + } + + return -1; +} + +uintptr_t mcall_send_ipi(uintptr_t recipient) +{ + die("mcall_send_ipi is currently not implemented"); + return 0; +} + +uintptr_t mcall_clear_ipi(void) +{ + // only clear SSIP if no other events are pending + if (HLS()->device_response_queue_head == NULL) { + clear_csr(mip, MIP_SSIP); + mb(); + } + + return atomic_swap(&HLS()->ipi_pending, 0); +} + +uintptr_t mcall_shutdown(void) +{ + die("mcall_shutdown is currently not implemented"); + return 0; +} + +uintptr_t mcall_set_timer(unsigned long long when) +{ + printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); + return 0; +} + +uintptr_t mcall_dev_req(sbi_device_message *m) +{ + die("mcall_dev_req is currently not implemented"); + return 0; +} + +uintptr_t mcall_dev_resp(void) +{ + die("mcall_dev_resp is currently not implemented"); + return 0; +} + +void hls_init(uint32_t hart_id) +{ + memset(HLS(), 0, sizeof(*HLS())); + HLS()->hart_id = hart_id; +} + +uintptr_t mcall_console_putchar(uint8_t ch) +{ + do_putchar(ch); + return 0; +} diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ad49928..8a7b513 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -17,7 +17,7 @@ #include <arch/exception.h> #include <arch/sbi.h> #include <console/console.h> -#include <spike_util.h> +#include <mcall.h> #include <string.h> #include <vm.h> diff --git a/src/mainboard/emulation/qemu-riscv/Makefile.inc b/src/mainboard/emulation/qemu-riscv/Makefile.inc index 4fbe401..36f1fca 100644 --- a/src/mainboard/emulation/qemu-riscv/Makefile.inc +++ b/src/mainboard/emulation/qemu-riscv/Makefile.inc @@ -13,14 +13,11 @@ ## GNU General Public License for more details. bootblock-y += uart.c -bootblock-y += qemu_util.c bootblock-y += rom_media.c romstage-y += romstage.c -romstage-y += qemu_util.c romstage-y += uart.c romstage-y += rom_media.c ramstage-y += uart.c -ramstage-y += qemu_util.c ramstage-y += rom_media.c bootblock-y += memlayout.ld diff --git a/src/mainboard/emulation/qemu-riscv/qemu_util.c b/src/mainboard/emulation/qemu-riscv/qemu_util.c deleted file mode 100644 index c97a61f..0000000 --- a/src/mainboard/emulation/qemu-riscv/qemu_util.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ - -#include <arch/barrier.h> -#include <arch/errno.h> -#include <atomic.h> -#include <console/console.h> -#include <spike_util.h> -#include <string.h> -#include <vm.h> - -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) -{ - if (id == 0) { - mprv_write_ulong(&info->base, 2U*GiB); - - /* TODO: Return the correct value */ - mprv_write_ulong(&info->size, 1*GiB); - return 0; - } - - return -1; -} - -uintptr_t mcall_send_ipi(uintptr_t recipient) -{ - die("mcall_send_ipi is currently not implemented"); - return 0; -} - -uintptr_t mcall_clear_ipi(void) -{ - // only clear SSIP if no other events are pending - if (HLS()->device_response_queue_head == NULL) { - clear_csr(mip, MIP_SSIP); - mb(); - } - - return atomic_swap(&HLS()->ipi_pending, 0); -} - -uintptr_t mcall_shutdown(void) -{ - die("mcall_shutdown is currently not implemented"); - return 0; -} - -uintptr_t mcall_set_timer(unsigned long long when) -{ - printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); - return 0; -} - -uintptr_t mcall_dev_req(sbi_device_message *m) -{ - die("mcall_dev_req is currently not implemented"); - return 0; -} - -uintptr_t mcall_dev_resp(void) -{ - die("mcall_dev_resp is currently not implemented"); - return 0; -} - -void hls_init(uint32_t hart_id) -{ - memset(HLS(), 0, sizeof(*HLS())); - HLS()->hart_id = hart_id; -} - -uintptr_t mcall_console_putchar(uint8_t ch) -{ - do_putchar(ch); - return 0; -} diff --git a/src/mainboard/emulation/spike-riscv/Makefile.inc b/src/mainboard/emulation/spike-riscv/Makefile.inc index e3c9481..36f1fca 100644 --- a/src/mainboard/emulation/spike-riscv/Makefile.inc +++ b/src/mainboard/emulation/spike-riscv/Makefile.inc @@ -13,14 +13,11 @@ ## GNU General Public License for more details. bootblock-y += uart.c -bootblock-y += spike_util.c bootblock-y += rom_media.c romstage-y += romstage.c romstage-y += uart.c -romstage-y += spike_util.c romstage-y += rom_media.c ramstage-y += uart.c -ramstage-y += spike_util.c ramstage-y += rom_media.c bootblock-y += memlayout.ld diff --git a/src/mainboard/emulation/spike-riscv/spike_util.c b/src/mainboard/emulation/spike-riscv/spike_util.c deleted file mode 100644 index c97a61f..0000000 --- a/src/mainboard/emulation/spike-riscv/spike_util.c +++ /dev/null @@ -1,100 +0,0 @@ -/* - * Copyright (c) 2013, The Regents of the University of California (Regents). - * All Rights Reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution. - * 3. Neither the name of the Regents nor the - * names of its contributors may be used to endorse or promote products - * derived from this software without specific prior written permission. - * - * IN NO EVENT SHALL REGENTS BE LIABLE TO ANY PARTY FOR DIRECT, INDIRECT, - * SPECIAL, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING LOST PROFITS, ARISING - * OUT OF THE USE OF THIS SOFTWARE AND ITS DOCUMENTATION, EVEN IF REGENTS HAS - * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * REGENTS SPECIFICALLY DISCLAIMS ANY WARRANTIES, INCLUDING, BUT NOT LIMITED TO, - * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR - * PURPOSE. THE SOFTWARE AND ACCOMPANYING DOCUMENTATION, IF ANY, PROVIDED - * HEREUNDER IS PROVIDED "AS IS". REGENTS HAS NO OBLIGATION TO PROVIDE - * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS. - */ - -#include <arch/barrier.h> -#include <arch/errno.h> -#include <atomic.h> -#include <console/console.h> -#include <spike_util.h> -#include <string.h> -#include <vm.h> - -uintptr_t mcall_query_memory(uintptr_t id, memory_block_info *info) -{ - if (id == 0) { - mprv_write_ulong(&info->base, 2U*GiB); - - /* TODO: Return the correct value */ - mprv_write_ulong(&info->size, 1*GiB); - return 0; - } - - return -1; -} - -uintptr_t mcall_send_ipi(uintptr_t recipient) -{ - die("mcall_send_ipi is currently not implemented"); - return 0; -} - -uintptr_t mcall_clear_ipi(void) -{ - // only clear SSIP if no other events are pending - if (HLS()->device_response_queue_head == NULL) { - clear_csr(mip, MIP_SSIP); - mb(); - } - - return atomic_swap(&HLS()->ipi_pending, 0); -} - -uintptr_t mcall_shutdown(void) -{ - die("mcall_shutdown is currently not implemented"); - return 0; -} - -uintptr_t mcall_set_timer(unsigned long long when) -{ - printk(BIOS_DEBUG, "mcall_set_timer is currently not implemented, ignoring\n"); - return 0; -} - -uintptr_t mcall_dev_req(sbi_device_message *m) -{ - die("mcall_dev_req is currently not implemented"); - return 0; -} - -uintptr_t mcall_dev_resp(void) -{ - die("mcall_dev_resp is currently not implemented"); - return 0; -} - -void hls_init(uint32_t hart_id) -{ - memset(HLS(), 0, sizeof(*HLS())); - HLS()->hart_id = hart_id; -} - -uintptr_t mcall_console_putchar(uint8_t ch) -{ - do_putchar(ch); - return 0; -} diff --git a/src/mainboard/emulation/spike-riscv/uart.c b/src/mainboard/emulation/spike-riscv/uart.c index 8513849..57647fe 100644 --- a/src/mainboard/emulation/spike-riscv/uart.c +++ b/src/mainboard/emulation/spike-riscv/uart.c @@ -17,7 +17,6 @@ #include <console/uart.h> #include <arch/io.h> #include <boot/coreboot_tables.h> -#include <spike_util.h> uintptr_t uart_platform_base(int idx) {

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Patch set updated for coreboot: intel/skylake: Add support to enable wake-on-usb attach/detach
by Furquan Shaikh 18 Oct '16

18 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17056 -gerrit commit c20e4b714259c419efc99c698b6a59d937addf34 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Oct 18 14:25:25 2016 -0700 intel/skylake: Add support to enable wake-on-usb attach/detach Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/skylake/acpi.c | 2 ++ src/soc/intel/skylake/acpi/globalnvs.asl | 1 + src/soc/intel/skylake/acpi/xhci.asl | 37 ++++++++++++++++++++++++++++++++ src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/include/soc/nvs.h | 3 ++- src/soc/intel/skylake/include/soc/usb.h | 2 ++ 6 files changed, 47 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 28a0a6e..b839b75 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -198,6 +198,8 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* Fill in the Wifi Region id */ gnvs->cid1 = wifi_regulatory_domain(); + + gnvs->uweb = config->usb_wake_enable_bitmap; } unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 2bff7d3..6d95f0f 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -64,6 +64,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) NHLA, 64, // 0x31 - NHLT Address NHLL, 32, // 0x39 - NHLT Length CID1, 16, // 0x3d - Wifi Country Identifier + UWEB, 16, // 0x3f - USB Wake Enable Bitmap /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 1a1c6e3..cab23e1 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -15,6 +15,30 @@ * GNU General Public License for more details. */ +/* + * Enable wake-up on USB attach/detach for given port. + * Arg0 - Port Number + * Arg1 - XHCI Memory-mapped address + */ +Method (UPWE, 2, Serialized) +{ + /* + * PORTSCN starts at offset 0x480 for port 1, 0x490 for port 2 and so + * on. Get the region base address by using port number. + */ + Add (0x480, Multiply (Subtract (Arg0, 1), 0x10), Local0) + OperationRegion (PSCN, SystemMemory, + Add (ShiftLeft (Arg1, 16), Local0), 0x10) + Field (PSCN, AnyAcc, NoLock, Preserve) + { + , 25, + UPCE, 1, + UPDE, 1, + } + Store (One, UPCE) + Store (One, UPDE) +} + /* XHCI Controller 0:14.0 */ Device (XHCI) @@ -26,6 +50,19 @@ Device (XHCI) Method (_DSW, 3) { Store (Arg0, PMEE) + + /* Get USB Wake enable bitmask. Take only lower 10 bits. */ + Store (\UWEB, Local0) + And (Local0, 0x3FF, Local0) + + While (One) { + FindSetRightBit (Local0, Local1) + If (LEqual (Local1, Zero)) { + Break + } + UPWE (Local1, XMEM) + Store (And (Local0, Subtract (Local0, 1)), Local0) + } } Name (_S3D, 3) /* D3 supported in S3 */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 00393b2..ed9b8d4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -395,6 +395,9 @@ struct soc_intel_skylake_config { /* Use custom SD card detect GPIO configuration */ struct acpi_gpio sdcard_cd_gpio; + + /* Wake Enable Bitmap for USB ports */ + u16 usb_wake_enable_bitmap; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index f9d5b71..f89f82b 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -54,7 +54,8 @@ typedef struct { u64 nhla; /* 0x31 - NHLT Address */ u32 nhll; /* 0x39 - NHLT Length */ u16 cid1; /* 0x3d - Wifi Country Identifier */ - u8 unused[193]; + u16 uweb; /* 0x3f - USB Wake Enable Bitmap */ + u8 unused[191]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index e5b0495..f837366 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -169,4 +169,6 @@ struct usb3_port_config { .tx_downscale_amp = 0x00, \ } +#define USB2_PORT(x) (1 << (x - 1)) + #endif

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New patch to review for coreboot: intel/skylake: Add support to enable wake-on-usb attach/detach
by Furquan Shaikh 18 Oct '16

18 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17056 -gerrit commit 8fd56615f7fe0b32e9dcdb6d408eee405acd165b Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Oct 18 14:25:25 2016 -0700 intel/skylake: Add support to enable wake-on-usb attach/detach Three things are required to enable wake-on-usb: 1. 5V to USB ports should be enabled in S3. 2. ASL file needs to have appropriate wake bit set. 3. XHCI controller should have the wake on attach/detach bit set for the corresponding port in PORTSCN register. Only part missing was #3. This CL adds support to allow mainboard to define a bitmap in devicetree corresponding to the ports that it wants to enable wake-on-usb feature. Based on the bitmap, wake on attach/detach bits in PORTSCN would be set by xhci.asl for the appropriate ports. BUG=chrome-os-partner:58734 BRANCH=None TEST=Verified that with port 5 enabled, chell wakes up from S3 on usb attach/detach. Change-Id: I40a22a450e52f74a0ab93ebb8170555d834ebdaf Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/chell/devicetree.cb | 3 +++ src/soc/intel/skylake/acpi.c | 2 ++ src/soc/intel/skylake/acpi/globalnvs.asl | 1 + src/soc/intel/skylake/acpi/xhci.asl | 37 ++++++++++++++++++++++++++++++++ src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/include/soc/nvs.h | 3 ++- src/soc/intel/skylake/include/soc/usb.h | 2 ++ 7 files changed, 50 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/chell/devicetree.cb b/src/mainboard/google/chell/devicetree.cb index 230a9a6..9576516 100644 --- a/src/mainboard/google/chell/devicetree.cb +++ b/src/mainboard/google/chell/devicetree.cb @@ -186,6 +186,9 @@ chip soc/intel/skylake # Send an extra VR mailbox command for the supported MPS IMVP8 model register "SendVrMbxCmd" = "1" + # Wake for USB port 5 + register "usb_wake_enable_bitmap" = "USB2_PORT(5)" + device cpu_cluster 0 on device lapic 0 on end end diff --git a/src/soc/intel/skylake/acpi.c b/src/soc/intel/skylake/acpi.c index 28a0a6e..b839b75 100644 --- a/src/soc/intel/skylake/acpi.c +++ b/src/soc/intel/skylake/acpi.c @@ -198,6 +198,8 @@ static void acpi_create_gnvs(global_nvs_t *gnvs) /* Fill in the Wifi Region id */ gnvs->cid1 = wifi_regulatory_domain(); + + gnvs->uweb = config->usb_wake_enable_bitmap; } unsigned long acpi_fill_mcfg(unsigned long current) diff --git a/src/soc/intel/skylake/acpi/globalnvs.asl b/src/soc/intel/skylake/acpi/globalnvs.asl index 2bff7d3..6d95f0f 100644 --- a/src/soc/intel/skylake/acpi/globalnvs.asl +++ b/src/soc/intel/skylake/acpi/globalnvs.asl @@ -64,6 +64,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve) NHLA, 64, // 0x31 - NHLT Address NHLL, 32, // 0x39 - NHLT Length CID1, 16, // 0x3d - Wifi Country Identifier + UWEB, 16, // 0x3f - USB Wake Enable Bitmap /* ChromeOS specific */ Offset (0x100), diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 1a1c6e3..cab23e1 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -15,6 +15,30 @@ * GNU General Public License for more details. */ +/* + * Enable wake-up on USB attach/detach for given port. + * Arg0 - Port Number + * Arg1 - XHCI Memory-mapped address + */ +Method (UPWE, 2, Serialized) +{ + /* + * PORTSCN starts at offset 0x480 for port 1, 0x490 for port 2 and so + * on. Get the region base address by using port number. + */ + Add (0x480, Multiply (Subtract (Arg0, 1), 0x10), Local0) + OperationRegion (PSCN, SystemMemory, + Add (ShiftLeft (Arg1, 16), Local0), 0x10) + Field (PSCN, AnyAcc, NoLock, Preserve) + { + , 25, + UPCE, 1, + UPDE, 1, + } + Store (One, UPCE) + Store (One, UPDE) +} + /* XHCI Controller 0:14.0 */ Device (XHCI) @@ -26,6 +50,19 @@ Device (XHCI) Method (_DSW, 3) { Store (Arg0, PMEE) + + /* Get USB Wake enable bitmask. Take only lower 10 bits. */ + Store (\UWEB, Local0) + And (Local0, 0x3FF, Local0) + + While (One) { + FindSetRightBit (Local0, Local1) + If (LEqual (Local1, Zero)) { + Break + } + UPWE (Local1, XMEM) + Store (And (Local0, Subtract (Local0, 1)), Local0) + } } Name (_S3D, 3) /* D3 supported in S3 */ diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 00393b2..ed9b8d4 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -395,6 +395,9 @@ struct soc_intel_skylake_config { /* Use custom SD card detect GPIO configuration */ struct acpi_gpio sdcard_cd_gpio; + + /* Wake Enable Bitmap for USB ports */ + u16 usb_wake_enable_bitmap; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/include/soc/nvs.h b/src/soc/intel/skylake/include/soc/nvs.h index f9d5b71..f89f82b 100644 --- a/src/soc/intel/skylake/include/soc/nvs.h +++ b/src/soc/intel/skylake/include/soc/nvs.h @@ -54,7 +54,8 @@ typedef struct { u64 nhla; /* 0x31 - NHLT Address */ u32 nhll; /* 0x39 - NHLT Length */ u16 cid1; /* 0x3d - Wifi Country Identifier */ - u8 unused[193]; + u16 uweb; /* 0x3f - USB Wake Enable Bitmap */ + u8 unused[191]; /* ChromeOS specific (0x100 - 0xfff) */ chromeos_acpi_t chromeos; diff --git a/src/soc/intel/skylake/include/soc/usb.h b/src/soc/intel/skylake/include/soc/usb.h index e5b0495..f837366 100644 --- a/src/soc/intel/skylake/include/soc/usb.h +++ b/src/soc/intel/skylake/include/soc/usb.h @@ -169,4 +169,6 @@ struct usb3_port_config { .tx_downscale_amp = 0x00, \ } +#define USB2_PORT(x) (1 << (x - 1)) + #endif

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Patch set updated for coreboot: marvell/mvmap2315: Compose BOOTBLOCK region
by Daisuke Nojiri 18 Oct '16

18 Oct '16

Daisuke Nojiri (dnojiri(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16747 -gerrit commit f1a9fd8b8b3c095ca3601297d82790efb9050e87 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Sep 23 17:40:15 2016 -0700 marvell/mvmap2315: Compose BOOTBLOCK region This patch adds a Makefile rule for mvmap2315 to install a BDB and bootblock code in the BOOTBLOCK region. The resulting BDB has a header and data both signed by a RSA-4096 key. BUG=chrome-os-partner:57889 BRANCH=none TEST=emerge-rotor coreboot and examined the output binary. Booted coreboot.rom on Palladium. Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- 3rdparty/blobs | 2 +- src/soc/marvell/mvmap2315/Makefile.inc | 75 +++++++++++++++++++++++++++++++++- 2 files changed, 75 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8ad2d63..9ba0703 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8ad2d6385652e14b6f0d35ab9b474c31ddeb1773 +Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1 diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index d30ab68..c6426f1 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -63,4 +63,77 @@ romstage-y += wdt.c CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ -endif +# +# Common Boot Flow parameters +# +BOOTBLOCK_REGION_SIZE = 131072 +BOOTBLOCK_TYPE = 1 +BOOTBLOCK_PARTITION = 1 +BOOTBLOCK_LOAD_ADDRESS = 0xe000c000 +BDB = $(obj)/bdb.bin +BDB_LOAD_ADDRESS = 0xe0000000 +DATA_VERSION = 2 + +# +# Keys used to create BDB +# +KEYDIR = $(VBOOT_SOURCE)/tests/testkeys +BDBKEY_PUB = $(KEYDIR)/bdbkey.keyb +BDBKEY_PRI = $(KEYDIR)/bdbkey.pem +BDBKEY_DIGEST = $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin +# Use bdbkeys because mvmap2315's bootROM doesn't support RSA3072b with +# exponent 3 and the algorithms for BDB key and data key have to match. +DATAKEY_PUB = $(KEYDIR)/bdbkey.keyb +DATAKEY_PRI = $(KEYDIR)/bdbkey.pem + +# Calculate bootblock.raw.bin's size and offset +.PHONY: bootblock_offset +bootblock_offset: $(objcbfs)/bootblock.raw.bin + $(eval BOOTBLOCK_SIZE = $(call file-size, $<)) + $(eval BOOTBLOCK_OFFSET = $(call int-subtract, \ + $(BOOTBLOCK_REGION_SIZE) $(BOOTBLOCK_SIZE))) + +# +# Create BDB +# +# TODO: Verify sign algorithms of the BDB key and data key are supported +$(BDB): $(objcbfs)/bootblock.raw.bin $(FUTILITY) bootblock_offset \ + $(BDBKEY_PRI) $(BDBKEY_PUB) $(DATAKEY_PRI) $(DATAKEY_PUB) \ + $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin + $(FUTILITY) bdb --create $@.tmp \ + --bdbkey_pri $(BDBKEY_PRI) --bdbkey_pub $(BDBKEY_PUB) \ + --datakey_pri $(DATAKEY_PRI) --datakey_pub $(DATAKEY_PUB) \ + --load_address $(BDB_LOAD_ADDRESS) + $(FUTILITY) bdb --add $@.tmp \ + --data $< \ + --offset $(BOOTBLOCK_OFFSET) \ + --partition $(BOOTBLOCK_PARTITION) \ + --type $(BOOTBLOCK_TYPE) \ + --load_address $(BOOTBLOCK_LOAD_ADDRESS) + $(FUTILITY) bdb --resign $@.tmp \ + --datakey_pri $(DATAKEY_PRI) \ + --data_version $(DATA_VERSION) + $(FUTILITY) bdb --verify $@.tmp --key_digest $(BDBKEY_DIGEST) + mv $@.tmp $@ + +# +# Create custom bootblock.bin +# +# This overrides generic pattern rule *.raw.bin -> *.bin for bootblock.bin. +# bootblock.bin is structured as follows: +# +------------------+ +# | BDB | +# +------------------+ +# | 000............0 | +# +------------------+ +# |bootblock.raw.bin | +# +------------------+ +# And this will be placed in BOOTBLOCK region. +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BDB) bootblock_offset + dd if=/dev/zero bs=1 count=$(BOOTBLOCK_REGION_SIZE) of=$@.tmp + dd if=$(BDB) bs=1 count=$(call file-size, $(BDB)) conv=notrunc of=$@.tmp + dd if=$(objcbfs)/bootblock.raw.bin bs=1 count=$(BOOTBLOCK_SIZE) \ + seek=$(BOOTBLOCK_OFFSET) conv=notrunc of=$@.tmp + mv $@.tmp $@ + +endif \ No newline at end of file

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Patch set updated for coreboot: mvmap2315: Skip uart_init when serial is disabled
by Daisuke Nojiri 18 Oct '16

18 Oct '16

Daisuke Nojiri (dnojiri(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16746 -gerrit commit 06700318abc0a640a950fea0fbee7041c1f4f448 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Mon Sep 26 10:46:53 2016 -0700 mvmap2315: Skip uart_init when serial is disabled When coreboot is built with CONFIG_CONSOLE_SERIAL not set, uart_init does not exist, causing compilation to fail. This patch fixes it by skipping uart_init when serial is disabled. BUG=none BRANCH=none TEST=emerge-rotor coreboot Change-Id: If7f475eae9008b392f8f1e5cb5568c93113ee3f1 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/soc/marvell/mvmap2315/bootblock.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/marvell/mvmap2315/bootblock.c b/src/soc/marvell/mvmap2315/bootblock.c index 6b0a333..57fd38c 100644 --- a/src/soc/marvell/mvmap2315/bootblock.c +++ b/src/soc/marvell/mvmap2315/bootblock.c @@ -93,9 +93,11 @@ void bootblock_soc_init(void) printk(BIOS_DEBUG, "Powering up the AP core0.\n"); ap_start((void *)MVMAP2315_ROMSTAGE_BASE); - /* initializing UART1 to free UART0 to be used by romstage */ - uart_num = 1; - uart_init(uart_num); + /* Initializing UART1 to free UART0 to be used by AP */ + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL)) { + uart_num = 1; + uart_init(uart_num); + } while (read32((void *)MVMAP2315_BOOTBLOCK_CB1) != 0x4) ;

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Patch merged into coreboot/master: rk3399: display: Use edid_set_framebuffer_bits_per_pixel() helper
by gerrit＠coreboot.org 18 Oct '16

18 Oct '16

the following patch was just integrated into master: commit e74f5eaa432b6483da56c5e964a6f5fbf29cbaed Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 17 18:14:41 2016 -0700 rk3399: display: Use edid_set_framebuffer_bits_per_pixel() helper This refactoring was already carried into RK3288 with commit 6911219 (edid: Add helper function to calculate bits-per-pixel dependent values) but it seems that the code for RK3399 was copy&pasted from it too early to pick this up. Fix that so that future Rockchip SoCs can copy&paste the right thing. Change-Id: I5050c58d18db38fffabc7666e67a622d4a828590 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: https://review.coreboot.org/17050 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See https://review.coreboot.org/17050 for details. -gerrit

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New patch to review for coreboot: intel/broadwell: "free" memory after use
by Patrick Georgi 18 Oct '16

18 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17055 -gerrit commit d495199b2b828ac7784c8322c5671ca87a14e1a1 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Tue Oct 18 19:46:33 2016 +0200 intel/broadwell: "free" memory after use While we stub out free(), tools like coverity scan have no idea, and it might change in the future. So free it. Change-Id: I1d93a6f45b64445662daa95b51128140ad0a87e2 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1260716 --- src/soc/intel/broadwell/me.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/broadwell/me.c b/src/soc/intel/broadwell/me.c index 893c19b..1b086ec 100644 --- a/src/soc/intel/broadwell/me.c +++ b/src/soc/intel/broadwell/me.c @@ -966,6 +966,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) } #undef ASSIGN_FIELD_PTR + free(mbp); return ret; }

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coreboot-gerrit October 2016