coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: intel/{skylake, apollolake}: Enable signalling of error condition
by Patrick Georgi 18 Oct '16

18 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17054 -gerrit commit d822f5ab8a89e6748597d503e8fcf4b028645975 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Jul 29 18:37:56 2016 +0200 intel/{skylake,apollolake}: Enable signalling of error condition Testing for "devfn < 0" on an unsigned doesn't work, and i2c_bus_to_devfn returns an int (with -1 for "error"), so use int for devfn. Adapt Change-Id I7d1cdb6af4140f7dc322141c0c018d8418627434 to fix more instances. Change-Id: I001a9b484a68e018798a65c0fae11f8df7d9f564 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Found-by: Coverity Scan #1357450, #1357449 --- src/soc/intel/apollolake/i2c_early.c | 2 +- src/soc/intel/skylake/i2c.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/i2c_early.c b/src/soc/intel/apollolake/i2c_early.c index 968e993..82883f8 100644 --- a/src/soc/intel/apollolake/i2c_early.c +++ b/src/soc/intel/apollolake/i2c_early.c @@ -32,7 +32,7 @@ static int i2c_early_init_bus(unsigned bus) const struct lpss_i2c_speed_config *sptr; enum i2c_speed speed; pci_devfn_t dev; - unsigned devfn; + int devfn; uintptr_t base; uint32_t value; void *reg; diff --git a/src/soc/intel/skylake/i2c.c b/src/soc/intel/skylake/i2c.c index eebe665..d37c290 100644 --- a/src/soc/intel/skylake/i2c.c +++ b/src/soc/intel/skylake/i2c.c @@ -24,7 +24,7 @@ uintptr_t lpss_i2c_base_address(unsigned bus) { - unsigned devfn; + int devfn; struct device *dev; struct resource *res;

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Patch merged into coreboot/master: arch/riscv: In trap handler, don't print SP twice
by gerrit＠coreboot.org 18 Oct '16

18 Oct '16

the following patch was just integrated into master: commit 0bc12abc2b26c0b4098ac76a6d42219b359c7a22 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Oct 12 00:18:02 2016 +0200 arch/riscv: In trap handler, don't print SP twice The stack pointer (SP) is already printed in print_trap_information. Don't print it again in handle_misaligned_{load,store}. Change-Id: I156cf5734a16605decc2280e54e6db3089e094a2 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-on: https://review.coreboot.org/16996 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/16996 for details. -gerrit

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Patch merged into coreboot/master: Revert "[WIP] console/Kconfig: Calculate COM port base addresses only on x86"
by gerrit＠coreboot.org 18 Oct '16

18 Oct '16

the following patch was just integrated into master: commit 96aff03dcd3a60a0c85abf92d2a8578f05600606 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Sat Oct 15 00:33:13 2016 +0200 Revert "[WIP] console/Kconfig: Calculate COM port base addresses only on x86" This reverts commit 2c8f3bd91b54e85b4d2e24894ee8bbbfb9ad8a31. I mistakenly commited a WIP, sorry. Change-Id: I3c66c688dbfd903ecf5303abcdf6b5ded84585c7 Reviewed-on: https://review.coreboot.org/17028 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Nico Huber <nico.h(a)gmx.de> See https://review.coreboot.org/17028 for details. -gerrit

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Patch merged into coreboot/master: northbridge/via/vx800: Convert 'for (; ; )' to 'die'
by gerrit＠coreboot.org 18 Oct '16

18 Oct '16

the following patch was just integrated into master: commit b05eee46c35487dc694edb5b4d0d070a8d29f915 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Tue Oct 11 19:05:56 2016 +0200 northbridge/via/vx800: Convert 'for (;;)' to 'die' Change-Id: I3f99190401d8df1415328da9c3b928194593901c Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/16989 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/16989 for details. -gerrit

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Patch set updated for coreboot: mainboard/google/reef: add snappy variant
by Wisley Chen 18 Oct '16

18 Oct '16

Wisley Chen (wisley.chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17043 -gerrit commit bb35dcb0a95975ace58ebec37a270861dd7108b9 Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Mon Oct 17 18:30:54 2016 +0800 mainboard/google/reef: add snappy variant Create the initial Snappy variant which refers to the Reef device. Snappy, an Apollolake-platform, is deviated from reference board Reef. BRANCH=master BUG=None TEST=Built & booted Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6 --- src/mainboard/google/reef/Kconfig | 4 + src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/snappy/devicetree.cb | 173 +++++++++++++++++++++ .../variants/snappy/include/variant/acpi/dptf.asl | 89 +++++++++++ .../reef/variants/snappy/include/variant/ec.h | 21 +++ .../reef/variants/snappy/include/variant/gpio.h | 21 +++ 6 files changed, 313 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 19b1bd1..d5d64c8 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -51,16 +51,19 @@ config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF default "pyro" if BOARD_GOOGLE_PYRO + default "snappy" if BOARD_GOOGLE_SNAPPY config DEVICETREE string default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO + default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY default "variants/baseboard/devicetree.cb" config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF default "Pyro" if BOARD_GOOGLE_PYRO + default "Snappy" if BOARD_GOOGLE_SNAPPY config MAINBOARD_FAMILY string @@ -71,6 +74,7 @@ config GBB_HWID depends on CHROMEOS default "REEF TEST 3240" if BOARD_GOOGLE_REEF default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO + default "SNAPPY TEST 1088" if BOARD_GOOGLE_SNAPPY config MAX_CPUS int diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index d73e69b..63e6ada 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -7,3 +7,8 @@ config BOARD_GOOGLE_PYRO bool "Pyro" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_SNAPPY + bool "Snappy" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb new file mode 100644 index 0000000..43ec2ed --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -0,0 +1,173 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..43e2e93 --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 100 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/ec.h b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h new file mode 100644 index 0000000..586f106 --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h new file mode 100644 index 0000000..6d1ce5a --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */

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Patch set updated for coreboot: mainboard/google/reef: add snappy variant
by Wisley Chen 18 Oct '16

18 Oct '16

Wisley Chen (wisley.chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17043 -gerrit commit c38de8c5d9fdc051c5ac0afa610962af1915c3df Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Mon Oct 17 18:30:54 2016 +0800 mainboard/google/reef: add snappy variant Create the initial Snappy variant which refers to the Reef device. Snappy, an Apollolake-platform, is deviated from reference board Reef. BRANCH=master BUG=None TEST=Built & booted Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6 --- src/mainboard/google/reef/Kconfig | 4 + src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/snappy/devicetree.cb | 173 +++++++++++++++++++++ .../variants/snappy/include/variant/acpi/dptf.asl | 89 +++++++++++ .../reef/variants/snappy/include/variant/ec.h | 21 +++ .../reef/variants/snappy/include/variant/gpio.h | 21 +++ 6 files changed, 313 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 19b1bd1..d5d64c8 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -51,16 +51,19 @@ config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF default "pyro" if BOARD_GOOGLE_PYRO + default "snappy" if BOARD_GOOGLE_SNAPPY config DEVICETREE string default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO + default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY default "variants/baseboard/devicetree.cb" config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF default "Pyro" if BOARD_GOOGLE_PYRO + default "Snappy" if BOARD_GOOGLE_SNAPPY config MAINBOARD_FAMILY string @@ -71,6 +74,7 @@ config GBB_HWID depends on CHROMEOS default "REEF TEST 3240" if BOARD_GOOGLE_REEF default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO + default "SNAPPY TEST 1088" if BOARD_GOOGLE_SNAPPY config MAX_CPUS int diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index d73e69b..63e6ada 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -7,3 +7,8 @@ config BOARD_GOOGLE_PYRO bool "Pyro" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_SNAPPY + bool "Snappy" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb new file mode 100644 index 0000000..43ec2ed --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -0,0 +1,173 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..43e2e93 --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 100 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/ec.h b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h new file mode 100644 index 0000000..586f106 --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h new file mode 100644 index 0000000..6d1ce5a --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */

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Patch set updated for coreboot: mainboard/google/reef: add snappy variant
by Wisley 18 Oct '16

18 Oct '16

Wisley (wisley.chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17043 -gerrit commit 2d9811bc1623d81ec2973168f38a3d51b64cd2ee Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Mon Oct 17 18:30:54 2016 +0800 mainboard/google/reef: add snappy variant Create the initial Snappy variant which refers to the Reef device. Snappy, an Apollolake-platform, is deviated from reference board Reef. BRANCH=master BUG=None TEST=Built & booted Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6 --- src/mainboard/google/reef/Kconfig | 4 + src/mainboard/google/reef/Kconfig.name | 5 + .../google/reef/variants/snappy/devicetree.cb | 173 +++++++++++++++++++++ .../variants/snappy/include/variant/acpi/dptf.asl | 89 +++++++++++ .../reef/variants/snappy/include/variant/ec.h | 21 +++ .../reef/variants/snappy/include/variant/gpio.h | 21 +++ 6 files changed, 313 insertions(+) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index 19b1bd1..d5d64c8 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -51,16 +51,19 @@ config VARIANT_DIR string default "reef" if BOARD_GOOGLE_REEF default "pyro" if BOARD_GOOGLE_PYRO + default "snappy" if BOARD_GOOGLE_SNAPPY config DEVICETREE string default "variants/pyro/devicetree.cb" if BOARD_GOOGLE_PYRO + default "variants/snappy/devicetree.cb" if BOARD_GOOGLE_SNAPPY default "variants/baseboard/devicetree.cb" config MAINBOARD_PART_NUMBER string default "Reef" if BOARD_GOOGLE_REEF default "Pyro" if BOARD_GOOGLE_PYRO + default "Snappy" if BOARD_GOOGLE_SNAPPY config MAINBOARD_FAMILY string @@ -71,6 +74,7 @@ config GBB_HWID depends on CHROMEOS default "REEF TEST 3240" if BOARD_GOOGLE_REEF default "PYRO TEST 0290" if BOARD_GOOGLE_PYRO + default "SNAPPY TEST 1088" if BOARD_GOOGLE_SNAPPY config MAX_CPUS int diff --git a/src/mainboard/google/reef/Kconfig.name b/src/mainboard/google/reef/Kconfig.name index d73e69b..63e6ada 100644 --- a/src/mainboard/google/reef/Kconfig.name +++ b/src/mainboard/google/reef/Kconfig.name @@ -7,3 +7,8 @@ config BOARD_GOOGLE_PYRO bool "Pyro" select BOARD_GOOGLE_BASEBOARD_REEF select BASEBOARD_REEF_LAPTOP + +config BOARD_GOOGLE_SNAPPY + bool "Snappy" + select BOARD_GOOGLE_BASEBOARD_REEF + select BASEBOARD_REEF_LAPTOP diff --git a/src/mainboard/google/reef/variants/snappy/devicetree.cb b/src/mainboard/google/reef/variants/snappy/devicetree.cb new file mode 100644 index 0000000..43ec2ed --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/devicetree.cb @@ -0,0 +1,173 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C2 bus early for TPM access + register "i2c[2].early_init" = "1" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl new file mode 100644 index 0000000..43e2e93 --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl @@ -0,0 +1,89 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 80 +#define DPTF_CPU_ACTIVE_AC2 70 +#define DPTF_CPU_ACTIVE_AC3 60 +#define DPTF_CPU_ACTIVE_AC4 50 + +#define DPTF_TSR0_SENSOR_ID 0 +#define DPTF_TSR0_SENSOR_NAME "Battery" +#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_CRITICAL 70 + +#define DPTF_TSR1_SENSOR_ID 1 +#define DPTF_TSR1_SENSOR_NAME "Ambient" +#define DPTF_TSR1_PASSIVE 60 +#define DPTF_TSR1_CRITICAL 70 + +#define DPTF_TSR2_SENSOR_ID 2 +#define DPTF_TSR2_SENSOR_NAME "Charger" +#define DPTF_TSR2_PASSIVE 55 +#define DPTF_TSR2_CRITICAL 100 + +#define DPTF_ENABLE_CHARGER + +/* Charger performance states, board-specific values from charger and EC */ +Name (CHPS, Package () { + Package () { 0, 0, 0, 0, 255, 0xBB8, "mA", 0 }, /* 3A (MAX) */ + Package () { 0, 0, 0, 0, 24, 0x600, "mA", 0 }, /* 1.5A */ + Package () { 0, 0, 0, 0, 16, 0x400, "mA", 0 }, /* 1.0A */ + Package () { 0, 0, 0, 0, 8, 0x200, "mA", 0 }, /* 0.5A */ + Package () { 0, 0, 0, 0, 0, 0x000, "mA", 0 }, /* 0.0A */ +}) + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 50, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 0 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR0, 100, 600, 0, 0, 0, 0 }, + +#ifdef DPTF_ENABLE_CHARGER + /* Charger Effect on Temp Sensor 1 */ + Package () { \_SB.DPTF.TCHG, \_SB.DPTF.TSR1, 200, 600, 0, 0, 0, 0 }, +#endif + + /* CPU Effect on Temp Sensor 1 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 600, 0, 0, 0, 0 }, + + /* CPU Effect on Temp Sensor 2 */ + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 600, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 1600, /* PowerLimitMinimum */ + 12000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 6000, /* PowerLimitMinimum */ + 8000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/ec.h b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h new file mode 100644 index 0000000..586f106 --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/include/variant/ec.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include <baseboard/ec.h> + +#endif diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h new file mode 100644 index 0000000..6d1ce5a --- /dev/null +++ b/src/mainboard/google/reef/variants/snappy/include/variant/gpio.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include <baseboard/gpio.h> + +#endif /* MAINBOARD_GPIO_H */

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New patch to review for coreboot: kunimitsu: Add choice to select FSP driver
by Naresh Solanki 17 Oct '16

17 Oct '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17051 -gerrit commit 31eb2a865a89de5cea8f0e7baf4b4b984556f4dd Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Oct 18 07:19:36 2016 +0530 kunimitsu: Add choice to select FSP driver Add choice to select between FSP 1.1 & FSP2.0 driver to be used. Change-Id: Ied7eab6f4a2191e0bcf220cde5ca519a3c3e2d76 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/intel/kunimitsu/Kconfig | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/mainboard/intel/kunimitsu/Kconfig b/src/mainboard/intel/kunimitsu/Kconfig index 67143ca..9bc607e 100644 --- a/src/mainboard/intel/kunimitsu/Kconfig +++ b/src/mainboard/intel/kunimitsu/Kconfig @@ -19,6 +19,19 @@ config BOARD_SPECIFIC_OPTIONS # dummy select MONOTONIC_TIMER_MSR select SOC_INTEL_SKYLAKE +choice + prompt "FSP driver" + default KUNIMITSU_USES_FSP1_1 + +config KUNIMITSU_USES_FSP1_1 + bool "FSP driver 1.1" + +config KUNIMITSU_USES_FSP2_0 + bool "FSP driver 2.0" + select MAINBOARD_USES_FSP2_0 + +endchoice + config CHROMEOS select LID_SWITCH

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Patch set updated for coreboot: soc/intel/skylake: Allow selecting FSP driver in Kconfig
by Naresh Solanki 17 Oct '16

17 Oct '16

Naresh Solanki (naresh.solanki(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17044 -gerrit commit 4bcdd8e33a6c0869c0bc9a2267918fbc10bed620 Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Mon Oct 17 17:21:08 2016 +0530 soc/intel/skylake: Allow selecting FSP driver in Kconfig Enable mainboard Kconfig to select between FSP 2.0 & 1.1 driver to be used. If mainboard Kconfig selects MAINBOARD_USES_FSP2_0 the FSP2_0 driver is used else FSP1_1. Change-Id: I724aaa87c2b0b8f6ddb18f61af9c37176ef632f2 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 3c843f5..5a1d878 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -52,24 +52,26 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_MFENCE select UDELAY_TSC -choice - prompt "FSP Driver" - default USE_FSP1_1_DRIVER +config MAINBOARD_USES_FSP2_0 + bool + default n config USE_FSP2_0_DRIVER bool "Build with FSP 2.0" + depends on MAINBOARD_USES_FSP2_0 + default y if MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP2_0 select ADD_VBT_DATA_FILE select SOC_INTEL_COMMON_GFX_OPREGION config USE_FSP1_1_DRIVER bool "Build with FSP 1.1" + depends on !MAINBOARD_USES_FSP2_0 + default y if !MAINBOARD_USES_FSP2_0 select PLATFORM_USES_FSP1_1 select GOP_SUPPORT select DISPLAY_FSP_ENTRY_POINTS -endchoice - config CHROMEOS select CHROMEOS_RAMOOPS_DYNAMIC select EC_SOFTWARE_SYNC if EC_GOOGLE_CHROMEEC

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Patch merged into coreboot/master: mainboard/google/reef: Configure PERST pin for reef DVT
by gerrit＠coreboot.org 17 Oct '16

17 Oct '16

the following patch was just integrated into master: commit 1ac773fa55195b1fd39eeb5ed83b302b04151c58 Author: Vaibhav Shankar <vaibhav.shankar(a)intel.com> Date: Fri Oct 14 16:08:32 2016 -0700 mainboard/google/reef: Configure PERST pin for reef DVT Configure GPIO 122 as PERST on DVT. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:55877 TEST=S0ix functional on DVT Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri(a)intel.com> Change-Id: Iab18b2de621a1a9226c78493f6defa15081db875 Reviewed-on: https://review.coreboot.org/17030 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17030 for details. -gerrit

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coreboot-gerrit October 2016