coreboot-gerrit October 2016

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Patch set updated for coreboot: util/crossgcc: Implement buildgcc script checksum verification
by Philipp Deppenwiese 20 Oct '16

20 Oct '16

Philipp Deppenwiese (zaolin.daisuki(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/15170 -gerrit commit 2e45ad48108929a11cc99ffde26389929b70c6e6 Author: Philipp Deppenwiese <zaolin(a)das-labor.org> Date: Mon Jun 13 17:01:07 2016 -0700 util/crossgcc: Implement buildgcc script checksum verification In order to build a secure toolchain https and checksum verification should be used for the sources. The hash alogrithm has changed from SHA1 to SHA384 for security reasons. Add gpg verification for file hash upgrades by developers. DO NOT MERGE! JUST REVIEW! SOME CHECKSUMS ARE MISSING.. Change-Id: Id45097fc7e8435fadce4bda75769592af2730b0c Signed-off-by: Philipp Deppenwiese <zaolin(a)das-labor.org> --- util/crossgcc/buildgcc | 205 ++++++++++++++++----- util/crossgcc/gpg.keyring | Bin 0 -> 222182 bytes util/crossgcc/sum/Python-3.5.1.tar.xz.cksum | 1 - .../sum/acpica-unix2-20160318.tar.gz.cksum | 1 - util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum | 2 +- .../sum/clang-tools-extra-3.8.0.src.tar.xz.cksum | 2 +- .../sum/compiler-rt-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum | 1 - util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum | 2 +- util/crossgcc/sum/gdb-7.11.tar.xz.cksum | 2 +- util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum | 2 +- util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum | 1 - util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum | 2 +- util/crossgcc/sum/make-4.1.tar.bz2.cksum | 2 +- util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum | 2 +- util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum | 2 +- util/lint/lint-stable-003-whitespace | 2 +- 18 files changed, 175 insertions(+), 58 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index da3f0f2..2267f14 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -6,6 +6,8 @@ # # Copyright (C) 2011 by Sage Electronic Engineering # +# Copyright (C) 2016 by Philipp Deppenwiese +# # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; version 2 of the License. @@ -18,8 +20,8 @@ cd $(dirname $0) -CROSSGCC_DATE="July 14th, 2016" -CROSSGCC_VERSION="1.41" +CROSSGCC_DATE="October 20th, 2016" +CROSSGCC_VERSION="1.50" CROSSGCC_COMMIT=$( git describe ) # default settings @@ -31,6 +33,7 @@ DESTDIR= SAVETEMPS=0 SKIPPYTHON=1 BOOTSTRAP=0 +GENERATE_CHECKSUMS=0 # GCC toolchain version numbers GMP_VERSION=6.1.0 @@ -48,26 +51,28 @@ EXPAT_VERSION=2.1.1 CLANG_VERSION=3.8.0 MAKE_VERSION=4.1 +GPG_KEYRING=$(pwd)/gpg.keyring + # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if # a completely new URL is added here, it probably needs to be added # to the jenkins build as well, or the builder won't download it. -GMP_ARCHIVE="http://ftpmirror.gnu.org/gmp/gmp-${GMP_VERSION}.tar.xz" -MPFR_ARCHIVE="http://ftpmirror.gnu.org/mpfr/mpfr-${MPFR_VERSION}.tar.xz" -MPC_ARCHIVE="http://ftpmirror.gnu.org/mpc/mpc-${MPC_VERSION}.tar.gz" +GMP_ARCHIVE="https://ftp.gnu.org/gnu/gmp/gmp-${GMP_VERSION}.tar.xz" +MPFR_ARCHIVE="https://ftp.gnu.org/gnu/mpfr/mpfr-${MPFR_VERSION}.tar.xz" +MPC_ARCHIVE="https://ftp.gnu.org/gnu/mpc/mpc-${MPC_VERSION}.tar.gz" LIBELF_ARCHIVE="http://www.mr511.de/software/libelf-${LIBELF_VERSION}.tar.gz" -GCC_ARCHIVE="http://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2" -BINUTILS_ARCHIVE="http://ftpmirror.gnu.org/binutils/binutils-${BINUTILS_VERSION}.tar.bz2" -GDB_ARCHIVE="http://ftpmirror.gnu.org/gdb/gdb-${GDB_VERSION}.tar.xz" +GCC_ARCHIVE="https://ftp.gnu.org/gnu/gcc/gcc-${GCC_VERSION}/gcc-${GCC_VERSION}.tar.bz2" +BINUTILS_ARCHIVE="https://ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.bz2" +GDB_ARCHIVE="https://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.xz" IASL_ARCHIVE="https://acpica.org/sites/acpica/files/acpica-unix2-${IASL_VERSION}.tar.gz" -PYTHON_ARCHIVE="http://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION}…" -EXPAT_ARCHIVE="http://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.t…" +PYTHON_ARCHIVE="https://www.python.org/ftp/python/${PYTHON_VERSION}/Python-${PYTHON_VERSION…" +EXPAT_ARCHIVE="https://downloads.sourceforge.net/sourceforge/expat/expat-${EXPAT_VERSION}.…" # CLANG toolchain archive locations LLVM_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/llvm-${CLANG_VERSION}.src.tar.xz" CFE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/cfe-${CLANG_VERSION}.src.tar.xz" CRT_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/compiler-rt-${CLANG_VERSION}.src.…" CTE_ARCHIVE="http://llvm.org/releases/${CLANG_VERSION}/clang-tools-extra-${CLANG_VERSION…" -MAKE_ARCHIVE="http://ftpmirror.gnu.org/make/make-${MAKE_VERSION}.tar.bz2" +MAKE_ARCHIVE="https://ftp.gnu.org/gnu/make/make-${MAKE_VERSION}.tar.bz2" ALL_ARCHIVES="$GMP_ARCHIVE $MPFR_ARCHIVE $MPC_ARCHIVE $LIBELF_ARCHIVE \ $GCC_ARCHIVE $BINUTILS_ARCHIVE $GDB_ARCHIVE $IASL_ARCHIVE \ @@ -102,6 +107,8 @@ blue='\033[0;34m' BLUE='\033[1;34m' cyan='\033[0;36m' CYAN='\033[1;36m' +yellow='\033[0;93m' +YELLOW='\033[1;93m' NC='\033[0m' # No Color UNAME=$(uname | grep -iq cygwin && echo Cygwin || uname) @@ -203,50 +210,146 @@ check_for_library() { rm -rf "${LIBTEST_FILE}.c" "${LIBTEST_FILE}" } -check_sum() { - test -z "$CHECKSUM" || \ - test "$(cat sum/$1.cksum 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" = \ - "$($CHECKSUM tarballs/$1 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@')" +verify_signature() { + local SIGNATURE_FILE="$1" + local SOURCE_FILE="$2" + + if [ -z "${GPG}" ] ; then + printf "\n${RED}GPG tool not found.${NC}\n" + return 1 + fi + + if [ ! -f "${GPG_KEYRING}" ] ; then + printf "\n${RED}The gpg keyring can't be found not found.${NC}\n" + return 1 + fi + + if [ ! -f "tarballs/${SIGNATURE_FILE}" ] ; then + printf "\n * ${RED}No signature file found for package: ${SOURCE_FILE} !! PLEASE CHECK MANUALLY WHAT YOU DOWNLOADED, ABORTING CHECKSUM CREATION.${NC}\n" + return 1 + fi + + if [ ! -f "tarballs/${SOURCE_FILE}" ] ; then + printf "\n${RED}Source file couldn't be downloaded.${NC}\n" + return 1 + fi + + GPG_OUTPUT=$(${GPG} --no-default-keyring --keyring ${GPG_KEYRING} --status-fd 1 --verify "tarballs/${SIGNATURE_FILE}" "tarballs/${SOURCE_FILE}" 2>&1) + if [ "${?}" == "0" ] ; then + printf "\n * ${GREEN}Signature is good and verified!${NC}" + return 0 + fi + + printf "\n${RED}Failed to verify signature of package.${NC}\n" + printf "\n${RED}Error: ${GPG_OUTPUT} ${NC}\n" + return 1 } -compute_sum() { - test ! -f sum/$1.cksum && test -f tarballs/$1 && \ - (test -z "$CHECKSUM" || $CHECKSUM tarballs/$1 > sum/$1.cksum ) && \ - printf "(checksum created. ${RED}Note. Please upload sum/$1.cksum if the corresponding archive is upgraded.)${NC}" +calculate_checksum() { + local SOURCE_FILE=$1 + + test ! -f sum/$SOURCE_FILE.cksum && test -f tarballs/$SOURCE_FILE && \ + (test -z "$CHECKSUM" || $CHECKSUM tarballs/$SOURCE_FILE > sum/$SOURCE_FILE.cksum ) && \ + printf "\n * Checksum created. ${CYAN}Note. Please upload sum/$SOURCE_FILE.cksum if the corresponding archive is upgraded.${NC}" +} + +verify_checksum() { + local STATIC_HASH=$(cat sum/$1.cksum 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@') + local FILE_HASH=$($CHECKSUM tarballs/$1 2>/dev/null | sed -e 's@.*$[0-9a-f]\{40,\}$.*@\1@') + + if [ "${STATIC_HASH}" != "${FILE_HASH}" ] ; then + printf "\n${RED}Failed to verify checksum of package ${1}.${NC}\n" + exit 1 + fi + + printf "\n * ${GREEN}Checksum 0x${FILE_HASH} verified.${NC}\n" +} + +validate_url() { + if [ `wget -S --spider $1 2>&1 | grep 'HTTP/1.1 200 OK'` ]; then return 1; else return 0; fi } download_showing_percentage() { - url=$1 - printf " ..${red} 0%%" - wget --no-check-certificate $url 2>&1 | while read line; do - printf "${red}" - echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' - printf "${NC}" - done + local NO_WARNING="$2" + local URL=$1 + printf " ..${YELLOW} 0%%${NC}" + + validate_url ${URL} + if [ "${?}" == "1" ] ; then + wget ${URL} 2>&1 | while read line; do + printf "${YELLOW}" + echo $line | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' + printf "${NC}" + done + elif [ -z "$NO_WARNING" ]; then + printf "\n${RED} %s is not valid.${NC}\n", "${URL}" + fi } download() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" + signature="${archive}.sig" - FILE=$(basename $archive) - printf " * $FILE " + local SOURCE_FILE=$(basename ${archive}) + local SIGNATURE_FILE=$(basename ${signature}) - if test -f tarballs/$FILE && check_sum $FILE ; then + if test -f tarballs/${SOURCE_FILE} ; then printf "(cached)" else - printf "(downloading from $archive)" - rm -f tarballs/$FILE + rm -f tarballs/${SOURCE_FILE}* cd tarballs - download_showing_percentage $archive + + printf " * ${SOURCE_FILE} " + printf "(downloading from $archive)" + download_showing_percentage ${archive} 1 + cd .. - compute_sum $FILE fi - if [ ! -f tarballs/$FILE ]; then - printf "\n${RED}Failed to download $FILE.${NC}\n" + if [ ! -f tarballs/${SOURCE_FILE} ]; then + printf "\n${RED}Failed to download ${SOURCE_FILE}.${NC}\n" exit 1 fi + + verify_checksum ${SOURCE_FILE} ${archive} + printf "\n" +} + +generate_checksums() { + package=$1 + archive="$(eval echo \$$package"_ARCHIVE")" + signature="${archive}.sig" + local SOURCE_FILE=$(basename ${archive}) + local SIGNATURE_FILE=$(basename ${signature}) + + rm -f tarballs/${SOURCE_FILE}* + rm -f sum/${SOURCE_FILE}.cksum* + cd tarballs + + printf " * ${SOURCE_FILE} " + printf "(downloading from $archive)" + download_showing_percentage ${archive} 1 + + printf "\n" + + printf " * ${SOURCE_FILE} " + printf "(downloading signature file of $archive)" + download_showing_percentage ${signature} 1 + + cd .. + + verify_signature ${SIGNATURE_FILE} ${SOURCE_FILE} + if [ "${?}" == "0" ] ; then + calculate_checksum ${SOURCE_FILE} + verify_checksum ${SOURCE_FILE} ${archive} + fi + + if [ ! -f tarballs/${SOURCE_FILE} ]; then + printf "\n${RED}Failed to download ${SOURCE_FILE}.${NC}\n" + exit 1 + fi + printf "\n" } @@ -254,6 +357,10 @@ unpack_and_patch() { package=$1 archive="$(eval echo \$$package"_ARCHIVE")" dir="$(eval echo \$$package"_DIR")" + FILE="$(basename $archive)" + + verify_checksum ${FILE} ${archive} + test -d ${dir} && test -f ${dir}/.unpack_success || ( printf " * $(basename $archive)\n" FLAGS=zxf @@ -368,7 +475,7 @@ cleanup() myhelp() { - printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S]\n" + printf "Usage: $0 [-V] [-c] [-p <platform>] [-d <target directory>] [-D <dest dir>] [-C] [-G] [-S] [-g]\n" printf " $0 [-V|--version]\n" printf " $0 [-h|--help]\n\n" @@ -398,7 +505,9 @@ myhelp() printf "GDB specific options:\n" printf " [-p|--platform <platform>] target platform to build cross compiler for\n" printf " (defaults to $TARGETARCH)\n" - printf " [-S|--scripting] build scripting support for GDB\n\n" + printf " [-S|--scripting] build scripting support for GDB\n" + printf " [-g|--generate-checksums] re-generates the checksum for all packages and\n" + printf " verifies them with the help of gpg signatures\n\n" printf "Platforms for GCC & GDB:\n" printf " x86_64 i386-elf i386-mingw32 mipsel-elf riscv-elf arm aarch64\n" printf " powerpc64le-linux-gnu nds32le-elf\n\n" @@ -415,6 +524,7 @@ myversion() cat << EOF Copyright (C) 2008-2010 by coresystems GmbH Copyright (C) 2011 by Sage Electronic Engineering +Copyright (C) 2016 by Philipp Deppenwiese This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by @@ -682,7 +792,7 @@ getopt - > /dev/null 2>/dev/null || gcc -o getopt getopt.c getoptbrand="$(getopt -V | sed -e '1!d' -e 's,^$......$.*,\1,')" if [ "${getoptbrand}" = "getopt" ]; then # Detected GNU getopt that supports long options. - args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported: Vhcd:bp:l:P:j:D:tSys: -- "$@") + args=$(getopt -l version,help,clean,directory:,bootstrap,platform:,languages:,package:,jobs:,destdir:,savetemps,scripting,ccache,supported:generate_checksums: Vhcd:bp:l:P:j:D:tSys:g: -- "$@") eval set "$args" else # Detected non-GNU getopt @@ -711,9 +821,10 @@ while true ; do -S|--scripting) shift; SKIPPYTHON=0;; -y|--ccache) shift; USECCACHE=1;; -s|--supported) shift; PRINTSTABLE="$1"; shift;; + -g|--generate-checksums) shift; GENERATE_CHECKSUMS=1;; --urls) shift; printf "%s\n" "$ALL_ARCHIVES"; exit 0;; --nocolor) shift; \ - unset red RED green GREEN blue BLUE cyan CYAN NC;; + unset red RED green GREEN blue BLUE cyan CYAN yellow YELLOW NC;; --) shift; break;; -*) printf "Invalid option\n\n"; myhelp; exit 1;; *) break;; @@ -783,11 +894,11 @@ esac TAR=$(searchtool tar) || exit $? PATCH=$(searchtool patch) || exit $? MAKE=$(searchtool make) || exit $? -SHA1SUM=$(searchtool sha1sum) -SHA512SUM=$(searchtool sha512sum) -CHECKSUM=$SHA1SUM +SHA384SUM=$(searchtool sha384sum) +CHECKSUM=$SHA384SUM LBZIP2=$(searchtool lbzip2 "" nofail) PIGZ=$(searchtool pigz "" nofail) +GPG=$(searchtool gpg "GnuPG" nofail) searchtool m4 > /dev/null searchtool bison > /dev/null @@ -865,6 +976,16 @@ export PATH=$DESTDIR$TARGETDIR/bin:$PATH # Download, unpack, patch and build all packages +if [ "$GENERATE_CHECKSUMS" = 1 ]; then + mkdir -p tarballs + PACKAGES="GMP MPFR MPC LIBELF GCC BINUTILS GDB IASL PYTHON EXPAT LLVM CFE CRT CTE MAKE" + for P in $PACKAGES; do + generate_checksums $P + done + + exit 0 +fi + printf "Downloading tarballs ... \n" mkdir -p tarballs for P in $PACKAGES; do diff --git a/util/crossgcc/gpg.keyring b/util/crossgcc/gpg.keyring new file mode 100644 index 0000000..8cbce7e Binary files /dev/null and b/util/crossgcc/gpg.keyring differ diff --git a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum b/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum deleted file mode 100644 index 58affb0..0000000 --- a/util/crossgcc/sum/Python-3.5.1.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -0186da436db76776196612b98bb9c2f76acfe90e tarballs/Python-3.5.1.tar.xz diff --git a/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum deleted file mode 100644 index 2f9b331..0000000 --- a/util/crossgcc/sum/acpica-unix2-20160318.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -786811c1501b9cc90c988293a1c3afefa33b60cc tarballs/acpica-unix2-20160318.tar.gz diff --git a/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum b/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum index 4bd0bce..85535bb 100644 --- a/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum +++ b/util/crossgcc/sum/binutils-2.26.1.tar.bz2.cksum @@ -1 +1 @@ -624cd377e3a8eef3db83a56ce289a60f556b3ec2 tarballs/binutils-2.26.1.tar.bz2 +30cc8be8c230d69b966b80268223b823b3d301c83472317a4b6ff3aa9dd528a31cb1af33640097854e0e34743b1339b7 tarballs/binutils-2.26.1.tar.bz2 diff --git a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum index 7ba8c8c..b278aac 100644 --- a/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/cfe-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -2230ef962f2df3c13ec93f5b04b0e3cdff94b2ce tarballs/cfe-3.8.0.src.tar.xz +3edbe3cafc58ad6fc3d3a133156a656ea7756e8a36176b29bba63434d6f073cef63241cc6df8337fcab3832dd5b5c485 tarballs/cfe-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum index e9d8d72..dd5c566 100644 --- a/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/clang-tools-extra-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -a99d8b6fc5e593c4671424b327779318a1856acf tarballs/clang-tools-extra-3.8.0.src.tar.xz +abd447239f09295f8592225bb7e07ba57cedc3d19a4972b45cd7d70a2db82106d1874a5be03656f8209a0e8a1308fb31 tarballs/clang-tools-extra-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum index 081705d..9239365 100644 --- a/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/compiler-rt-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -480ea09e369dac6de1f3759b27fa19417b26b69e tarballs/compiler-rt-3.8.0.src.tar.xz +4560d512f3c3a0dbcc5c29ab7754b07d91ffa1ddc1c06a5215f3d325bc3f138ebf483e2a37abb10fc36cd125e6bf559e tarballs/compiler-rt-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum b/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum deleted file mode 100644 index 882e501..0000000 --- a/util/crossgcc/sum/expat-2.1.1.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -ff91419882ac52151050dad0ee8190645fbeee08 tarballs/expat-2.1.1.tar.bz2 diff --git a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum index bb05e39..2b81f5e 100644 --- a/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum +++ b/util/crossgcc/sum/gcc-5.3.0.tar.bz2.cksum @@ -1 +1 @@ -0612270b103941da08376df4d0ef4e5662a2e9eb tarballs/gcc-5.3.0.tar.bz2 +4184972f66dc929686c30936cf8f5085829d8584118ebc3e2ec53a40754afbefc351cfd2c211c09dd3b6eb4ab4759820 tarballs/gcc-5.3.0.tar.bz2 diff --git a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum index ffe5a1c..9cc5d91 100644 --- a/util/crossgcc/sum/gdb-7.11.tar.xz.cksum +++ b/util/crossgcc/sum/gdb-7.11.tar.xz.cksum @@ -1 +1 @@ -466208d771d97d3dfcf965d5c835a669cff8d847 tarballs/gdb-7.11.tar.xz +82f89ef35ea1916d5faa67b7fefa2ac3627894d245c43fb4e20828274566cbbb5d7f83899baad77a3cf7fe9fec6f8c7b tarballs/gdb-7.11.tar.xz diff --git a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum index 348b80f..7e00489 100644 --- a/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum +++ b/util/crossgcc/sum/gmp-6.1.0.tar.xz.cksum @@ -1 +1 @@ -99d691607613e749aa5d7c0c2a89aeab38fec070 tarballs/gmp-6.1.0.tar.xz +ec69b394cbcf887ab0717473b04bb70ce30102abf24869eca5acb781de405d3a5670fabb776ba68cfe6e117631522d9f tarballs/gmp-6.1.0.tar.xz diff --git a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum b/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum deleted file mode 100644 index daa27c6..0000000 --- a/util/crossgcc/sum/libelf-0.8.13.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -c1d6ac5f182d19dd685c4dfd74eedbfe3992425d tarballs/libelf-0.8.13.tar.gz diff --git a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum index 2f0af53..547ad8f 100644 --- a/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum +++ b/util/crossgcc/sum/llvm-3.8.0.src.tar.xz.cksum @@ -1 +1 @@ -723ac918979255706434a05f5af34b71c49c9971 tarballs/llvm-3.8.0.src.tar.xz +5d5a012e4d494a4534fcec7643ad28bab7467b96029b6d497e1d523357ae7c9e8bd86400dc90e261d791d6391a369b30 tarballs/llvm-3.8.0.src.tar.xz diff --git a/util/crossgcc/sum/make-4.1.tar.bz2.cksum b/util/crossgcc/sum/make-4.1.tar.bz2.cksum index 02807c6..455d779 100644 --- a/util/crossgcc/sum/make-4.1.tar.bz2.cksum +++ b/util/crossgcc/sum/make-4.1.tar.bz2.cksum @@ -1 +1 @@ -0d701882fd6fd61a9652cb8d866ad7fc7de54d58 tarballs/make-4.1.tar.bz2 +8a3adbc49c19db130bfd3c2b7df061d9419b77019d21d23765cf1c961bc6a35d611dbda4241316e98cecc09adccecd90 tarballs/make-4.1.tar.bz2 diff --git a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum index c7ca1ac..70ee62f 100644 --- a/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum +++ b/util/crossgcc/sum/mpc-1.0.3.tar.gz.cksum @@ -1 +1 @@ -b8be66396c726fdc36ebb0f692ed8a8cca3bcc66 tarballs/mpc-1.0.3.tar.gz +dceeb2566d6145fa771641d22de3bef866fa601fe1fa964bc680a275919080bd12bc1abab4f68cecdbaef71d295b7397 tarballs/mpc-1.0.3.tar.gz diff --git a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum index 90f90eb..54cd485 100644 --- a/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum +++ b/util/crossgcc/sum/mpfr-3.1.4.tar.xz.cksum @@ -1 +1 @@ -cedc0055d55b6ee4cd17e1e6119ed412520ff81a tarballs/mpfr-3.1.4.tar.xz +30a2807378f578544538810b24bb65d44268015e5d2390d8ae6383fe3939b3bba1e85279789400a226b365010de4bbcd tarballs/mpfr-3.1.4.tar.xz diff --git a/util/lint/lint-stable-003-whitespace b/util/lint/lint-stable-003-whitespace index 3dbd473..144cda1 100755 --- a/util/lint/lint-stable-003-whitespace +++ b/util/lint/lint-stable-003-whitespace @@ -15,5 +15,5 @@ # DESCR: Check for superfluous whitespace in the tree LC_ALL=C export LC_ALL -grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ +grep -l "[[:space:]][[:space:]]*$" `git ls-files src util |egrep -v "(^3rdparty|^src/vendorcode/|^util/kconfig/|^util/nvidia/cbootimage$|\<COPYING\>|\<LICENSE\>|\<README\>|_shipped$|\.keyring$|\.patch$|\.bin$|\.hex$|\.jpg$)"` | \ sed -e "s,^.*$,File & has lines ending with whitespace.,"

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support
by Brenton Dong 19 Oct '16

19 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17062 -gerrit commit 416a94b5bcef92388f9dca272f6c894da668a09f Author: brenton <brenton.m.dong(a)intel.com> Date: Tue Oct 18 11:35:15 2016 -0700 drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs Verified on Intel LeafHill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without Coreboot implementation of CAR init/teardown Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: brenton <brenton.m.dong(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 17 ++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 11 +++++ src/drivers/intel/fsp2_0/include/fsp/api.h | 1 + src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 + src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/temp_ram_exit.c | 50 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/util.c | 2 + 7 files changed, 84 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3ffb402..62bdd50 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -53,6 +53,11 @@ config DISPLAY_UPD_DATA Display the user specified product data prior to memory initialization. +config FSP_T_CBFS + string "Name of FSP-T in CBFS" + depends on FSP_CAR + default "fspt.bin" + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" @@ -61,6 +66,12 @@ config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" +config FSP_T_FILE + string "Intel FSP-T (temp ram init) binary path and filename" + depends on FSP_CAR + help + The path and filename of the Intel FSP-M binary for this platform. + config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES @@ -73,6 +84,12 @@ config FSP_S_FILE help The path and filename of the Intel FSP-S binary for this platform. +config FSP_CAR + bool "Use FSP TempRamInit & TempRamExit APIs" + default n + help + Use FSP APIs to initialize & Tear Down the Cache-As-Ram + config FSP_M_XIP bool "Is FSP-M XIP" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index beeec7c..87d2be5 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -38,11 +38,22 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c +postcar-$(CONFIG_FSP_CAR) += util.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +ifeq ($(CONFIG_FSP_CAR),y) +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_T_CBFS) +$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) +$(CONFIG_FSP_T_CBFS)-type := fsp +ifeq ($(CONFIG_FSP_T_XIP),y) +$(CONFIG_FSP_T_CBFS)-options := --xip +endif +endif # CONFIG_FSP_CAR + cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 553fc52..61a5140 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -39,6 +39,7 @@ enum fsp_notify_phase { /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); +uint32_t temp_ram_exit(void); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 6351b32..c84c33e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -34,6 +34,8 @@ struct fsp_header { uint16_t component_attribute; size_t cfg_region_offset; size_t cfg_region_size; + size_t temp_ram_init_entry; + size_t temp_ram_exit_entry; size_t notify_phase_entry_offset; size_t memory_init_entry_offset; size_t silicon_init_entry_offset; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 04f8c00..13c6ab2 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -101,6 +101,7 @@ void fsp_handle_reset(uint32_t status); /* SoC/chipset must provide this to handle platform-specific reset codes */ void chipset_handle_reset(uint32_t status); +typedef asmlinkage uint32_t (*temp_ram_exit_fn)(void *param); typedef asmlinkage uint32_t (*fsp_memory_init_fn) (void *raminit_upd, void **hob_list); typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c new file mode 100644 index 0000000..1bf1e24 --- /dev/null +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> + +#include <cbfs.h> + +uint32_t temp_ram_exit(void) +{ + struct fsp_header hdr; + uint32_t status; + temp_ram_exit_fn fsp_temp_ram_exit; + struct cbfsf file_desc; + struct region_device file_data; + const char *name = CONFIG_FSP_M_CBFS; + + if (cbfs_boot_locate(&file_desc, name, NULL)) { + printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); + die("FSPM not available for CAR Exit!\n"); + } + + cbfs_file_data(&file_data, &file_desc); + + if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS) + return CB_ERR; + + fsp_temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); + printk(BIOS_DEBUG, "Calling TempRamExit: 0x%p\n", fsp_temp_ram_exit); + status = fsp_temp_ram_exit(NULL); + printk(BIOS_DEBUG, "TempRamExit returned 0x%08x\n", status); + + return status; +} diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index e7e4f16..7453b59 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -52,6 +52,8 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) hdr->component_attribute = read16(raw_hdr + 34); hdr->cfg_region_offset = read32(raw_hdr + 36); hdr->cfg_region_size = read32(raw_hdr + 40); + hdr->temp_ram_init_entry = read32(raw_hdr + 48); + hdr->temp_ram_exit_entry = read32(raw_hdr + 64); hdr->notify_phase_entry_offset = read32(raw_hdr + 56); hdr->memory_init_entry_offset = read32(raw_hdr + 60); hdr->silicon_init_entry_offset = read32(raw_hdr + 68);

1 0

Patch set updated for coreboot: soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
by Brenton Dong 19 Oct '16

19 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17063 -gerrit commit 4e284ca9023a3c62cf69ab2662a77f1b11c8a50e Author: brenton <brenton.m.dong(a)intel.com> Date: Tue Oct 18 13:57:54 2016 -0700 soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to Initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel LeafHill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without Coreboot implementation of CAR init/teardown Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: brenton <brenton.m.dong(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 15 +++- .../intel/apollolake/bootblock/cache_as_ram_FSP.S | 98 ++++++++++++++++++++++ src/soc/intel/apollolake/exit_car_FSP.S | 29 +++++++ src/soc/intel/apollolake/include/soc/postcar.h | 26 ++++++ src/soc/intel/apollolake/postcar.c | 34 ++++++++ 5 files changed, 200 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4f867e1..c2bbc11 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += gpio.c @@ -22,6 +21,12 @@ bootblock-y += spi.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ifeq ($(CONFIG_FSP_CAR),y) +bootblock-y += bootblock/cache_as_ram_FSP.S +else +bootblock-y += bootblock/cache_as_ram.S +endif + romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c @@ -75,13 +80,19 @@ ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c -postcar-y += exit_car.S postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +ifeq ($(CONFIG_FSP_CAR),y) +postcar-y += exit_car_FSP.S +postcar-y += postcar.c +else +postcar-y += exit_car.S +endif + verstage-y += car.c verstage-y += i2c_early.c verstage-y += heci.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_FSP.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_FSP.S new file mode 100644 index 0000000..d8929c6 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram_FSP.S @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/cpu.h> + +#include <../../../arch/x86/walkcbfs.S> + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add $0x94, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebx), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + nop + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Microcode Location */ + .long 0 /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_IBBL_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_IBBL_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "blobs/fspt.bin\x00" diff --git a/src/soc/intel/apollolake/exit_car_FSP.S b/src/soc/intel/apollolake/exit_car_FSP.S new file mode 100644 index 0000000..e3a7b36 --- /dev/null +++ b/src/soc/intel/apollolake/exit_car_FSP.S @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +#include <soc/cpu.h> + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov $CONFIG_RAMTOP, %esp + + /* Call C code */ + call post_car_main diff --git a/src/soc/intel/apollolake/include/soc/postcar.h b/src/soc/intel/apollolake/include/soc/postcar.h new file mode 100644 index 0000000..7e31def --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/postcar.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_POSTCAR_H_ +#define _SOC_APOLLOLAKE_POSTCAR_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +void post_car_main(void); + +#endif /* _SOC_APOLLOLAKE_POSTCAR_H_ */ diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c new file mode 100644 index 0000000..0b0e4ca --- /dev/null +++ b/src/soc/intel/apollolake/postcar.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <string.h> +#include <cbmem.h> +#include <arch/cpu.h> +#include <arch/stages.h> +#include <fsp/util.h> +#include <soc/postcar.h> +#include <boot_device.h> + +void post_car_main(void) +{ + temp_ram_exit(); + + /* Recover cbmem so infrastruture using it is functional. */ + cbmem_initialize(); + + copy_and_run(); +}

1 0

Patch set updated for coreboot: soc/intel/apollolake: add Multiple FMAP build
by Brenton Dong 19 Oct '16

19 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17064 -gerrit commit b5ea715620e83c2485de0234408130d9aac2ad17 Author: brenton <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:21:12 2016 -0700 soc/intel/apollolake: add Multiple FMAP build Multiple coreboot binaries with separate FMAPs and separate CBFSs allow coreboot to run separate stages from different regions (SRAM, CAR, Mem) When enabling Multiple FMAP, 3 Coreboot Images will be created. IBBL: Contains bootblock, CAR init (FSP-T) and hands off to IBBM IBBM: Contains romstage, Mem Init (FSP-M) and postcar OBB: Contains ramstage, Silicon Init (FSP-S), and the rest of the components in the original single coreboot.rom file. This is the same image as the original coreboot.rom minus the components moved to the IBBL and IBBM Add functions to select which region cbfs files will be loaded from Verified on Intel LeafHill CRB and confirmed that the coreboot builds 3 separate coreboot files which can be loaded and booted. Verified that other ApolloLake projects can build correctly with this option disabled. Change-Id: Iab3c353b65e1e0fc9d04fcee6a82a330927db41e Signed-off-by: brenton <brenton.m.dong(a)intel.com> --- Makefile.inc | 47 ++++++++++ src/arch/x86/Makefile.inc | 2 + src/drivers/intel/fsp2_0/Makefile.inc | 5 + src/soc/intel/apollolake/Kconfig | 6 ++ src/soc/intel/apollolake/Makefile.inc | 4 + src/soc/intel/apollolake/bootblock/bootblock.c | 57 ++++++++++++ src/soc/intel/apollolake/chip.c | 9 +- src/soc/intel/apollolake/include/soc/bootregion.h | 28 ++++++ src/soc/intel/apollolake/include/soc/cse.h | 30 ++++++ src/soc/intel/apollolake/include/soc/mmio.h | 35 +++++++ src/soc/intel/apollolake/mmap_boot.c | 2 + src/soc/intel/apollolake/mmap_boot_cse.c | 53 +++++++++++ src/soc/intel/apollolake/postcar.c | 10 ++ src/soc/intel/apollolake/romstage.c | 108 ++++++++++++++++++++++ 14 files changed, 395 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 127f372..9e25883 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -826,11 +826,13 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) ifeq ($(CONFIG_ARCH_X86),y) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) $(CBFSTOOL) $@.tmp add \ -f $(objcbfs)/bootblock.bin \ -n bootblock \ -t bootblock \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) +endif # ifeq ($(CONFIG_MULTIPLE_FMAP),y) else # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ @@ -865,6 +867,49 @@ $(REFCODE_BLOB): $(RMODTOOL) $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ endif + +ifeq ($(CONFIG_MULTIPLE_FMAP),y) + +.PHONY:$(obj)/coreboot_ibbl.rom +$(obj)/coreboot_ibbl.rom: $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(obj)/ibbl_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbl_fmap.fmap -r $(shell cat $(obj)/ibbl_fmap.desc) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_T_FILE)) \ + -n blobs/fspt.bin -t fsp -y -b 0xC0 + mv $@.tmp $@ + @printf "\ncoreboot IBBL image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +.PHONY:$(obj)/coreboot_ibbm.rom +$(obj)/coreboot_ibbm.rom: $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(objcbfs)/romstage.elf \ + $(objcbfs)/postcar.elf \ + $(obj)/ibbm_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbm_fmap.fmap -r $(shell cat $(obj)/ibbm_fmap.desc) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/romstage.elf \ + -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ + $(CBFSTOOL_PRE_OPTS) -b 0 + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_M_FILE)) \ + -n blobs/fspm.bin -t fsp -y + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/postcar.elf \ + -n $(CONFIG_CBFS_PREFIX)/postcar + mv $@.tmp $@ + @printf "\ncoreboot IBBM image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +coreboot: $(obj)/coreboot_ibbl.rom $(obj)/coreboot_ibbm.rom + +endif # ifneq ($(CONFIG_MULTIPLE_FMAP),y) + $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty @@ -892,6 +937,7 @@ endif @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage-type := stage @@ -924,6 +970,7 @@ endif # CONFIG_NO_FIXED_XIP_ROM_SIZE endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 +endif # CONFIG_MULTIPLE_FMAP cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 782ca63..fc7eb5c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -300,10 +300,12 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ # Add postcar to CBFS +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage $(CONFIG_CBFS_PREFIX)/postcar-compression := none +endif #CONFIG_MULTIPLE_FMAP ############################################################################### # ramstage diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 87d2be5..7d14d02 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -45,6 +45,8 @@ CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +ifneq ($(CONFIG_MULTIPLE_FMAP),y) + ifeq ($(CONFIG_FSP_CAR),y) cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_T_CBFS) $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) @@ -57,6 +59,9 @@ endif # CONFIG_FSP_CAR cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp + +endif #CONFIG_MULTIPLE_FMAP + ifeq ($(CONFIG_FSP_M_XIP),y) $(CONFIG_FSP_M_CBFS)-options := --xip endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 6c178c3..eeba42a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -81,6 +81,12 @@ config TPM_ON_FAST_SPI TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. +config MULTIPLE_FMAP + depends on FSP_CAR + bool + help + Enable build with mulitple coreboot images and each will has its own fmap. + config SOC_INTEL_COMMON_RESET bool default y diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index c2bbc11..b73f532 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -15,6 +15,7 @@ bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += itss.c bootblock-y += lpc_lib.c +bootblock-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c bootblock-y += mmap_boot.c bootblock-y += pmutil.c bootblock-y += spi.c @@ -37,6 +38,7 @@ romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c romstage-y += memmap.c romstage-y += meminit.c +romstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c romstage-y += mmap_boot.c romstage-y += tsc_freq.c romstage-y += pmutil.c @@ -65,6 +67,7 @@ ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += lpc.c ramstage-y += lpc_lib.c ramstage-y += memmap.c +ramstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c ramstage-y += mmap_boot.c ramstage-y += p2sb.c ramstage-y += uart.c @@ -81,6 +84,7 @@ ramstage-y += spi.c ramstage-y += xhci.c postcar-y += memmap.c +postcar-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 28a9128..22a4d44 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -14,6 +14,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include <string.h> #include <arch/cpu.h> #include <bootblock_common.h> #include <cpu/x86/mtrr.h> @@ -31,6 +32,53 @@ #include <spi-generic.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm0(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_num; + uint32_t state; + msr_t msr; + + /* Request data from CSE */ + host_to_cse = (ibbm_size << 4) | 0xC0000000; + CSE_HOST2CSE = host_to_cse; + + /* Wait for response */ + do { + cse_to_host = CSE_CSE2HOST; + chunk_num = (cse_to_host >> 28) & 3; + } while (!chunk_num); + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* + * The 1st 128K should have been loaded into SRAM now + * However, since the top 32K IBBL is still cached, we can only read + * (128-32)K at this moment. The remaining will be read in romstage. + */ + memcpy((void *)ibbm_base, (void *)(~CSE_IBB_SRAM_SIZE + 1), + CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE); + + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + the temporary memory */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + static const struct pad_config tpm_spi_configs[] = { PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ }; @@ -92,6 +140,15 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp) enable_cmos_upper_bank(); +#if CONFIG_MULTIPLE_FMAP + /* Loading IBBM into CAR */ + load_ibbm0(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE, CONFIG_IBBM_ROM_SIZE); + + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); +#endif //CONFIG_MULTIPLE_FMAP + /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(base_timestamp); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d722992..0a184eb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -35,9 +35,12 @@ #include <soc/pm.h> #include <soc/p2sb.h> #include <soc/northbridge.h> - #include "chip.h" +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif /* CONFIG_MULTIPLE_FMAP */ + static void *vbt; static struct region_device vbt_rdev; @@ -267,6 +270,10 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_OBB); +#endif //CONFIG_MULTIPLE_FMAP + fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ diff --git a/src/soc/intel/apollolake/include/soc/bootregion.h b/src/soc/intel/apollolake/include/soc/bootregion.h new file mode 100644 index 0000000..dde562a --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootregion.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_BOOT_RGN_H_ +#define _SOC_LEAFHILL_BOOT_RGN_H_ + +#define BOOT_REGION_IBBL 0 +#define BOOT_REGION_IBBM 1 +#define BOOT_REGION_OBB 2 + +/* Set current active boot region */ +void set_boot_region(int region_id); + +#endif /* _SOC_LEAFHILL_BOOT_RGN_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/cse.h b/src/soc/intel/apollolake/include/soc/cse.h new file mode 100644 index 0000000..ed2b136 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cse.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_CSE_H_ +#define _SOC_LEAFHILL_CSE_H_ + +#define HOST2CSE 0x70 +#define CSE2HOST 0x60 +#define CSE_IBB_SRAM_SIZE 0x20000 + +#define CSE_CFG_BASE (CONFIG_MMCONF_BASE_ADDRESS + 0x78000) +#define CSE_VIDDID (*(volatile int32_t *)CSE_CFG_BASE) +#define CSE_HOST2CSE (*(volatile int32_t *)(CSE_CFG_BASE + HOST2CSE)) +#define CSE_CSE2HOST (*(volatile int32_t *)(CSE_CFG_BASE + CSE2HOST)) + +#endif /* _SOC_LEAFHILL_CSE_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/mmio.h b/src/soc/intel/apollolake/include/soc/mmio.h new file mode 100644 index 0000000..674e071 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/mmio.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMIO_H_ +#define _SOC_MMIO_H_ + + +#define MmioRead32(x) (*(volatile uint32_t *)(unsigned int)(x)) +#define MmioWrite32(x, y) (*(volatile uint32_t *)(unsigned int)(x) = y) +#define MmioRead16(x) (*(volatile uint16_t *)(unsigned int)(x)) +#define MmioWrite16(x, y) (*(volatile uint16_t *)(unsigned int)(x) = y) +#define MmioRead8(x) (*(volatile uint8_t *)(unsigned int)(x)) +#define MmioWrite8(x, y) (*(volatile uint8_t *)(unsigned int)(x) = y) + +#define PCIE_MMIO(Bus, Device, Function, Register) \ + ((unsigned int)CONFIG_MMCONF_BASE_ADDRESS + \ + (unsigned int)(Bus << 20) + \ + (unsigned int)(Device << 15) + \ + (unsigned int)(Function << 12) + \ + (unsigned int)(Register) \ + ) + +#endif diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index bf2e5b9..994f7b8 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -113,6 +113,7 @@ static void bios_mmap_init(void) car_set_var(bios_size, size); } +#if !CONFIG_MULTIPLE_FMAP const struct region_device *boot_device_ro(void) { bios_mmap_init(); @@ -122,6 +123,7 @@ const struct region_device *boot_device_ro(void) return &real_dev_ptr->rdev; } +#endif //CONFIG_MULTIPLE_FMAP static int iafw_boot_region_properties(struct cbfs_props *props) { diff --git a/src/soc/intel/apollolake/mmap_boot_cse.c b/src/soc/intel/apollolake/mmap_boot_cse.c new file mode 100644 index 0000000..d5b4526 --- /dev/null +++ b/src/soc/intel/apollolake/mmap_boot_cse.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> +#include <soc/bootregion.h> +#include <soc/intel/common/nvm.h> +#include <arch/early_variables.h> + +/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ +#define rom_base(x) (void *)(uintptr_t)(-(int32_t)(x)) +#define IBBL_ROM_BASE rom_base(CONFIG_IBBL_ROM_SIZE) +#define IBBM_ROM_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ + - CONFIG_IBBM_ROM_SIZE) + +static int curr_boot_region CAR_GLOBAL; + +static const struct mem_region_device boot_dev[] = { + MEM_REGION_DEV_RO_INIT(IBBL_ROM_BASE, CONFIG_IBBL_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(IBBM_ROM_BASE, CONFIG_IBBM_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(CONFIG_RAMTOP, CONFIG_ROM_SIZE) +}; + +#if CONFIG_MULTIPLE_FMAP +const struct region_device *boot_device_ro(void) +{ + return &boot_dev[car_get_var(curr_boot_region)].rdev; +} +#endif //CONFIG_MULTIPLE_FMAP + +void set_boot_region(int rgn_idx) +{ + if (rgn_idx < sizeof(boot_dev)/sizeof(boot_dev[0])) + car_set_var(curr_boot_region, rgn_idx); +} diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c index 0b0e4ca..7c24fe9 100644 --- a/src/soc/intel/apollolake/postcar.c +++ b/src/soc/intel/apollolake/postcar.c @@ -23,9 +23,19 @@ #include <soc/postcar.h> #include <boot_device.h> +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif + void post_car_main(void) { +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_IBBM); + temp_ram_exit(); + set_boot_region(BOOT_REGION_OBB); +#else temp_ram_exit(); +#endif /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1f6a38f..69d7273 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -41,6 +41,12 @@ #include <string.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <cpu/x86/msr.h> +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + static struct chipset_power_state power_state CAR_GLOBAL; /* High Performance Event Timer Configuration */ @@ -100,6 +106,92 @@ static void migrate_power_state(int is_recovery) } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm1(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t state; + uint32_t size; + uint8_t ring_idx; + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_idx; + uint32_t chunk_size; + uint32_t chunk_num; + uint32_t ibb_remaining; + uint8_t *src; + uint8_t *dst; + uint8_t *ptr; + msr_t msr; + + /* Set IBBL cache to UC */ + msr = rdmsr(0x202); + msr.lo &= ~0x0f; + wrmsr(0x202, msr); + + /* Init variables */ + size = CONFIG_IBBL_ROM_SIZE; + dst = (uint8_t *)ibbm_base; + src = (uint8_t *)(~CONFIG_IBBL_ROM_SIZE + 1); + memcpy(dst, src, size); + + cse_to_host = CSE_CSE2HOST; + host_to_cse = CSE_HOST2CSE; + chunk_num = (cse_to_host >> 28) & 3; + if (chunk_num == 3) + chunk_num = 4; + chunk_size = CSE_IBB_SRAM_SIZE / chunk_num; + chunk_idx = chunk_num; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~0x0f) | (cse_to_host & 0x0f); + CSE_HOST2CSE = host_to_cse; + + ibb_remaining = ibbm_size - size; + while (ibb_remaining > 0) { + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* Calculate ring index */ + ring_idx = (uint8_t)(chunk_idx % chunk_num); + if (state & (1 << ring_idx)) { + /* Calculate source and dest. address in ring buffer */ + src += chunk_size; + dst += chunk_size; + if (src == 0) + src = (uint8_t *)(~CSE_IBB_SRAM_SIZE + 1); + if (ibb_remaining < chunk_size) + size = ibb_remaining; + else + size = chunk_size; + + /* Move data from SRAM into temporary memory */ + memcpy(dst, src, size); + ibb_remaining -= size; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~(1 << ring_idx)) | + (cse_to_host & (1 << ring_idx)); + CSE_HOST2CSE = host_to_cse; + + chunk_idx++; + } + } + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + * the temporary memory + */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -109,6 +201,10 @@ asmlinkage void car_stage_entry(void) void *smm_base; size_t smm_size; uintptr_t tseg_base; +#if CONFIG_MULTIPLE_FMAP + uint32_t ibbm_base; + uint32_t ibbm_loaded; +#endif //CONFIG_MULTIPLE_FMAP timestamp_add_now(TS_START_ROMSTAGE); @@ -117,6 +213,18 @@ asmlinkage void car_stage_entry(void) console_init(); +#if CONFIG_MULTIPLE_FMAP + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); + + /* load the remaining IBBM */ + ibbm_loaded = CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE; + ibbm_base = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE; + load_ibbm1(ibbm_base + ibbm_loaded, + CONFIG_IBBM_ROM_SIZE - ibbm_loaded); +#endif //CONFIG_MULTIPLE_FMAP + s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1*KiB))

1 0

Patch set updated for coreboot: mainboard/intel/leafhill: add LeafHill CRB mainboard directory
by Brenton Dong 19 Oct '16

19 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17065 -gerrit commit ad39b8432712ae4234b5805e821d46edbef4f4a7 Author: brenton <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:40:39 2016 -0700 mainboard/intel/leafhill: add LeafHill CRB mainboard directory LeafHill CRB is an Intel Customer Reference Board with ApolloLake silicon and LPDDR4 Down Verified on Intel LeafHill CRB and confirmed to boot Change-Id: Ieeed6a7e5e9b6f02e4dd7e15cbcb58894c3c4eac Signed-off-by: brenton <brenton.m.dong(a)intel.com> --- src/mainboard/intel/leafhill/Kconfig | 45 ++++++++++ src/mainboard/intel/leafhill/Kconfig.name | 3 + src/mainboard/intel/leafhill/Makefile.inc | 64 ++++++++++++++ src/mainboard/intel/leafhill/acpi_tables.c | 14 +++ src/mainboard/intel/leafhill/board.h | 36 ++++++++ src/mainboard/intel/leafhill/board_info.txt | 6 ++ src/mainboard/intel/leafhill/brd_gpio.h | 65 ++++++++++++++ src/mainboard/intel/leafhill/devicetree.cb | 56 ++++++++++++ src/mainboard/intel/leafhill/dsdt.asl | 37 ++++++++ src/mainboard/intel/leafhill/ibb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/obb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/romstage.c | 128 ++++++++++++++++++++++++++++ 12 files changed, 466 insertions(+) diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig new file mode 100644 index 0000000..462e458 --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_LEAFHILL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default intel/leafhill + +config MAINBOARD_PART_NUMBER + string + default "LeafHill" + +config MAINBOARD_VENDOR + string + default "Intel" + +config IFD_BIOS_END + hex + default 0x6FF000 + +config IFD_BIOS_START + hex + default 0x1000 + +config IBBL_ROM_SIZE + hex + default 0x10000 + +config IBBM_ROM_SIZE + hex + default 0x62000 + +config OBB_ROM_SIZE + hex + default 0x100000 + +config OBB_ROM_BASE + hex + default 0x200000 + +endif diff --git a/src/mainboard/intel/leafhill/Kconfig.name b/src/mainboard/intel/leafhill/Kconfig.name new file mode 100644 index 0000000..72664cd --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_INTEL_LEAFHILL + bool "LeafHill" + diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc new file mode 100644 index 0000000..271b20a --- /dev/null +++ b/src/mainboard/intel/leafhill/Makefile.inc @@ -0,0 +1,64 @@ +#Nothing here yet + +MAINBOARD_PATH := $(src)/mainboard/$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) +IBB_FLASHMAP := $(MAINBOARD_PATH)/ibb_fmap.fmd + +IBBL_FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_IBBL_ROM_SIZE)) +IBBL_FMAP_ROM_SIZE := $(CONFIG_IBBL_ROM_SIZE) +IBBL_FMAP_BIOS_BASE := 0 +IBBL_FMAP_BIOS_SIZE := $(IBBL_FMAP_ROM_SIZE) +IBBL_FMAP_FMAP_BASE := 0 +IBBL_FMAP_FMAP_SIZE := 0x100 +IBBL_FMAP_CBFS_BASE := $(IBBL_FMAP_FMAP_SIZE) +IBBL_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBL_FMAP_BIOS_SIZE) $(IBBL_FMAP_FMAP_SIZE)) + +$(obj)/ibbl_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBL_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBL_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBL_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBL_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBL_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBL_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBL_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBL_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbl_fmap.fmap +$(obj)/ibbl_fmap_config.h: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.desc: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.fmap: $(obj)/ibbl_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h -R $(obj)/ibbl_fmap.desc $< $@ + + +IBBM_FMAP_CAR_TOP := $(call int-add, $(CONFIG_DCACHE_RAM_BASE) $(CONFIG_DCACHE_RAM_SIZE)) +IBBM_FMAP_ROM_ADDR := $(call int-subtract, $(IBBM_FMAP_CAR_TOP) $(CONFIG_IBBM_ROM_SIZE)) +IBBM_FMAP_ROM_SIZE := $(CONFIG_IBBM_ROM_SIZE) +IBBM_FMAP_BIOS_BASE := 0 +IBBM_FMAP_BIOS_SIZE := $(IBBM_FMAP_ROM_SIZE) +IBBM_FMAP_FMAP_BASE := 0 +IBBM_FMAP_FMAP_SIZE := 0x100 +IBBM_FMAP_CBFS_BASE := $(IBBM_FMAP_FMAP_SIZE) +IBBM_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBM_FMAP_BIOS_SIZE) $(IBBM_FMAP_FMAP_SIZE)) + +$(obj)/ibbm_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBM_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBM_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBM_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBM_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBM_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBM_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBM_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBM_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbm_fmap.fmap +$(obj)/ibbm_fmap_config.h: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.desc: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.fmap: $(obj)/ibbm_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h -R $(obj)/ibbm_fmap.desc $< $@ + +# brenton: changed this to headerromstage-y += brd_gpio.c diff --git a/src/mainboard/intel/leafhill/acpi_tables.c b/src/mainboard/intel/leafhill/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/intel/leafhill/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/intel/leafhill/board.h b/src/mainboard/intel/leafhill/board.h new file mode 100644 index 0000000..90e2a10 --- /dev/null +++ b/src/mainboard/intel/leafhill/board.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOARD_H_ +#define _SOC_BOARD_H_ + +typedef struct { + uint32_t VendorDeviceId; //Codec Vendor/Device ID + uint8_t RevisionId; //Coden Revision ID. 0xFF matches any rev + uint8_t SdiNo; //SDI number, 0xFF matches any SDI. + uint16_t DataDwords; //Number of data DWORDs following header + uint8_t FrontPanelSupport; + uint8_t Padding[3]; +} BL_HDA_VERB_TABLE_HEADER; + +typedef struct { + BL_HDA_VERB_TABLE_HEADER VerbTableHeader; + uint32_t VerbTableData[]; +} BL_HDAUDIO_VERB_TABLE; + +void config_board_gpio(void); + + +#endif diff --git a/src/mainboard/intel/leafhill/board_info.txt b/src/mainboard/intel/leafhill/board_info.txt new file mode 100644 index 0000000..eb95944 --- /dev/null +++ b/src/mainboard/intel/leafhill/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Apollolake RVP Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h new file mode 100644 index 0000000..3cd47a7 --- /dev/null +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/mmio.h> +#include <soc/gpio.h> +#include "board.h" + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb new file mode 100644 index 0000000..746aaf3 --- /dev/null +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -0,0 +1,56 @@ +chip soc/intel/apollolake + + register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 + register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot + register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl new file mode 100644 index 0000000..53a7b0f --- /dev/null +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> + +} diff --git a/src/mainboard/intel/leafhill/ibb_fmap.fmd b/src/mainboard/intel/leafhill/ibb_fmap.fmd new file mode 100644 index 0000000..06e905c --- /dev/null +++ b/src/mainboard/intel/leafhill/ibb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/src/mainboard/intel/leafhill/obb_fmap.fmd b/src/mainboard/intel/leafhill/obb_fmap.fmd new file mode 100644 index 0000000..d0d0720 --- /dev/null +++ b/src/mainboard/intel/leafhill/obb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@0x200000 0x100000 { + BIOS@0 0x100000 { + FMAP@0 0x100 + COREBOOT(CBFS)@0x100 1048320 + } +} \ No newline at end of file diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c new file mode 100644 index 0000000..256570a --- /dev/null +++ b/src/mainboard/intel/leafhill/romstage.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/romstage.h> +#include <console/console.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "board.h" +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* DRAM Config settings */ + mupd->FspmConfig.Package = 0x1; + mupd->FspmConfig.Profile = 0xB; + mupd->FspmConfig.MemoryDown = 0x1; + mupd->FspmConfig.DDR3LPageSize = 0x0; + mupd->FspmConfig.DDR3LASR = 0x0; + mupd->FspmConfig.ScramblerSupport = 0x1; + mupd->FspmConfig.ChannelHashMask = 0x36; + mupd->FspmConfig.SliceHashMask = 0x9; + mupd->FspmConfig.InterleavedMode = 0x2; + mupd->FspmConfig.ChannelsSlicesEnable = 0x0; + mupd->FspmConfig.MinRefRate2xEnable = 0x0; + mupd->FspmConfig.DualRankSupportEnable = 0x1; + mupd->FspmConfig.RmtMode = 0x0; + mupd->FspmConfig.MemorySizeLimit = 0x1800; + mupd->FspmConfig.LowMemoryMaxValue = 0x0; + mupd->FspmConfig.DisableFastBoot = 0x0; + mupd->FspmConfig.HighMemoryMaxValue = 0x0; + mupd->FspmConfig.DIMM0SPDAddress = 0x0; + mupd->FspmConfig.DIMM1SPDAddress = 0x0; + mupd->FspmConfig.Ch0_RankEnable = 0x3; + mupd->FspmConfig.Ch0_DeviceWidth = 0x1; + mupd->FspmConfig.Ch0_DramDensity = 0x2; + mupd->FspmConfig.Ch0_Option = 0x3; + mupd->FspmConfig.Ch0_OdtConfig = 0x0; + mupd->FspmConfig.Ch0_TristateClk1 = 0x0; + mupd->FspmConfig.Ch0_Mode2N = 0x0; + mupd->FspmConfig.Ch0_OdtLevels = 0x0; + mupd->FspmConfig.Ch1_RankEnable = 0x3; + mupd->FspmConfig.Ch1_DeviceWidth = 0x1; + mupd->FspmConfig.Ch1_DramDensity = 0x2; + mupd->FspmConfig.Ch1_Option = 0x3; + mupd->FspmConfig.Ch1_OdtConfig = 0x0; + mupd->FspmConfig.Ch1_TristateClk1 = 0x0; + mupd->FspmConfig.Ch1_Mode2N = 0x0; + mupd->FspmConfig.Ch1_OdtLevels = 0x0; + mupd->FspmConfig.Ch2_RankEnable = 0x3; + mupd->FspmConfig.Ch2_DeviceWidth = 0x1; + mupd->FspmConfig.Ch2_DramDensity = 0x2; + mupd->FspmConfig.Ch2_Option = 0x3; + mupd->FspmConfig.Ch2_OdtConfig = 0x0; + mupd->FspmConfig.Ch2_TristateClk1 = 0x0; + mupd->FspmConfig.Ch2_Mode2N = 0x0; + mupd->FspmConfig.Ch2_OdtLevels = 0x0; + mupd->FspmConfig.Ch3_RankEnable = 0x3; + mupd->FspmConfig.Ch3_DeviceWidth = 0x1; + mupd->FspmConfig.Ch3_DramDensity = 0x2; + mupd->FspmConfig.Ch3_Option = 0x3; + mupd->FspmConfig.Ch3_OdtConfig = 0x0; + mupd->FspmConfig.Ch3_TristateClk1 = 0x0; + mupd->FspmConfig.Ch3_Mode2N = 0x0; + mupd->FspmConfig.Ch3_OdtLevels = 0x0; + mupd->FspmConfig.RmtCheckRun = 0x0; + mupd->FspmConfig.MrcDataSaving = 0x1; + mupd->FspmConfig.MrcFastBoot = 0x1; + + memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + mupd->FspmConfig.MsgLevelMask = 0x0; + + /* Request FSP to load the coreboot primary CBFS */ + mupd->FspmConfig.OemLoadingBase = CONFIG_OBB_ROM_BASE; + strcpy((char *)mupd->FspmConfig.OemFileName, "OBB"); + +}

1 0

New patch to review for coreboot: mainboard/intel/leafhill: add LeafHill CRB mainboard directory
by Brenton Dong 19 Oct '16

19 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17065 -gerrit commit 2d02dc4333bec7c093b59fd9490b70e684c4cfc7 Author: brenton <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:40:39 2016 -0700 mainboard/intel/leafhill: add LeafHill CRB mainboard directory LeafHill CRB is an Intel Customer Reference Board with ApolloLake silicon and LPDDR4 Down Verified on Intel LeafHill CRB and confirmed to boot Change-Id: Ieeed6a7e5e9b6f02e4dd7e15cbcb58894c3c4eac Signed-off-by: brenton <brenton.m.dong(a)intel.com> --- src/mainboard/intel/leafhill/Kconfig | 45 ++++++++++ src/mainboard/intel/leafhill/Kconfig.name | 3 + src/mainboard/intel/leafhill/Makefile.inc | 64 ++++++++++++++ src/mainboard/intel/leafhill/acpi_tables.c | 14 +++ src/mainboard/intel/leafhill/board.h | 36 ++++++++ src/mainboard/intel/leafhill/board_info.txt | 6 ++ src/mainboard/intel/leafhill/brd_gpio.h | 65 ++++++++++++++ src/mainboard/intel/leafhill/devicetree.cb | 56 ++++++++++++ src/mainboard/intel/leafhill/dsdt.asl | 37 ++++++++ src/mainboard/intel/leafhill/ibb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/obb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/romstage.c | 128 ++++++++++++++++++++++++++++ 12 files changed, 466 insertions(+) diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig new file mode 100755 index 0000000..462e458 --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_LEAFHILL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default intel/leafhill + +config MAINBOARD_PART_NUMBER + string + default "LeafHill" + +config MAINBOARD_VENDOR + string + default "Intel" + +config IFD_BIOS_END + hex + default 0x6FF000 + +config IFD_BIOS_START + hex + default 0x1000 + +config IBBL_ROM_SIZE + hex + default 0x10000 + +config IBBM_ROM_SIZE + hex + default 0x62000 + +config OBB_ROM_SIZE + hex + default 0x100000 + +config OBB_ROM_BASE + hex + default 0x200000 + +endif diff --git a/src/mainboard/intel/leafhill/Kconfig.name b/src/mainboard/intel/leafhill/Kconfig.name new file mode 100644 index 0000000..72664cd --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_INTEL_LEAFHILL + bool "LeafHill" + diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc new file mode 100755 index 0000000..271b20a --- /dev/null +++ b/src/mainboard/intel/leafhill/Makefile.inc @@ -0,0 +1,64 @@ +#Nothing here yet + +MAINBOARD_PATH := $(src)/mainboard/$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) +IBB_FLASHMAP := $(MAINBOARD_PATH)/ibb_fmap.fmd + +IBBL_FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_IBBL_ROM_SIZE)) +IBBL_FMAP_ROM_SIZE := $(CONFIG_IBBL_ROM_SIZE) +IBBL_FMAP_BIOS_BASE := 0 +IBBL_FMAP_BIOS_SIZE := $(IBBL_FMAP_ROM_SIZE) +IBBL_FMAP_FMAP_BASE := 0 +IBBL_FMAP_FMAP_SIZE := 0x100 +IBBL_FMAP_CBFS_BASE := $(IBBL_FMAP_FMAP_SIZE) +IBBL_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBL_FMAP_BIOS_SIZE) $(IBBL_FMAP_FMAP_SIZE)) + +$(obj)/ibbl_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBL_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBL_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBL_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBL_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBL_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBL_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBL_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBL_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbl_fmap.fmap +$(obj)/ibbl_fmap_config.h: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.desc: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.fmap: $(obj)/ibbl_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h -R $(obj)/ibbl_fmap.desc $< $@ + + +IBBM_FMAP_CAR_TOP := $(call int-add, $(CONFIG_DCACHE_RAM_BASE) $(CONFIG_DCACHE_RAM_SIZE)) +IBBM_FMAP_ROM_ADDR := $(call int-subtract, $(IBBM_FMAP_CAR_TOP) $(CONFIG_IBBM_ROM_SIZE)) +IBBM_FMAP_ROM_SIZE := $(CONFIG_IBBM_ROM_SIZE) +IBBM_FMAP_BIOS_BASE := 0 +IBBM_FMAP_BIOS_SIZE := $(IBBM_FMAP_ROM_SIZE) +IBBM_FMAP_FMAP_BASE := 0 +IBBM_FMAP_FMAP_SIZE := 0x100 +IBBM_FMAP_CBFS_BASE := $(IBBM_FMAP_FMAP_SIZE) +IBBM_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBM_FMAP_BIOS_SIZE) $(IBBM_FMAP_FMAP_SIZE)) + +$(obj)/ibbm_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBM_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBM_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBM_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBM_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBM_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBM_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBM_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBM_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbm_fmap.fmap +$(obj)/ibbm_fmap_config.h: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.desc: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.fmap: $(obj)/ibbm_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h -R $(obj)/ibbm_fmap.desc $< $@ + +# brenton: changed this to headerromstage-y += brd_gpio.c diff --git a/src/mainboard/intel/leafhill/acpi_tables.c b/src/mainboard/intel/leafhill/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/intel/leafhill/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/intel/leafhill/board.h b/src/mainboard/intel/leafhill/board.h new file mode 100755 index 0000000..90e2a10 --- /dev/null +++ b/src/mainboard/intel/leafhill/board.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOARD_H_ +#define _SOC_BOARD_H_ + +typedef struct { + uint32_t VendorDeviceId; //Codec Vendor/Device ID + uint8_t RevisionId; //Coden Revision ID. 0xFF matches any rev + uint8_t SdiNo; //SDI number, 0xFF matches any SDI. + uint16_t DataDwords; //Number of data DWORDs following header + uint8_t FrontPanelSupport; + uint8_t Padding[3]; +} BL_HDA_VERB_TABLE_HEADER; + +typedef struct { + BL_HDA_VERB_TABLE_HEADER VerbTableHeader; + uint32_t VerbTableData[]; +} BL_HDAUDIO_VERB_TABLE; + +void config_board_gpio(void); + + +#endif diff --git a/src/mainboard/intel/leafhill/board_info.txt b/src/mainboard/intel/leafhill/board_info.txt new file mode 100644 index 0000000..eb95944 --- /dev/null +++ b/src/mainboard/intel/leafhill/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Apollolake RVP Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h new file mode 100755 index 0000000..3cd47a7 --- /dev/null +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/mmio.h> +#include <soc/gpio.h> +#include "board.h" + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb new file mode 100644 index 0000000..746aaf3 --- /dev/null +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -0,0 +1,56 @@ +chip soc/intel/apollolake + + register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 + register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot + register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl new file mode 100644 index 0000000..53a7b0f --- /dev/null +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> + +} diff --git a/src/mainboard/intel/leafhill/ibb_fmap.fmd b/src/mainboard/intel/leafhill/ibb_fmap.fmd new file mode 100755 index 0000000..06e905c --- /dev/null +++ b/src/mainboard/intel/leafhill/ibb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/src/mainboard/intel/leafhill/obb_fmap.fmd b/src/mainboard/intel/leafhill/obb_fmap.fmd new file mode 100755 index 0000000..d0d0720 --- /dev/null +++ b/src/mainboard/intel/leafhill/obb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@0x200000 0x100000 { + BIOS@0 0x100000 { + FMAP@0 0x100 + COREBOOT(CBFS)@0x100 1048320 + } +} \ No newline at end of file diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c new file mode 100755 index 0000000..256570a --- /dev/null +++ b/src/mainboard/intel/leafhill/romstage.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/romstage.h> +#include <console/console.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "board.h" +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* DRAM Config settings */ + mupd->FspmConfig.Package = 0x1; + mupd->FspmConfig.Profile = 0xB; + mupd->FspmConfig.MemoryDown = 0x1; + mupd->FspmConfig.DDR3LPageSize = 0x0; + mupd->FspmConfig.DDR3LASR = 0x0; + mupd->FspmConfig.ScramblerSupport = 0x1; + mupd->FspmConfig.ChannelHashMask = 0x36; + mupd->FspmConfig.SliceHashMask = 0x9; + mupd->FspmConfig.InterleavedMode = 0x2; + mupd->FspmConfig.ChannelsSlicesEnable = 0x0; + mupd->FspmConfig.MinRefRate2xEnable = 0x0; + mupd->FspmConfig.DualRankSupportEnable = 0x1; + mupd->FspmConfig.RmtMode = 0x0; + mupd->FspmConfig.MemorySizeLimit = 0x1800; + mupd->FspmConfig.LowMemoryMaxValue = 0x0; + mupd->FspmConfig.DisableFastBoot = 0x0; + mupd->FspmConfig.HighMemoryMaxValue = 0x0; + mupd->FspmConfig.DIMM0SPDAddress = 0x0; + mupd->FspmConfig.DIMM1SPDAddress = 0x0; + mupd->FspmConfig.Ch0_RankEnable = 0x3; + mupd->FspmConfig.Ch0_DeviceWidth = 0x1; + mupd->FspmConfig.Ch0_DramDensity = 0x2; + mupd->FspmConfig.Ch0_Option = 0x3; + mupd->FspmConfig.Ch0_OdtConfig = 0x0; + mupd->FspmConfig.Ch0_TristateClk1 = 0x0; + mupd->FspmConfig.Ch0_Mode2N = 0x0; + mupd->FspmConfig.Ch0_OdtLevels = 0x0; + mupd->FspmConfig.Ch1_RankEnable = 0x3; + mupd->FspmConfig.Ch1_DeviceWidth = 0x1; + mupd->FspmConfig.Ch1_DramDensity = 0x2; + mupd->FspmConfig.Ch1_Option = 0x3; + mupd->FspmConfig.Ch1_OdtConfig = 0x0; + mupd->FspmConfig.Ch1_TristateClk1 = 0x0; + mupd->FspmConfig.Ch1_Mode2N = 0x0; + mupd->FspmConfig.Ch1_OdtLevels = 0x0; + mupd->FspmConfig.Ch2_RankEnable = 0x3; + mupd->FspmConfig.Ch2_DeviceWidth = 0x1; + mupd->FspmConfig.Ch2_DramDensity = 0x2; + mupd->FspmConfig.Ch2_Option = 0x3; + mupd->FspmConfig.Ch2_OdtConfig = 0x0; + mupd->FspmConfig.Ch2_TristateClk1 = 0x0; + mupd->FspmConfig.Ch2_Mode2N = 0x0; + mupd->FspmConfig.Ch2_OdtLevels = 0x0; + mupd->FspmConfig.Ch3_RankEnable = 0x3; + mupd->FspmConfig.Ch3_DeviceWidth = 0x1; + mupd->FspmConfig.Ch3_DramDensity = 0x2; + mupd->FspmConfig.Ch3_Option = 0x3; + mupd->FspmConfig.Ch3_OdtConfig = 0x0; + mupd->FspmConfig.Ch3_TristateClk1 = 0x0; + mupd->FspmConfig.Ch3_Mode2N = 0x0; + mupd->FspmConfig.Ch3_OdtLevels = 0x0; + mupd->FspmConfig.RmtCheckRun = 0x0; + mupd->FspmConfig.MrcDataSaving = 0x1; + mupd->FspmConfig.MrcFastBoot = 0x1; + + memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + mupd->FspmConfig.MsgLevelMask = 0x0; + + /* Request FSP to load the coreboot primary CBFS */ + mupd->FspmConfig.OemLoadingBase = CONFIG_OBB_ROM_BASE; + strcpy((char *)mupd->FspmConfig.OemFileName, "OBB"); + +}

1 0

New patch to review for coreboot: soc/intel/apollolake: add Multiple FMAP build
by Brenton Dong 19 Oct '16

19 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17064 -gerrit commit f12eabf318f9969df36e91bf15707303ade03667 Author: brenton <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:21:12 2016 -0700 soc/intel/apollolake: add Multiple FMAP build Multiple coreboot binaries with separate FMAPs and separate CBFSs allow coreboot to run separate stages from different regions (SRAM, CAR, Mem) When enabling Multiple FMAP, 3 Coreboot Images will be created. IBBL: Contains bootblock, CAR init (FSP-T) and hands off to IBBM IBBM: Contains romstage, Mem Init (FSP-M) and postcar OBB: Contains ramstage, Silicon Init (FSP-S), and the rest of the components in the original single coreboot.rom file. This is the same image as the original coreboot.rom minus the components moved to the IBBL and IBBM Add functions to select which region cbfs files will be loaded from Verified on Intel LeafHill CRB and confirmed that the coreboot builds 3 separate coreboot files which can be loaded and booted. Verified that other ApolloLake projects can build correctly with this option disabled. Change-Id: Iab3c353b65e1e0fc9d04fcee6a82a330927db41e Signed-off-by: brenton <brenton.m.dong(a)intel.com> --- Makefile.inc | 47 ++++++++++ src/arch/x86/Makefile.inc | 2 + src/drivers/intel/fsp2_0/Makefile.inc | 5 + src/soc/intel/apollolake/Kconfig | 6 ++ src/soc/intel/apollolake/Makefile.inc | 4 + src/soc/intel/apollolake/bootblock/bootblock.c | 57 ++++++++++++ src/soc/intel/apollolake/chip.c | 9 +- src/soc/intel/apollolake/include/soc/bootregion.h | 28 ++++++ src/soc/intel/apollolake/include/soc/cse.h | 30 ++++++ src/soc/intel/apollolake/include/soc/mmio.h | 35 +++++++ src/soc/intel/apollolake/mmap_boot.c | 2 + src/soc/intel/apollolake/mmap_boot_cse.c | 53 +++++++++++ src/soc/intel/apollolake/postcar.c | 10 ++ src/soc/intel/apollolake/romstage.c | 108 ++++++++++++++++++++++ 14 files changed, 395 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc old mode 100644 new mode 100755 index 127f372..9e25883 --- a/Makefile.inc +++ b/Makefile.inc @@ -826,11 +826,13 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) ifeq ($(CONFIG_ARCH_X86),y) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) $(CBFSTOOL) $@.tmp add \ -f $(objcbfs)/bootblock.bin \ -n bootblock \ -t bootblock \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) +endif # ifeq ($(CONFIG_MULTIPLE_FMAP),y) else # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ @@ -865,6 +867,49 @@ $(REFCODE_BLOB): $(RMODTOOL) $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ endif + +ifeq ($(CONFIG_MULTIPLE_FMAP),y) + +.PHONY:$(obj)/coreboot_ibbl.rom +$(obj)/coreboot_ibbl.rom: $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(obj)/ibbl_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbl_fmap.fmap -r $(shell cat $(obj)/ibbl_fmap.desc) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_T_FILE)) \ + -n blobs/fspt.bin -t fsp -y -b 0xC0 + mv $@.tmp $@ + @printf "\ncoreboot IBBL image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +.PHONY:$(obj)/coreboot_ibbm.rom +$(obj)/coreboot_ibbm.rom: $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(objcbfs)/romstage.elf \ + $(objcbfs)/postcar.elf \ + $(obj)/ibbm_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbm_fmap.fmap -r $(shell cat $(obj)/ibbm_fmap.desc) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/romstage.elf \ + -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ + $(CBFSTOOL_PRE_OPTS) -b 0 + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_M_FILE)) \ + -n blobs/fspm.bin -t fsp -y + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/postcar.elf \ + -n $(CONFIG_CBFS_PREFIX)/postcar + mv $@.tmp $@ + @printf "\ncoreboot IBBM image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +coreboot: $(obj)/coreboot_ibbl.rom $(obj)/coreboot_ibbm.rom + +endif # ifneq ($(CONFIG_MULTIPLE_FMAP),y) + $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty @@ -892,6 +937,7 @@ endif @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage-type := stage @@ -924,6 +970,7 @@ endif # CONFIG_NO_FIXED_XIP_ROM_SIZE endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 +endif # CONFIG_MULTIPLE_FMAP cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc old mode 100644 new mode 100755 index 782ca63..fc7eb5c --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -300,10 +300,12 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ # Add postcar to CBFS +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage $(CONFIG_CBFS_PREFIX)/postcar-compression := none +endif #CONFIG_MULTIPLE_FMAP ############################################################################### # ramstage diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 87d2be5..7d14d02 100755 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -45,6 +45,8 @@ CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +ifneq ($(CONFIG_MULTIPLE_FMAP),y) + ifeq ($(CONFIG_FSP_CAR),y) cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_T_CBFS) $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) @@ -57,6 +59,9 @@ endif # CONFIG_FSP_CAR cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp + +endif #CONFIG_MULTIPLE_FMAP + ifeq ($(CONFIG_FSP_M_XIP),y) $(CONFIG_FSP_M_CBFS)-options := --xip endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig old mode 100644 new mode 100755 index 6c178c3..eeba42a --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -81,6 +81,12 @@ config TPM_ON_FAST_SPI TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. +config MULTIPLE_FMAP + depends on FSP_CAR + bool + help + Enable build with mulitple coreboot images and each will has its own fmap. + config SOC_INTEL_COMMON_RESET bool default y diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index c2bbc11..b73f532 100755 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -15,6 +15,7 @@ bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += itss.c bootblock-y += lpc_lib.c +bootblock-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c bootblock-y += mmap_boot.c bootblock-y += pmutil.c bootblock-y += spi.c @@ -37,6 +38,7 @@ romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c romstage-y += memmap.c romstage-y += meminit.c +romstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c romstage-y += mmap_boot.c romstage-y += tsc_freq.c romstage-y += pmutil.c @@ -65,6 +67,7 @@ ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += lpc.c ramstage-y += lpc_lib.c ramstage-y += memmap.c +ramstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c ramstage-y += mmap_boot.c ramstage-y += p2sb.c ramstage-y += uart.c @@ -81,6 +84,7 @@ ramstage-y += spi.c ramstage-y += xhci.c postcar-y += memmap.c +postcar-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c old mode 100644 new mode 100755 index 28a9128..22a4d44 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -14,6 +14,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include <string.h> #include <arch/cpu.h> #include <bootblock_common.h> #include <cpu/x86/mtrr.h> @@ -31,6 +32,53 @@ #include <spi-generic.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm0(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_num; + uint32_t state; + msr_t msr; + + /* Request data from CSE */ + host_to_cse = (ibbm_size << 4) | 0xC0000000; + CSE_HOST2CSE = host_to_cse; + + /* Wait for response */ + do { + cse_to_host = CSE_CSE2HOST; + chunk_num = (cse_to_host >> 28) & 3; + } while (!chunk_num); + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* + * The 1st 128K should have been loaded into SRAM now + * However, since the top 32K IBBL is still cached, we can only read + * (128-32)K at this moment. The remaining will be read in romstage. + */ + memcpy((void *)ibbm_base, (void *)(~CSE_IBB_SRAM_SIZE + 1), + CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE); + + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + the temporary memory */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + static const struct pad_config tpm_spi_configs[] = { PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ }; @@ -92,6 +140,15 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp) enable_cmos_upper_bank(); +#if CONFIG_MULTIPLE_FMAP + /* Loading IBBM into CAR */ + load_ibbm0(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE, CONFIG_IBBM_ROM_SIZE); + + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); +#endif //CONFIG_MULTIPLE_FMAP + /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(base_timestamp); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c old mode 100644 new mode 100755 index d722992..0a184eb --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -35,9 +35,12 @@ #include <soc/pm.h> #include <soc/p2sb.h> #include <soc/northbridge.h> - #include "chip.h" +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif /* CONFIG_MULTIPLE_FMAP */ + static void *vbt; static struct region_device vbt_rdev; @@ -267,6 +270,10 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_OBB); +#endif //CONFIG_MULTIPLE_FMAP + fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ diff --git a/src/soc/intel/apollolake/include/soc/bootregion.h b/src/soc/intel/apollolake/include/soc/bootregion.h new file mode 100755 index 0000000..dde562a --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootregion.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_BOOT_RGN_H_ +#define _SOC_LEAFHILL_BOOT_RGN_H_ + +#define BOOT_REGION_IBBL 0 +#define BOOT_REGION_IBBM 1 +#define BOOT_REGION_OBB 2 + +/* Set current active boot region */ +void set_boot_region(int region_id); + +#endif /* _SOC_LEAFHILL_BOOT_RGN_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/cse.h b/src/soc/intel/apollolake/include/soc/cse.h new file mode 100755 index 0000000..ed2b136 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cse.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_CSE_H_ +#define _SOC_LEAFHILL_CSE_H_ + +#define HOST2CSE 0x70 +#define CSE2HOST 0x60 +#define CSE_IBB_SRAM_SIZE 0x20000 + +#define CSE_CFG_BASE (CONFIG_MMCONF_BASE_ADDRESS + 0x78000) +#define CSE_VIDDID (*(volatile int32_t *)CSE_CFG_BASE) +#define CSE_HOST2CSE (*(volatile int32_t *)(CSE_CFG_BASE + HOST2CSE)) +#define CSE_CSE2HOST (*(volatile int32_t *)(CSE_CFG_BASE + CSE2HOST)) + +#endif /* _SOC_LEAFHILL_CSE_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/mmio.h b/src/soc/intel/apollolake/include/soc/mmio.h new file mode 100755 index 0000000..674e071 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/mmio.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMIO_H_ +#define _SOC_MMIO_H_ + + +#define MmioRead32(x) (*(volatile uint32_t *)(unsigned int)(x)) +#define MmioWrite32(x, y) (*(volatile uint32_t *)(unsigned int)(x) = y) +#define MmioRead16(x) (*(volatile uint16_t *)(unsigned int)(x)) +#define MmioWrite16(x, y) (*(volatile uint16_t *)(unsigned int)(x) = y) +#define MmioRead8(x) (*(volatile uint8_t *)(unsigned int)(x)) +#define MmioWrite8(x, y) (*(volatile uint8_t *)(unsigned int)(x) = y) + +#define PCIE_MMIO(Bus, Device, Function, Register) \ + ((unsigned int)CONFIG_MMCONF_BASE_ADDRESS + \ + (unsigned int)(Bus << 20) + \ + (unsigned int)(Device << 15) + \ + (unsigned int)(Function << 12) + \ + (unsigned int)(Register) \ + ) + +#endif diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c old mode 100644 new mode 100755 index bf2e5b9..994f7b8 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -113,6 +113,7 @@ static void bios_mmap_init(void) car_set_var(bios_size, size); } +#if !CONFIG_MULTIPLE_FMAP const struct region_device *boot_device_ro(void) { bios_mmap_init(); @@ -122,6 +123,7 @@ const struct region_device *boot_device_ro(void) return &real_dev_ptr->rdev; } +#endif //CONFIG_MULTIPLE_FMAP static int iafw_boot_region_properties(struct cbfs_props *props) { diff --git a/src/soc/intel/apollolake/mmap_boot_cse.c b/src/soc/intel/apollolake/mmap_boot_cse.c new file mode 100755 index 0000000..d5b4526 --- /dev/null +++ b/src/soc/intel/apollolake/mmap_boot_cse.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> +#include <soc/bootregion.h> +#include <soc/intel/common/nvm.h> +#include <arch/early_variables.h> + +/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ +#define rom_base(x) (void *)(uintptr_t)(-(int32_t)(x)) +#define IBBL_ROM_BASE rom_base(CONFIG_IBBL_ROM_SIZE) +#define IBBM_ROM_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ + - CONFIG_IBBM_ROM_SIZE) + +static int curr_boot_region CAR_GLOBAL; + +static const struct mem_region_device boot_dev[] = { + MEM_REGION_DEV_RO_INIT(IBBL_ROM_BASE, CONFIG_IBBL_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(IBBM_ROM_BASE, CONFIG_IBBM_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(CONFIG_RAMTOP, CONFIG_ROM_SIZE) +}; + +#if CONFIG_MULTIPLE_FMAP +const struct region_device *boot_device_ro(void) +{ + return &boot_dev[car_get_var(curr_boot_region)].rdev; +} +#endif //CONFIG_MULTIPLE_FMAP + +void set_boot_region(int rgn_idx) +{ + if (rgn_idx < sizeof(boot_dev)/sizeof(boot_dev[0])) + car_set_var(curr_boot_region, rgn_idx); +} diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c index 0b0e4ca..7c24fe9 100755 --- a/src/soc/intel/apollolake/postcar.c +++ b/src/soc/intel/apollolake/postcar.c @@ -23,9 +23,19 @@ #include <soc/postcar.h> #include <boot_device.h> +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif + void post_car_main(void) { +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_IBBM); + temp_ram_exit(); + set_boot_region(BOOT_REGION_OBB); +#else temp_ram_exit(); +#endif /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c old mode 100644 new mode 100755 index 1f6a38f..69d7273 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -41,6 +41,12 @@ #include <string.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <cpu/x86/msr.h> +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + static struct chipset_power_state power_state CAR_GLOBAL; /* High Performance Event Timer Configuration */ @@ -100,6 +106,92 @@ static void migrate_power_state(int is_recovery) } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm1(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t state; + uint32_t size; + uint8_t ring_idx; + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_idx; + uint32_t chunk_size; + uint32_t chunk_num; + uint32_t ibb_remaining; + uint8_t *src; + uint8_t *dst; + uint8_t *ptr; + msr_t msr; + + /* Set IBBL cache to UC */ + msr = rdmsr(0x202); + msr.lo &= ~0x0f; + wrmsr(0x202, msr); + + /* Init variables */ + size = CONFIG_IBBL_ROM_SIZE; + dst = (uint8_t *)ibbm_base; + src = (uint8_t *)(~CONFIG_IBBL_ROM_SIZE + 1); + memcpy(dst, src, size); + + cse_to_host = CSE_CSE2HOST; + host_to_cse = CSE_HOST2CSE; + chunk_num = (cse_to_host >> 28) & 3; + if (chunk_num == 3) + chunk_num = 4; + chunk_size = CSE_IBB_SRAM_SIZE / chunk_num; + chunk_idx = chunk_num; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~0x0f) | (cse_to_host & 0x0f); + CSE_HOST2CSE = host_to_cse; + + ibb_remaining = ibbm_size - size; + while (ibb_remaining > 0) { + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* Calculate ring index */ + ring_idx = (uint8_t)(chunk_idx % chunk_num); + if (state & (1 << ring_idx)) { + /* Calculate source and dest. address in ring buffer */ + src += chunk_size; + dst += chunk_size; + if (src == 0) + src = (uint8_t *)(~CSE_IBB_SRAM_SIZE + 1); + if (ibb_remaining < chunk_size) + size = ibb_remaining; + else + size = chunk_size; + + /* Move data from SRAM into temporary memory */ + memcpy(dst, src, size); + ibb_remaining -= size; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~(1 << ring_idx)) | + (cse_to_host & (1 << ring_idx)); + CSE_HOST2CSE = host_to_cse; + + chunk_idx++; + } + } + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + * the temporary memory + */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -109,6 +201,10 @@ asmlinkage void car_stage_entry(void) void *smm_base; size_t smm_size; uintptr_t tseg_base; +#if CONFIG_MULTIPLE_FMAP + uint32_t ibbm_base; + uint32_t ibbm_loaded; +#endif //CONFIG_MULTIPLE_FMAP timestamp_add_now(TS_START_ROMSTAGE); @@ -117,6 +213,18 @@ asmlinkage void car_stage_entry(void) console_init(); +#if CONFIG_MULTIPLE_FMAP + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); + + /* load the remaining IBBM */ + ibbm_loaded = CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE; + ibbm_base = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE; + load_ibbm1(ibbm_base + ibbm_loaded, + CONFIG_IBBM_ROM_SIZE - ibbm_loaded); +#endif //CONFIG_MULTIPLE_FMAP + s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1*KiB))

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New patch to review for coreboot: soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
by Brenton Dong 19 Oct '16

19 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17063 -gerrit commit ab9b777862fa47f9421483cee3a47f4b69fbce89 Author: brenton <brenton.m.dong(a)intel.com> Date: Tue Oct 18 13:57:54 2016 -0700 soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to Initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel LeafHill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without Coreboot implementation of CAR init/teardown Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: brenton <brenton.m.dong(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 15 +++- .../intel/apollolake/bootblock/cache_as_ram_FSP.S | 98 ++++++++++++++++++++++ src/soc/intel/apollolake/exit_car_FSP.S | 29 +++++++ src/soc/intel/apollolake/include/soc/postcar.h | 26 ++++++ src/soc/intel/apollolake/postcar.c | 34 ++++++++ 5 files changed, 200 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc old mode 100644 new mode 100755 index 4f867e1..c2bbc11 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += gpio.c @@ -22,6 +21,12 @@ bootblock-y += spi.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ifeq ($(CONFIG_FSP_CAR),y) +bootblock-y += bootblock/cache_as_ram_FSP.S +else +bootblock-y += bootblock/cache_as_ram.S +endif + romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c @@ -75,13 +80,19 @@ ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c -postcar-y += exit_car.S postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +ifeq ($(CONFIG_FSP_CAR),y) +postcar-y += exit_car_FSP.S +postcar-y += postcar.c +else +postcar-y += exit_car.S +endif + verstage-y += car.c verstage-y += i2c_early.c verstage-y += heci.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_FSP.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_FSP.S new file mode 100755 index 0000000..d8929c6 --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram_FSP.S @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/cpu.h> + +#include <../../../arch/x86/walkcbfs.S> + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add $0x94, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebx), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + nop + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Microcode Location */ + .long 0 /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_IBBL_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_IBBL_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "blobs/fspt.bin\x00" diff --git a/src/soc/intel/apollolake/exit_car_FSP.S b/src/soc/intel/apollolake/exit_car_FSP.S new file mode 100755 index 0000000..e3a7b36 --- /dev/null +++ b/src/soc/intel/apollolake/exit_car_FSP.S @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +#include <soc/cpu.h> + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov $CONFIG_RAMTOP, %esp + + /* Call C code */ + call post_car_main diff --git a/src/soc/intel/apollolake/include/soc/postcar.h b/src/soc/intel/apollolake/include/soc/postcar.h new file mode 100755 index 0000000..7e31def --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/postcar.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_POSTCAR_H_ +#define _SOC_APOLLOLAKE_POSTCAR_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +void post_car_main(void); + +#endif /* _SOC_APOLLOLAKE_POSTCAR_H_ */ diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c new file mode 100755 index 0000000..0b0e4ca --- /dev/null +++ b/src/soc/intel/apollolake/postcar.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <string.h> +#include <cbmem.h> +#include <arch/cpu.h> +#include <arch/stages.h> +#include <fsp/util.h> +#include <soc/postcar.h> +#include <boot_device.h> + +void post_car_main(void) +{ + temp_ram_exit(); + + /* Recover cbmem so infrastruture using it is functional. */ + cbmem_initialize(); + + copy_and_run(); +}

1 0

New patch to review for coreboot: drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support
by Brenton Dong 19 Oct '16

19 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17062 -gerrit commit 0d1c39bf83a66fa7bfc533c6e843e1541a6725f0 Author: brenton <brenton.m.dong(a)intel.com> Date: Tue Oct 18 11:35:15 2016 -0700 drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs Verified on Intel LeafHill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without Coreboot implementation of CAR init/teardown Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: brenton <brenton.m.dong(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 17 ++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 11 +++++ src/drivers/intel/fsp2_0/include/fsp/api.h | 1 + src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 + src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/temp_ram_exit.c | 50 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/util.c | 2 + 7 files changed, 84 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig old mode 100644 new mode 100755 index 3ffb402..62bdd50 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -53,6 +53,11 @@ config DISPLAY_UPD_DATA Display the user specified product data prior to memory initialization. +config FSP_T_CBFS + string "Name of FSP-T in CBFS" + depends on FSP_CAR + default "fspt.bin" + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" @@ -61,6 +66,12 @@ config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" +config FSP_T_FILE + string "Intel FSP-T (temp ram init) binary path and filename" + depends on FSP_CAR + help + The path and filename of the Intel FSP-M binary for this platform. + config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES @@ -73,6 +84,12 @@ config FSP_S_FILE help The path and filename of the Intel FSP-S binary for this platform. +config FSP_CAR + bool "Use FSP TempRamInit & TempRamExit APIs" + default n + help + Use FSP APIs to initialize & Tear Down the Cache-As-Ram + config FSP_M_XIP bool "Is FSP-M XIP" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc old mode 100644 new mode 100755 index beeec7c..87d2be5 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -38,11 +38,22 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c +postcar-$(CONFIG_FSP_CAR) += util.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +ifeq ($(CONFIG_FSP_CAR),y) +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_T_CBFS) +$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) +$(CONFIG_FSP_T_CBFS)-type := fsp +ifeq ($(CONFIG_FSP_T_XIP),y) +$(CONFIG_FSP_T_CBFS)-options := --xip +endif +endif # CONFIG_FSP_CAR + cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h old mode 100644 new mode 100755 index 553fc52..61a5140 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -39,6 +39,7 @@ enum fsp_notify_phase { /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); +uint32_t temp_ram_exit(void); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h old mode 100644 new mode 100755 index 6351b32..c84c33e --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -34,6 +34,8 @@ struct fsp_header { uint16_t component_attribute; size_t cfg_region_offset; size_t cfg_region_size; + size_t temp_ram_init_entry; + size_t temp_ram_exit_entry; size_t notify_phase_entry_offset; size_t memory_init_entry_offset; size_t silicon_init_entry_offset; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 04f8c00..13c6ab2 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -101,6 +101,7 @@ void fsp_handle_reset(uint32_t status); /* SoC/chipset must provide this to handle platform-specific reset codes */ void chipset_handle_reset(uint32_t status); +typedef asmlinkage uint32_t (*temp_ram_exit_fn)(void *param); typedef asmlinkage uint32_t (*fsp_memory_init_fn) (void *raminit_upd, void **hob_list); typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c new file mode 100755 index 0000000..1bf1e24 --- /dev/null +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> + +#include <cbfs.h> + +uint32_t temp_ram_exit(void) +{ + struct fsp_header hdr; + uint32_t status; + temp_ram_exit_fn fsp_temp_ram_exit; + struct cbfsf file_desc; + struct region_device file_data; + const char *name = CONFIG_FSP_M_CBFS; + + if (cbfs_boot_locate(&file_desc, name, NULL)) { + printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); + die("FSPM not available for CAR Exit!\n"); + } + + cbfs_file_data(&file_data, &file_desc); + + if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS) + return CB_ERR; + + fsp_temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); + printk(BIOS_DEBUG, "Calling TempRamExit: 0x%p\n", fsp_temp_ram_exit); + status = fsp_temp_ram_exit(NULL); + printk(BIOS_DEBUG, "TempRamExit returned 0x%08x\n", status); + + return status; +} diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c old mode 100644 new mode 100755 index e7e4f16..7453b59 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -52,6 +52,8 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) hdr->component_attribute = read16(raw_hdr + 34); hdr->cfg_region_offset = read32(raw_hdr + 36); hdr->cfg_region_size = read32(raw_hdr + 40); + hdr->temp_ram_init_entry = read32(raw_hdr + 48); + hdr->temp_ram_exit_entry = read32(raw_hdr + 64); hdr->notify_phase_entry_offset = read32(raw_hdr + 56); hdr->memory_init_entry_offset = read32(raw_hdr + 60); hdr->silicon_init_entry_offset = read32(raw_hdr + 68);

1 0

Patch set updated for coreboot: RISCV: Clean up the common architectural code
by Ronald G. Minnich 19 Oct '16

19 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17058 -gerrit commit 54a36c9805a8c06446bcf951900f24aa8ffcdc25 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Oct 19 08:07:13 2016 -0700 RISCV: Clean up the common architectural code We provide a standard payload that makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 1 + src/arch/riscv/boot.c | 4 ++++ src/arch/riscv/include/vm.h | 10 ---------- src/arch/riscv/payload.S | 35 +++++++++++++++++++++++++++++++++++ src/arch/riscv/trap_handler.c | 1 + src/arch/riscv/virtual_memory.c | 41 ++++++++++++++++++++++++++++++----------- 6 files changed, 71 insertions(+), 21 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 4bab459..cf6ce99 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -96,6 +96,7 @@ ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += sbi.S +ramstage-y += payload.S ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 7435490..35a9123 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <lib.h> #include <program_loading.h> #include <vm.h> #include <arch/encoding.h> @@ -21,9 +22,12 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); + void riscvpayload(void); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { + hexdump((void *)0x81000000, 128); initVirtualMemory(); + riscvpayload(); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index bee2ed4..6472cad 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -37,16 +37,6 @@ #define VA_BITS 39 #define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) -#define PROT_READ 1 -#define PROT_WRITE 2 -#define PROT_EXEC 4 - -#define MAP_PRIVATE 0x2 -#define MAP_FIXED 0x10 -#define MAP_ANONYMOUS 0x20 -#define MAP_POPULATE 0x8000 -#define MREMAP_FIXED 0x2 - #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S new file mode 100644 index 0000000..bc9654a --- /dev/null +++ b/src/arch/riscv/payload.S @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .global riscvpayload +riscvpayload: + /* Jump to 0xffffffff81000000 in S-mode */ + li t0, 0xffffffff81000000 + csrw mepc, t0 + csrr t0, mstatus + li t1, ~(3<<11) + and t0, t0, t1 + li t2, (1<<11) + or t0, t0, t2 + csrw mstatus, t0 + +#if 0 // remove for testing. +.L2: + li a5,1107296256 + li a4,48 + sw a4,0(a5) + j .L2 +#endif + // We're still in toolchain no mans land. + .word 0x30200073 + //mret diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index ad49928..d2b05bd 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -163,6 +163,7 @@ void trap_handler(trapframe *tf) { break; } + //print_page_table(); die("Can't recover from trap. Halting.\n"); } diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index be8b488..8b75a3d 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -94,7 +94,7 @@ static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level) /* Print the page table structures to the console */ void print_page_table(void) { - print_page_table_at(root_page_table, 0, 0); + print_page_table_at((void *)(read_csr(sptbr) << RISCV_PGSHIFT), 0, 0); } void flush_tlb(void) @@ -115,9 +115,9 @@ pte_t ptd_create(uintptr_t ppn) pte_t pte_create(uintptr_t ppn, int prot, int user) { pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_R | PTE_V; - if (prot & PROT_WRITE) + if (prot & PTE_W) pte |= PTE_W; - if (prot & PROT_EXEC) + if (prot & PTE_X) pte |= PTE_X; if (user) pte |= PTE_U; @@ -147,21 +147,32 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); l2_idx += ((vaddr - virtMemStart) >> l2_shift); - middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, PROT_READ|PROT_WRITE|PROT_EXEC, 0); + middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, + PTE_R|PTE_W|PTE_X, 0); } // map SBI at top of vaddr space - uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface + // only need to map a single page for sbi interface + uintptr_t num_sbi_pages = 1; uintptr_t sbiStartAddress = (uintptr_t) &sbi_page; uintptr_t sbiAddr = sbiStartAddress; for (uintptr_t i = 0; i < num_sbi_pages; i++) { uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; - sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, PROT_READ|PROT_EXEC, 0); + sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, + PTE_R|PTE_X, 0); sbiAddr += RISCV_PGSIZE; } pte_t* sbi_pte = middle_pt + ((num_middle_pts << RISCV_PGLEVEL_BITS)-1); *sbi_pte = ptd_create((uintptr_t)sbi_pt >> RISCV_PGSHIFT); + // IO space. + root_pt[0] = pte_create(0, PTE_W|PTE_R, 0); + root_pt[1] = pte_create(0x40000000>>RISCV_PGSHIFT, + PTE_W|PTE_R, 0); + + // Start of RAM + root_pt[2] = pte_create(0x80000000>>RISCV_PGSHIFT, + PTE_W|PTE_R, 0); mb(); root_page_table = root_pt; uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT; @@ -185,12 +196,14 @@ void initVirtualMemory(void) { printk(BIOS_DEBUG, "-----------------------------\n"); } + // TODO: Figure out how to grab this from cbfs printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x90000000; // TODO: Figure out how to grab this from cbfs - uintptr_t virtualStart = 0xffffffff80000000; - uintptr_t pageTableStart = 0x91400000; + uintptr_t physicalStart = 0x81000000; + uintptr_t virtualStart = 0xffffffff81000000; + uintptr_t pageTableStart = 0x80800000; init_vm(virtualStart, physicalStart, pageTableStart); mb(); + flush_tlb(); #if IS_ENABLED(CONFIG_DEBUG_PRINT_PAGE_TABLES) printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); @@ -211,6 +224,7 @@ void mstatus_init(void) set_csr(mie, MIP_MSIP); /* Configure which exception causes are delegated to supervisor mode */ +/* set_csr(medeleg, (1 << CAUSE_MISALIGNED_FETCH) | (1 << CAUSE_FAULT_FETCH) | (1 << CAUSE_ILLEGAL_INSTRUCTION) @@ -220,7 +234,12 @@ void mstatus_init(void) | (1 << CAUSE_USER_ECALL) ); +*/ /* Enable all user/supervisor-mode counters */ - write_csr(mscounteren, 0b111); - write_csr(mucounteren, 0b111); + /* We'll turn these on once lowrisc gets their bitstream up to + * 1.9. Right now there's no agreement on the values for these + * architectural registers. + */ + //write_csr(mscounteren, 0b111); + //write_csr(mucounteren, 0b111); }

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coreboot-gerrit October 2016