coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: nb/i945/gma.c: Do not try to load vbios when selecting native init
by Arthur Heymans 20 Oct '16

20 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17075 -gerrit commit 718f0aca8483d83d97df9f9bb0ebfabc3a1fea74 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 20 20:18:12 2016 +0200 nb/i945/gma.c: Do not try to load vbios when selecting native init This fixes a typo introduced in 9c5fc62f: "nb/i945/gma.c: use IS_ENABLED instead of #if, #endif". Change-Id: I2c9ca796767a507483c32867f9b7f172842a1ab3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 4baed80..3e68aa3 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -594,7 +594,7 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { + if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI Init, will run VBIOS */ pci_dev_init(dev); }

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Patch merged into coreboot/master: util/inteltool: Remove unnecessary whitespace
by gerrit＠coreboot.org 20 Oct '16

20 Oct '16

the following patch was just integrated into master: commit de2918bd1a4af616ca60833e66850fda9340826e Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 19 18:13:55 2016 +0200 util/inteltool: Remove unnecessary whitespace Change-Id: Id42a2901cf76e6b867f62a752a38bbd6f6e5f54e Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/17059 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Martin Roth <martinroth(a)google.com> See https://review.coreboot.org/17059 for details. -gerrit

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Patch merged into coreboot/master: util/inteltool: Use tabs for indents
by gerrit＠coreboot.org 20 Oct '16

20 Oct '16

the following patch was just integrated into master: commit 94501508922c9c7f0c141ce0440f64d800a35a28 Author: Elyes HAOUAS <ehaouas(a)noos.fr> Date: Wed Oct 19 17:59:10 2016 +0200 util/inteltool: Use tabs for indents Change-Id: I9d27c276053c51021166f4b22d150060e415d08f Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> Reviewed-on: https://review.coreboot.org/17025 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> See https://review.coreboot.org/17025 for details. -gerrit

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Patch set updated for coreboot: lars/kunimitsu: Add other sensor in _ART for fan control
by Sumeet R Pawnikar 20 Oct '16

20 Oct '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17066 -gerrit commit 94cb987f3ccf327bd2cae8266e97710869a031ac Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Oct 18 10:22:52 2016 +0530 lars/kunimitsu: Add other sensor in _ART for fan control This patch updates the _ART table with other external sensor TSR0 for Fan speed control on Skylake-U based Kunimitsu and Lars boards. Also, updates the temperature values in DPTF policy for better performance. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on kunimitsu and lars EVT boards. Verified this updated _ART table on these boards with different workloads. Change-Id: Ib195910c5eb00e004e8b9bd50e266ade3c175be2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/332349 --- src/mainboard/google/lars/acpi/dptf.asl | 30 +++++++++++++++---------- src/mainboard/intel/kunimitsu/acpi/dptf.asl | 34 ++++++++++++++++++----------- 2 files changed, 40 insertions(+), 24 deletions(-) diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl index 7fcf567..b8f0a7a 100644 --- a/src/mainboard/google/lars/acpi/dptf.asl +++ b/src/mainboard/google/lars/acpi/dptf.asl @@ -14,28 +14,32 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_PASSIVE 95 #define DPTF_CPU_CRITICAL 99 #define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 70 -#define DPTF_CPU_ACTIVE_AC3 60 -#define DPTF_CPU_ACTIVE_AC4 50 +#define DPTF_CPU_ACTIVE_AC1 77 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_ACTIVE_AC0 120 +#define DPTF_TSR0_ACTIVE_AC1 110 +#define DPTF_TSR0_ACTIVE_AC2 47 +#define DPTF_TSR0_ACTIVE_AC3 44 +#define DPTF_TSR0_ACTIVE_AC4 41 +#define DPTF_TSR0_ACTIVE_AC5 38 +#define DPTF_TSR0_ACTIVE_AC6 35 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_PASSIVE 63 +#define DPTF_TSR1_CRITICAL 68 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_PASSIVE 64 +#define DPTF_TSR2_CRITICAL 69 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -79,8 +83,12 @@ Name (DART, Package () { * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0, 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40, + 35, 0, 0, 0 } }) #endif diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl index e011c97..b2bfe88 100644 --- a/src/mainboard/intel/kunimitsu/acpi/dptf.asl +++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl @@ -14,28 +14,32 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 70 -#define DPTF_CPU_ACTIVE_AC3 60 -#define DPTF_CPU_ACTIVE_AC4 50 +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 77 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_ACTIVE_AC0 120 +#define DPTF_TSR0_ACTIVE_AC1 110 +#define DPTF_TSR0_ACTIVE_AC2 47 +#define DPTF_TSR0_ACTIVE_AC3 44 +#define DPTF_TSR0_ACTIVE_AC4 41 +#define DPTF_TSR0_ACTIVE_AC5 38 +#define DPTF_TSR0_ACTIVE_AC6 35 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_PASSIVE 63 +#define DPTF_TSR1_CRITICAL 68 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_PASSIVE 64 +#define DPTF_TSR2_CRITICAL 69 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -79,8 +83,12 @@ Name (DART, Package () { * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0, 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40, + 35, 0, 0, 0 } }) #endif

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Patch merged into coreboot/master: kunimitsu: Add choice to select FSP driver
by gerrit＠coreboot.org 20 Oct '16

20 Oct '16

the following patch was just integrated into master: commit 124a368702b111442e26b5a3db65ebf8e5c6816c Author: Naresh G Solanki <naresh.solanki(a)intel.com> Date: Tue Oct 18 07:19:36 2016 +0530 kunimitsu: Add choice to select FSP driver Add choice to select between FSP 1.1 & FSP2.0 driver to be used. Change-Id: Ied7eab6f4a2191e0bcf220cde5ca519a3c3e2d76 Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Reviewed-on: https://review.coreboot.org/17051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17051 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: add snappy variant
by gerrit＠coreboot.org 20 Oct '16

20 Oct '16

the following patch was just integrated into master: commit 084a343b58d7effadb8f2c226c183cdb8cf2a351 Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Mon Oct 17 18:30:54 2016 +0800 mainboard/google/reef: add snappy variant Create the initial Snappy variant which refers to the Reef device. Snappy, an Apollolake-platform, is deviated from reference board Reef. BRANCH=master BUG=None TEST=Built & booted Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6 Reviewed-on: https://review.coreboot.org/17043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17043 for details. -gerrit

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Patch set updated for coreboot: [DON'T MERGE] Investigating CL #16987
by Jonathan Neuschäfer 20 Oct '16

20 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17060 -gerrit commit c71dc80c9c5d84d81ef5cf58c5f9206bd05dbf3e Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Wed Oct 19 02:18:54 2016 +0200 [DON'T MERGE] Investigating CL #16987 https://review.coreboot.org/#/c/16987/ results in a crash in AMDFWTOOL for some boards, on jenkins. With this patch, I try to figure out what's going on. Change-Id: Ic36b8be2b0ee458311dcc8e9139df2b4d113b4ba Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- Makefile.inc | 2 +- src/mainboard/emulation/Kconfig | 1 + src/southbridge/amd/pi/hudson/Makefile.inc | 3 +++ util/abuild/abuild | 2 +- util/amdfwtool/amdfwtool.c | 4 ++++ 5 files changed, 10 insertions(+), 2 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 127f372..f95488c 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -487,7 +487,7 @@ $(IFDFAKE): $(top)/util/ifdfake/ifdfake.c AMDFWTOOL:=$(objutil)/amdfwtool/amdfwtool $(AMDFWTOOL): $(top)/util/amdfwtool/amdfwtool.c @printf " HOSTCC $(subst $(obj)/,,$(@))\n" - $(HOSTCC) $(HOSTCFLAGS) -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< + $(HOSTCC) $(HOSTCFLAGS) -fsanitize=address -DCONFIG_ROM_SIZE=$(CONFIG_ROM_SIZE) -o $@ $< CBOOTIMAGE:=$(objutil)/cbootimage/cbootimage diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 1dc89ca..bd0a807 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -2,6 +2,7 @@ if VENDOR_EMULATION choice prompt "Mainboard model" + #default BOARD_EMULATION_QEMU_X86_I440FX source "src/mainboard/emulation/*/Kconfig.name" diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 291e25f..107be69 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -206,6 +206,8 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(AMDFWTOOL) rm -f $@ @printf " AMDFWTOOL $(subst $(obj)/,,$(@))\n" + @printf " HOSTCC version: " + $(HOSTCC) --version $(AMDFWTOOL) \ $(OPT_HUDSON_XHCI_FWM_FILE) \ $(OPT_HUDSON_IMC_FWM_FILE) \ @@ -235,6 +237,7 @@ $(obj)/amdfw.rom: $(call strip_quotes, $(CONFIG_HUDSON_XHCI_FWM_FILE)) \ $(OPT_2SMUFIRMWARE2_FILE) \ $(OPT_2SMUSCS_FILE) \ --output $@ + please_fail_here cbfs-files-y += apu/amdfw apu/amdfw-file := $(obj)/amdfw.rom diff --git a/util/abuild/abuild b/util/abuild/abuild index a2a428b..8fa62dc 100755 --- a/util/abuild/abuild +++ b/util/abuild/abuild @@ -671,7 +671,7 @@ else junit '<testsuite>' if [ "$mode" != "text" ]; then for xmlfile in $TARGET/abuild/*_*.xml; do - cat $xmlfile >> $REAL_XMLFILE + cat $xmlfile | tr -d '\0' >> $REAL_XMLFILE done fi XMLFILE=$REAL_XMLFILE diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index 3dff2ac..cb4687d 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -391,6 +391,9 @@ int main(int argc, char **argv) int targetfd; char *output; + FILE *tty = stderr; + + fprintf(tty, "#0 AMDFWTOOL: allocating rom, %u bytes\n", CONFIG_ROM_SIZE); rom = malloc(CONFIG_ROM_SIZE); memset (rom, 0xFF, CONFIG_ROM_SIZE); if (!rom) { @@ -542,6 +545,7 @@ int main(int argc, char **argv) amd_romsig[4] = current + ROM_BASE_ADDRESS; current += 0x200; /* Conservative size of pspdir */ + fprintf(tty, "#0 ANDFWTOOL: calling integrate_psp_firmwares at %u\n", current); current = integrate_psp_firmwares(rom, current, pspdir, amd_psp_fw_table); }

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Patch set updated for coreboot: 3rdparty/vboot: update to latest master for rotor support
by Martin Roth 20 Oct '16

20 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17061 -gerrit commit afe380a7ac2c3394415415c04a4aa7fdb5f75234 Author: Martin Roth <martinroth(a)google.com> Date: Wed Oct 19 13:39:57 2016 -0600 3rdparty/vboot: update to latest master for rotor support This pulls in the bdb support for futility so that rotor can build. Change-Id: Icfa432fb840bea3e1616933ed02cf34a681fa3ce Signed-off-by: Martin Roth <martinroth(a)google.com> --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 46b77fb..ea72ee4 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 46b77fb2f04941c869c3a98cd17e9209c36b2917 +Subproject commit ea72ee454aea5e0f378275fe7114cf683b7db938

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Patch set updated for coreboot: lars/kunimitsu: Add other sensor in _ART for fan control
by Sumeet R Pawnikar 20 Oct '16

20 Oct '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17066 -gerrit commit 85c808762130b7015c341695ac4e3fc8b101b5c3 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Oct 18 10:22:52 2016 +0530 lars/kunimitsu: Add other sensor in _ART for fan control This patch updates the _ART table with other external sensor TSR0 for Fan speed control on Skylake-U based Kunimitsu and Lars boards. Also, updates the temperature values in DPTF policy for better performance. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on kunimitsu and lars EVT boards. Verified this updated _ART table on these boards with different workloads. Change-Id: Ib195910c5eb00e004e8b9bd50e266ade3c175be2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/332349 --- src/mainboard/google/lars/acpi/dptf.asl | 30 +++++++++++++++---------- src/mainboard/intel/kunimitsu/acpi/dptf.asl | 34 ++++++++++++++++++----------- 2 files changed, 40 insertions(+), 24 deletions(-) diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl index 7fcf567..b8f0a7a 100644 --- a/src/mainboard/google/lars/acpi/dptf.asl +++ b/src/mainboard/google/lars/acpi/dptf.asl @@ -14,28 +14,32 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 +#define DPTF_CPU_PASSIVE 95 #define DPTF_CPU_CRITICAL 99 #define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 70 -#define DPTF_CPU_ACTIVE_AC3 60 -#define DPTF_CPU_ACTIVE_AC4 50 +#define DPTF_CPU_ACTIVE_AC1 77 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_ACTIVE_AC0 120 +#define DPTF_TSR0_ACTIVE_AC1 110 +#define DPTF_TSR0_ACTIVE_AC2 47 +#define DPTF_TSR0_ACTIVE_AC3 44 +#define DPTF_TSR0_ACTIVE_AC4 41 +#define DPTF_TSR0_ACTIVE_AC5 38 +#define DPTF_TSR0_ACTIVE_AC6 35 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_PASSIVE 63 +#define DPTF_TSR1_CRITICAL 68 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_PASSIVE 64 +#define DPTF_TSR2_CRITICAL 69 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -79,8 +83,12 @@ Name (DART, Package () { * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0, 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40, + 35, 0, 0, 0 } }) #endif diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl index e011c97..b2bfe88 100644 --- a/src/mainboard/intel/kunimitsu/acpi/dptf.asl +++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl @@ -14,28 +14,32 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 80 -#define DPTF_CPU_CRITICAL 90 -#define DPTF_CPU_ACTIVE_AC0 90 -#define DPTF_CPU_ACTIVE_AC1 80 -#define DPTF_CPU_ACTIVE_AC2 70 -#define DPTF_CPU_ACTIVE_AC3 60 -#define DPTF_CPU_ACTIVE_AC4 50 +#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_CRITICAL 99 +#define DPTF_CPU_ACTIVE_AC0 90 +#define DPTF_CPU_ACTIVE_AC1 77 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 48 +#define DPTF_TSR0_PASSIVE 65 #define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_ACTIVE_AC0 120 +#define DPTF_TSR0_ACTIVE_AC1 110 +#define DPTF_TSR0_ACTIVE_AC2 47 +#define DPTF_TSR0_ACTIVE_AC3 44 +#define DPTF_TSR0_ACTIVE_AC4 41 +#define DPTF_TSR0_ACTIVE_AC5 38 +#define DPTF_TSR0_ACTIVE_AC6 35 #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 60 -#define DPTF_TSR1_CRITICAL 70 +#define DPTF_TSR1_PASSIVE 63 +#define DPTF_TSR1_CRITICAL 68 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 55 -#define DPTF_TSR2_CRITICAL 70 +#define DPTF_TSR2_PASSIVE 64 +#define DPTF_TSR2_CRITICAL 69 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -79,8 +83,12 @@ Name (DART, Package () { * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 90, 80, 70, 60, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0, 0, 0, 0 + }, + Package () { + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40, + 35, 0, 0, 0 } }) #endif

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New patch to review for coreboot: mb/kontron/ktqm77: Enable native gfx init through libgfxinit
by Nico Huber 20 Oct '16

20 Oct '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17074 -gerrit commit 53f45b7fe87c7dec9c5f332d7082660dd2da947c Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Oct 19 13:41:42 2016 +0200 mb/kontron/ktqm77: Enable native gfx init through libgfxinit Change-Id: Ie16b3236e7378a2062b3081e4530d7a4791b4b66 Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/mainboard/kontron/ktqm77/Kconfig | 2 ++ src/mainboard/kontron/ktqm77/Makefile.inc | 2 ++ src/mainboard/kontron/ktqm77/gma-mainboard.ads | 21 +++++++++++++++++++++ 3 files changed, 25 insertions(+) diff --git a/src/mainboard/kontron/ktqm77/Kconfig b/src/mainboard/kontron/ktqm77/Kconfig index 77ad91b..d0f0d2c 100644 --- a/src/mainboard/kontron/ktqm77/Kconfig +++ b/src/mainboard/kontron/ktqm77/Kconfig @@ -12,6 +12,8 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_ACPI_RESUME select ENABLE_VMX + select MAINBOARD_HAS_NATIVE_VGA_INIT + select MAINBOARD_HAS_LIBGFXINIT config MAINBOARD_DIR string diff --git a/src/mainboard/kontron/ktqm77/Makefile.inc b/src/mainboard/kontron/ktqm77/Makefile.inc index 3dae61e..ea035d3 100644 --- a/src/mainboard/kontron/ktqm77/Makefile.inc +++ b/src/mainboard/kontron/ktqm77/Makefile.inc @@ -1 +1,3 @@ romstage-y += gpio.c + +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/kontron/ktqm77/gma-mainboard.ads b/src/mainboard/kontron/ktqm77/gma-mainboard.ads new file mode 100644 index 0000000..cf86617 --- /dev/null +++ b/src/mainboard/kontron/ktqm77/gma-mainboard.ads @@ -0,0 +1,21 @@ +with HW.GFX.GMA; + +use HW.GFX.GMA; + +private package GMA.Mainboard is + + -- For a three-pipe setup, bandwidth is shared between the 2nd and + -- the 3rd pipe (if it's not eDP). Thus, probe ports that likely + -- have a high-resolution display attached first, `Internal` last. + + ports : constant Port_List := + (DP2, + DP3, + Digital1, + Digital2, + Digital3, + Analog, + Internal, + others => Disabled); + +end GMA.Mainboard;

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coreboot-gerrit October 2016