coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

1 participants
1281 discussions

New patch to review for coreboot: drivers/i2c/generic: Return correct name for acpi_name
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17077 -gerrit commit bc6f3c480cdb6969b3578a945f4a9e854e19784b Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Oct 18 15:11:32 2016 -0700 drivers/i2c/generic: Return correct name for acpi_name Return config->name if it is not NULL. BUG=chrome-os-partner:55988 Change-Id: I9ae229949b73de6f991383daae8d962d6cf457a7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/generic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 30a280b..c11a889 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -86,7 +86,7 @@ static const char *i2c_generic_acpi_name(struct device *dev) static char name[5]; if (config->name) - return name; + return config->name; snprintf(name, sizeof(name), "D%03.3X", dev->path.i2c.device); name[4] = '\0';

1 0

Patch set updated for coreboot: mb/emulation: Select QEMU-i440fx by default
by Jonathan Neuschäfer 20 Oct '16

20 Oct '16

Jonathan Neuschäfer (j.neuschaefer(a)gmx.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16987 -gerrit commit 50545375728d29be07a6f4711a66776215b838c2 Author: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> Date: Thu Oct 20 02:46:49 2016 +0200 mb/emulation: Select QEMU-i440fx by default It's a better default than QEMU-armv7, which is currently the default board when coreboot is configured for the first time, because most coreboot development targets x86. With this patch, the minimal steps to coreboot+SeaBIOS booting in QEMU become: git clone https://review.coreboot.org/coreboot.git && cd coreboot make crossgcc-x86 make olddefconfig && make qemu-system-x86_64 -bios build/coreboot.rom Change-Id: Ie44a5d95547a55df93f29082c3b5a86fb83aa1e7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net> --- src/mainboard/emulation/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/emulation/Kconfig b/src/mainboard/emulation/Kconfig index 1dc89ca..759b1de 100644 --- a/src/mainboard/emulation/Kconfig +++ b/src/mainboard/emulation/Kconfig @@ -2,6 +2,7 @@ if VENDOR_EMULATION choice prompt "Mainboard model" + default BOARD_EMULATION_QEMU_X86_I440FX source "src/mainboard/emulation/*/Kconfig.name"

1 0

Patch set updated for coreboot: nb/intel/sandybridge/gma: Always initialize DP buffer translation
by Nico Huber 20 Oct '16

20 Oct '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17073 -gerrit commit 19daa48201122dfc400eaef54999657e2f33a0a6 Author: Nico Huber <nico.huber(a)secunet.com> Date: Wed Oct 19 15:20:17 2016 +0200 nb/intel/sandybridge/gma: Always initialize DP buffer translation These settings should be always made by the firmware, no matter if we set up graphics or not. It looks like Linux doesn't even know these registers. The values are taken from the PRMs for Sandy Bridge and Ivy Bridge [1, 2]. They match the settings that were done in the native graphics path for Ivy Bridge. I expect the differences to be an update (i.e. the set- tings we did on the Sandy Bridge path were just outdated). Also, these settings affect the PCH and not the CPU which are independent from each other. [1] Intel® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 3 Part 3: PCH Display Registers (SandyBridge) Doc Ref #: IHD-OS-V3 Pt3 – 05 11 https://01.org/sites/default/files/documentation/snb_ihd_os_vol3_part3.pdf [2] Intel ® OpenSource HD Graphics Programmer’s Reference Manual (PRM) Volume 3 Part 4: South Display Engine Registers (Ivy Bridge) Doc Ref #: IHD-OS-V3 Pt 4 – 05 12 https://01.org/sites/default/files/documentation/ivb_ihd_os_vol3_part4.pdf Change-Id: I83cc90c7558b93273a727f332fb0d8ced47ed70e Signed-off-by: Nico Huber <nico.huber(a)secunet.com> --- src/northbridge/intel/sandybridge/gma.c | 12 ++++++++++++ .../intel/sandybridge/gma_ivybridge_lvds.c | 20 -------------------- .../intel/sandybridge/gma_sandybridge_lvds.c | 10 ---------- 3 files changed, 12 insertions(+), 30 deletions(-) diff --git a/src/northbridge/intel/sandybridge/gma.c b/src/northbridge/intel/sandybridge/gma.c index f0d96ce..f050eb2 100644 --- a/src/northbridge/intel/sandybridge/gma.c +++ b/src/northbridge/intel/sandybridge/gma.c @@ -494,6 +494,18 @@ static void gma_pm_init_pre_vbios(struct device *dev) reg32 = gtt_read(0x6c024); reg32 &= ~0x000001c0; gtt_write(0x6c024, reg32); + + /* Initialize DP buffer translation with recommended defaults */ + gtt_write(0xe4f00, 0x0100030c); + gtt_write(0xe4f04, 0x00b8230c); + gtt_write(0xe4f08, 0x06f8930c); + gtt_write(0xe4f0c, 0x05f8e38e); + gtt_write(0xe4f10, 0x00b8030c); + gtt_write(0xe4f14, 0x0b78830c); + gtt_write(0xe4f18, 0x09f8d3cf); + gtt_write(0xe4f1c, 0x01e8030c); + gtt_write(0xe4f20, 0x09f863cf); + gtt_write(0xe4f24, 0x0ff803cf); } static void gma_pm_init_post_vbios(struct device *dev) diff --git a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c index 831e8ce..29dc76e 100644 --- a/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c @@ -76,16 +76,6 @@ static void enable_port(u8 *mmio) write32(mmio + 0xf2060, 0x10); write32(mmio + 0x9840, 0x0); write32(mmio + 0x42000, 0xa0000000); - write32(mmio + 0xe4f00, 0x100030c); - write32(mmio + 0xe4f04, 0xb8230c); - write32(mmio + 0xe4f08, 0x6f8930c); - write32(mmio + 0xe4f0c, 0x5f8e38e); - write32(mmio + 0xe4f10, 0xb8030c); - write32(mmio + 0xe4f14, 0xb78830c); - write32(mmio + 0xe4f18, 0x9f8d3cf); - write32(mmio + 0xe4f1c, 0x1e8030c); - write32(mmio + 0xe4f20, 0x9f863cf); - write32(mmio + 0xe4f24, 0xff803cf); read32(mmio + 0xe4100); write32(mmio + 0xc4030, 0x10); write32(mmio + 0xe4110, 0x8004003e); @@ -115,16 +105,6 @@ static void enable_port(u8 *mmio) read32(mmio + 0xe1140); write32(mmio + 0xc4030, 0x10); read32(mmio + 0xc4000); - write32(mmio + 0xe4f00, 0x100030c); - write32(mmio + 0xe4f04, 0xb8230c); - write32(mmio + 0xe4f08, 0x6f8930c); - write32(mmio + 0xe4f0c, 0x5f8e38e); - write32(mmio + 0xe4f10, 0xb8030c); - write32(mmio + 0xe4f14, 0xb78830c); - write32(mmio + 0xe4f18, 0x9f8d3cf); - write32(mmio + 0xe4f1c, 0x1e8030c); - write32(mmio + 0xe4f20, 0x9f863cf); - write32(mmio + 0xe4f24, 0xff803cf); read32(mmio + 0xe4200); write32(mmio + 0xc4030, 0x1010); write32(mmio + 0xe4210, 0x8004003e); diff --git a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c index c2c8087..acd90a2 100644 --- a/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c +++ b/src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c @@ -94,16 +94,6 @@ static void power_port(u8 *mmio) read32(mmio + 0x000e4210); // = 0x5144003e read32(mmio + 0x000e4210); // = 0x5144003e write32(mmio + 0x000e4210, 0x5344003e); - write32(mmio + 0x000e4f00, 0x0100030c); - write32(mmio + 0x000e4f04, 0x00b8230c); - write32(mmio + 0x000e4f08, 0x06f8930c); - write32(mmio + 0x000e4f0c, 0x09f8e38e); - write32(mmio + 0x000e4f10, 0x00b8030c); - write32(mmio + 0x000e4f14, 0x0b78830c); - write32(mmio + 0x000e4f18, 0x0ff8d3cf); - write32(mmio + 0x000e4f1c, 0x01e8030c); - write32(mmio + 0x000e4f20, 0x0ff863cf); - write32(mmio + 0x000e4f24, 0x0ff803cf); write32(mmio + 0x000c4030, 0x00001000); read32(mmio + 0x000c4000); // = 0x00000000 write32(mmio + 0x000c4030, 0x00001000);

1 0

New patch to review for coreboot: nb/i945/gma.c use an if else statement for use of native init
by Arthur Heymans 20 Oct '16

20 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17076 -gerrit commit a03c438fa8f27b0787267aee05895b2275e665c9 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Thu Oct 20 20:44:54 2016 +0200 nb/i945/gma.c use an if else statement for use of native init Change-Id: I1e964ed939ca5282008253e3fbdd1d2fa5cbf278 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 3e68aa3..c74384a 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -594,11 +594,6 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); - if (!IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { - /* PCI Init, will run VBIOS */ - pci_dev_init(dev); - } - if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* This should probably run before post VBIOS init. */ printk(BIOS_SPEW, "Initializing VGA without OPROM.\n"); @@ -637,6 +632,9 @@ static void gma_func0_init(struct device *dev) generate_fake_intel_oprom(&conf->gfx, dev, "$VBT LAKEPORT-G"); } + } else { + /* PCI Init, will run VBIOS */ + pci_dev_init(dev); } }

1 0

Patch set updated for coreboot: intel/kunimitsu: Update DPTF settings
by Sumeet R Pawnikar 20 Oct '16

20 Oct '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17069 -gerrit commit 886a2422facf3bb258764d484f8c1ebe270eece7 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Oct 18 11:15:22 2016 +0530 intel/kunimitsu: Update DPTF settings After tuning the temperature values for optimal performance, this patch updates few DPTF settings for Kunimitsu board. BUG=None BRANCH=None TEST=Built and booted on Kunimitsu boards. Verified these updated DPTF settings with different workloads. Change-Id: Ic1c319262d80cc5cb29a8630af213822308f8bed Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/350223 --- src/mainboard/intel/kunimitsu/acpi/dptf.asl | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl index b2bfe88..df2c0eb 100644 --- a/src/mainboard/intel/kunimitsu/acpi/dptf.asl +++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl @@ -14,15 +14,15 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_PASSIVE 94 #define DPTF_CPU_CRITICAL 99 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 77 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 65 -#define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_PASSIVE 66 +#define DPTF_TSR0_CRITICAL 71 #define DPTF_TSR0_ACTIVE_AC0 120 #define DPTF_TSR0_ACTIVE_AC1 110 #define DPTF_TSR0_ACTIVE_AC2 47 @@ -33,13 +33,13 @@ #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 63 -#define DPTF_TSR1_CRITICAL 68 +#define DPTF_TSR1_PASSIVE 75 +#define DPTF_TSR1_CRITICAL 80 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 64 -#define DPTF_TSR2_CRITICAL 69 +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 70 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -83,12 +83,12 @@ Name (DART, Package () { * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 72, 0, 0, 0, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40, - 35, 0, 0, 0 + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 72, 68, 49, 39, 38, + 37, 0, 0, 0 } }) #endif @@ -125,8 +125,8 @@ Name (MPPC, Package () }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ + 25000, /* PowerLimitMinimum */ + 25000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */

1 0

Patch set updated for coreboot: marvell/mvmap2315: Compose BOOTBLOCK region
by Martin Roth 20 Oct '16

20 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16747 -gerrit commit 0a06ca73e585ed164d02b5674990001c13dd3ca7 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Sep 23 17:40:15 2016 -0700 marvell/mvmap2315: Compose BOOTBLOCK region This patch adds a Makefile rule for mvmap2315 to install a BDB and bootblock code in the BOOTBLOCK region. The resulting BDB has a header and data both signed by a RSA-4096 key. BUG=chrome-os-partner:57889 BRANCH=none TEST=emerge-rotor coreboot and examined the output binary. Booted coreboot.rom on Palladium. Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/soc/marvell/mvmap2315/Makefile.inc | 75 +++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index d30ab68..c6426f1 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -63,4 +63,77 @@ romstage-y += wdt.c CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ -endif +# +# Common Boot Flow parameters +# +BOOTBLOCK_REGION_SIZE = 131072 +BOOTBLOCK_TYPE = 1 +BOOTBLOCK_PARTITION = 1 +BOOTBLOCK_LOAD_ADDRESS = 0xe000c000 +BDB = $(obj)/bdb.bin +BDB_LOAD_ADDRESS = 0xe0000000 +DATA_VERSION = 2 + +# +# Keys used to create BDB +# +KEYDIR = $(VBOOT_SOURCE)/tests/testkeys +BDBKEY_PUB = $(KEYDIR)/bdbkey.keyb +BDBKEY_PRI = $(KEYDIR)/bdbkey.pem +BDBKEY_DIGEST = $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin +# Use bdbkeys because mvmap2315's bootROM doesn't support RSA3072b with +# exponent 3 and the algorithms for BDB key and data key have to match. +DATAKEY_PUB = $(KEYDIR)/bdbkey.keyb +DATAKEY_PRI = $(KEYDIR)/bdbkey.pem + +# Calculate bootblock.raw.bin's size and offset +.PHONY: bootblock_offset +bootblock_offset: $(objcbfs)/bootblock.raw.bin + $(eval BOOTBLOCK_SIZE = $(call file-size, $<)) + $(eval BOOTBLOCK_OFFSET = $(call int-subtract, \ + $(BOOTBLOCK_REGION_SIZE) $(BOOTBLOCK_SIZE))) + +# +# Create BDB +# +# TODO: Verify sign algorithms of the BDB key and data key are supported +$(BDB): $(objcbfs)/bootblock.raw.bin $(FUTILITY) bootblock_offset \ + $(BDBKEY_PRI) $(BDBKEY_PUB) $(DATAKEY_PRI) $(DATAKEY_PUB) \ + $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin + $(FUTILITY) bdb --create $@.tmp \ + --bdbkey_pri $(BDBKEY_PRI) --bdbkey_pub $(BDBKEY_PUB) \ + --datakey_pri $(DATAKEY_PRI) --datakey_pub $(DATAKEY_PUB) \ + --load_address $(BDB_LOAD_ADDRESS) + $(FUTILITY) bdb --add $@.tmp \ + --data $< \ + --offset $(BOOTBLOCK_OFFSET) \ + --partition $(BOOTBLOCK_PARTITION) \ + --type $(BOOTBLOCK_TYPE) \ + --load_address $(BOOTBLOCK_LOAD_ADDRESS) + $(FUTILITY) bdb --resign $@.tmp \ + --datakey_pri $(DATAKEY_PRI) \ + --data_version $(DATA_VERSION) + $(FUTILITY) bdb --verify $@.tmp --key_digest $(BDBKEY_DIGEST) + mv $@.tmp $@ + +# +# Create custom bootblock.bin +# +# This overrides generic pattern rule *.raw.bin -> *.bin for bootblock.bin. +# bootblock.bin is structured as follows: +# +------------------+ +# | BDB | +# +------------------+ +# | 000............0 | +# +------------------+ +# |bootblock.raw.bin | +# +------------------+ +# And this will be placed in BOOTBLOCK region. +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BDB) bootblock_offset + dd if=/dev/zero bs=1 count=$(BOOTBLOCK_REGION_SIZE) of=$@.tmp + dd if=$(BDB) bs=1 count=$(call file-size, $(BDB)) conv=notrunc of=$@.tmp + dd if=$(objcbfs)/bootblock.raw.bin bs=1 count=$(BOOTBLOCK_SIZE) \ + seek=$(BOOTBLOCK_OFFSET) conv=notrunc of=$@.tmp + mv $@.tmp $@ + +endif \ No newline at end of file

1 0

Patch set updated for coreboot: google/lars: Update DPTF settings
by Sumeet R Pawnikar 20 Oct '16

20 Oct '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17068 -gerrit commit c48afcdd4c0587e472a9576e5fa027726d959c48 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Oct 18 11:07:39 2016 +0530 google/lars: Update DPTF settings After tuning the temperature values for optimal performance, this patch updates few DPTF settings for lars boards. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on lars DVT boards. Verified these updated DPTF settings with different workloads. Change-Id: I4c040526c31c3263ed3a9b4cccff3b7a021cfcdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/338877 --- src/mainboard/google/lars/acpi/dptf.asl | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/lars/acpi/dptf.asl b/src/mainboard/google/lars/acpi/dptf.asl index b8f0a7a..82a23f8 100644 --- a/src/mainboard/google/lars/acpi/dptf.asl +++ b/src/mainboard/google/lars/acpi/dptf.asl @@ -14,15 +14,15 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_PASSIVE 94 #define DPTF_CPU_CRITICAL 99 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 77 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 65 -#define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_PASSIVE 66 +#define DPTF_TSR0_CRITICAL 71 #define DPTF_TSR0_ACTIVE_AC0 120 #define DPTF_TSR0_ACTIVE_AC1 110 #define DPTF_TSR0_ACTIVE_AC2 47 @@ -33,13 +33,13 @@ #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 63 -#define DPTF_TSR1_CRITICAL 68 +#define DPTF_TSR1_PASSIVE 75 +#define DPTF_TSR1_CRITICAL 80 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 64 -#define DPTF_TSR2_CRITICAL 69 +#define DPTF_TSR2_PASSIVE 65 +#define DPTF_TSR2_CRITICAL 70 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -83,12 +83,12 @@ Name (DART, Package () { * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 72, 0, 0, 0, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40, - 35, 0, 0, 0 + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 72, 68, 49, 39, 38, + 37, 0, 0, 0 } }) #endif

1 0

Patch set updated for coreboot: intel/kunimitsu: Update DPTF settings
by Sumeet R Pawnikar 20 Oct '16

20 Oct '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17069 -gerrit commit 3f9a89988be0def327ab96d3b14fb722adf3f7f9 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Oct 18 11:15:22 2016 +0530 intel/kunimitsu: Update DPTF settings After tuning the temperature values for optimal performance, this patch updates few DPTF settings for Kunimitsu board. BUG=None BRANCH=None TEST=Built and booted on Kunimitsu boards. Verified these updated DPTF settings with different workloads. Change-Id: Ic1c319262d80cc5cb29a8630af213822308f8bed Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/350223 --- src/mainboard/intel/kunimitsu/acpi/dptf.asl | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/acpi/dptf.asl b/src/mainboard/intel/kunimitsu/acpi/dptf.asl index b2bfe88..9791151 100644 --- a/src/mainboard/intel/kunimitsu/acpi/dptf.asl +++ b/src/mainboard/intel/kunimitsu/acpi/dptf.asl @@ -14,15 +14,15 @@ * GNU General Public License for more details. */ -#define DPTF_CPU_PASSIVE 95 +#define DPTF_CPU_PASSIVE 94 #define DPTF_CPU_CRITICAL 99 #define DPTF_CPU_ACTIVE_AC0 90 #define DPTF_CPU_ACTIVE_AC1 77 #define DPTF_TSR0_SENSOR_ID 0 #define DPTF_TSR0_SENSOR_NAME "TMP432_Internal" -#define DPTF_TSR0_PASSIVE 65 -#define DPTF_TSR0_CRITICAL 70 +#define DPTF_TSR0_PASSIVE 66 +#define DPTF_TSR0_CRITICAL 71 #define DPTF_TSR0_ACTIVE_AC0 120 #define DPTF_TSR0_ACTIVE_AC1 110 #define DPTF_TSR0_ACTIVE_AC2 47 @@ -33,13 +33,13 @@ #define DPTF_TSR1_SENSOR_ID 1 #define DPTF_TSR1_SENSOR_NAME "TMP432_Power_top" -#define DPTF_TSR1_PASSIVE 63 -#define DPTF_TSR1_CRITICAL 68 +#define DPTF_TSR1_PASSIVE 75 +#define DPTF_TSR1_CRITICAL 80 #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "TMP432_CPU_bottom" -#define DPTF_TSR2_PASSIVE 64 -#define DPTF_TSR2_CRITICAL 69 +#define DPTF_TSR2_PASSIVE 65 +define DPTF_TSR2_CRITICAL 70 #define DPTF_ENABLE_CHARGER #define DPTF_ENABLE_FAN_CONTROL @@ -83,12 +83,12 @@ Name (DART, Package () { * Source, Target, Weight, AC0, AC1, AC2, AC3, AC4, AC5, AC6, * AC7, AC8, AC9 */ - \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 81, 0, 0, 0, 0, 0, + \_SB.DPTF.TFN1, \_SB.PCI0.B0D4, 100, 100, 72, 0, 0, 0, 0, 0, 0, 0, 0 }, Package () { - \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 81, 68, 56, 48, 40, - 35, 0, 0, 0 + \_SB.DPTF.TFN1, \_SB.DPTF.TSR0, 100, 100, 72, 68, 49, 39, 38, + 37, 0, 0, 0 } }) #endif @@ -125,8 +125,8 @@ Name (MPPC, Package () }, Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ - 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ + 25000, /* PowerLimitMinimum */ + 25000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */

1 0

Patch set updated for coreboot: soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control
by Sumeet R Pawnikar 20 Oct '16

20 Oct '16

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17067 -gerrit commit f78cc3cc11c3e92799a459a583af57860758c4b4 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Tue Oct 18 10:57:58 2016 +0530 soc/intel/skylake: Add _ACx methods for TSR0 sensor for fan control This patch adds the _ACx methods for other external sensor TSR0 for Fan speed control on Skylake-U based Kunimitsu and Lars boards. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on kunimitsu and lars EVT boards. Verified these _ACx methods with _ART table on these boards with different workloads. Change-Id: Ia7b81e03da936c4a0f69057e43f18efd7c3b9f17 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Reviewed-on: https://chromium-review.googlesource.com/332368 --- src/soc/intel/skylake/acpi/dptf/cpu.asl | 20 ---------------- src/soc/intel/skylake/acpi/dptf/thermal.asl | 37 +++++++++++++++++++++++++++++ 2 files changed, 37 insertions(+), 20 deletions(-) diff --git a/src/soc/intel/skylake/acpi/dptf/cpu.asl b/src/soc/intel/skylake/acpi/dptf/cpu.asl index 32e8863..6278b9f 100644 --- a/src/soc/intel/skylake/acpi/dptf/cpu.asl +++ b/src/soc/intel/skylake/acpi/dptf/cpu.asl @@ -22,26 +22,6 @@ #define DPTF_CPU_CRITICAL 90 #endif -#ifndef DPTF_CPU_ACTIVE_AC0 -#define DPTF_CPU_ACTIVE_AC0 90 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC1 -#define DPTF_CPU_ACTIVE_AC1 80 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC2 -#define DPTF_CPU_ACTIVE_AC2 70 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC3 -#define DPTF_CPU_ACTIVE_AC3 60 -#endif - -#ifndef DPTF_CPU_ACTIVE_AC4 -#define DPTF_CPU_ACTIVE_AC4 50 -#endif - External (\_PR.CP00._PSS, PkgObj) External (\_PR.CP00._TSS, PkgObj) External (\_PR.CP00._TPC, MethodObj) diff --git a/src/soc/intel/skylake/acpi/dptf/thermal.asl b/src/soc/intel/skylake/acpi/dptf/thermal.asl index 97484e5..a171eb1 100644 --- a/src/soc/intel/skylake/acpi/dptf/thermal.asl +++ b/src/soc/intel/skylake/acpi/dptf/thermal.asl @@ -111,6 +111,43 @@ Device (TSR0) { \_SB.PCI0.LPCB.EC0.PATD (TMPI) } + +#ifdef DPTF_ENABLE_FAN_CONTROL + Method (_AC0) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC0)) + } + + Method (_AC1) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC1)) + } + + Method (_AC2) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC2)) + } + + Method (_AC3) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC3)) + } + + Method (_AC4) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC4)) + } + + Method (_AC5) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC5)) + } + + Method (_AC6) + { + Return (\_SB.DPTF.CTOK (DPTF_TSR0_ACTIVE_AC6)) + } +#endif } #endif

1 0

Patch set updated for coreboot: marvell/mvmap2315: Compose BOOTBLOCK region
by Martin Roth 20 Oct '16

20 Oct '16

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16747 -gerrit commit 2966d1ce596b7e7a095ae40404c803bd352f6555 Author: Daisuke Nojiri <dnojiri(a)chromium.org> Date: Fri Sep 23 17:40:15 2016 -0700 marvell/mvmap2315: Compose BOOTBLOCK region This patch adds a Makefile rule for mvmap2315 to install a BDB and bootblock code in the BOOTBLOCK region. The resulting BDB has a header and data both signed by a RSA-4096 key. BUG=chrome-os-partner:57889 BRANCH=none TEST=emerge-rotor coreboot and examined the output binary. Booted coreboot.rom on Palladium. Change-Id: I1e20a09b12f8f8ed4d095aa588e3eb930f359fc5 Signed-off-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- 3rdparty/blobs | 2 +- src/soc/marvell/mvmap2315/Makefile.inc | 75 +++++++++++++++++++++++++++++++++- 2 files changed, 75 insertions(+), 2 deletions(-) diff --git a/3rdparty/blobs b/3rdparty/blobs index 8ad2d63..9ba0703 160000 --- a/3rdparty/blobs +++ b/3rdparty/blobs @@ -1 +1 @@ -Subproject commit 8ad2d6385652e14b6f0d35ab9b474c31ddeb1773 +Subproject commit 9ba07035ed0acb28902cce826ea833cf531d57c1 diff --git a/src/soc/marvell/mvmap2315/Makefile.inc b/src/soc/marvell/mvmap2315/Makefile.inc index d30ab68..c6426f1 100644 --- a/src/soc/marvell/mvmap2315/Makefile.inc +++ b/src/soc/marvell/mvmap2315/Makefile.inc @@ -63,4 +63,77 @@ romstage-y += wdt.c CPPFLAGS_common += -Isrc/soc/marvell/mvmap2315/include/ -endif +# +# Common Boot Flow parameters +# +BOOTBLOCK_REGION_SIZE = 131072 +BOOTBLOCK_TYPE = 1 +BOOTBLOCK_PARTITION = 1 +BOOTBLOCK_LOAD_ADDRESS = 0xe000c000 +BDB = $(obj)/bdb.bin +BDB_LOAD_ADDRESS = 0xe0000000 +DATA_VERSION = 2 + +# +# Keys used to create BDB +# +KEYDIR = $(VBOOT_SOURCE)/tests/testkeys +BDBKEY_PUB = $(KEYDIR)/bdbkey.keyb +BDBKEY_PRI = $(KEYDIR)/bdbkey.pem +BDBKEY_DIGEST = $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin +# Use bdbkeys because mvmap2315's bootROM doesn't support RSA3072b with +# exponent 3 and the algorithms for BDB key and data key have to match. +DATAKEY_PUB = $(KEYDIR)/bdbkey.keyb +DATAKEY_PRI = $(KEYDIR)/bdbkey.pem + +# Calculate bootblock.raw.bin's size and offset +.PHONY: bootblock_offset +bootblock_offset: $(objcbfs)/bootblock.raw.bin + $(eval BOOTBLOCK_SIZE = $(call file-size, $<)) + $(eval BOOTBLOCK_OFFSET = $(call int-subtract, \ + $(BOOTBLOCK_REGION_SIZE) $(BOOTBLOCK_SIZE))) + +# +# Create BDB +# +# TODO: Verify sign algorithms of the BDB key and data key are supported +$(BDB): $(objcbfs)/bootblock.raw.bin $(FUTILITY) bootblock_offset \ + $(BDBKEY_PRI) $(BDBKEY_PUB) $(DATAKEY_PRI) $(DATAKEY_PUB) \ + $(VBOOT_SOURCE)/tests/testdata/bdbkey_digest.bin + $(FUTILITY) bdb --create $@.tmp \ + --bdbkey_pri $(BDBKEY_PRI) --bdbkey_pub $(BDBKEY_PUB) \ + --datakey_pri $(DATAKEY_PRI) --datakey_pub $(DATAKEY_PUB) \ + --load_address $(BDB_LOAD_ADDRESS) + $(FUTILITY) bdb --add $@.tmp \ + --data $< \ + --offset $(BOOTBLOCK_OFFSET) \ + --partition $(BOOTBLOCK_PARTITION) \ + --type $(BOOTBLOCK_TYPE) \ + --load_address $(BOOTBLOCK_LOAD_ADDRESS) + $(FUTILITY) bdb --resign $@.tmp \ + --datakey_pri $(DATAKEY_PRI) \ + --data_version $(DATA_VERSION) + $(FUTILITY) bdb --verify $@.tmp --key_digest $(BDBKEY_DIGEST) + mv $@.tmp $@ + +# +# Create custom bootblock.bin +# +# This overrides generic pattern rule *.raw.bin -> *.bin for bootblock.bin. +# bootblock.bin is structured as follows: +# +------------------+ +# | BDB | +# +------------------+ +# | 000............0 | +# +------------------+ +# |bootblock.raw.bin | +# +------------------+ +# And this will be placed in BOOTBLOCK region. +$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin $(BDB) bootblock_offset + dd if=/dev/zero bs=1 count=$(BOOTBLOCK_REGION_SIZE) of=$@.tmp + dd if=$(BDB) bs=1 count=$(call file-size, $(BDB)) conv=notrunc of=$@.tmp + dd if=$(objcbfs)/bootblock.raw.bin bs=1 count=$(BOOTBLOCK_SIZE) \ + seek=$(BOOTBLOCK_OFFSET) conv=notrunc of=$@.tmp + mv $@.tmp $@ + +endif \ No newline at end of file

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2016