coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: drivers/i2c/generic: Enable support for adding PowerResource for device
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17081 -gerrit commit aaaf30604e69548beaeac82481565d558cea07ac Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 16:01:04 2016 -0700 drivers/i2c/generic: Enable support for adding PowerResource for device Add support to allow a device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: 1. Reset GPIO - Mandatory if PowerResource needs to be defined 2. Reset delay - Delay after reset GPIO is de-asserted (default 0) 3. Enable GPIO - Optional if a separate GPIO exists for enable 4. Enable delay - Delay after enable GPIO is asserted (default 0) BUG=chrome-os-partner:55988 Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 9 +++++++++ src/drivers/i2c/generic/generic.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..e84fc38 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,13 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + + /* GPIO used to take device out of reset or to put it into reset. */ + unsigned reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned reset_delay_ms; + /* GPIO used to enable device. */ + unsigned enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned enable_delay_ms; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index c11a889..7f078b0 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,42 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) +{ + if (!config->reset_gpio) + return; + + const char *power_res_dev_states[] = { "_PR0", "_PR3" }; + + /* PowerResource (PRIC, 0, 0) */ + acpigen_write_power_res("PRIC", 0, 0, power_res_dev_states, + ARRAY_SIZE(power_res_dev_states)); + + /* Method (_STA, 0, NotSerialized) { Return (0x1) } */ + acpigen_write_STA(0x1); + + /* Method (_ON, 0, Serialized) */ + acpigen_write_method_serialized("_ON", 0); + acpigen_soc_set_tx_gpio(config->reset_gpio); + if (config->enable_gpio) { + acpigen_soc_set_tx_gpio(config->enable_gpio); + acpigen_write_sleep(config->enable_delay_ms); + } + acpigen_soc_clear_tx_gpio(config->reset_gpio); + acpigen_write_sleep(config->reset_delay_ms); + acpigen_pop_len(); /* _ON method */ + + /* Method (_OFF, 0, Serialized) */ + acpigen_write_method_serialized("_OFF", 0); + acpigen_soc_set_tx_gpio(config->reset_gpio); + if (config->enable_gpio) + acpigen_soc_clear_tx_gpio(config->enable_gpio); + acpigen_pop_len(); /* _OFF method */ + + acpigen_pop_len(); /* PowerResource PRIC */ +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -72,6 +108,9 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpi_dp_write(dsd); } + /* Power Resource */ + i2c_generic_add_power_res(config); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

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Patch set updated for coreboot: arch/x86/acpigen: Add support for interacting with GPIOs
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17080 -gerrit commit bc0682240eb567cda96e6dd76a8c49ee095c0a1d Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 07:12:49 2016 -0700 arch/x86/acpigen: Add support for interacting with GPIOs Since reading/toggling of GPIOs is platform-dependent task, provide an interface with common functions to generate ACPI AML code for manipulating GPIOs: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio Provide weak implementations of above functions. These functions are expected to be implemented by every SoC that uses ACPI. This allows drivers to easily generate ACPI AML code to interact GPIOs. BUG=chrome-os-partner:55988 Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 29 +++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 22 ++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 43de1d5..44c77cc 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -976,3 +976,32 @@ void acpigen_write_else(void) acpigen_emit_byte(ELSE_OP); acpigen_write_len_f(); } + +/* Soc-implemented functions -- weak definitions. */ +int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("read_rx_gpio not available"); + return -1; +} + +int __attribute__((weak)) acpigen_soc_get_tx_gpio(unsigned gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("get_tx_gpio not available"); + return -1; +} + +int __attribute__((weak)) acpigen_soc_set_tx_gpio(unsigned gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("set_tx_gpio not available"); + return -1; +} + +int __attribute__((weak)) acpigen_soc_clear_tx_gpio(unsigned gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("clear_tx_gpio not available"); + return -1; +} diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index c2936e2..8ac8f48 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -160,4 +160,26 @@ void acpigen_write_else(void); int get_cst_entries(acpi_cstate_t **); +/* + * Soc-implemented functions for generating ACPI AML code for GPIO handling. All + * these functions are expected to use only Local5, Local6 and Local7 + * variables. If the functions call into another ACPI method, then there is no + * restriction on the use of Local variables. In case of get/read functions, + * return value is expected to be stored in Local0 variable. + * + * All functions return 0 on success and -1 on error. + */ + +/* Generate ACPI AML code to return Rx value of GPIO in Local0. */ +int acpigen_soc_read_rx_gpio(unsigned gpio_num); + +/* Generate ACPI AML code to return Tx value of GPIO in Local0. */ +int acpigen_soc_get_tx_gpio(unsigned gpio_num); + +/* Generate ACPI AML code to set Tx value of GPIO to 1. */ +int acpigen_soc_set_tx_gpio(unsigned gpio_num); + +/* Generate ACPI AML code to set Tx value of GPIO to 0. */ +int acpigen_soc_clear_tx_gpio(unsigned gpio_num); + #endif

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Patch set updated for coreboot: mainboard/google/reef: Add PowerResource for ELAN touchscreen
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17083 -gerrit commit cd12358c06340cd31099279df699bf54bfab8ed7 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:48:45 2016 -0700 mainboard/google/reef: Add PowerResource for ELAN touchscreen Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:55988 Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 00df9bd..30d61f6 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -142,6 +142,10 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "GPIO_36" + register "reset_delay_ms" = "20" + register "enable_gpio" = "GPIO_152" + register "enable_delay_ms" = "1" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: soc/intel/apollolake: Implement GPIO ACPI AML generating functions
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17082 -gerrit commit 12dfb358ab83e097079f265f08af8416101f2a62 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:45:26 2016 -0700 soc/intel/apollolake: Implement GPIO ACPI AML generating functions Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio BUG=chrome-os-partner:55988 Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/apollolake/acpi.c | 81 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index ba22aee..ef93200 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -267,3 +267,84 @@ uint16_t soc_get_acpi_base_address(void) { return ACPI_PMIO_BASE; } + +static int acpigen_soc_get_gpio_val(unsigned gpio_num, uint32_t mask) +{ + assert (gpio_num < TOTAL_PADS); + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); + + /* Store (\_SB.GPC0 (addr), Local5) */ + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.GPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + /* If (And (Local5, mask)) */ + acpigen_write_if_and(LOCAL5_OP, mask); + + /* Store (One, Local0) */ + acpigen_write_store_ops(ONE_OP, LOCAL0_OP); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + + /* Store (Zero, Local0) */ + acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); + + acpigen_pop_len(); /* Else */ + + return 0; +} + +static int acpigen_soc_set_gpio_val(unsigned gpio_num, uint32_t val) +{ + assert (gpio_num < TOTAL_PADS); + + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); + + /* Store (\_SB.GPC0 (addr), Local5) */ + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.GPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + if (val) { + /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ + acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); + } else { + /* Not (PAD_CFG0_TX_STATE, Local6) */ + acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); + + /* And (Local5, Local6, Local5) */ + acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); + } + + /* \_SB.SPC0 (addr, Local5) */ + acpigen_emit_namestring("\\_SB.SPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); +} + +int acpigen_soc_get_tx_gpio(unsigned gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); +} + +int acpigen_soc_set_tx_gpio(unsigned gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 1); +} + +int acpigen_soc_clear_tx_gpio(unsigned gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 0); +}

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New patch to review for coreboot: mainboard/google/reef: Add PowerResource for ELAN touchscreen
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17083 -gerrit commit 9b6ac02df2f78247abe6d61a1a40fdef90b747e5 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:48:45 2016 -0700 mainboard/google/reef: Add PowerResource for ELAN touchscreen Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:55988 Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 00df9bd..30d61f6 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -142,6 +142,10 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "GPIO_36" + register "reset_delay_ms" = "20" + register "enable_gpio" = "GPIO_152" + register "enable_delay_ms" = "1" device i2c 10 on end end end # - I2C 3

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New patch to review for coreboot: soc/intel/apollolake: Implement GPIO ACPI AML generating functions
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17082 -gerrit commit 7756c76007d1916728125fcbc82b6c46b98a29f9 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:45:26 2016 -0700 soc/intel/apollolake: Implement GPIO ACPI AML generating functions Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio BUG=chrome-os-partner:55988 Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/apollolake/acpi.c | 81 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index ba22aee..ef93200 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -267,3 +267,84 @@ uint16_t soc_get_acpi_base_address(void) { return ACPI_PMIO_BASE; } + +static int acpigen_soc_get_gpio_val(unsigned gpio_num, uint32_t mask) +{ + assert (gpio_num < TOTAL_PADS); + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); + + /* Store (\_SB.GPC0 (addr), Local5) */ + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.GPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + /* If (And (Local5, mask)) */ + acpigen_write_if_and(LOCAL5_OP, mask); + + /* Store (One, Local0) */ + acpigen_write_store_ops(ONE_OP, LOCAL0_OP); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + + /* Store (Zero, Local0) */ + acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); + + acpigen_pop_len(); /* Else */ + + return 0; +} + +static int acpigen_soc_set_gpio_val(unsigned gpio_num, uint32_t val) +{ + assert (gpio_num < TOTAL_PADS); + + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); + + /* Store (\_SB.GPC0 (addr), Local5) */ + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.GPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + if (val) { + /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ + acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); + } else { + /* Not (PAD_CFG0_TX_STATE, Local6) */ + acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); + + /* And (Local5, Local6, Local5) */ + acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); + } + + /* \_SB.SPC0 (addr, Local5) */ + acpigen_emit_namestring("\\_SB.SPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); +} + +int acpigen_soc_get_tx_gpio(unsigned gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); +} + +int acpigen_soc_set_tx_gpio(unsigned gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 1); +} + +int acpigen_soc_clear_tx_gpio(unsigned gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 0); +}

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New patch to review for coreboot: i2c/generic: Enable support for adding PowerResource for device
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17081 -gerrit commit a84a82198313b9b5287cb295c92b67b4cc37ce1d Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 16:01:04 2016 -0700 i2c/generic: Enable support for adding PowerResource for device Add support to allow a device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: 1. Reset GPIO - Mandatory if PowerResource needs to be defined 2. Reset delay - Delay after reset GPIO is de-asserted (default 0) 3. Enable GPIO - Optional if a separate GPIO exists for enable 4. Enable delay - Delay after enable GPIO is asserted (default 0) BUG=chrome-os-partner:55988 Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 9 +++++++++ src/drivers/i2c/generic/generic.c | 39 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 48 insertions(+) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..e84fc38 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,13 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + + /* GPIO used to take device out of reset or to put it into reset. */ + unsigned reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned reset_delay_ms; + /* GPIO used to enable device. */ + unsigned enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned enable_delay_ms; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index c11a889..7f078b0 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,42 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) +{ + if (!config->reset_gpio) + return; + + const char *power_res_dev_states[] = { "_PR0", "_PR3" }; + + /* PowerResource (PRIC, 0, 0) */ + acpigen_write_power_res("PRIC", 0, 0, power_res_dev_states, + ARRAY_SIZE(power_res_dev_states)); + + /* Method (_STA, 0, NotSerialized) { Return (0x1) } */ + acpigen_write_STA(0x1); + + /* Method (_ON, 0, Serialized) */ + acpigen_write_method_serialized("_ON", 0); + acpigen_soc_set_tx_gpio(config->reset_gpio); + if (config->enable_gpio) { + acpigen_soc_set_tx_gpio(config->enable_gpio); + acpigen_write_sleep(config->enable_delay_ms); + } + acpigen_soc_clear_tx_gpio(config->reset_gpio); + acpigen_write_sleep(config->reset_delay_ms); + acpigen_pop_len(); /* _ON method */ + + /* Method (_OFF, 0, Serialized) */ + acpigen_write_method_serialized("_OFF", 0); + acpigen_soc_set_tx_gpio(config->reset_gpio); + if (config->enable_gpio) + acpigen_soc_clear_tx_gpio(config->enable_gpio); + acpigen_pop_len(); /* _OFF method */ + + acpigen_pop_len(); /* PowerResource PRIC */ +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -72,6 +108,9 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpi_dp_write(dsd); } + /* Power Resource */ + i2c_generic_add_power_res(config); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

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New patch to review for coreboot: x86/acpigen: Add support for interacting with GPIOs
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17080 -gerrit commit 4afa11b82e5dc98d47e5dc7d030b0a8a27006171 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 07:12:49 2016 -0700 x86/acpigen: Add support for interacting with GPIOs Since reading/toggling of GPIOs is platform-dependent task, provide an interface with common functions to generate ACPI AML code for manipulating GPIOs: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio Provide weak implementations of above functions. These functions are expected to be implemented by every SoC that uses ACPI. This allows drivers to easily generate ACPI AML code to interact GPIOs. BUG=chrome-os-partner:55988 Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 29 +++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 22 ++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 43de1d5..44c77cc 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -976,3 +976,32 @@ void acpigen_write_else(void) acpigen_emit_byte(ELSE_OP); acpigen_write_len_f(); } + +/* Soc-implemented functions -- weak definitions. */ +int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("read_rx_gpio not available"); + return -1; +} + +int __attribute__((weak)) acpigen_soc_get_tx_gpio(unsigned gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("get_tx_gpio not available"); + return -1; +} + +int __attribute__((weak)) acpigen_soc_set_tx_gpio(unsigned gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("set_tx_gpio not available"); + return -1; +} + +int __attribute__((weak)) acpigen_soc_clear_tx_gpio(unsigned gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("clear_tx_gpio not available"); + return -1; +} diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index c2936e2..8ac8f48 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -160,4 +160,26 @@ void acpigen_write_else(void); int get_cst_entries(acpi_cstate_t **); +/* + * Soc-implemented functions for generating ACPI AML code for GPIO handling. All + * these functions are expected to use only Local5, Local6 and Local7 + * variables. If the functions call into another ACPI method, then there is no + * restriction on the use of Local variables. In case of get/read functions, + * return value is expected to be stored in Local0 variable. + * + * All functions return 0 on success and -1 on error. + */ + +/* Generate ACPI AML code to return Rx value of GPIO in Local0. */ +int acpigen_soc_read_rx_gpio(unsigned gpio_num); + +/* Generate ACPI AML code to return Tx value of GPIO in Local0. */ +int acpigen_soc_get_tx_gpio(unsigned gpio_num); + +/* Generate ACPI AML code to set Tx value of GPIO to 1. */ +int acpigen_soc_set_tx_gpio(unsigned gpio_num); + +/* Generate ACPI AML code to set Tx value of GPIO to 0. */ +int acpigen_soc_clear_tx_gpio(unsigned gpio_num); + #endif

1 0

New patch to review for coreboot: arch/x86/acpigen: Add new functions to acpigen library
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17079 -gerrit commit 827df83aa1eee0688be501c707293fa0db5faa96 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 23:12:38 2016 -0700 arch/x86/acpigen: Add new functions to acpigen library Add functions to support generation of following AML operations: 1. PowerResource 2. Store 3. Or 4. And 5. Not 6. Debug 7. If 8. Else 9. Serialized method BUG=chrome-os-partner:55988 Change-Id: I606736b38e6a55ffdc3e814b6ae0fa367ef7595b Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 116 +++++++++++++++++++++++++++++++++++- src/arch/x86/include/arch/acpigen.h | 15 +++++ 2 files changed, 129 insertions(+), 2 deletions(-) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 27fa07a..43de1d5 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -438,12 +438,22 @@ void acpigen_write_empty_PTC(void) acpigen_pop_len(); } -void acpigen_write_method(const char *name, int nargs) +static void __acpigen_write_method(const char *name, uint8_t flags) { acpigen_emit_byte(METHOD_OP); acpigen_write_len_f(); acpigen_emit_namestring(name); - acpigen_emit_byte(nargs & 7); + acpigen_emit_byte(flags); +} + +void acpigen_write_method(const char *name, int nargs) +{ + __acpigen_write_method(name, (nargs & 7)); +} + +void acpigen_write_method_serialized(const char *name, int nargs) +{ + __acpigen_write_method(name, (nargs & 7) | (1 << 3)); } void acpigen_write_device(const char *name) @@ -864,3 +874,105 @@ void acpigen_write_uuid(const char *uuid) acpigen_pop_len(); } + +void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, + const char *dev_states[], size_t dev_states_count) +{ + int i; + for (i = 0; i < dev_states_count; i++) { + acpigen_write_name(dev_states[i]); + acpigen_write_package(1); + acpigen_emit_simple_namestring(name); + acpigen_pop_len(); /* Package */ + } + + acpigen_emit_ext_op(POWER_RES_OP); + + acpigen_write_len_f(); + + acpigen_emit_simple_namestring(name); + acpigen_emit_byte(level); + acpigen_emit_word(order); +} + +void acpigen_write_sleep(uint64_t sleep_ms) +{ + acpigen_emit_ext_op(SLEEP_OP); + acpigen_write_integer(sleep_ms); +} + +void acpigen_write_store(void) +{ + acpigen_emit_byte(STORE_OP); +} + +void acpigen_write_store_ops(uint8_t src, uint8_t dst) +{ + acpigen_write_store(); + acpigen_emit_byte(src); + acpigen_emit_byte(dst); +} + +void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res) +{ + acpigen_emit_byte(OR_OP); + acpigen_emit_byte(arg1); + acpigen_emit_byte(arg2); + acpigen_emit_byte(res); +} + +void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res) +{ + acpigen_emit_byte(AND_OP); + acpigen_emit_byte(arg1); + acpigen_emit_byte(arg2); + acpigen_emit_byte(res); +} + +void acpigen_write_not(uint8_t arg, uint8_t res) +{ + acpigen_emit_byte(NOT_OP); + acpigen_emit_byte(arg); + acpigen_emit_byte(res); +} + +void acpigen_write_debug_string(const char *str) +{ + acpigen_write_store(); + acpigen_write_string(str); + acpigen_emit_ext_op(DEBUG_OP); +} + +void acpigen_write_debug_integer(uint64_t val) +{ + acpigen_write_store(); + acpigen_write_integer(val); + acpigen_emit_ext_op(DEBUG_OP); +} + +void acpigen_write_debug_op(uint8_t op) +{ + acpigen_write_store(); + acpigen_emit_byte(op); + acpigen_emit_ext_op(DEBUG_OP); +} + +void acpigen_write_if(void) +{ + acpigen_emit_byte(IF_OP); + acpigen_write_len_f(); +} + +void acpigen_write_if_and(uint8_t arg1, uint8_t arg2) +{ + acpigen_write_if(); + acpigen_emit_byte(AND_OP); + acpigen_emit_byte(arg1); + acpigen_emit_byte(arg2); +} + +void acpigen_write_else(void) +{ + acpigen_emit_byte(ELSE_OP); + acpigen_write_len_f(); +} diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 4e8456d..c2936e2 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -114,6 +114,7 @@ void acpigen_write_name_integer(const char *name, uint64_t val); void acpigen_write_coreboot_hid(enum coreboot_acpi_ids id); void acpigen_write_scope(const char *name); void acpigen_write_method(const char *name, int nargs); +void acpigen_write_method_serialized(const char *name, int nargs); void acpigen_write_device(const char *name); void acpigen_write_PPC(u8 nr); void acpigen_write_PPC_NVS(void); @@ -142,6 +143,20 @@ void acpigen_write_mainboard_resource_template(void); void acpigen_write_mainboard_resources(const char *scope, const char *name); void acpigen_write_irq(u16 mask); void acpigen_write_uuid(const char *uuid); +void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, + const char *dev_states[], size_t dev_states_count); +void acpigen_write_sleep(uint64_t sleep_ms); +void acpigen_write_store(void); +void acpigen_write_store_ops(uint8_t src, uint8_t dst); +void acpigen_write_or(uint8_t arg1, uint8_t arg2, uint8_t res); +void acpigen_write_and(uint8_t arg1, uint8_t arg2, uint8_t res); +void acpigen_write_not(uint8_t arg, uint8_t res); +void acpigen_write_debug_string(const char *str); +void acpigen_write_debug_integer(uint64_t val); +void acpigen_write_debug_op(uint8_t op); +void acpigen_write_if(void); +void acpigen_write_if_and(uint8_t arg1, uint8_t arg2); +void acpigen_write_else(void); int get_cst_entries(acpi_cstate_t **);

1 0

New patch to review for coreboot: arch/x86/acpigen: Clean up acpigen library
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17078 -gerrit commit 2c620224387de51c3e2f883e1ebc087dd004fe32 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 23:09:05 2016 -0700 arch/x86/acpigen: Clean up acpigen library Instead of using hard-coded values for emitting op codes and prefix codes, define and use enum constants. With this change, it becomes easier to read the code as well. BUG=chrome-os-partner:55988 Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 72 ++++++++++++++++--------------------- src/arch/x86/include/arch/acpigen.h | 48 +++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 41 deletions(-) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 00f8bd0..27fa07a 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -73,6 +73,12 @@ void acpigen_emit_byte(unsigned char b) (*gencurrent++) = b; } +void acpigen_emit_ext_op(uint8_t op) +{ + acpigen_emit_byte(EXT_OP_PREFIX); + acpigen_emit_byte(op); +} + void acpigen_emit_word(unsigned int data) { acpigen_emit_byte(data & 0xff); @@ -90,8 +96,7 @@ void acpigen_emit_dword(unsigned int data) char *acpigen_write_package(int nr_el) { char *p; - /* package op */ - acpigen_emit_byte(0x12); + acpigen_emit_byte(PACKAGE_OP); acpigen_write_len_f(); p = acpigen_get_current(); acpigen_emit_byte(nr_el); @@ -100,46 +105,42 @@ char *acpigen_write_package(int nr_el) void acpigen_write_byte(unsigned int data) { - /* byte op */ - acpigen_emit_byte(0xa); + acpigen_emit_byte(BYTE_PREFIX); acpigen_emit_byte(data & 0xff); } void acpigen_write_word(unsigned int data) { - /* word op */ - acpigen_emit_byte(0xb); + acpigen_emit_byte(WORD_PREFIX); acpigen_emit_word(data); } void acpigen_write_dword(unsigned int data) { - /* dword op */ - acpigen_emit_byte(0xc); + acpigen_emit_byte(DWORD_PREFIX); acpigen_emit_dword(data); } void acpigen_write_qword(uint64_t data) { - /* qword op */ - acpigen_emit_byte(0xe); + acpigen_emit_byte(QWORD_PREFIX); acpigen_emit_dword(data & 0xffffffff); acpigen_emit_dword((data >> 32) & 0xffffffff); } void acpigen_write_zero(void) { - acpigen_emit_byte(0x00); + acpigen_emit_byte(ZERO_OP); } void acpigen_write_one(void) { - acpigen_emit_byte(0x01); + acpigen_emit_byte(ONE_OP); } void acpigen_write_ones(void) { - acpigen_emit_byte(0xff); + acpigen_emit_byte(ONES_OP); } void acpigen_write_integer(uint64_t data) @@ -216,7 +217,7 @@ void acpigen_emit_string(const char *string) void acpigen_write_string(const char *string) { - acpigen_emit_byte(0x0d); + acpigen_emit_byte(STRING_PREFIX); acpigen_emit_string(string); } @@ -251,8 +252,7 @@ static void acpigen_emit_simple_namestring(const char *name) { } static void acpigen_emit_double_namestring(const char *name, int dotpos) { - /* mark dual name prefix */ - acpigen_emit_byte(0x2e); + acpigen_emit_byte(DUAL_NAME_PREFIX); acpigen_emit_simple_namestring(name); acpigen_emit_simple_namestring(&name[dotpos + 1]); } @@ -260,9 +260,8 @@ static void acpigen_emit_double_namestring(const char *name, int dotpos) { static void acpigen_emit_multi_namestring(const char *name) { int count = 0; unsigned char *pathlen; - /* mark multi name prefix */ - acpigen_emit_byte(0x2f); - acpigen_emit_byte(0x0); + acpigen_emit_byte(MULTI_NAME_PREFIX); + acpigen_emit_byte(ZERO_OP); pathlen = ((unsigned char *) acpigen_get_current()) - 1; while (name[0] != '\0') { @@ -299,7 +298,7 @@ void acpigen_emit_namestring(const char *namepath) { /* If we have only \\ or only ^...^. Then we need to put a null name (0x00). */ if (namepath[0] == '\0') { - acpigen_emit_byte(0x00); + acpigen_emit_byte(ZERO_OP); return; } @@ -323,15 +322,13 @@ void acpigen_emit_namestring(const char *namepath) { void acpigen_write_name(const char *name) { - /* name op */ - acpigen_emit_byte(0x8); + acpigen_emit_byte(NAME_OP); acpigen_emit_namestring(name); } void acpigen_write_scope(const char *name) { - /* scope op */ - acpigen_emit_byte(0x10); + acpigen_emit_byte(SCOPE_OP); acpigen_write_len_f(); acpigen_emit_namestring(name); } @@ -343,9 +340,7 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { */ char pscope[16]; - /* processor op */ - acpigen_emit_byte(0x5b); - acpigen_emit_byte(0x83); + acpigen_emit_ext_op(PROCESSOR_OP); acpigen_write_len_f(); snprintf(pscope, sizeof(pscope), @@ -445,8 +440,7 @@ void acpigen_write_empty_PTC(void) void acpigen_write_method(const char *name, int nargs) { - /* method op */ - acpigen_emit_byte(0x14); + acpigen_emit_byte(METHOD_OP); acpigen_write_len_f(); acpigen_emit_namestring(name); acpigen_emit_byte(nargs & 7); @@ -454,9 +448,7 @@ void acpigen_write_method(const char *name, int nargs) void acpigen_write_device(const char *name) { - /* device op */ - acpigen_emit_byte(0x5b); - acpigen_emit_byte(0x82); + acpigen_emit_ext_op(DEVICE_OP); acpigen_write_len_f(); acpigen_emit_namestring(name); } @@ -467,7 +459,7 @@ void acpigen_write_STA(uint8_t status) * Method (_STA, 0, NotSerialized) { Return (status) } */ acpigen_write_method("_STA", 0); - acpigen_emit_byte(0xa4); + acpigen_emit_byte(RETURN_OP); acpigen_write_byte(status); acpigen_pop_len(); } @@ -484,8 +476,7 @@ void acpigen_write_PPC(u8 nr) } */ acpigen_write_method("_PPC", 0); - /* return */ - acpigen_emit_byte(0xa4); + acpigen_emit_byte(RETURN_OP); /* arg */ acpigen_write_byte(nr); acpigen_pop_len(); @@ -504,8 +495,7 @@ void acpigen_write_PPC_NVS(void) } */ acpigen_write_method("_PPC", 0); - /* return */ - acpigen_emit_byte(0xa4); + acpigen_emit_byte(RETURN_OP); /* arg */ acpigen_emit_namestring("PPCM"); acpigen_pop_len(); @@ -521,7 +511,7 @@ void acpigen_write_TPC(const char *gnvs_tpc_limit) } */ acpigen_write_method("_TPC", 0); - acpigen_emit_byte(0xa4); /* ReturnOp */ + acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring(gnvs_tpc_limit); acpigen_pop_len(); } @@ -731,9 +721,9 @@ void acpigen_write_resourcetemplate_header(void) * resource items, terminated by the end tag. * (small item 0xf, len 1) */ - acpigen_emit_byte(0x11); /* Buffer opcode */ + acpigen_emit_byte(BUFFER_OP); acpigen_write_len_f(); - acpigen_emit_byte(0x0b); /* Word opcode */ + acpigen_emit_byte(WORD_PREFIX); len_stack[ltop++] = acpigen_get_current(); acpigen_emit_byte(0x00); acpigen_emit_byte(0x00); @@ -862,7 +852,7 @@ void acpigen_write_uuid(const char *uuid) return; /* BufferOp */ - acpigen_emit_byte(0x11); + acpigen_emit_byte(BUFFER_OP); acpigen_write_len_f(); /* Buffer length in bytes */ diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index f513698..4e8456d 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -34,6 +34,53 @@ ACPI_STATUS_DEVICE_SHOW_IN_UI |\ ACPI_STATUS_DEVICE_STATE_OK) +/* ACPI Op/Prefix Codes */ +enum { + ZERO_OP = 0x00, + ONE_OP = 0x01, + NAME_OP = 0x08, + SCOPE_OP = 0x10, + BUFFER_OP = 0x11, + BYTE_PREFIX = 0x0A, + WORD_PREFIX = 0x0B, + DWORD_PREFIX = 0x0C, + STRING_PREFIX = 0x0D, + QWORD_PREFIX = 0x0E, + PACKAGE_OP = 0x12, + METHOD_OP = 0x14, + DUAL_NAME_PREFIX = 0x2E, + MULTI_NAME_PREFIX = 0x2F, + EXT_OP_PREFIX = 0x5B, + SLEEP_OP = 0x22, + DEBUG_OP = 0x31, + DEVICE_OP = 0x82, + PROCESSOR_OP = 0x83, + POWER_RES_OP = 0x84, + LOCAL0_OP = 0x60, + LOCAL1_OP = 0x61, + LOCAL2_OP = 0x62, + LOCAL3_OP = 0x63, + LOCAL4_OP = 0x64, + LOCAL5_OP = 0x65, + LOCAL6_OP = 0x66, + LOCAL7_OP = 0x67, + ARG0_OP = 0x68, + ARG1_OP = 0x69, + ARG2_OP = 0x6A, + ARG3_OP = 0x6B, + ARG4_OP = 0x6C, + ARG5_OP = 0x6D, + ARG6_OP = 0x6E, + STORE_OP = 0x70, + AND_OP = 0x7B, + OR_OP = 0x7D, + NOT_OP = 0x80, + IF_OP = 0xA0, + ELSE_OP = 0xA1, + RETURN_OP = 0xA4, + ONES_OP = 0xFF, +}; + void acpigen_write_len_f(void); void acpigen_pop_len(void); void acpigen_set_current(char *curr); @@ -44,6 +91,7 @@ void acpigen_write_one(void); void acpigen_write_ones(void); void acpigen_write_byte(unsigned int data); void acpigen_emit_byte(unsigned char data); +void acpigen_emit_ext_op(uint8_t op); void acpigen_emit_word(unsigned int data); void acpigen_emit_dword(unsigned int data); void acpigen_emit_stream(const char *data, int size);

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coreboot-gerrit October 2016