coreboot-gerrit October 2016

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Patch set updated for coreboot: soc/intel/apollolake: add Multiple FMAP build
by Brenton Dong 21 Oct '16

21 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17064 -gerrit commit 53dec8baddef16d1335dcc9dacc3d5398c54e975 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:21:12 2016 -0700 soc/intel/apollolake: add Multiple FMAP build Multiple coreboot binaries with separate FMAPs and separate CBFSs allow coreboot to run separate stages from different regions (SRAM, CAR, Mem). When enabling Multiple FMAP, 3 Coreboot Images will be created. IBBL: Contains bootblock, CAR init (FSP-T) and hands off to IBBM. IBBM: Contains romstage, mem init (FSP-M) and postcar. OBB: Contains ramstage, silicon init (FSP-S), and the rest of the components in the original single coreboot.rom file. This is the same image as the original coreboot.rom minus the components moved to the IBBL and IBBM. Add functions to select which region cbfs files will be loaded from. Verified on Intel Leaf Hill CRB and confirmed that the coreboot builds 3 separate coreboot files which can be loaded and booted. Verified that other ApolloLake projects can build correctly with this option disabled. Change-Id: Iab3c353b65e1e0fc9d04fcee6a82a330927db41e Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- Makefile.inc | 47 ++++++++++ src/arch/x86/Makefile.inc | 2 + src/drivers/intel/fsp2_0/Makefile.inc | 5 + src/soc/intel/apollolake/Kconfig | 6 ++ src/soc/intel/apollolake/Makefile.inc | 4 + src/soc/intel/apollolake/bootblock/bootblock.c | 57 ++++++++++++ src/soc/intel/apollolake/chip.c | 9 +- src/soc/intel/apollolake/include/soc/bootregion.h | 28 ++++++ src/soc/intel/apollolake/include/soc/cse.h | 30 ++++++ src/soc/intel/apollolake/include/soc/mmio.h | 35 +++++++ src/soc/intel/apollolake/mmap_boot.c | 2 + src/soc/intel/apollolake/mmap_boot_cse.c | 53 +++++++++++ src/soc/intel/apollolake/postcar.c | 10 ++ src/soc/intel/apollolake/romstage.c | 108 ++++++++++++++++++++++ 14 files changed, 395 insertions(+), 1 deletion(-) diff --git a/Makefile.inc b/Makefile.inc index 127f372..9e25883 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -826,11 +826,13 @@ ifneq ($(CONFIG_UPDATE_IMAGE),y) $(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc $(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc) ifeq ($(CONFIG_ARCH_X86),y) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) $(CBFSTOOL) $@.tmp add \ -f $(objcbfs)/bootblock.bin \ -n bootblock \ -t bootblock \ -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) +endif # ifeq ($(CONFIG_MULTIPLE_FMAP),y) else # ifeq ($(CONFIG_ARCH_X86),y) $(CBFSTOOL) $@.tmp write -u \ -r BOOTBLOCK \ @@ -865,6 +867,49 @@ $(REFCODE_BLOB): $(RMODTOOL) $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ endif + +ifeq ($(CONFIG_MULTIPLE_FMAP),y) + +.PHONY:$(obj)/coreboot_ibbl.rom +$(obj)/coreboot_ibbl.rom: $(call strip_quotes,$(CONFIG_FSP_T_FILE)) $(obj)/ibbl_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbl_fmap.fmap -r $(shell cat $(obj)/ibbl_fmap.desc) + $(CBFSTOOL) $@.tmp add \ + -f $(objcbfs)/bootblock.bin \ + -n bootblock \ + -t bootblock \ + -b -$(call file-size,$(objcbfs)/bootblock.bin) $(cbfs-autogen-attributes) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_T_FILE)) \ + -n blobs/fspt.bin -t fsp -y -b 0xC0 + mv $@.tmp $@ + @printf "\ncoreboot IBBL image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +.PHONY:$(obj)/coreboot_ibbm.rom +$(obj)/coreboot_ibbm.rom: $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(objcbfs)/romstage.elf \ + $(objcbfs)/postcar.elf \ + $(obj)/ibbm_fmap.desc $(CBFSTOOL) $$(INTERMEDIATE) + $(CBFSTOOL) $@.tmp create -M $(obj)/ibbm_fmap.fmap -r $(shell cat $(obj)/ibbm_fmap.desc) + $(CBFSTOOL) $@.tmp add-master-header + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/romstage.elf \ + -n $(CONFIG_CBFS_PREFIX)/romstage -c none \ + $(CBFSTOOL_PRE_OPTS) -b 0 + $(CBFSTOOL) $@.tmp add \ + -f $(call strip_quotes,$(CONFIG_FSP_M_FILE)) \ + -n blobs/fspm.bin -t fsp -y + $(CBFSTOOL) $@.tmp add-stage \ + -f $(objcbfs)/postcar.elf \ + -n $(CONFIG_CBFS_PREFIX)/postcar + mv $@.tmp $@ + @printf "\ncoreboot IBBM image size is 0x%x\n" `stat -L -c %s $@` + $(CBFSTOOL) $@ print + +coreboot: $(obj)/coreboot_ibbl.rom $(obj)/coreboot_ibbm.rom + +endif # ifneq ($(CONFIG_MULTIPLE_FMAP),y) + $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/ramstage.elf $(CBFSTOOL) $$(INTERMEDIATE) @printf " CBFS $(subst $(obj)/,,$(@))\n" # The full ROM may be larger than the CBFS part, so create an empty @@ -892,6 +937,7 @@ endif @printf " CBFSPRINT $(subst $(obj)/,,$(@))\n\n" $(CBFSTOOL) $@ print -r $(subst $(spc),$(comma),$(all-regions)) +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-y += $(CONFIG_CBFS_PREFIX)/romstage $(CONFIG_CBFS_PREFIX)/romstage-file := $(objcbfs)/romstage.elf $(CONFIG_CBFS_PREFIX)/romstage-type := stage @@ -924,6 +970,7 @@ endif # CONFIG_NO_FIXED_XIP_ROM_SIZE endif # CONFIG_NO_XIP_EARLY_STAGES endif # CONFIG_ARCH_ROMSTAGE_X86_32 / CONFIG_ARCH_ROMSTAGE_X86_64 +endif # CONFIG_MULTIPLE_FMAP cbfs-files-y += $(CONFIG_CBFS_PREFIX)/ramstage $(CONFIG_CBFS_PREFIX)/ramstage-file := $(objcbfs)/ramstage.elf diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 782ca63..fc7eb5c 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -300,10 +300,12 @@ $(objcbfs)/postcar.elf: $(objcbfs)/postcar.debug.rmod cp $< $@ # Add postcar to CBFS +ifneq ($(CONFIG_MULTIPLE_FMAP),y) cbfs-files-$(CONFIG_POSTCAR_STAGE) += $(CONFIG_CBFS_PREFIX)/postcar $(CONFIG_CBFS_PREFIX)/postcar-file := $(objcbfs)/postcar.elf $(CONFIG_CBFS_PREFIX)/postcar-type := stage $(CONFIG_CBFS_PREFIX)/postcar-compression := none +endif #CONFIG_MULTIPLE_FMAP ############################################################################### # ramstage diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index c5b719d..6866cc1 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -46,6 +46,8 @@ CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +ifneq ($(CONFIG_MULTIPLE_FMAP),y) + ifeq ($(CONFIG_FSP_CAR),y) cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_T_CBFS) $(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) @@ -58,6 +60,9 @@ endif # CONFIG_FSP_CAR cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp + +endif #CONFIG_MULTIPLE_FMAP + ifeq ($(CONFIG_FSP_M_XIP),y) $(CONFIG_FSP_M_CBFS)-options := --xip endif diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 6c178c3..eeba42a 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -81,6 +81,12 @@ config TPM_ON_FAST_SPI TPM part is conntected on Fast SPI interface, but the LPC MMIO TPM transactions are decoded and serialized over the SPI interface. +config MULTIPLE_FMAP + depends on FSP_CAR + bool + help + Enable build with mulitple coreboot images and each will has its own fmap. + config SOC_INTEL_COMMON_RESET bool default y diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index b4a79f0..fdbc903 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -15,6 +15,7 @@ bootblock-y += gpio.c bootblock-y += heci.c bootblock-y += itss.c bootblock-y += lpc_lib.c +bootblock-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c bootblock-y += mmap_boot.c bootblock-y += pmutil.c bootblock-y += spi.c @@ -37,6 +38,7 @@ romstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c romstage-y += lpc_lib.c romstage-y += memmap.c romstage-y += meminit.c +romstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c romstage-y += mmap_boot.c romstage-y += tsc_freq.c romstage-y += pmutil.c @@ -65,6 +67,7 @@ ramstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c ramstage-y += lpc.c ramstage-y += lpc_lib.c ramstage-y += memmap.c +ramstage-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c ramstage-y += mmap_boot.c ramstage-y += p2sb.c ramstage-y += uart.c @@ -81,6 +84,7 @@ ramstage-y += spi.c ramstage-y += xhci.c postcar-y += memmap.c +postcar-$(CONFIG_MULTIPLE_FMAP) += mmap_boot_cse.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 28a9128..22a4d44 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -14,6 +14,7 @@ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. */ +#include <string.h> #include <arch/cpu.h> #include <bootblock_common.h> #include <cpu/x86/mtrr.h> @@ -31,6 +32,53 @@ #include <spi-generic.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm0(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_num; + uint32_t state; + msr_t msr; + + /* Request data from CSE */ + host_to_cse = (ibbm_size << 4) | 0xC0000000; + CSE_HOST2CSE = host_to_cse; + + /* Wait for response */ + do { + cse_to_host = CSE_CSE2HOST; + chunk_num = (cse_to_host >> 28) & 3; + } while (!chunk_num); + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* + * The 1st 128K should have been loaded into SRAM now + * However, since the top 32K IBBL is still cached, we can only read + * (128-32)K at this moment. The remaining will be read in romstage. + */ + memcpy((void *)ibbm_base, (void *)(~CSE_IBB_SRAM_SIZE + 1), + CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE); + + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + the temporary memory */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + static const struct pad_config tpm_spi_configs[] = { PAD_CFG_NF(GPIO_106, NATIVE, DEEP, NF3), /* FST_SPI_CS2_N */ }; @@ -92,6 +140,15 @@ void asmlinkage bootblock_c_entry(uint64_t base_timestamp) enable_cmos_upper_bank(); +#if CONFIG_MULTIPLE_FMAP + /* Loading IBBM into CAR */ + load_ibbm0(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE, CONFIG_IBBM_ROM_SIZE); + + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); +#endif //CONFIG_MULTIPLE_FMAP + /* Call lib/bootblock.c main */ bootblock_main_with_timestamp(base_timestamp); } diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index d722992..0a184eb 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -35,9 +35,12 @@ #include <soc/pm.h> #include <soc/p2sb.h> #include <soc/northbridge.h> - #include "chip.h" +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif /* CONFIG_MULTIPLE_FMAP */ + static void *vbt; static struct region_device vbt_rdev; @@ -267,6 +270,10 @@ static void soc_init(void *data) * default policy that doesn't honor boards' requirements. */ itss_snapshot_irq_polarities(GPIO_IRQ_START, GPIO_IRQ_END); +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_OBB); +#endif //CONFIG_MULTIPLE_FMAP + fsp_silicon_init(); /* Restore GPIO IRQ polarities back to previous settings. */ diff --git a/src/soc/intel/apollolake/include/soc/bootregion.h b/src/soc/intel/apollolake/include/soc/bootregion.h new file mode 100644 index 0000000..dde562a --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/bootregion.h @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_BOOT_RGN_H_ +#define _SOC_LEAFHILL_BOOT_RGN_H_ + +#define BOOT_REGION_IBBL 0 +#define BOOT_REGION_IBBM 1 +#define BOOT_REGION_OBB 2 + +/* Set current active boot region */ +void set_boot_region(int region_id); + +#endif /* _SOC_LEAFHILL_BOOT_RGN_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/cse.h b/src/soc/intel/apollolake/include/soc/cse.h new file mode 100644 index 0000000..ed2b136 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/cse.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_LEAFHILL_CSE_H_ +#define _SOC_LEAFHILL_CSE_H_ + +#define HOST2CSE 0x70 +#define CSE2HOST 0x60 +#define CSE_IBB_SRAM_SIZE 0x20000 + +#define CSE_CFG_BASE (CONFIG_MMCONF_BASE_ADDRESS + 0x78000) +#define CSE_VIDDID (*(volatile int32_t *)CSE_CFG_BASE) +#define CSE_HOST2CSE (*(volatile int32_t *)(CSE_CFG_BASE + HOST2CSE)) +#define CSE_CSE2HOST (*(volatile int32_t *)(CSE_CFG_BASE + CSE2HOST)) + +#endif /* _SOC_LEAFHILL_CSE_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/mmio.h b/src/soc/intel/apollolake/include/soc/mmio.h new file mode 100644 index 0000000..674e071 --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/mmio.h @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_MMIO_H_ +#define _SOC_MMIO_H_ + + +#define MmioRead32(x) (*(volatile uint32_t *)(unsigned int)(x)) +#define MmioWrite32(x, y) (*(volatile uint32_t *)(unsigned int)(x) = y) +#define MmioRead16(x) (*(volatile uint16_t *)(unsigned int)(x)) +#define MmioWrite16(x, y) (*(volatile uint16_t *)(unsigned int)(x) = y) +#define MmioRead8(x) (*(volatile uint8_t *)(unsigned int)(x)) +#define MmioWrite8(x, y) (*(volatile uint8_t *)(unsigned int)(x) = y) + +#define PCIE_MMIO(Bus, Device, Function, Register) \ + ((unsigned int)CONFIG_MMCONF_BASE_ADDRESS + \ + (unsigned int)(Bus << 20) + \ + (unsigned int)(Device << 15) + \ + (unsigned int)(Function << 12) + \ + (unsigned int)(Register) \ + ) + +#endif diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index bf2e5b9..994f7b8 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -113,6 +113,7 @@ static void bios_mmap_init(void) car_set_var(bios_size, size); } +#if !CONFIG_MULTIPLE_FMAP const struct region_device *boot_device_ro(void) { bios_mmap_init(); @@ -122,6 +123,7 @@ const struct region_device *boot_device_ro(void) return &real_dev_ptr->rdev; } +#endif //CONFIG_MULTIPLE_FMAP static int iafw_boot_region_properties(struct cbfs_props *props) { diff --git a/src/soc/intel/apollolake/mmap_boot_cse.c b/src/soc/intel/apollolake/mmap_boot_cse.c new file mode 100644 index 0000000..d5b4526 --- /dev/null +++ b/src/soc/intel/apollolake/mmap_boot_cse.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <boot_device.h> +#include <cbfs.h> +#include <commonlib/region.h> +#include <console/console.h> +#include <fmap.h> +#include <soc/bootregion.h> +#include <soc/intel/common/nvm.h> +#include <arch/early_variables.h> + +/* The ROM is memory mapped just below 4GiB. Form a pointer for the base. */ +#define rom_base(x) (void *)(uintptr_t)(-(int32_t)(x)) +#define IBBL_ROM_BASE rom_base(CONFIG_IBBL_ROM_SIZE) +#define IBBM_ROM_BASE (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE \ + - CONFIG_IBBM_ROM_SIZE) + +static int curr_boot_region CAR_GLOBAL; + +static const struct mem_region_device boot_dev[] = { + MEM_REGION_DEV_RO_INIT(IBBL_ROM_BASE, CONFIG_IBBL_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(IBBM_ROM_BASE, CONFIG_IBBM_ROM_SIZE), + MEM_REGION_DEV_RO_INIT(CONFIG_RAMTOP, CONFIG_ROM_SIZE) +}; + +#if CONFIG_MULTIPLE_FMAP +const struct region_device *boot_device_ro(void) +{ + return &boot_dev[car_get_var(curr_boot_region)].rdev; +} +#endif //CONFIG_MULTIPLE_FMAP + +void set_boot_region(int rgn_idx) +{ + if (rgn_idx < sizeof(boot_dev)/sizeof(boot_dev[0])) + car_set_var(curr_boot_region, rgn_idx); +} diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c index 0b0e4ca..7c24fe9 100644 --- a/src/soc/intel/apollolake/postcar.c +++ b/src/soc/intel/apollolake/postcar.c @@ -23,9 +23,19 @@ #include <soc/postcar.h> #include <boot_device.h> +#if CONFIG_MULTIPLE_FMAP +#include <soc/bootregion.h> +#endif + void post_car_main(void) { +#if CONFIG_MULTIPLE_FMAP + set_boot_region(BOOT_REGION_IBBM); + temp_ram_exit(); + set_boot_region(BOOT_REGION_OBB); +#else temp_ram_exit(); +#endif /* Recover cbmem so infrastruture using it is functional. */ cbmem_initialize(); diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 1f6a38f..69d7273 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -41,6 +41,12 @@ #include <string.h> #include <timestamp.h> +#if CONFIG_MULTIPLE_FMAP +#include <cpu/x86/msr.h> +#include <soc/cse.h> +#include <soc/bootregion.h> +#endif //CONFIG_MULTIPLE_FMAP + static struct chipset_power_state power_state CAR_GLOBAL; /* High Performance Event Timer Configuration */ @@ -100,6 +106,92 @@ static void migrate_power_state(int is_recovery) } ROMSTAGE_CBMEM_INIT_HOOK(migrate_power_state); +#if CONFIG_MULTIPLE_FMAP +static void load_ibbm1(uint32_t ibbm_base, uint32_t ibbm_size) +{ + uint32_t state; + uint32_t size; + uint8_t ring_idx; + uint32_t host_to_cse; + uint32_t cse_to_host; + uint32_t chunk_idx; + uint32_t chunk_size; + uint32_t chunk_num; + uint32_t ibb_remaining; + uint8_t *src; + uint8_t *dst; + uint8_t *ptr; + msr_t msr; + + /* Set IBBL cache to UC */ + msr = rdmsr(0x202); + msr.lo &= ~0x0f; + wrmsr(0x202, msr); + + /* Init variables */ + size = CONFIG_IBBL_ROM_SIZE; + dst = (uint8_t *)ibbm_base; + src = (uint8_t *)(~CONFIG_IBBL_ROM_SIZE + 1); + memcpy(dst, src, size); + + cse_to_host = CSE_CSE2HOST; + host_to_cse = CSE_HOST2CSE; + chunk_num = (cse_to_host >> 28) & 3; + if (chunk_num == 3) + chunk_num = 4; + chunk_size = CSE_IBB_SRAM_SIZE / chunk_num; + chunk_idx = chunk_num; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~0x0f) | (cse_to_host & 0x0f); + CSE_HOST2CSE = host_to_cse; + + ibb_remaining = ibbm_size - size; + while (ibb_remaining > 0) { + + /* Check whether there is ring buffer ready to copy */ + state = (cse_to_host ^ host_to_cse) & 0x0F; + while (state == 0) { + cse_to_host = CSE_CSE2HOST; + state = (cse_to_host ^ host_to_cse) & 0x0F; + } + + /* Calculate ring index */ + ring_idx = (uint8_t)(chunk_idx % chunk_num); + if (state & (1 << ring_idx)) { + /* Calculate source and dest. address in ring buffer */ + src += chunk_size; + dst += chunk_size; + if (src == 0) + src = (uint8_t *)(~CSE_IBB_SRAM_SIZE + 1); + if (ibb_remaining < chunk_size) + size = ibb_remaining; + else + size = chunk_size; + + /* Move data from SRAM into temporary memory */ + memcpy(dst, src, size); + ibb_remaining -= size; + + /* Send ACK to CSE */ + ptr = (uint8_t *)&host_to_cse; + *ptr = ((*ptr) & ~(1 << ring_idx)) | + (cse_to_host & (1 << ring_idx)); + CSE_HOST2CSE = host_to_cse; + + chunk_idx++; + } + } + /* Set BIT8 in MSR 0x120 to allow IBB to be executed from + * the temporary memory + */ + msr = rdmsr(0x120); + msr.lo |= (1<<8); + wrmsr(0x120, msr); +} +#endif //CONFIG_MULTIPLE_FMAP + asmlinkage void car_stage_entry(void) { struct postcar_frame pcf; @@ -109,6 +201,10 @@ asmlinkage void car_stage_entry(void) void *smm_base; size_t smm_size; uintptr_t tseg_base; +#if CONFIG_MULTIPLE_FMAP + uint32_t ibbm_base; + uint32_t ibbm_loaded; +#endif //CONFIG_MULTIPLE_FMAP timestamp_add_now(TS_START_ROMSTAGE); @@ -117,6 +213,18 @@ asmlinkage void car_stage_entry(void) console_init(); +#if CONFIG_MULTIPLE_FMAP + /* Switch to new boot device in CAR */ + set_boot_region(BOOT_REGION_IBBM); + + /* load the remaining IBBM */ + ibbm_loaded = CSE_IBB_SRAM_SIZE - CONFIG_IBBL_ROM_SIZE; + ibbm_base = CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE + - CONFIG_IBBM_ROM_SIZE; + load_ibbm1(ibbm_base + ibbm_loaded, + CONFIG_IBBM_ROM_SIZE - ibbm_loaded); +#endif //CONFIG_MULTIPLE_FMAP + s3wake = fill_power_state(ps) == ACPI_S3; fsp_memory_init(s3wake); if (postcar_frame_init(&pcf, 1*KiB))

1 0

Patch set updated for coreboot: mainboard/intel/leafhill: add LeafHill CRB (Apollo Lake)
by Brenton Dong 21 Oct '16

21 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17065 -gerrit commit d667944c6b48450abb3ce5ed9b820ecb7ec59c13 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Wed Oct 19 14:40:39 2016 -0700 mainboard/intel/leafhill: add LeafHill CRB (Apollo Lake) Leaf Hill CRB is an Intel Customer Reference Board with ApolloLake silicon and LPDDR4 Down. Verified on Intel Leaf Hill CRB and confirmed to boot using Intel UEFI Payload and Yocto Linux. Change-Id: Ieeed6a7e5e9b6f02e4dd7e15cbcb58894c3c4eac Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/mainboard/intel/leafhill/Kconfig | 45 ++++++++++ src/mainboard/intel/leafhill/Kconfig.name | 3 + src/mainboard/intel/leafhill/Makefile.inc | 64 ++++++++++++++ src/mainboard/intel/leafhill/acpi_tables.c | 14 +++ src/mainboard/intel/leafhill/board.h | 36 ++++++++ src/mainboard/intel/leafhill/board_info.txt | 6 ++ src/mainboard/intel/leafhill/brd_gpio.h | 65 ++++++++++++++ src/mainboard/intel/leafhill/devicetree.cb | 56 ++++++++++++ src/mainboard/intel/leafhill/dsdt.asl | 37 ++++++++ src/mainboard/intel/leafhill/ibb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/obb_fmap.fmd | 6 ++ src/mainboard/intel/leafhill/romstage.c | 128 ++++++++++++++++++++++++++++ 12 files changed, 466 insertions(+) diff --git a/src/mainboard/intel/leafhill/Kconfig b/src/mainboard/intel/leafhill/Kconfig new file mode 100644 index 0000000..462e458 --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig @@ -0,0 +1,45 @@ +if BOARD_INTEL_LEAFHILL + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_TABLES + +config MAINBOARD_DIR + string + default intel/leafhill + +config MAINBOARD_PART_NUMBER + string + default "LeafHill" + +config MAINBOARD_VENDOR + string + default "Intel" + +config IFD_BIOS_END + hex + default 0x6FF000 + +config IFD_BIOS_START + hex + default 0x1000 + +config IBBL_ROM_SIZE + hex + default 0x10000 + +config IBBM_ROM_SIZE + hex + default 0x62000 + +config OBB_ROM_SIZE + hex + default 0x100000 + +config OBB_ROM_BASE + hex + default 0x200000 + +endif diff --git a/src/mainboard/intel/leafhill/Kconfig.name b/src/mainboard/intel/leafhill/Kconfig.name new file mode 100644 index 0000000..72664cd --- /dev/null +++ b/src/mainboard/intel/leafhill/Kconfig.name @@ -0,0 +1,3 @@ +config BOARD_INTEL_LEAFHILL + bool "LeafHill" + diff --git a/src/mainboard/intel/leafhill/Makefile.inc b/src/mainboard/intel/leafhill/Makefile.inc new file mode 100644 index 0000000..271b20a --- /dev/null +++ b/src/mainboard/intel/leafhill/Makefile.inc @@ -0,0 +1,64 @@ +#Nothing here yet + +MAINBOARD_PATH := $(src)/mainboard/$(call strip_quotes,$(CONFIG_MAINBOARD_DIR)) +IBB_FLASHMAP := $(MAINBOARD_PATH)/ibb_fmap.fmd + +IBBL_FMAP_ROM_ADDR := $(call int-subtract, 0x100000000 $(CONFIG_IBBL_ROM_SIZE)) +IBBL_FMAP_ROM_SIZE := $(CONFIG_IBBL_ROM_SIZE) +IBBL_FMAP_BIOS_BASE := 0 +IBBL_FMAP_BIOS_SIZE := $(IBBL_FMAP_ROM_SIZE) +IBBL_FMAP_FMAP_BASE := 0 +IBBL_FMAP_FMAP_SIZE := 0x100 +IBBL_FMAP_CBFS_BASE := $(IBBL_FMAP_FMAP_SIZE) +IBBL_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBL_FMAP_BIOS_SIZE) $(IBBL_FMAP_FMAP_SIZE)) + +$(obj)/ibbl_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBL_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBL_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBL_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBL_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBL_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBL_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBL_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBL_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbl_fmap.fmap +$(obj)/ibbl_fmap_config.h: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.desc: $(obj)/ibbl_fmap.fmap +$(obj)/ibbl_fmap.fmap: $(obj)/ibbl_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbl_fmap_config.h -R $(obj)/ibbl_fmap.desc $< $@ + + +IBBM_FMAP_CAR_TOP := $(call int-add, $(CONFIG_DCACHE_RAM_BASE) $(CONFIG_DCACHE_RAM_SIZE)) +IBBM_FMAP_ROM_ADDR := $(call int-subtract, $(IBBM_FMAP_CAR_TOP) $(CONFIG_IBBM_ROM_SIZE)) +IBBM_FMAP_ROM_SIZE := $(CONFIG_IBBM_ROM_SIZE) +IBBM_FMAP_BIOS_BASE := 0 +IBBM_FMAP_BIOS_SIZE := $(IBBM_FMAP_ROM_SIZE) +IBBM_FMAP_FMAP_BASE := 0 +IBBM_FMAP_FMAP_SIZE := 0x100 +IBBM_FMAP_CBFS_BASE := $(IBBM_FMAP_FMAP_SIZE) +IBBM_FMAP_CBFS_SIZE := $(call int-subtract, $(IBBM_FMAP_BIOS_SIZE) $(IBBM_FMAP_FMAP_SIZE)) + +$(obj)/ibbm_fmap.fmd: $(top)/Makefile.inc $(IBB_FLASHMAP) $(obj)/config.h $(MAINBOARD_PATH)/Makefile.inc + sed -e "s,##ROM_BASE##,$(IBBM_FMAP_ROM_ADDR)," \ + -e "s,##ROM_SIZE##,$(IBBM_FMAP_ROM_SIZE)," \ + -e "s,##BIOS_BASE##,$(IBBM_FMAP_BIOS_BASE)," \ + -e "s,##BIOS_SIZE##,$(IBBM_FMAP_BIOS_SIZE)," \ + -e "s,##FMAP_BASE##,$(IBBM_FMAP_FMAP_BASE)," \ + -e "s,##FMAP_SIZE##,$(IBBM_FMAP_FMAP_SIZE)," \ + -e "s,##CBFS_BASE##,$(IBBM_FMAP_CBFS_BASE)," \ + -e "s,##CBFS_SIZE##,$(IBBM_FMAP_CBFS_SIZE)," \ + $(IBB_FLASHMAP) > $@.tmp + mv $@.tmp $@ + +# generated at the same time as ibbm_fmap.fmap +$(obj)/ibbm_fmap_config.h: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.desc: $(obj)/ibbm_fmap.fmap +$(obj)/ibbm_fmap.fmap: $(obj)/ibbm_fmap.fmd $(FMAPTOOL) + echo " FMAP $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h $< $@" + $(FMAPTOOL) -h $(obj)/ibbm_fmap_config.h -R $(obj)/ibbm_fmap.desc $< $@ + +# brenton: changed this to headerromstage-y += brd_gpio.c diff --git a/src/mainboard/intel/leafhill/acpi_tables.c b/src/mainboard/intel/leafhill/acpi_tables.c new file mode 100644 index 0000000..8d4d1cf --- /dev/null +++ b/src/mainboard/intel/leafhill/acpi_tables.c @@ -0,0 +1,14 @@ +/* + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Blank file required by build system assumptions of this file being present. + */ diff --git a/src/mainboard/intel/leafhill/board.h b/src/mainboard/intel/leafhill/board.h new file mode 100644 index 0000000..90e2a10 --- /dev/null +++ b/src/mainboard/intel/leafhill/board.h @@ -0,0 +1,36 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_BOARD_H_ +#define _SOC_BOARD_H_ + +typedef struct { + uint32_t VendorDeviceId; //Codec Vendor/Device ID + uint8_t RevisionId; //Coden Revision ID. 0xFF matches any rev + uint8_t SdiNo; //SDI number, 0xFF matches any SDI. + uint16_t DataDwords; //Number of data DWORDs following header + uint8_t FrontPanelSupport; + uint8_t Padding[3]; +} BL_HDA_VERB_TABLE_HEADER; + +typedef struct { + BL_HDA_VERB_TABLE_HEADER VerbTableHeader; + uint32_t VerbTableData[]; +} BL_HDAUDIO_VERB_TABLE; + +void config_board_gpio(void); + + +#endif diff --git a/src/mainboard/intel/leafhill/board_info.txt b/src/mainboard/intel/leafhill/board_info.txt new file mode 100644 index 0000000..eb95944 --- /dev/null +++ b/src/mainboard/intel/leafhill/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: Apollolake RVP Reference Board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/leafhill/brd_gpio.h b/src/mainboard/intel/leafhill/brd_gpio.h new file mode 100644 index 0000000..3cd47a7 --- /dev/null +++ b/src/mainboard/intel/leafhill/brd_gpio.h @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <soc/mmio.h> +#include <soc/gpio.h> +#include "board.h" + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/intel/leafhill/devicetree.cb b/src/mainboard/intel/leafhill/devicetree.cb new file mode 100644 index 0000000..746aaf3 --- /dev/null +++ b/src/mainboard/intel/leafhill/devicetree.cb @@ -0,0 +1,56 @@ +chip soc/intel/apollolake + + register "pcie_rp0_clkreq_pin" = "2" # PCIe slot 2 + register "pcie_rp1_clkreq_pin" = "3" # Wifi+BT M2 slot + register "pcie_rp2_clkreq_pin" = "0" # PCIe slot 1 + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + device cpu_cluster 0 on + device lapic 0 on end + end + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 11.0 on end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 + device pci 13.2 on end # - Onboard Lan + device pci 13.3 on end # - PCIe-A 3 + device pci 14.0 on end # - PCIe-B 0 + device pci 14.1 on end # - Onboard M2 Slot(Wifi/BT) + device pci 15.0 on end # - XHCI + device pci 15.1 on end # - XDCI + device pci 16.0 on end # - I2C 0 + device pci 16.1 on end # - I2C 1 + device pci 16.2 on end # - I2C 2 + device pci 16.3 on end # - I2C 3 + device pci 17.0 on end # - I2C 4 + device pci 17.1 on end # - I2C 5 + device pci 17.2 on end # - I2C 6 + device pci 17.3 on end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 on end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 on end # - SPI 1 + device pci 19.2 on end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 on end # - SDIO + device pci 1f.0 on end # - LPC + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/intel/leafhill/dsdt.asl b/src/mainboard/intel/leafhill/dsdt.asl new file mode 100644 index 0000000..53a7b0f --- /dev/null +++ b/src/mainboard/intel/leafhill/dsdt.asl @@ -0,0 +1,37 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corp. + * (Written by Lijian Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, /* DSDT revision: ACPI v2.0 */ + "COREv4", /* OEM id */ + "COREBOOT", /* OEM table id */ + 0x20110725 /* OEM revision */ +) +{ + Scope (\_SB) { + Device (PCI0) + { + Name (_HID, EISAID ("PNP0A08")) /* PCIe */ + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> + +} diff --git a/src/mainboard/intel/leafhill/ibb_fmap.fmd b/src/mainboard/intel/leafhill/ibb_fmap.fmd new file mode 100644 index 0000000..06e905c --- /dev/null +++ b/src/mainboard/intel/leafhill/ibb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@##ROM_BASE## ##ROM_SIZE## { + BIOS@##BIOS_BASE## ##BIOS_SIZE## { + FMAP@##FMAP_BASE## ##FMAP_SIZE## + COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE## + } +} diff --git a/src/mainboard/intel/leafhill/obb_fmap.fmd b/src/mainboard/intel/leafhill/obb_fmap.fmd new file mode 100644 index 0000000..d0d0720 --- /dev/null +++ b/src/mainboard/intel/leafhill/obb_fmap.fmd @@ -0,0 +1,6 @@ +FLASH@0x200000 0x100000 { + BIOS@0 0x100000 { + FMAP@0 0x100 + COREBOOT(CBFS)@0x100 1048320 + } +} \ No newline at end of file diff --git a/src/mainboard/intel/leafhill/romstage.c b/src/mainboard/intel/leafhill/romstage.c new file mode 100644 index 0000000..256570a --- /dev/null +++ b/src/mainboard/intel/leafhill/romstage.c @@ -0,0 +1,128 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Lance Zhao <lijian.zhao(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/romstage.h> +#include <console/console.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "board.h" +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* DRAM Config settings */ + mupd->FspmConfig.Package = 0x1; + mupd->FspmConfig.Profile = 0xB; + mupd->FspmConfig.MemoryDown = 0x1; + mupd->FspmConfig.DDR3LPageSize = 0x0; + mupd->FspmConfig.DDR3LASR = 0x0; + mupd->FspmConfig.ScramblerSupport = 0x1; + mupd->FspmConfig.ChannelHashMask = 0x36; + mupd->FspmConfig.SliceHashMask = 0x9; + mupd->FspmConfig.InterleavedMode = 0x2; + mupd->FspmConfig.ChannelsSlicesEnable = 0x0; + mupd->FspmConfig.MinRefRate2xEnable = 0x0; + mupd->FspmConfig.DualRankSupportEnable = 0x1; + mupd->FspmConfig.RmtMode = 0x0; + mupd->FspmConfig.MemorySizeLimit = 0x1800; + mupd->FspmConfig.LowMemoryMaxValue = 0x0; + mupd->FspmConfig.DisableFastBoot = 0x0; + mupd->FspmConfig.HighMemoryMaxValue = 0x0; + mupd->FspmConfig.DIMM0SPDAddress = 0x0; + mupd->FspmConfig.DIMM1SPDAddress = 0x0; + mupd->FspmConfig.Ch0_RankEnable = 0x3; + mupd->FspmConfig.Ch0_DeviceWidth = 0x1; + mupd->FspmConfig.Ch0_DramDensity = 0x2; + mupd->FspmConfig.Ch0_Option = 0x3; + mupd->FspmConfig.Ch0_OdtConfig = 0x0; + mupd->FspmConfig.Ch0_TristateClk1 = 0x0; + mupd->FspmConfig.Ch0_Mode2N = 0x0; + mupd->FspmConfig.Ch0_OdtLevels = 0x0; + mupd->FspmConfig.Ch1_RankEnable = 0x3; + mupd->FspmConfig.Ch1_DeviceWidth = 0x1; + mupd->FspmConfig.Ch1_DramDensity = 0x2; + mupd->FspmConfig.Ch1_Option = 0x3; + mupd->FspmConfig.Ch1_OdtConfig = 0x0; + mupd->FspmConfig.Ch1_TristateClk1 = 0x0; + mupd->FspmConfig.Ch1_Mode2N = 0x0; + mupd->FspmConfig.Ch1_OdtLevels = 0x0; + mupd->FspmConfig.Ch2_RankEnable = 0x3; + mupd->FspmConfig.Ch2_DeviceWidth = 0x1; + mupd->FspmConfig.Ch2_DramDensity = 0x2; + mupd->FspmConfig.Ch2_Option = 0x3; + mupd->FspmConfig.Ch2_OdtConfig = 0x0; + mupd->FspmConfig.Ch2_TristateClk1 = 0x0; + mupd->FspmConfig.Ch2_Mode2N = 0x0; + mupd->FspmConfig.Ch2_OdtLevels = 0x0; + mupd->FspmConfig.Ch3_RankEnable = 0x3; + mupd->FspmConfig.Ch3_DeviceWidth = 0x1; + mupd->FspmConfig.Ch3_DramDensity = 0x2; + mupd->FspmConfig.Ch3_Option = 0x3; + mupd->FspmConfig.Ch3_OdtConfig = 0x0; + mupd->FspmConfig.Ch3_TristateClk1 = 0x0; + mupd->FspmConfig.Ch3_Mode2N = 0x0; + mupd->FspmConfig.Ch3_OdtLevels = 0x0; + mupd->FspmConfig.RmtCheckRun = 0x0; + mupd->FspmConfig.MrcDataSaving = 0x1; + mupd->FspmConfig.MrcFastBoot = 0x1; + + memcpy(mupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(mupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + mupd->FspmConfig.MsgLevelMask = 0x0; + + /* Request FSP to load the coreboot primary CBFS */ + mupd->FspmConfig.OemLoadingBase = CONFIG_OBB_ROM_BASE; + strcpy((char *)mupd->FspmConfig.OemFileName, "OBB"); + +}

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New patch to review for coreboot: google/reef/variants/pyro: Use WCOM Touchscreen driver
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17093 -gerrit commit 7867032f3bd41de94732110fa10efabfcac542d0 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:45:59 2016 -0700 google/reef/variants/pyro: Use WCOM Touchscreen driver BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 3 +++ src/mainboard/google/reef/variants/pyro/devicetree.cb | 7 ++++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d5d64c8..6045f47 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -40,6 +40,9 @@ config DRIVERS_I2C_DA7219 config DRIVERS_I2C_GENERIC default y +config DRIVERS_I2C_WACOM_TS + default y + config DRIVERS_PS2_KEYBOARD default y diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 43ec2ed..f1fccb8 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -132,10 +132,11 @@ chip soc/intel/apollolake end # - I2C 2 device pci 16.3 on chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" + register "hid" = ""WCOM50C1"" + register "cid" = ""PNP0C50"" + register "desc" = ""WCOM Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + register "hid_desc_reg_offset" = "0x1" device i2c 10 on end end end # - I2C 3

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New patch to review for coreboot: drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17092 -gerrit commit 27f2a99ea340c5f9969ad28e41f089b91abdcb27 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:42:45 2016 -0700 drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver BUG=chrome-os-partner:57846 Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/wacom_ts/Kconfig | 3 ++ src/drivers/i2c/wacom_ts/Makefile.inc | 1 + src/drivers/i2c/wacom_ts/chip.h | 7 ++++ src/drivers/i2c/wacom_ts/ts.c | 67 +++++++++++++++++++++++++++++++++++ 4 files changed, 78 insertions(+) diff --git a/src/drivers/i2c/wacom_ts/Kconfig b/src/drivers/i2c/wacom_ts/Kconfig new file mode 100644 index 0000000..50da3f1 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_I2C_WACOM_TS + bool + select DRIVERS_I2C_GENERIC diff --git a/src/drivers/i2c/wacom_ts/Makefile.inc b/src/drivers/i2c/wacom_ts/Makefile.inc new file mode 100644 index 0000000..9455099 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_WACOM_TS) += ts.c diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h new file mode 100644 index 0000000..6eb4641 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -0,0 +1,7 @@ + +#include <drivers/i2c/generic/generic.h> + +struct drivers_i2c_wacom_ts_config { + I2C_GENERIC_CONFIG; + uint8_t hid_desc_reg_offset; +}; diff --git a/src/drivers/i2c/wacom_ts/ts.c b/src/drivers/i2c/wacom_ts/ts.c new file mode 100644 index 0000000..0b221ac --- /dev/null +++ b/src/drivers/i2c/wacom_ts/ts.c @@ -0,0 +1,67 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <arch/acpigen_dsm.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <drivers/i2c/generic/generic.h> +#include <gpio.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +static void i2c_wacom_ts_fill_dsm(struct device *dev) +{ + struct drivers_i2c_wacom_ts_config *config = dev->chip_info; + struct dsm_i2c_hid_config dsm_config; + + dsm_config.hid_desc_reg_offset = config->hid_desc_reg_offset; + + acpigen_write_dsm_i2c_hid(&dsm_config); +} + +static void i2c_wacom_ts_fill_ssdt_generator(struct device *dev) +{ + i2c_generic_fill_ssdt(dev, &i2c_wacom_ts_fill_dsm); +} + +static const char *i2c_wacom_ts_acpi_name(struct device *dev) +{ + return ("WCTS"); +} + +static struct device_operations i2c_wacom_ts_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &i2c_wacom_ts_acpi_name, + .acpi_fill_ssdt_generator = &i2c_wacom_ts_fill_ssdt_generator, +#endif +}; + +static void i2c_wacom_ts_enable(struct device *dev) +{ + dev->ops = &i2c_wacom_ts_ops; +} + +struct chip_operations drivers_i2c_wacom_ts_ops = { + CHIP_NAME("Wacom Touchscreen Device") + .enable_dev = &i2c_wacom_ts_enable +};

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New patch to review for coreboot: arch/x86/acpigen_dsm: Add support for DSM types
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17091 -gerrit commit 770d36cff3ca82c40650471f1391d4bd27860313 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:40:17 2016 -0700 arch/x86/acpigen_dsm: Add support for DSM types Currently, the only supported DSM type is I2C HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required callbacks for generating ACPI AML codes for different function identifiers for I2C HID. BUG=chrome-os-partner:57846 Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/Makefile.inc | 1 + src/arch/x86/acpigen_dsm.c | 65 +++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen_dsm.h | 27 ++++++++++++++ 3 files changed, 93 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 782ca63..c4bb1cc 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -313,6 +313,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-y += boot.c diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c new file mode 100644 index 0000000..c6d614a --- /dev/null +++ b/src/arch/x86/acpigen_dsm.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <arch/acpigen_dsm.h> +#include <stdlib.h> + +/* ------------------- I2C HID DSM ---------------------------- */ + +#define ACPI_DSM_I2C_HID_UUID "3CDFF6F7-4267-4555-AD05-B30A3D8938DE" + +static void i2c_hid_func0_cb(void *arg) +{ + /* ToInteger (Arg1, Local2) */ + acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); + /* If (LEqual (Local2, 0x0)) */ + acpigen_write_if_lequal(LOCAL2_OP, 0x0); + /* Return (Buffer (One) { 0x1f }) */ + acpigen_write_return_singleton_buffer(0x1f); + acpigen_pop_len(); /* Pop : If */ + /* Else */ + acpigen_write_else(); + /* If (LEqual (Local2, 0x1)) */ + acpigen_write_if_lequal(LOCAL2_OP, 0x1); + /* Return (Buffer (One) { 0x3f }) */ + acpigen_write_return_singleton_buffer(0x3f); + acpigen_pop_len(); /* Pop : If */ + /* Else */ + acpigen_write_else(); + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + acpigen_pop_len(); /* Pop : Else */ + acpigen_pop_len(); /* Pop : Else */ +} + +static void i2c_hid_func1_cb(void *arg) +{ + struct dsm_i2c_hid_config *config = arg; + acpigen_write_return_byte(config->hid_desc_reg_offset); +} + +static void (*i2c_hid_callbacks[2])(void *) = { + i2c_hid_func0_cb, + i2c_hid_func1_cb, +}; + +void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config) +{ + acpigen_write_dsm(ACPI_DSM_I2C_HID_UUID, i2c_hid_callbacks, + ARRAY_SIZE(i2c_hid_callbacks), config); +} + +/* ------------------- End: I2C HID DSM ------------------------- */ diff --git a/src/arch/x86/include/arch/acpigen_dsm.h b/src/arch/x86/include/arch/acpigen_dsm.h new file mode 100644 index 0000000..2d8bb48 --- /dev/null +++ b/src/arch/x86/include/arch/acpigen_dsm.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ACPIGEN_DSM_H__ +#define __ARCH_ACPIGEN_DSM_H__ + +#include <stdint.h> + +struct dsm_i2c_hid_config { + uint8_t hid_desc_reg_offset; +}; + +void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config); + +#endif /* __ARCH_ACPIGEN_DSM_H__ */

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New patch to review for coreboot: arch/x86/acpigen: Add support for _DSM method generation
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17090 -gerrit commit 32212b4b622449021651556ba1d8091c663ac16e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:37:41 2016 -0700 arch/x86/acpigen: Add support for _DSM method generation Add acpigen_write_dsm that generates ACPI AML code for _DSM method. Caller should provide set of callbacks with callback[i] corresponding to function index i of DSM method. Local0 and Local1 should not be used in any of the callbacks. BUG=chrome-os-partner:57846 Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 60 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 8 +++++ 2 files changed, 68 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index e42b620..e712564 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1030,6 +1030,66 @@ void acpigen_write_return_byte(uint8_t arg) acpigen_write_byte(arg); } +/* + * Generate ACPI AML code for _DSM method. + * This function takes as input uuid for the device, set of callbacks and + * argument to pass into the callbacks. Callbacks should ensure that Local0 and + * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. + */ +void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), + size_t count, void *arg) +{ + size_t i; + + /* Method (_DSM, 4, Serialized) */ + acpigen_write_method_serialized("_DSM", 0x4); + + /* ToBuffer (Arg0, Local0) */ + acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid(uuid); + + /* ToInteger (Arg2, Local1) */ + acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); + acpigen_write_debug_op(LOCAL1_OP); + + for (i = 0; i < count; i++) { + /* If (Lequal (Local1, i)) */ + acpigen_write_if_lequal(LOCAL1_OP, i); + + /* Callback to write if handler. */ + if (callbacks[i]) + callbacks[i](arg); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + } + + /* Default case: Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + /* Pop lengths for all the else clauses. */ + for (i = 0; i < count; i++) + acpigen_pop_len(); + + acpigen_pop_len(); /* If (LEqual (Local0, ToUUID(uuid))) */ + + /* Else */ + acpigen_write_else(); + + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + acpigen_pop_len(); /* Else */ + acpigen_pop_len(); /* Method _DSM */ +} + /* Soc-implemented functions -- weak definitions. */ int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned gpio_num) { diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index aeb61d3..5cca53f 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -167,6 +167,14 @@ void acpigen_write_byte_buffer(uint8_t *arr, uint8_t size); void acpigen_write_return_byte_buffer(uint8_t *arr, uint8_t size); void acpigen_write_return_singleton_buffer(uint8_t arg); void acpigen_write_return_byte(uint8_t arg); +/* + * Generate ACPI AML code for _DSM method. + * This function takes as input uuid for the device, set of callbacks and + * argument to pass into the callbacks. Callbacks should ensure that Local0 and + * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. + */ +void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), + size_t count, void *arg); int get_cst_entries(acpi_cstate_t **);

1 0

New patch to review for coreboot: drivers/i2c/generic: Re-factor SSDT generation code
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17089 -gerrit commit f230c588a66b15db26b13234a51183b948b75f86 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:24:07 2016 -0700 drivers/i2c/generic: Re-factor SSDT generation code 1. Export i2c_generic_fill_ssdt to allow other device-specific i2c drivers to share and re-use the same code for generating AML code for SSDT. In order to achieve this, following changes are required: a. Add macro I2C_GENERIC_CONFIG that defines a structure with all generic i2c device-tree properties. This macro should be placed by the using driver at the start of its config structure. b. Accept a callback function to add any device specific information to SSDT. If generic driver is used directly by a device, callback would be NULL. Other devices using a separate i2c driver can provide a callback to add any properties to SSDT. 2. Allow device to provide _CID. BUG=chrome-os-partner:57846 Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 31 +-------------- src/drivers/i2c/generic/generic.c | 16 +++++++- src/drivers/i2c/generic/generic.h | 80 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+), 31 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index e84fc38..4614ba3 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -1,34 +1,7 @@ #include <arch/acpi_device.h> #include <device/i2c.h> +#include "generic.h" struct drivers_i2c_generic_config { - const char *hid; /* ACPI _HID (required) */ - const char *name; /* ACPI Device Name */ - const char *desc; /* Device Description */ - unsigned uid; /* ACPI _UID */ - enum i2c_speed speed; /* Bus speed in Hz, default is I2C_SPEED_FAST */ - unsigned wake; /* Wake GPE */ - struct acpi_irq irq; /* Interrupt */ - - /* - * This flag will add a device propery which will indicate - * to the OS that it should probe this device before adding it. - * - * This can be used to declare a device that may not exist on - * the board, for example to support multiple trackpad vendors. - */ - int probed; - - /* GPIO used to indicate if this device is present */ - unsigned device_present_gpio; - unsigned device_present_gpio_invert; - - /* GPIO used to take device out of reset or to put it into reset. */ - unsigned reset_gpio; - /* Delay to be inserted after device is taken out of reset. */ - unsigned reset_delay_ms; - /* GPIO used to enable device. */ - unsigned enable_gpio; - /* Delay to be inserted after device is enabled. */ - unsigned enable_delay_ms; + I2C_GENERIC_CONFIG; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 7f078b0..410f396 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -61,7 +61,8 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) acpigen_pop_len(); /* PowerResource PRIC */ } -static void i2c_generic_fill_ssdt(struct device *dev) +void i2c_generic_fill_ssdt(struct device *dev, + void (*callback)(struct device *dev)) { struct drivers_i2c_generic_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); @@ -85,6 +86,8 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", config->hid); + if (config->cid) + acpigen_write_name_string("_CID", config->cid); acpigen_write_name_integer("_UID", config->uid); acpigen_write_name_string("_DDN", config->desc); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); @@ -111,6 +114,10 @@ static void i2c_generic_fill_ssdt(struct device *dev) /* Power Resource */ i2c_generic_add_power_res(config); + /* Callback if any. */ + if (callback) + callback(dev); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ @@ -118,6 +125,11 @@ static void i2c_generic_fill_ssdt(struct device *dev) config->desc ? : dev->chip_ops->name, dev_path(dev)); } +static void i2c_generic_fill_ssdt_generator(struct device *dev) +{ + i2c_generic_fill_ssdt(dev, NULL); +} + /* Use name specified in config or build one from I2C address */ static const char *i2c_generic_acpi_name(struct device *dev) { @@ -139,7 +151,7 @@ static struct device_operations i2c_generic_ops = { .enable_resources = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_name = &i2c_generic_acpi_name, - .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt, + .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt_generator, #endif }; diff --git a/src/drivers/i2c/generic/generic.h b/src/drivers/i2c/generic/generic.h new file mode 100644 index 0000000..60445c2 --- /dev/null +++ b/src/drivers/i2c/generic/generic.h @@ -0,0 +1,80 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_GENERIC_GENERIC_H__ +#define __I2C_GENERIC_GENERIC_H__ + +#include <device/device.h> + +/* + * Macro defining all the generic i2c device-tree properties that are used by + * ssdt generator. Drivers using i2c_generic_fill_ssdt should place this macro + * at the start of their config structure. + */ +#define I2C_GENERIC_CONFIG \ + struct { \ + /* ACPI _HID (required) */ \ + const char *hid; \ + /* ACPI _CID */ \ + const char *cid; \ + /* ACPI Device Name */ \ + const char *name; \ + /* Device Description */ \ + const char *desc; \ + /* ACPI _UID */ \ + unsigned uid; \ + /* Bus speed in Hz, default is I2C_SPEED_FAST */ \ + enum i2c_speed speed; \ + /* Wake GPE */ \ + unsigned wake; \ + /* Interrupt */ \ + struct acpi_irq irq; \ + /* \ + * This flag will add a device propery which will \ + * indicate to the OS that it should probe this \ + * device before adding it. \ + * \ + * This can be used to declare a device that may not \ + * exist on the board, for example to support multiple \ + * trackpad vendors. \ + */ \ + int probed; \ + /* GPIO used to indicate if this device is present */ \ + unsigned device_present_gpio; \ + unsigned device_present_gpio_invert; \ + /* \ + * GPIO used to take device out of reset or to put \ + * it into reset. */ \ + unsigned reset_gpio; \ + /* \ + * Delay to be inserted after device is taken out of \ + * reset. */ \ + unsigned reset_delay_ms; \ + /* GPIO used to enable device. */ \ + unsigned enable_gpio; \ + /* Delay to be inserted after device is enabled. */ \ + unsigned enable_delay_ms; \ + } + +/* + * Fills in generic information about i2c device from device-tree + * properties. Place I2C_GENERIC_CONFIG at the start of device config + * structure. Callback can be provided to fill in any device-specific + * information in SSDT. + */ +void i2c_generic_fill_ssdt(struct device *dev, + void (*callback)(struct device *dev)); + +#endif /* __I2C_GENERIC_GENERIC_H__ */

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New patch to review for coreboot: arch/x86/acpigen: Add more functions to ACPIGEN library
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17088 -gerrit commit 16475d7ac9974f9bb65c8ee0e7c7d8f97e97bedc Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:21:07 2016 -0700 arch/x86/acpigen: Add more functions to ACPIGEN library 1. If (LEqual (Op1, Op2)) 2. ToBuffer (src, dst) 3. ToInteger (src, dst) 4. Buffer (n) { op1, op2 .... } 5. Return ( ) BUG=chrome-os-partner:57846 Change-Id: I24fe647c690b2dd4849f0c53b2672ac7a2caa2de Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 53 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 10 +++++++ 2 files changed, 63 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 44c77cc..e42b620 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -971,12 +971,65 @@ void acpigen_write_if_and(uint8_t arg1, uint8_t arg2) acpigen_emit_byte(arg2); } +void acpigen_write_if_lequal(uint8_t arg1, uint8_t arg2) +{ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(arg1); + acpigen_emit_byte(arg2); +} + void acpigen_write_else(void) { acpigen_emit_byte(ELSE_OP); acpigen_write_len_f(); } +void acpigen_write_to_buffer(uint8_t src, uint8_t dst) +{ + acpigen_emit_byte(TO_BUFFER_OP); + acpigen_emit_byte(src); + acpigen_emit_byte(dst); +} + +void acpigen_write_to_integer(uint8_t src, uint8_t dst) +{ + acpigen_emit_byte(TO_INTEGER_OP); + acpigen_emit_byte(src); + acpigen_emit_byte(dst); +} + +void acpigen_write_byte_buffer(uint8_t *arr, uint8_t size) +{ + uint8_t i; + + acpigen_emit_byte(BUFFER_OP); + acpigen_write_len_f(); + acpigen_emit_byte(size); + + for (i = 0; i < size; i++) + acpigen_emit_byte(arr[i]); + + acpigen_pop_len(); +} + +void acpigen_write_return_byte_buffer(uint8_t *arr, uint8_t size) +{ + acpigen_emit_byte(RETURN_OP); + acpigen_write_byte_buffer(arr, size); +} + +void acpigen_write_return_singleton_buffer(uint8_t arg) +{ + acpigen_write_return_byte_buffer(&arg, 1); +} + +void acpigen_write_return_byte(uint8_t arg) +{ + acpigen_emit_byte(RETURN_OP); + acpigen_write_byte(arg); +} + /* Soc-implemented functions -- weak definitions. */ int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned gpio_num) { diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 8ac8f48..aeb61d3 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -75,6 +75,9 @@ enum { AND_OP = 0x7B, OR_OP = 0x7D, NOT_OP = 0x80, + LEQUAL_OP = 0x93, + TO_BUFFER_OP = 0x96, + TO_INTEGER_OP = 0x99, IF_OP = 0xA0, ELSE_OP = 0xA1, RETURN_OP = 0xA4, @@ -156,7 +159,14 @@ void acpigen_write_debug_integer(uint64_t val); void acpigen_write_debug_op(uint8_t op); void acpigen_write_if(void); void acpigen_write_if_and(uint8_t arg1, uint8_t arg2); +void acpigen_write_if_lequal(uint8_t arg1, uint8_t arg2); void acpigen_write_else(void); +void acpigen_write_to_buffer(uint8_t src, uint8_t dst); +void acpigen_write_to_integer(uint8_t src, uint8_t dst); +void acpigen_write_byte_buffer(uint8_t *arr, uint8_t size); +void acpigen_write_return_byte_buffer(uint8_t *arr, uint8_t size); +void acpigen_write_return_singleton_buffer(uint8_t arg); +void acpigen_write_return_byte(uint8_t arg); int get_cst_entries(acpi_cstate_t **);

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Patch set updated for coreboot: RISCV: Clean up the common architectural code
by Ronald G. Minnich 21 Oct '16

21 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17058 -gerrit commit e0f7279cfd4d30f0f848e2769235bfb6c3ddf3f4 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Oct 19 08:07:13 2016 -0700 RISCV: Clean up the common architectural code We provide a standard payload that makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual memory setup code. We now use the _stack and _estack from memlayout so we know where things are. As time goes on maybe we can kill all the magic numbers. I'm getting a confusing error on the bootblock that I hope Julius can explain to me: LINK cbfs/fallback/bootblock.debug /home/rminnich/projects/riscv/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-ld.bfd: build/cbfs/fallback/bootblock.debug: warning: allocated section `.data' not in segment OBJCOPY cbfs/fallback/bootblock.elf /home/rminnich/projects/riscv/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-objcopy: build/cbfs/fallback/stEfxjQH: warning: allocated section `.data' not in segment /home/rminnich/projects/riscv/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-objcopy: build/cbfs/fallback/st5PV1nG: warning: allocated section `.data' not in segment OBJCOPY bootblock.raw.bin /home/rminnich/projects/riscv/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-objcopy: build/cbfs/fallback/bootblock.elf.tmp: warning: allocated section `.data' not in segment Also: Performing operation on 'BOOTBLOCK' region... W: Written area will abut bottom of target region: any unused space will keep its current contents Couple of WTFs here, any advice anyone? Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 1 + src/arch/riscv/boot.c | 3 ++ src/arch/riscv/bootblock.S | 11 +++--- src/arch/riscv/include/arch/memlayout.h | 4 +-- src/arch/riscv/include/vm.h | 13 ++----- src/arch/riscv/payload.S | 28 +++++++++++++++ src/arch/riscv/virtual_memory.c | 46 ++++++++++++++++-------- src/include/symbols.h | 4 +++ src/mainboard/emulation/qemu-riscv/memlayout.ld | 1 + src/mainboard/emulation/spike-riscv/memlayout.ld | 3 +- 10 files changed, 82 insertions(+), 32 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 4bab459..cf6ce99 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -96,6 +96,7 @@ ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += sbi.S +ramstage-y += payload.S ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 7435490..8464bac 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <lib.h> #include <program_loading.h> #include <vm.h> #include <arch/encoding.h> @@ -21,9 +22,11 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); + void riscvpayload(void); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { initVirtualMemory(); + riscvpayload(); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 514511e..63df92b 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -19,13 +19,16 @@ .section ".text._start", "ax", %progbits +.globl _stack +.global _estack .globl _start _start: -#define STACK_START 0x80800000 /* 2GiB + 8MiB */ -#define STACK_SIZE 0x0000fff0 - li sp, STACK_START + STACK_SIZE + + # N.B. This only works on low 4G of the address space + # and the stack must be page-aligned. + la sp, _estack # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE @@ -33,7 +36,7 @@ _start: call hls_init # poison the stack - li t1, STACK_START + la t1, _stack li t0, 0xdeadbeef sd t0, 0(t1) diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 4d2af59..5d01141 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -18,8 +18,8 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -/* TODO: Double-check that that's the correct alignment for our ABI. */ -#define STACK(addr, size) REGION(stack, addr, size, 8) +#define STACK(addr, size) REGION(stack, addr, size, 4096) +#define PAGETABLES(addr, size) REGION(pagetables, addr, size, 4096) /* TODO: Need to add DMA_COHERENT region like on ARM? */ diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index bee2ed4..c3de47a 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -37,16 +37,6 @@ #define VA_BITS 39 #define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) -#define PROT_READ 1 -#define PROT_WRITE 2 -#define PROT_EXEC 4 - -#define MAP_PRIVATE 0x2 -#define MAP_FIXED 0x10 -#define MAP_ANONYMOUS 0x20 -#define MAP_POPULATE 0x8000 -#define MREMAP_FIXED 0x2 - #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) @@ -66,7 +56,8 @@ pte_t pte_create(uintptr_t ppn, int prot, int user); void print_page_table(void); -void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart); +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, + pte_t *pageTableStart); void mstatus_init(void); // need to setup mstatus so we know we have virtual memory void flush_tlb(void); diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S new file mode 100644 index 0000000..f66f729 --- /dev/null +++ b/src/arch/riscv/payload.S @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .global riscvpayload +riscvpayload: + /* Jump to 0xffffffff81000000 in S-mode */ + li t0, 0xffffffff81000000 + csrw mepc, t0 + csrr t0, mstatus + li t1, ~(3<<11) + and t0, t0, t1 + li t2, (1<<11) + or t0, t0, t2 + csrw mstatus, t0 + + // We're still in toolchain no mans land. + .word 0x30200073 + //mret diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index be8b488..34b0f9d 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <stdint.h> #include <vm.h> +#include <symbols.h> pte_t* root_page_table; @@ -94,7 +95,7 @@ static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level) /* Print the page table structures to the console */ void print_page_table(void) { - print_page_table_at(root_page_table, 0, 0); + print_page_table_at((void *)(read_csr(sptbr) << RISCV_PGSHIFT), 0, 0); } void flush_tlb(void) @@ -115,17 +116,17 @@ pte_t ptd_create(uintptr_t ppn) pte_t pte_create(uintptr_t ppn, int prot, int user) { pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_R | PTE_V; - if (prot & PROT_WRITE) + if (prot & PTE_W) pte |= PTE_W; - if (prot & PROT_EXEC) + if (prot & PTE_X) pte |= PTE_X; if (user) pte |= PTE_U; return pte; } -void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart) { - pte_t* sbi_pt = (pte_t*) pageTableStart; +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, pte_t *sbi_pt) +{ memset(sbi_pt, 0, RISCV_PGSIZE); // need to leave room for sbi page uintptr_t memorySize = 0x7F000000; // 0xFFF... - 0xFFFFFFFF81000000 - RISCV_PGSIZE @@ -147,21 +148,32 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); l2_idx += ((vaddr - virtMemStart) >> l2_shift); - middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, PROT_READ|PROT_WRITE|PROT_EXEC, 0); + middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, + PTE_R|PTE_W|PTE_X, 0); } // map SBI at top of vaddr space - uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface + // only need to map a single page for sbi interface + uintptr_t num_sbi_pages = 1; uintptr_t sbiStartAddress = (uintptr_t) &sbi_page; uintptr_t sbiAddr = sbiStartAddress; for (uintptr_t i = 0; i < num_sbi_pages; i++) { uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; - sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, PROT_READ|PROT_EXEC, 0); + sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, + PTE_R|PTE_X, 0); sbiAddr += RISCV_PGSIZE; } pte_t* sbi_pte = middle_pt + ((num_middle_pts << RISCV_PGLEVEL_BITS)-1); *sbi_pte = ptd_create((uintptr_t)sbi_pt >> RISCV_PGSHIFT); + // IO space. + root_pt[0] = pte_create(0, PTE_W|PTE_R, 0); + root_pt[1] = pte_create(0x40000000>>RISCV_PGSHIFT, + PTE_W|PTE_R, 0); + + // Start of RAM + root_pt[2] = pte_create(0x80000000>>RISCV_PGSHIFT, + PTE_W|PTE_R, 0); mb(); root_page_table = root_pt; uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT; @@ -185,12 +197,13 @@ void initVirtualMemory(void) { printk(BIOS_DEBUG, "-----------------------------\n"); } + // TODO: Figure out how to grab this from cbfs printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x90000000; // TODO: Figure out how to grab this from cbfs - uintptr_t virtualStart = 0xffffffff80000000; - uintptr_t pageTableStart = 0x91400000; - init_vm(virtualStart, physicalStart, pageTableStart); + uintptr_t physicalStart = 0x81000000; + uintptr_t virtualStart = 0xffffffff81000000; + init_vm(virtualStart, physicalStart, (pte_t *)_pagetables); mb(); + flush_tlb(); #if IS_ENABLED(CONFIG_DEBUG_PRINT_PAGE_TABLES) printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); @@ -220,7 +233,12 @@ void mstatus_init(void) | (1 << CAUSE_USER_ECALL) ); + /* Enable all user/supervisor-mode counters */ - write_csr(mscounteren, 0b111); - write_csr(mucounteren, 0b111); + /* We'll turn these on once lowrisc gets their bitstream up to + * 1.9. Right now there's no agreement on the values for these + * architectural registers. + */ + //write_csr(mscounteren, 0b111); + //write_csr(mucounteren, 0b111); } diff --git a/src/include/symbols.h b/src/include/symbols.h index d7cb35c..ea44293 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -41,6 +41,10 @@ extern u8 _stack[]; extern u8 _estack[]; #define _stack_size (_estack - _stack) +extern u8 _pagetables[]; +extern u8 _epagetables[]; +#define _pagetables_size (_epagetables - _pagetables) + extern u8 _preram_cbfs_cache[]; extern u8 _epreram_cbfs_cache[]; #define _preram_cbfs_cache_size (_epreram_cbfs_cache - _preram_cbfs_cache) diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 615d1f2..8cc6d41 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -24,5 +24,6 @@ SECTIONS ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) + PAGETABLES(0x80000+8K, 60K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 8d35a64..8596723 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -23,7 +23,8 @@ SECTIONS { DRAM_START(START) BOOTBLOCK(START, 64K) - STACK(START + 8M, 64K) + STACK(START + 8M, 4K) + PAGETABLES(START + 8M + 4K, 60K) ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K)

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Patch set updated for coreboot: RISCV: Clean up the common architectural code
by Ronald G. Minnich 21 Oct '16

21 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17058 -gerrit commit 99f15bae93a6751b9997139ecd7659f378aa7366 Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Oct 19 08:07:13 2016 -0700 RISCV: Clean up the common architectural code We provide a standard payload that makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual memory setup code. We now use the _stack and _estack from memlayout so we know where things are. As time goes on maybe we can kill all the magic numbers. I'm getting a confusing error on the bootblock that I hope Julius can explain to me: LINK cbfs/fallback/bootblock.debug /home/rminnich/projects/riscv/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-ld.bfd: build/cbfs/fallback/bootblock.debug: warning: allocated section `.data' not in segment OBJCOPY cbfs/fallback/bootblock.elf /home/rminnich/projects/riscv/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-objcopy: build/cbfs/fallback/stEfxjQH: warning: allocated section `.data' not in segment /home/rminnich/projects/riscv/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-objcopy: build/cbfs/fallback/st5PV1nG: warning: allocated section `.data' not in segment OBJCOPY bootblock.raw.bin /home/rminnich/projects/riscv/coreboot/util/crossgcc/xgcc/bin/riscv64-elf-objcopy: build/cbfs/fallback/bootblock.elf.tmp: warning: allocated section `.data' not in segment Also: Performing operation on 'BOOTBLOCK' region... W: Written area will abut bottom of target region: any unused space will keep its current contents Couple of WTFs here, any advice anyone? Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 1 + src/arch/riscv/boot.c | 3 ++ src/arch/riscv/bootblock.S | 11 +++--- src/arch/riscv/include/arch/memlayout.h | 4 +-- src/arch/riscv/include/vm.h | 13 ++----- src/arch/riscv/payload.S | 28 +++++++++++++++ src/arch/riscv/virtual_memory.c | 46 ++++++++++++++++-------- src/include/symbols.h | 4 +++ src/mainboard/emulation/qemu-riscv/memlayout.ld | 1 + src/mainboard/emulation/spike-riscv/memlayout.ld | 3 +- 10 files changed, 82 insertions(+), 32 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 4bab459..cf6ce99 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -96,6 +96,7 @@ ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += sbi.S +ramstage-y += payload.S ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 7435490..8464bac 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <lib.h> #include <program_loading.h> #include <vm.h> #include <arch/encoding.h> @@ -21,9 +22,11 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); + void riscvpayload(void); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { initVirtualMemory(); + riscvpayload(); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 514511e..63df92b 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -19,13 +19,16 @@ .section ".text._start", "ax", %progbits +.globl _stack +.global _estack .globl _start _start: -#define STACK_START 0x80800000 /* 2GiB + 8MiB */ -#define STACK_SIZE 0x0000fff0 - li sp, STACK_START + STACK_SIZE + + # N.B. This only works on low 4G of the address space + # and the stack must be page-aligned. + la sp, _estack # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE @@ -33,7 +36,7 @@ _start: call hls_init # poison the stack - li t1, STACK_START + la t1, _stack li t0, 0xdeadbeef sd t0, 0(t1) diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 4d2af59..5d01141 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -18,8 +18,8 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -/* TODO: Double-check that that's the correct alignment for our ABI. */ -#define STACK(addr, size) REGION(stack, addr, size, 8) +#define STACK(addr, size) REGION(stack, addr, size, 4096) +#define PAGETABLES(addr, size) REGION(pagetables, addr, size, 4096) /* TODO: Need to add DMA_COHERENT region like on ARM? */ diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index bee2ed4..c3de47a 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -37,16 +37,6 @@ #define VA_BITS 39 #define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) -#define PROT_READ 1 -#define PROT_WRITE 2 -#define PROT_EXEC 4 - -#define MAP_PRIVATE 0x2 -#define MAP_FIXED 0x10 -#define MAP_ANONYMOUS 0x20 -#define MAP_POPULATE 0x8000 -#define MREMAP_FIXED 0x2 - #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) @@ -66,7 +56,8 @@ pte_t pte_create(uintptr_t ppn, int prot, int user); void print_page_table(void); -void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart); +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, + pte_t *pageTableStart); void mstatus_init(void); // need to setup mstatus so we know we have virtual memory void flush_tlb(void); diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S new file mode 100644 index 0000000..f66f729 --- /dev/null +++ b/src/arch/riscv/payload.S @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .global riscvpayload +riscvpayload: + /* Jump to 0xffffffff81000000 in S-mode */ + li t0, 0xffffffff81000000 + csrw mepc, t0 + csrr t0, mstatus + li t1, ~(3<<11) + and t0, t0, t1 + li t2, (1<<11) + or t0, t0, t2 + csrw mstatus, t0 + + // We're still in toolchain no mans land. + .word 0x30200073 + //mret diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index be8b488..3cc4505 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -22,6 +22,7 @@ #include <stdint.h> #include <vm.h> +extern pte_t _pagetables[]; pte_t* root_page_table; /* Indent the following text by 2*level spaces */ @@ -94,7 +95,7 @@ static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level) /* Print the page table structures to the console */ void print_page_table(void) { - print_page_table_at(root_page_table, 0, 0); + print_page_table_at((void *)(read_csr(sptbr) << RISCV_PGSHIFT), 0, 0); } void flush_tlb(void) @@ -115,17 +116,17 @@ pte_t ptd_create(uintptr_t ppn) pte_t pte_create(uintptr_t ppn, int prot, int user) { pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_R | PTE_V; - if (prot & PROT_WRITE) + if (prot & PTE_W) pte |= PTE_W; - if (prot & PROT_EXEC) + if (prot & PTE_X) pte |= PTE_X; if (user) pte |= PTE_U; return pte; } -void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart) { - pte_t* sbi_pt = (pte_t*) pageTableStart; +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, pte_t *sbi_pt) +{ memset(sbi_pt, 0, RISCV_PGSIZE); // need to leave room for sbi page uintptr_t memorySize = 0x7F000000; // 0xFFF... - 0xFFFFFFFF81000000 - RISCV_PGSIZE @@ -147,21 +148,32 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); l2_idx += ((vaddr - virtMemStart) >> l2_shift); - middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, PROT_READ|PROT_WRITE|PROT_EXEC, 0); + middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, + PTE_R|PTE_W|PTE_X, 0); } // map SBI at top of vaddr space - uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface + // only need to map a single page for sbi interface + uintptr_t num_sbi_pages = 1; uintptr_t sbiStartAddress = (uintptr_t) &sbi_page; uintptr_t sbiAddr = sbiStartAddress; for (uintptr_t i = 0; i < num_sbi_pages; i++) { uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; - sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, PROT_READ|PROT_EXEC, 0); + sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, + PTE_R|PTE_X, 0); sbiAddr += RISCV_PGSIZE; } pte_t* sbi_pte = middle_pt + ((num_middle_pts << RISCV_PGLEVEL_BITS)-1); *sbi_pte = ptd_create((uintptr_t)sbi_pt >> RISCV_PGSHIFT); + // IO space. + root_pt[0] = pte_create(0, PTE_W|PTE_R, 0); + root_pt[1] = pte_create(0x40000000>>RISCV_PGSHIFT, + PTE_W|PTE_R, 0); + + // Start of RAM + root_pt[2] = pte_create(0x80000000>>RISCV_PGSHIFT, + PTE_W|PTE_R, 0); mb(); root_page_table = root_pt; uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT; @@ -185,12 +197,13 @@ void initVirtualMemory(void) { printk(BIOS_DEBUG, "-----------------------------\n"); } + // TODO: Figure out how to grab this from cbfs printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x90000000; // TODO: Figure out how to grab this from cbfs - uintptr_t virtualStart = 0xffffffff80000000; - uintptr_t pageTableStart = 0x91400000; - init_vm(virtualStart, physicalStart, pageTableStart); + uintptr_t physicalStart = 0x81000000; + uintptr_t virtualStart = 0xffffffff81000000; + init_vm(virtualStart, physicalStart, _pagetables); mb(); + flush_tlb(); #if IS_ENABLED(CONFIG_DEBUG_PRINT_PAGE_TABLES) printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); @@ -220,7 +233,12 @@ void mstatus_init(void) | (1 << CAUSE_USER_ECALL) ); + /* Enable all user/supervisor-mode counters */ - write_csr(mscounteren, 0b111); - write_csr(mucounteren, 0b111); + /* We'll turn these on once lowrisc gets their bitstream up to + * 1.9. Right now there's no agreement on the values for these + * architectural registers. + */ + //write_csr(mscounteren, 0b111); + //write_csr(mucounteren, 0b111); } diff --git a/src/include/symbols.h b/src/include/symbols.h index d7cb35c..ea44293 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -41,6 +41,10 @@ extern u8 _stack[]; extern u8 _estack[]; #define _stack_size (_estack - _stack) +extern u8 _pagetables[]; +extern u8 _epagetables[]; +#define _pagetables_size (_epagetables - _pagetables) + extern u8 _preram_cbfs_cache[]; extern u8 _epreram_cbfs_cache[]; #define _preram_cbfs_cache_size (_epreram_cbfs_cache - _preram_cbfs_cache) diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 615d1f2..8cc6d41 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -24,5 +24,6 @@ SECTIONS ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) + PAGETABLES(0x80000+8K, 60K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 8d35a64..8596723 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -23,7 +23,8 @@ SECTIONS { DRAM_START(START) BOOTBLOCK(START, 64K) - STACK(START + 8M, 64K) + STACK(START + 8M, 4K) + PAGETABLES(START + 8M + 4K, 60K) ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K)

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coreboot-gerrit October 2016