coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: google/reef/variants/pyro: Use WCOM Touchscreen driver
by Furquan Shaikh 22 Oct '16

22 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17093 -gerrit commit f5bdc080b5989dd73eb1f31f580855db711b1be5 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:45:59 2016 -0700 google/reef/variants/pyro: Use WCOM Touchscreen driver BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 3 +++ src/mainboard/google/reef/variants/pyro/devicetree.cb | 13 ++++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d5d64c8..6045f47 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -40,6 +40,9 @@ config DRIVERS_I2C_DA7219 config DRIVERS_I2C_GENERIC default y +config DRIVERS_I2C_WACOM_TS + default y + config DRIVERS_PS2_KEYBOARD default y diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 43ec2ed..62183cc 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -131,11 +131,14 @@ chip soc/intel/apollolake end end # - I2C 2 device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + chip drivers/i2c/wacom_ts + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_TS_DESC, + .irq = IRQ_EDGE_LOW(GPIO_21_IRQ), + }" + register "hid_desc_reg_offset" = "0x1" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: nb/i945/gma.c: Set the MSAC register correctly
by Arthur Heymans 22 Oct '16

22 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17094 -gerrit commit 04422a4a534565ac9a7c46e79170f3c693d9d0e1 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Oct 22 14:16:48 2016 +0200 nb/i945/gma.c: Set the MSAC register correctly This fixes an instability on 945gc where the IGD completely locks up the system, when for instance tasked to do something with compositing (like GNOME or GDM). TESTED on ga-945gcm-s2l and d945gclf TEST: launch GDM (gnome display manager) Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 4baed80..aefec8f 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -32,6 +32,7 @@ #include "chip.h" #define GDRST 0xc0 +#define MSAC 0x62 /* Multi Size Aperture Control */ #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) @@ -707,12 +708,25 @@ static void gma_ssdt(device_t device) drivers_intel_gma_displays_ssdt_generate(gfx); } +static void gma_func0_read_resources(device_t dev) +{ + u8 reg8; + + /* Set Untrusted Aperture Size to 256mb */ + reg8 = pci_read_config8(dev, MSAC); + reg8 &= ~0x3; + reg8 |= 0x2; + pci_write_config8(dev, MSAC, reg8); + + pci_dev_read_resources(dev); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_func0_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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New patch to review for coreboot: nb/intel/i945: add northbridge pci_id for 945G/GZ/GC/P/PL
by Arthur Heymans 22 Oct '16

22 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17096 -gerrit commit bd3d4119f6c3b404426dbc0fb3da4f0a6c4ddb69 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Oct 22 20:04:15 2016 +0200 nb/intel/i945: add northbridge pci_id for 945G/GZ/GC/P/PL Change-Id: I7bd363c7694c30f1adef89786579d8755b6af539 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/northbridge.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index ba8b251..9689db9 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -254,7 +254,7 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x27a0, 0x27ac, +static const unsigned short pci_device_ids[] = { 0x27a0, 0x27ac, 0x2770 0 }; static const struct pci_driver mc_driver __pci_driver = {

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Patch set updated for coreboot: nb/i945/gma.c: Set the MSAC register correctly
by Arthur Heymans 22 Oct '16

22 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17094 -gerrit commit ef0037d4538f261322a03dd615380a28ef6b18b6 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Oct 22 14:16:48 2016 +0200 nb/i945/gma.c: Set the MSAC register correctly This fixes an instability on 945gc where the IGD completely locks up the system, when for instance tasked to do something with compositing (like GNOME or GDM). TESTED on ga-945gcm-s2l and d945gclf TEST: launch GDM (gnome display manager) Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 4baed80..aefec8f 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -32,6 +32,7 @@ #include "chip.h" #define GDRST 0xc0 +#define MSAC 0x62 /* Multi Size Aperture Control */ #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) @@ -707,12 +708,25 @@ static void gma_ssdt(device_t device) drivers_intel_gma_displays_ssdt_generate(gfx); } +static void gma_func0_read_resources(device_t dev) +{ + u8 reg8; + + /* Set Untrusted Aperture Size to 256mb */ + reg8 = pci_read_config8(dev, MSAC); + reg8 &= ~0x3; + reg8 |= 0x2; + pci_write_config8(dev, MSAC, reg8); + + pci_dev_read_resources(dev); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_func0_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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New patch to review for coreboot: nb/intel/i945: Add PCI id for I945GC
by Nico Huber 22 Oct '16

22 Oct '16

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17095 -gerrit commit ec688c139eb7cc6ca7c967903976f71a6d43e26c Author: Nico Huber <nico.h(a)gmx.de> Date: Sat Oct 22 20:01:34 2016 +0200 nb/intel/i945: Add PCI id for I945GC Also drop an odd comment about the resource allocator which seems to work fine, with the right id. Change-Id: I9099211fe946c28f90dd7730345b81a3f7f6f545 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- src/northbridge/intel/i945/northbridge.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/i945/northbridge.c b/src/northbridge/intel/i945/northbridge.c index ba8b251..5d18591 100644 --- a/src/northbridge/intel/i945/northbridge.c +++ b/src/northbridge/intel/i945/northbridge.c @@ -177,11 +177,6 @@ static void mc_read_resources(device_t dev) pci_dev_read_resources(dev); - /* So, this is one of the big mysteries in the coreboot resource - * allocator. This resource should make sure that the address space - * of the PCIe memory mapped config space bar. But it does not. - */ - /* We use 0xcf as an unused index for our PCIe bar so that we find it again */ resource = new_resource(dev, 0xcf); resource->base = DEFAULT_PCIEXBAR; @@ -254,8 +249,10 @@ static struct device_operations mc_ops = { .ops_pci = &intel_pci_ops, }; -static const unsigned short pci_device_ids[] = { 0x27a0, 0x27ac, - 0 }; +static const unsigned short pci_device_ids[] = { + 0x2770, /* desktop */ + 0x27a0, 0x27ac, /* mobile */ + 0 }; static const struct pci_driver mc_driver __pci_driver = { .ops = &mc_ops,

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Patch set updated for coreboot: nb/intel/i945: make pci_mmio_size a cmos option
by Arthur Heymans 22 Oct '16

22 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/16856 -gerrit commit 384a4f2840ff3d725caed752a7f2f3d505a36165 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 3 17:16:48 2016 +0200 nb/intel/i945: make pci_mmio_size a cmos option Instead of hardcoding pci_mmio_size in raminit code, make this a cmos option. Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/apple/macbook21/cmos.default | 3 ++- src/mainboard/apple/macbook21/cmos.layout | 15 ++++++++++++--- src/mainboard/lenovo/t60/cmos.default | 3 ++- src/mainboard/lenovo/t60/cmos.layout | 15 ++++++++++++--- src/mainboard/lenovo/x60/cmos.default | 3 ++- src/mainboard/lenovo/x60/cmos.layout | 15 ++++++++++++--- src/northbridge/intel/i945/raminit.c | 9 ++++++--- 7 files changed, 48 insertions(+), 15 deletions(-) diff --git a/src/mainboard/apple/macbook21/cmos.default b/src/mainboard/apple/macbook21/cmos.default index 1cf350c..da61c1f 100644 --- a/src/mainboard/apple/macbook21/cmos.default +++ b/src/mainboard/apple/macbook21/cmos.default @@ -17,4 +17,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable -gfx_uma_size=8M \ No newline at end of file +gfx_uma_size=8M +pci_mmio_size=768M \ No newline at end of file diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 8329347..83f5111 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -60,9 +60,6 @@ entries 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -# coreboot config options: northbridge -411 3 e 11 gfx_uma_size - # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default @@ -70,6 +67,10 @@ entries 937 1 e 1 lpt #938 46 r 0 unused +# coreboot config options: northbridge +946 3 e 11 gfx_uma_size +949 3 e 10 pci_mmio_size + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved @@ -126,6 +127,14 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +10 0 256M +10 1 512M +10 2 768M +10 3 1024M +10 4 1280M +10 5 1536M +10 6 1792M +10 7 2048M 11 0 1M 11 1 4M 11 2 8M diff --git a/src/mainboard/lenovo/t60/cmos.default b/src/mainboard/lenovo/t60/cmos.default index 03b92e3..ea97a84 100644 --- a/src/mainboard/lenovo/t60/cmos.default +++ b/src/mainboard/lenovo/t60/cmos.default @@ -18,4 +18,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable -gfx_uma_size=8M \ No newline at end of file +gfx_uma_size=8M +pci_mmio_size=768M \ No newline at end of file diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 2cd4e7b..37d7aba 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -58,9 +58,6 @@ entries 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -# coreboot config options: northbridge -411 3 e 11 gfx_uma_size - # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default @@ -72,6 +69,10 @@ entries 944 1 e 2 hyper_threading #945 7 r 0 unused +# coreboot config options: northbridge +946 3 e 11 gfx_uma_size +949 3 e 10 pci_mmio_size + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved @@ -129,6 +130,14 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +10 0 256M +10 1 512M +10 2 768M +10 3 1024M +10 4 1280M +10 5 1536M +10 6 1792M +10 7 2048M 11 0 1M 11 1 4M 11 2 8M diff --git a/src/mainboard/lenovo/x60/cmos.default b/src/mainboard/lenovo/x60/cmos.default index 4e72734..4f71a45 100644 --- a/src/mainboard/lenovo/x60/cmos.default +++ b/src/mainboard/lenovo/x60/cmos.default @@ -18,4 +18,5 @@ fn_ctrl_swap=Disable sticky_fn=Disable power_management_beeps=Enable low_battery_beep=Enable -gfx_uma_size=8M \ No newline at end of file +gfx_uma_size=8M +pci_mmio_size=768M \ No newline at end of file diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 3e316c9..1936271 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -58,9 +58,6 @@ entries 408 1 e 1 nmi #409 2 e 7 power_on_after_fail -# coreboot config options: northbridge -411 3 e 11 gfx_uma_size - # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default @@ -72,6 +69,10 @@ entries 944 1 e 2 hyper_threading #945 7 r 0 unused +# coreboot config options: northbridge +946 3 e 11 gfx_uma_size +949 3 e 10 pci_mmio_size + # coreboot config options: check sums 984 16 h 0 check_sum #1000 24 r 0 amd_reserved @@ -129,6 +130,14 @@ enumerations 8 1 Yes 9 0 Secondary 9 1 Primary +10 0 256M +10 1 512M +10 2 768M +10 3 1024M +10 4 1280M +10 5 1536M +10 6 1792M +10 7 2048M 11 0 1M 11 1 4M 11 2 8M diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index 0b9e95c..dfe8fd1 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -26,6 +26,7 @@ #include "raminit.h" #include "i945.h" #include <cbmem.h> +#include <pc80/mc146818rtc.h> /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP @@ -1503,7 +1504,7 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) static int sdram_program_row_boundaries(struct sys_info *sysinfo) { int i; - int cum0, cum1, tolud, tom; + int cum0, cum1, tolud, tom, pci_mmio_size; printk(BIOS_DEBUG, "Setting RAM size...\n"); @@ -1541,9 +1542,11 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) /* The TOM register has a different format */ tom = tolud >> 3; + pci_mmio_size = 0x2; /* use 768M as default */ + get_option(&pci_mmio_size, "pci_mmio_size"); + /* Limit the value of TOLUD to leave some space for PCI memory. */ - if (tolud > 0xd0) - tolud = 0xd0; /* 3.25GB : 0.75GB */ + tolud = MIN(0x100 - ((pci_mmio_size + 1) << 4), tolud); pci_write_config8(PCI_DEV(0,0,0), TOLUD, tolud);

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Patch set updated for coreboot: nb/i945/gma.c: Set the MSAC register correctly
by Arthur Heymans 22 Oct '16

22 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17094 -gerrit commit 23ee511ad1e1ceb4fbc503cc6129a0f1aff73388 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Oct 22 14:16:48 2016 +0200 nb/i945/gma.c: Set the MSAC register correctly This fixes an instability on 945gc where the IGD completely locks up the system, when for instance tasked to do something with compositing (like GNOME or GDM). TESTED on ga-945gcm-s2l and d945gclf TEST: launch GDM (gnome display manager) Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 4baed80..bc5c04d 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -32,6 +32,7 @@ #include "chip.h" #define GDRST 0xc0 +#define MSAC 0x62 /* Multi Size Aperture Control */ #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) @@ -707,12 +708,25 @@ static void gma_ssdt(device_t device) drivers_intel_gma_displays_ssdt_generate(gfx); } +static void gma_func0_read_resources(device_t dev) +{ + u8 reg8; + + pci_dev_read_resources(dev); + + /* Set Untrusted Aperture Size to 256mb */ + reg8 = pci_read_config8(dev, MSAC); + reg8 &= ~0x3; + reg8 |= 0x2; + pci_write_config8(dev, MSAC, reg8); +} + static struct pci_operations gma_pci_ops = { .set_subsystem = gma_set_subsystem, }; static struct device_operations gma_func0_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = gma_func0_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = gma_func0_init,

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Patch set updated for coreboot: RISCV: Clean up the common architectural code
by Ronald G. Minnich 22 Oct '16

22 Oct '16

Ronald G. Minnich (rminnich(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17058 -gerrit commit 1745441d0f99d6769e6a250d1ec3e9a3af81996c Author: Ronald G. Minnich <rminnich(a)gmail.com> Date: Wed Oct 19 08:07:13 2016 -0700 RISCV: Clean up the common architectural code We provide a standard payload that makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual memory setup code. We now use the _stack and _estack from memlayout so we know where things are. As time goes on maybe we can kill all the magic numbers. Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich(a)gmail.com> --- src/arch/riscv/Makefile.inc | 1 + src/arch/riscv/boot.c | 3 ++ src/arch/riscv/bootblock.S | 11 +++--- src/arch/riscv/include/arch/memlayout.h | 4 +-- src/arch/riscv/include/vm.h | 13 ++----- src/arch/riscv/payload.S | 28 +++++++++++++++ src/arch/riscv/virtual_memory.c | 46 ++++++++++++++++-------- src/include/symbols.h | 4 +++ src/mainboard/emulation/qemu-riscv/memlayout.ld | 1 + src/mainboard/emulation/spike-riscv/memlayout.ld | 3 +- 10 files changed, 82 insertions(+), 32 deletions(-) diff --git a/src/arch/riscv/Makefile.inc b/src/arch/riscv/Makefile.inc index 4bab459..cf6ce99 100644 --- a/src/arch/riscv/Makefile.inc +++ b/src/arch/riscv/Makefile.inc @@ -96,6 +96,7 @@ ramstage-y += misc.c ramstage-y += boot.c ramstage-y += tables.c ramstage-y += sbi.S +ramstage-y += payload.S ramstage-y += \ $(top)/src/lib/memchr.c \ $(top)/src/lib/memcmp.c \ diff --git a/src/arch/riscv/boot.c b/src/arch/riscv/boot.c index 7435490..8464bac 100644 --- a/src/arch/riscv/boot.c +++ b/src/arch/riscv/boot.c @@ -13,6 +13,7 @@ * GNU General Public License for more details. */ +#include <lib.h> #include <program_loading.h> #include <vm.h> #include <arch/encoding.h> @@ -21,9 +22,11 @@ void arch_prog_run(struct prog *prog) { void (*doit)(void *) = prog_entry(prog); + void riscvpayload(void); if (ENV_RAMSTAGE && prog_type(prog) == PROG_PAYLOAD) { initVirtualMemory(); + riscvpayload(); } doit(prog_entry_arg(prog)); diff --git a/src/arch/riscv/bootblock.S b/src/arch/riscv/bootblock.S index 514511e..63df92b 100644 --- a/src/arch/riscv/bootblock.S +++ b/src/arch/riscv/bootblock.S @@ -19,13 +19,16 @@ .section ".text._start", "ax", %progbits +.globl _stack +.global _estack .globl _start _start: -#define STACK_START 0x80800000 /* 2GiB + 8MiB */ -#define STACK_SIZE 0x0000fff0 - li sp, STACK_START + STACK_SIZE + + # N.B. This only works on low 4G of the address space + # and the stack must be page-aligned. + la sp, _estack # make room for HLS and initialize it addi sp, sp, -64 // MENTRY_FRAME_SIZE @@ -33,7 +36,7 @@ _start: call hls_init # poison the stack - li t1, STACK_START + la t1, _stack li t0, 0xdeadbeef sd t0, 0(t1) diff --git a/src/arch/riscv/include/arch/memlayout.h b/src/arch/riscv/include/arch/memlayout.h index 4d2af59..5d01141 100644 --- a/src/arch/riscv/include/arch/memlayout.h +++ b/src/arch/riscv/include/arch/memlayout.h @@ -18,8 +18,8 @@ #ifndef __ARCH_MEMLAYOUT_H #define __ARCH_MEMLAYOUT_H -/* TODO: Double-check that that's the correct alignment for our ABI. */ -#define STACK(addr, size) REGION(stack, addr, size, 8) +#define STACK(addr, size) REGION(stack, addr, size, 4096) +#define PAGETABLES(addr, size) REGION(pagetables, addr, size, 4096) /* TODO: Need to add DMA_COHERENT region like on ARM? */ diff --git a/src/arch/riscv/include/vm.h b/src/arch/riscv/include/vm.h index bee2ed4..c3de47a 100644 --- a/src/arch/riscv/include/vm.h +++ b/src/arch/riscv/include/vm.h @@ -37,16 +37,6 @@ #define VA_BITS 39 #define MEGAPAGE_SIZE (SUPERPAGE_SIZE << RISCV_PGLEVEL_BITS) -#define PROT_READ 1 -#define PROT_WRITE 2 -#define PROT_EXEC 4 - -#define MAP_PRIVATE 0x2 -#define MAP_FIXED 0x10 -#define MAP_ANONYMOUS 0x20 -#define MAP_POPULATE 0x8000 -#define MREMAP_FIXED 0x2 - #define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) #define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) @@ -66,7 +56,8 @@ pte_t pte_create(uintptr_t ppn, int prot, int user); void print_page_table(void); -void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart); +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, + pte_t *pageTableStart); void mstatus_init(void); // need to setup mstatus so we know we have virtual memory void flush_tlb(void); diff --git a/src/arch/riscv/payload.S b/src/arch/riscv/payload.S new file mode 100644 index 0000000..f66f729 --- /dev/null +++ b/src/arch/riscv/payload.S @@ -0,0 +1,28 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + + .global riscvpayload +riscvpayload: + /* Jump to 0xffffffff81000000 in S-mode */ + li t0, 0xffffffff81000000 + csrw mepc, t0 + csrr t0, mstatus + li t1, ~(3<<11) + and t0, t0, t1 + li t2, (1<<11) + or t0, t0, t2 + csrw mstatus, t0 + + // We're still in toolchain no mans land. + .word 0x30200073 + //mret diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c index be8b488..34b0f9d 100644 --- a/src/arch/riscv/virtual_memory.c +++ b/src/arch/riscv/virtual_memory.c @@ -21,6 +21,7 @@ #include <console/console.h> #include <stdint.h> #include <vm.h> +#include <symbols.h> pte_t* root_page_table; @@ -94,7 +95,7 @@ static void print_page_table_at(pte_t *pt, intptr_t virt_addr, int level) /* Print the page table structures to the console */ void print_page_table(void) { - print_page_table_at(root_page_table, 0, 0); + print_page_table_at((void *)(read_csr(sptbr) << RISCV_PGSHIFT), 0, 0); } void flush_tlb(void) @@ -115,17 +116,17 @@ pte_t ptd_create(uintptr_t ppn) pte_t pte_create(uintptr_t ppn, int prot, int user) { pte_t pte = (ppn << PTE_PPN_SHIFT) | PTE_R | PTE_V; - if (prot & PROT_WRITE) + if (prot & PTE_W) pte |= PTE_W; - if (prot & PROT_EXEC) + if (prot & PTE_X) pte |= PTE_X; if (user) pte |= PTE_U; return pte; } -void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTableStart) { - pte_t* sbi_pt = (pte_t*) pageTableStart; +void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, pte_t *sbi_pt) +{ memset(sbi_pt, 0, RISCV_PGSIZE); // need to leave room for sbi page uintptr_t memorySize = 0x7F000000; // 0xFFF... - 0xFFFFFFFF81000000 - RISCV_PGSIZE @@ -147,21 +148,32 @@ void init_vm(uintptr_t virtMemStart, uintptr_t physMemStart, uintptr_t pageTable int l2_shift = RISCV_PGLEVEL_BITS + RISCV_PGSHIFT; size_t l2_idx = (virtMemStart >> l2_shift) & ((1 << RISCV_PGLEVEL_BITS)-1); l2_idx += ((vaddr - virtMemStart) >> l2_shift); - middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, PROT_READ|PROT_WRITE|PROT_EXEC, 0); + middle_pt[l2_idx] = pte_create(paddr >> RISCV_PGSHIFT, + PTE_R|PTE_W|PTE_X, 0); } // map SBI at top of vaddr space - uintptr_t num_sbi_pages = 1; // only need to map a single page for sbi interface + // only need to map a single page for sbi interface + uintptr_t num_sbi_pages = 1; uintptr_t sbiStartAddress = (uintptr_t) &sbi_page; uintptr_t sbiAddr = sbiStartAddress; for (uintptr_t i = 0; i < num_sbi_pages; i++) { uintptr_t idx = (1 << RISCV_PGLEVEL_BITS) - num_sbi_pages + i; - sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, PROT_READ|PROT_EXEC, 0); + sbi_pt[idx] = pte_create(sbiAddr >> RISCV_PGSHIFT, + PTE_R|PTE_X, 0); sbiAddr += RISCV_PGSIZE; } pte_t* sbi_pte = middle_pt + ((num_middle_pts << RISCV_PGLEVEL_BITS)-1); *sbi_pte = ptd_create((uintptr_t)sbi_pt >> RISCV_PGSHIFT); + // IO space. + root_pt[0] = pte_create(0, PTE_W|PTE_R, 0); + root_pt[1] = pte_create(0x40000000>>RISCV_PGSHIFT, + PTE_W|PTE_R, 0); + + // Start of RAM + root_pt[2] = pte_create(0x80000000>>RISCV_PGSHIFT, + PTE_W|PTE_R, 0); mb(); root_page_table = root_pt; uintptr_t ptbr = ((uintptr_t) root_pt) >> RISCV_PGSHIFT; @@ -185,12 +197,13 @@ void initVirtualMemory(void) { printk(BIOS_DEBUG, "-----------------------------\n"); } + // TODO: Figure out how to grab this from cbfs printk(BIOS_DEBUG, "Initializing virtual memory...\n"); - uintptr_t physicalStart = 0x90000000; // TODO: Figure out how to grab this from cbfs - uintptr_t virtualStart = 0xffffffff80000000; - uintptr_t pageTableStart = 0x91400000; - init_vm(virtualStart, physicalStart, pageTableStart); + uintptr_t physicalStart = 0x81000000; + uintptr_t virtualStart = 0xffffffff81000000; + init_vm(virtualStart, physicalStart, (pte_t *)_pagetables); mb(); + flush_tlb(); #if IS_ENABLED(CONFIG_DEBUG_PRINT_PAGE_TABLES) printk(BIOS_DEBUG, "Finished initializing virtual memory, starting walk...\n"); @@ -220,7 +233,12 @@ void mstatus_init(void) | (1 << CAUSE_USER_ECALL) ); + /* Enable all user/supervisor-mode counters */ - write_csr(mscounteren, 0b111); - write_csr(mucounteren, 0b111); + /* We'll turn these on once lowrisc gets their bitstream up to + * 1.9. Right now there's no agreement on the values for these + * architectural registers. + */ + //write_csr(mscounteren, 0b111); + //write_csr(mucounteren, 0b111); } diff --git a/src/include/symbols.h b/src/include/symbols.h index d7cb35c..ea44293 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -41,6 +41,10 @@ extern u8 _stack[]; extern u8 _estack[]; #define _stack_size (_estack - _stack) +extern u8 _pagetables[]; +extern u8 _epagetables[]; +#define _pagetables_size (_epagetables - _pagetables) + extern u8 _preram_cbfs_cache[]; extern u8 _epreram_cbfs_cache[]; #define _preram_cbfs_cache_size (_epreram_cbfs_cache - _preram_cbfs_cache) diff --git a/src/mainboard/emulation/qemu-riscv/memlayout.ld b/src/mainboard/emulation/qemu-riscv/memlayout.ld index 615d1f2..8cc6d41 100644 --- a/src/mainboard/emulation/qemu-riscv/memlayout.ld +++ b/src/mainboard/emulation/qemu-riscv/memlayout.ld @@ -24,5 +24,6 @@ SECTIONS ROMSTAGE(0x20000, 128K) STACK(0x40000, 0x3ff00) PRERAM_CBMEM_CONSOLE(0x80000, 8K) + PAGETABLES(0x80000+8K, 60K) RAMSTAGE(0x100000, 16M) } diff --git a/src/mainboard/emulation/spike-riscv/memlayout.ld b/src/mainboard/emulation/spike-riscv/memlayout.ld index 8d35a64..8596723 100644 --- a/src/mainboard/emulation/spike-riscv/memlayout.ld +++ b/src/mainboard/emulation/spike-riscv/memlayout.ld @@ -23,7 +23,8 @@ SECTIONS { DRAM_START(START) BOOTBLOCK(START, 64K) - STACK(START + 8M, 64K) + STACK(START + 8M, 4K) + PAGETABLES(START + 8M + 4K, 60K) ROMSTAGE(START + 8M + 64K, 128K) PRERAM_CBMEM_CONSOLE(START + 8M + 192k, 8K) RAMSTAGE(START + 8M + 200K, 256K)

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Patch set updated for coreboot: nb/i945/gma.c: Set the MSAC register correctly
by Arthur Heymans 22 Oct '16

22 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17094 -gerrit commit 764fb28a6b1c62699821e731c3cde6013f924403 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Oct 22 14:16:48 2016 +0200 nb/i945/gma.c: Set the MSAC register correctly This fixes an instability on 945gc where the IGD completely locks up the system, when for instance tasked to do something with compositing (like GNOME or GDM). TESTED on ga-945gcm-s2l and d945gclf TEST: launch GDM (gnome display manager) Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 4baed80..a0c5864 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -32,6 +32,7 @@ #include "chip.h" #define GDRST 0xc0 +#define MSAC 0x62 /* Multi Size Aperture Control */ #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) @@ -580,6 +581,7 @@ static int probe_edid(u8 *pmmio, u8 slave) static void gma_func0_init(struct device *dev) { + u8 reg8; u32 reg32; /* Unconditionally reset graphics */ @@ -594,6 +596,12 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + /* Set Untrusted Aperture Size to 256mb */ + reg8 = pci_read_config8(dev, MSAC); + reg8 &= ~0x3; + reg8 |= 0x2; + pci_write_config8(dev, MSAC, reg8); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI Init, will run VBIOS */ pci_dev_init(dev);

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Patch set updated for coreboot: nb/i945/gma.c: Set the MSAC register correctly
by Arthur Heymans 22 Oct '16

22 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17094 -gerrit commit 6d56d8c8c479146b775498482cb699612227e082 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Sat Oct 22 14:16:48 2016 +0200 nb/i945/gma.c: Set the MSAC register correctly This fixes an instability on 945gc caused by asking the IGD to do something with compositing, (e.g. launching gdm, gnome, ...) which completely locks up the system. TESTED on ga-945gcm-s2l and d945gclf TEST: launch GDM (gnome display manager) Change-Id: Iec49bccf3e3164df9dc1e0b54460a616fe92e04d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/gma.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/northbridge/intel/i945/gma.c b/src/northbridge/intel/i945/gma.c index 4baed80..a0c5864 100644 --- a/src/northbridge/intel/i945/gma.c +++ b/src/northbridge/intel/i945/gma.c @@ -32,6 +32,7 @@ #include "chip.h" #define GDRST 0xc0 +#define MSAC 0x62 /* Multi Size Aperture Control */ #define LVDS_CLOCK_A_POWERUP_ALL (3 << 8) #define LVDS_CLOCK_B_POWERUP_ALL (3 << 4) @@ -580,6 +581,7 @@ static int probe_edid(u8 *pmmio, u8 slave) static void gma_func0_init(struct device *dev) { + u8 reg8; u32 reg32; /* Unconditionally reset graphics */ @@ -594,6 +596,12 @@ static void gma_func0_init(struct device *dev) pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER | PCI_COMMAND_IO | PCI_COMMAND_MEMORY); + /* Set Untrusted Aperture Size to 256mb */ + reg8 = pci_read_config8(dev, MSAC); + reg8 &= ~0x3; + reg8 |= 0x2; + pci_write_config8(dev, MSAC, reg8); + if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)) { /* PCI Init, will run VBIOS */ pci_dev_init(dev);

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coreboot-gerrit October 2016