coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: arch/x86/acpigen: Clean up acpigen library
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17078 -gerrit commit 31bb1f0e07da490a8be560ce9ff74398c57aae78 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 23:09:05 2016 -0700 arch/x86/acpigen: Clean up acpigen library Instead of using hard-coded values for emitting op codes and prefix codes, define and use enum constants. With this change, it becomes easier to read the code as well. BUG=chrome-os-partner:55988 Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 72 ++++++++++++++++--------------------- src/arch/x86/include/arch/acpigen.h | 48 +++++++++++++++++++++++++ 2 files changed, 79 insertions(+), 41 deletions(-) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 00f8bd0..27fa07a 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -73,6 +73,12 @@ void acpigen_emit_byte(unsigned char b) (*gencurrent++) = b; } +void acpigen_emit_ext_op(uint8_t op) +{ + acpigen_emit_byte(EXT_OP_PREFIX); + acpigen_emit_byte(op); +} + void acpigen_emit_word(unsigned int data) { acpigen_emit_byte(data & 0xff); @@ -90,8 +96,7 @@ void acpigen_emit_dword(unsigned int data) char *acpigen_write_package(int nr_el) { char *p; - /* package op */ - acpigen_emit_byte(0x12); + acpigen_emit_byte(PACKAGE_OP); acpigen_write_len_f(); p = acpigen_get_current(); acpigen_emit_byte(nr_el); @@ -100,46 +105,42 @@ char *acpigen_write_package(int nr_el) void acpigen_write_byte(unsigned int data) { - /* byte op */ - acpigen_emit_byte(0xa); + acpigen_emit_byte(BYTE_PREFIX); acpigen_emit_byte(data & 0xff); } void acpigen_write_word(unsigned int data) { - /* word op */ - acpigen_emit_byte(0xb); + acpigen_emit_byte(WORD_PREFIX); acpigen_emit_word(data); } void acpigen_write_dword(unsigned int data) { - /* dword op */ - acpigen_emit_byte(0xc); + acpigen_emit_byte(DWORD_PREFIX); acpigen_emit_dword(data); } void acpigen_write_qword(uint64_t data) { - /* qword op */ - acpigen_emit_byte(0xe); + acpigen_emit_byte(QWORD_PREFIX); acpigen_emit_dword(data & 0xffffffff); acpigen_emit_dword((data >> 32) & 0xffffffff); } void acpigen_write_zero(void) { - acpigen_emit_byte(0x00); + acpigen_emit_byte(ZERO_OP); } void acpigen_write_one(void) { - acpigen_emit_byte(0x01); + acpigen_emit_byte(ONE_OP); } void acpigen_write_ones(void) { - acpigen_emit_byte(0xff); + acpigen_emit_byte(ONES_OP); } void acpigen_write_integer(uint64_t data) @@ -216,7 +217,7 @@ void acpigen_emit_string(const char *string) void acpigen_write_string(const char *string) { - acpigen_emit_byte(0x0d); + acpigen_emit_byte(STRING_PREFIX); acpigen_emit_string(string); } @@ -251,8 +252,7 @@ static void acpigen_emit_simple_namestring(const char *name) { } static void acpigen_emit_double_namestring(const char *name, int dotpos) { - /* mark dual name prefix */ - acpigen_emit_byte(0x2e); + acpigen_emit_byte(DUAL_NAME_PREFIX); acpigen_emit_simple_namestring(name); acpigen_emit_simple_namestring(&name[dotpos + 1]); } @@ -260,9 +260,8 @@ static void acpigen_emit_double_namestring(const char *name, int dotpos) { static void acpigen_emit_multi_namestring(const char *name) { int count = 0; unsigned char *pathlen; - /* mark multi name prefix */ - acpigen_emit_byte(0x2f); - acpigen_emit_byte(0x0); + acpigen_emit_byte(MULTI_NAME_PREFIX); + acpigen_emit_byte(ZERO_OP); pathlen = ((unsigned char *) acpigen_get_current()) - 1; while (name[0] != '\0') { @@ -299,7 +298,7 @@ void acpigen_emit_namestring(const char *namepath) { /* If we have only \\ or only ^...^. Then we need to put a null name (0x00). */ if (namepath[0] == '\0') { - acpigen_emit_byte(0x00); + acpigen_emit_byte(ZERO_OP); return; } @@ -323,15 +322,13 @@ void acpigen_emit_namestring(const char *namepath) { void acpigen_write_name(const char *name) { - /* name op */ - acpigen_emit_byte(0x8); + acpigen_emit_byte(NAME_OP); acpigen_emit_namestring(name); } void acpigen_write_scope(const char *name) { - /* scope op */ - acpigen_emit_byte(0x10); + acpigen_emit_byte(SCOPE_OP); acpigen_write_len_f(); acpigen_emit_namestring(name); } @@ -343,9 +340,7 @@ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { */ char pscope[16]; - /* processor op */ - acpigen_emit_byte(0x5b); - acpigen_emit_byte(0x83); + acpigen_emit_ext_op(PROCESSOR_OP); acpigen_write_len_f(); snprintf(pscope, sizeof(pscope), @@ -445,8 +440,7 @@ void acpigen_write_empty_PTC(void) void acpigen_write_method(const char *name, int nargs) { - /* method op */ - acpigen_emit_byte(0x14); + acpigen_emit_byte(METHOD_OP); acpigen_write_len_f(); acpigen_emit_namestring(name); acpigen_emit_byte(nargs & 7); @@ -454,9 +448,7 @@ void acpigen_write_method(const char *name, int nargs) void acpigen_write_device(const char *name) { - /* device op */ - acpigen_emit_byte(0x5b); - acpigen_emit_byte(0x82); + acpigen_emit_ext_op(DEVICE_OP); acpigen_write_len_f(); acpigen_emit_namestring(name); } @@ -467,7 +459,7 @@ void acpigen_write_STA(uint8_t status) * Method (_STA, 0, NotSerialized) { Return (status) } */ acpigen_write_method("_STA", 0); - acpigen_emit_byte(0xa4); + acpigen_emit_byte(RETURN_OP); acpigen_write_byte(status); acpigen_pop_len(); } @@ -484,8 +476,7 @@ void acpigen_write_PPC(u8 nr) } */ acpigen_write_method("_PPC", 0); - /* return */ - acpigen_emit_byte(0xa4); + acpigen_emit_byte(RETURN_OP); /* arg */ acpigen_write_byte(nr); acpigen_pop_len(); @@ -504,8 +495,7 @@ void acpigen_write_PPC_NVS(void) } */ acpigen_write_method("_PPC", 0); - /* return */ - acpigen_emit_byte(0xa4); + acpigen_emit_byte(RETURN_OP); /* arg */ acpigen_emit_namestring("PPCM"); acpigen_pop_len(); @@ -521,7 +511,7 @@ void acpigen_write_TPC(const char *gnvs_tpc_limit) } */ acpigen_write_method("_TPC", 0); - acpigen_emit_byte(0xa4); /* ReturnOp */ + acpigen_emit_byte(RETURN_OP); acpigen_emit_namestring(gnvs_tpc_limit); acpigen_pop_len(); } @@ -731,9 +721,9 @@ void acpigen_write_resourcetemplate_header(void) * resource items, terminated by the end tag. * (small item 0xf, len 1) */ - acpigen_emit_byte(0x11); /* Buffer opcode */ + acpigen_emit_byte(BUFFER_OP); acpigen_write_len_f(); - acpigen_emit_byte(0x0b); /* Word opcode */ + acpigen_emit_byte(WORD_PREFIX); len_stack[ltop++] = acpigen_get_current(); acpigen_emit_byte(0x00); acpigen_emit_byte(0x00); @@ -862,7 +852,7 @@ void acpigen_write_uuid(const char *uuid) return; /* BufferOp */ - acpigen_emit_byte(0x11); + acpigen_emit_byte(BUFFER_OP); acpigen_write_len_f(); /* Buffer length in bytes */ diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index f513698..4e8456d 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -34,6 +34,53 @@ ACPI_STATUS_DEVICE_SHOW_IN_UI |\ ACPI_STATUS_DEVICE_STATE_OK) +/* ACPI Op/Prefix Codes */ +enum { + ZERO_OP = 0x00, + ONE_OP = 0x01, + NAME_OP = 0x08, + SCOPE_OP = 0x10, + BUFFER_OP = 0x11, + BYTE_PREFIX = 0x0A, + WORD_PREFIX = 0x0B, + DWORD_PREFIX = 0x0C, + STRING_PREFIX = 0x0D, + QWORD_PREFIX = 0x0E, + PACKAGE_OP = 0x12, + METHOD_OP = 0x14, + DUAL_NAME_PREFIX = 0x2E, + MULTI_NAME_PREFIX = 0x2F, + EXT_OP_PREFIX = 0x5B, + SLEEP_OP = 0x22, + DEBUG_OP = 0x31, + DEVICE_OP = 0x82, + PROCESSOR_OP = 0x83, + POWER_RES_OP = 0x84, + LOCAL0_OP = 0x60, + LOCAL1_OP = 0x61, + LOCAL2_OP = 0x62, + LOCAL3_OP = 0x63, + LOCAL4_OP = 0x64, + LOCAL5_OP = 0x65, + LOCAL6_OP = 0x66, + LOCAL7_OP = 0x67, + ARG0_OP = 0x68, + ARG1_OP = 0x69, + ARG2_OP = 0x6A, + ARG3_OP = 0x6B, + ARG4_OP = 0x6C, + ARG5_OP = 0x6D, + ARG6_OP = 0x6E, + STORE_OP = 0x70, + AND_OP = 0x7B, + OR_OP = 0x7D, + NOT_OP = 0x80, + IF_OP = 0xA0, + ELSE_OP = 0xA1, + RETURN_OP = 0xA4, + ONES_OP = 0xFF, +}; + void acpigen_write_len_f(void); void acpigen_pop_len(void); void acpigen_set_current(char *curr); @@ -44,6 +91,7 @@ void acpigen_write_one(void); void acpigen_write_ones(void); void acpigen_write_byte(unsigned int data); void acpigen_emit_byte(unsigned char data); +void acpigen_emit_ext_op(uint8_t op); void acpigen_emit_word(unsigned int data); void acpigen_emit_dword(unsigned int data); void acpigen_emit_stream(const char *data, int size);

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Patch set updated for coreboot: drivers/i2c/generic: Re-factor SSDT generation code
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17089 -gerrit commit 45b0f42c8918749c4a3dd4711f47bea2183c1a69 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:24:07 2016 -0700 drivers/i2c/generic: Re-factor SSDT generation code 1. Export i2c_generic_fill_ssdt to allow other device-specific i2c drivers to share and re-use the same code for generating AML code for SSDT. In order to achieve this, following changes are required: a. Add macro I2C_GENERIC_CONFIG that defines a structure with all generic i2c device-tree properties. This macro should be placed by the using driver at the start of its config structure. b. Accept a callback function to add any device specific information to SSDT. If generic driver is used directly by a device, callback would be NULL. Other devices using a separate i2c driver can provide a callback to add any properties to SSDT. 2. Allow device to provide _CID. BUG=chrome-os-partner:57846 Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 33 +++++++++++++++++++++++++++++++++ src/drivers/i2c/generic/generic.c | 16 ++++++++++++++-- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index e84fc38..736de51 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -1,8 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_GENERIC_CHIP_H__ +#define __I2C_GENERIC_CHIP_H__ + #include <arch/acpi_device.h> #include <device/i2c.h> struct drivers_i2c_generic_config { const char *hid; /* ACPI _HID (required) */ + const char *cid; /* ACPI _CID */ const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ unsigned uid; /* ACPI _UID */ @@ -32,3 +51,17 @@ struct drivers_i2c_generic_config { /* Delay to be inserted after device is enabled. */ unsigned enable_delay_ms; }; + +/* + * Fills in generic information about i2c device from device-tree + * properties. Callback can be provided to fill in any + * device-specific information in SSDT. + * + * Drivers calling into this function to generate should place + * drivers_i2c_generic_config structure at the beginning of their device config + * structure. + */ +void i2c_generic_fill_ssdt(struct device *dev, + void (*callback)(struct device *dev)); + +#endif /* __I2C_GENERIC_CHIP_H__ */ diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index bf40a2a..83b0953 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -65,7 +65,8 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) acpigen_pop_len(); /* PowerResource PRIC */ } -static void i2c_generic_fill_ssdt(struct device *dev) +void i2c_generic_fill_ssdt(struct device *dev, + void (*callback)(struct device *dev)) { struct drivers_i2c_generic_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); @@ -89,6 +90,8 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", config->hid); + if (config->cid) + acpigen_write_name_string("_CID", config->cid); acpigen_write_name_integer("_UID", config->uid); acpigen_write_name_string("_DDN", config->desc); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); @@ -115,6 +118,10 @@ static void i2c_generic_fill_ssdt(struct device *dev) /* Power Resource */ i2c_generic_add_power_res(config); + /* Callback if any. */ + if (callback) + callback(dev); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ @@ -122,6 +129,11 @@ static void i2c_generic_fill_ssdt(struct device *dev) config->desc ? : dev->chip_ops->name, dev_path(dev)); } +static void i2c_generic_fill_ssdt_generator(struct device *dev) +{ + i2c_generic_fill_ssdt(dev, NULL); +} + /* Use name specified in config or build one from I2C address */ static const char *i2c_generic_acpi_name(struct device *dev) { @@ -143,7 +155,7 @@ static struct device_operations i2c_generic_ops = { .enable_resources = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_name = &i2c_generic_acpi_name, - .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt, + .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt_generator, #endif };

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Patch set updated for coreboot: drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17092 -gerrit commit ad84dc38bd9669c0d783ff034828bb4a0a8b28ca Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:42:45 2016 -0700 drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver BUG=chrome-os-partner:57846 Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/wacom_ts/Kconfig | 3 ++ src/drivers/i2c/wacom_ts/Makefile.inc | 1 + src/drivers/i2c/wacom_ts/chip.h | 30 ++++++++++++++++ src/drivers/i2c/wacom_ts/ts.c | 65 +++++++++++++++++++++++++++++++++++ 4 files changed, 99 insertions(+) diff --git a/src/drivers/i2c/wacom_ts/Kconfig b/src/drivers/i2c/wacom_ts/Kconfig new file mode 100644 index 0000000..50da3f1 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_I2C_WACOM_TS + bool + select DRIVERS_I2C_GENERIC diff --git a/src/drivers/i2c/wacom_ts/Makefile.inc b/src/drivers/i2c/wacom_ts/Makefile.inc new file mode 100644 index 0000000..9455099 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_WACOM_TS) += ts.c diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h new file mode 100644 index 0000000..b59f630 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_WACOM_TS_CHIP_H__ +#define __I2C_WACOM_TS_CHIP_H__ + +#include <drivers/i2c/generic/chip.h> + +#define WCOM50C1_HID "WCOM50C1" +#define PNP0C50_CID "PNP0C50" +#define WCOM_TS_DESC "WCOM Touchscreen" + +struct drivers_i2c_wacom_ts_config { + struct drivers_i2c_generic_config generic; + uint8_t hid_desc_reg_offset; +}; + +#endif /* __I2C_WACOM_TS_CHIP_H__ */ diff --git a/src/drivers/i2c/wacom_ts/ts.c b/src/drivers/i2c/wacom_ts/ts.c new file mode 100644 index 0000000..8757ccc --- /dev/null +++ b/src/drivers/i2c/wacom_ts/ts.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <arch/acpigen_dsm.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +static void i2c_wacom_ts_fill_dsm(struct device *dev) +{ + struct drivers_i2c_wacom_ts_config *config = dev->chip_info; + struct dsm_i2c_hid_config dsm_config = { + .hid_desc_reg_offset = config->hid_desc_reg_offset, + }; + + acpigen_write_dsm_i2c_hid(&dsm_config); +} + +static void i2c_wacom_ts_fill_ssdt_generator(struct device *dev) +{ + i2c_generic_fill_ssdt(dev, &i2c_wacom_ts_fill_dsm); +} + +static const char *i2c_wacom_ts_acpi_name(struct device *dev) +{ + return "WCTS"; +} + +static struct device_operations i2c_wacom_ts_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &i2c_wacom_ts_acpi_name, + .acpi_fill_ssdt_generator = &i2c_wacom_ts_fill_ssdt_generator, +#endif +}; + +static void i2c_wacom_ts_enable(struct device *dev) +{ + dev->ops = &i2c_wacom_ts_ops; +} + +struct chip_operations drivers_i2c_wacom_ts_ops = { + CHIP_NAME("Wacom Touchscreen Device") + .enable_dev = &i2c_wacom_ts_enable +};

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Patch set updated for coreboot: google/reef/variants/pyro: Use WCOM Touchscreen driver
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17093 -gerrit commit 25e511f0edf6916467097d1df78ef04b820f8cb7 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:45:59 2016 -0700 google/reef/variants/pyro: Use WCOM Touchscreen driver BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 3 +++ src/mainboard/google/reef/variants/pyro/devicetree.cb | 13 ++++++++----- 2 files changed, 11 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d5d64c8..6045f47 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -40,6 +40,9 @@ config DRIVERS_I2C_DA7219 config DRIVERS_I2C_GENERIC default y +config DRIVERS_I2C_WACOM_TS + default y + config DRIVERS_PS2_KEYBOARD default y diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 43ec2ed..62183cc 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -131,11 +131,14 @@ chip soc/intel/apollolake end end # - I2C 2 device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + chip drivers/i2c/wacom_ts + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_TS_DESC, + .irq = IRQ_EDGE_LOW(GPIO_21_IRQ), + }" + register "hid_desc_reg_offset" = "0x1" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: drivers/i2c/generic: Enable support for adding PowerResource for device
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17081 -gerrit commit 5bc735e0389a7c7b95046e6b68bd6f29126613e4 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 16:01:04 2016 -0700 drivers/i2c/generic: Enable support for adding PowerResource for device Add support to allow a device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: 1. Reset GPIO - Optional, GPIO to put device into reset or take it out of reset. 2. Reset delay - Delay after reset GPIO is de-asserted (default 0). 3. Enable GPIO - Optional, GPIO to enabled device. 4. Enable delay - Delay after enable GPIO is asserted (default 0). BUG=chrome-os-partner:55988 Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 9 ++++++++ src/drivers/i2c/generic/generic.c | 43 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..e84fc38 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,13 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + + /* GPIO used to take device out of reset or to put it into reset. */ + unsigned reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned reset_delay_ms; + /* GPIO used to enable device. */ + unsigned enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned enable_delay_ms; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index c11a889..bf40a2a 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,46 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) +{ + if (!config->reset_gpio && !config->enable_gpio) + return; + + const char *power_res_dev_states[] = { "_PR0", "_PR3" }; + + /* PowerResource (PRIC, 0, 0) */ + acpigen_write_power_res("PRIC", 0, 0, power_res_dev_states, + ARRAY_SIZE(power_res_dev_states)); + + /* Method (_STA, 0, NotSerialized) { Return (0x1) } */ + acpigen_write_STA(0x1); + + /* Method (_ON, 0, Serialized) */ + acpigen_write_method_serialized("_ON", 0); + if (config->reset_gpio) + acpigen_soc_set_tx_gpio(config->reset_gpio); + if (config->enable_gpio) { + acpigen_soc_set_tx_gpio(config->enable_gpio); + acpigen_write_sleep(config->enable_delay_ms); + } + if (config->reset_gpio) { + acpigen_soc_clear_tx_gpio(config->reset_gpio); + acpigen_write_sleep(config->reset_delay_ms); + } + acpigen_pop_len(); /* _ON method */ + + /* Method (_OFF, 0, Serialized) */ + acpigen_write_method_serialized("_OFF", 0); + if (config->reset_gpio) + acpigen_soc_set_tx_gpio(config->reset_gpio); + if (config->enable_gpio) + acpigen_soc_clear_tx_gpio(config->enable_gpio); + acpigen_pop_len(); /* _OFF method */ + + acpigen_pop_len(); /* PowerResource PRIC */ +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -72,6 +112,9 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpi_dp_write(dsd); } + /* Power Resource */ + i2c_generic_add_power_res(config); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

1 0

Patch set updated for coreboot: arch/x86/acpigen: Add support for interacting with GPIOs
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17080 -gerrit commit 139e272fa560c3262802c85fefc08b66374ff2b1 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 07:12:49 2016 -0700 arch/x86/acpigen: Add support for interacting with GPIOs Since reading/toggling of GPIOs is platform-dependent task, provide an interface with common functions to generate ACPI AML code for manipulating GPIOs: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio Provide weak implementations of above functions. These functions are expected to be implemented by every SoC that uses ACPI. This allows drivers to easily generate ACPI AML code to interact GPIOs. BUG=chrome-os-partner:55988 Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 29 +++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 22 ++++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index e0e957a..0a57263 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -992,3 +992,32 @@ void acpigen_write_else(void) acpigen_emit_byte(ELSE_OP); acpigen_write_len_f(); } + +/* Soc-implemented functions -- weak definitions. */ +int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("read_rx_gpio not available"); + return -1; +} + +int __attribute__((weak)) acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("get_tx_gpio not available"); + return -1; +} + +int __attribute__((weak)) acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("set_tx_gpio not available"); + return -1; +} + +int __attribute__((weak)) acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + printk(BIOS_ERR, "ERROR: %s not implemented\n", __func__); + acpigen_write_debug_string("clear_tx_gpio not available"); + return -1; +} diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index c2936e2..0c515da 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -160,4 +160,26 @@ void acpigen_write_else(void); int get_cst_entries(acpi_cstate_t **); +/* + * Soc-implemented functions for generating ACPI AML code for GPIO handling. All + * these functions are expected to use only Local5, Local6 and Local7 + * variables. If the functions call into another ACPI method, then there is no + * restriction on the use of Local variables. In case of get/read functions, + * return value is expected to be stored in Local0 variable. + * + * All functions return 0 on success and -1 on error. + */ + +/* Generate ACPI AML code to return Rx value of GPIO in Local0. */ +int acpigen_soc_read_rx_gpio(unsigned int gpio_num); + +/* Generate ACPI AML code to return Tx value of GPIO in Local0. */ +int acpigen_soc_get_tx_gpio(unsigned int gpio_num); + +/* Generate ACPI AML code to set Tx value of GPIO to 1. */ +int acpigen_soc_set_tx_gpio(unsigned int gpio_num); + +/* Generate ACPI AML code to set Tx value of GPIO to 0. */ +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num); + #endif

1 0

Patch set updated for coreboot: mainboard/google/reef: Add PowerResource for ELAN touchscreen
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17083 -gerrit commit 6728ce3fdf8b9fbab0ac103dd6eb4c3045549d79 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:48:45 2016 -0700 mainboard/google/reef: Add PowerResource for ELAN touchscreen Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:55988 Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 00df9bd..30d61f6 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -142,6 +142,10 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "GPIO_36" + register "reset_delay_ms" = "20" + register "enable_gpio" = "GPIO_152" + register "enable_delay_ms" = "1" device i2c 10 on end end end # - I2C 3

1 0

Patch set updated for coreboot: soc/intel/apollolake: Implement GPIO ACPI AML generating functions
by Furquan Shaikh 21 Oct '16

21 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17082 -gerrit commit d79caf3ea76bfbb14d5ea0223fc73ef57a296bda Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:45:26 2016 -0700 soc/intel/apollolake: Implement GPIO ACPI AML generating functions Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio BUG=chrome-os-partner:55988 Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/apollolake/acpi.c | 89 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index ba22aee..3c1faa5 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -267,3 +267,92 @@ uint16_t soc_get_acpi_base_address(void) { return ACPI_PMIO_BASE; } + +static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) +{ + /* + * Store (\_SB.GPC0 (addr), Local5) + * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in + * gpiolib.asl. + */ + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.GPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); +} + +static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) +{ + assert (gpio_num < TOTAL_PADS); + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); + + acpigen_soc_get_dw0_in_local5(addr); + + /* If (And (Local5, mask)) */ + acpigen_write_if_and(LOCAL5_OP, mask); + + /* Store (One, Local0) */ + acpigen_write_store_ops(ONE_OP, LOCAL0_OP); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + + /* Store (Zero, Local0) */ + acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); + + acpigen_pop_len(); /* Else */ + + return 0; +} + +static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) +{ + assert (gpio_num < TOTAL_PADS); + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); + + acpigen_soc_get_dw0_in_local5(addr); + + if (val) { + /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ + acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); + } else { + /* Not (PAD_CFG0_TX_STATE, Local6) */ + acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); + + /* And (Local5, Local6, Local5) */ + acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); + } + + /* + * \_SB.SPC0 (addr, Local5) + * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in + * gpiolib.asl. + */ + acpigen_emit_namestring("\\_SB.SPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 1); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 0); +}

1 0

Patch set updated for coreboot: drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support
by Brenton Dong 21 Oct '16

21 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17062 -gerrit commit 60adad6332503a53acd17863aa5b4d954d3b035e Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Tue Oct 18 11:35:15 2016 -0700 drivers/intel/fsp2_0: add FSP TempRamInit & TempRamExit API support FSP v2.0 Specification adds APIs TempRamInit & TempRamExit for Cache-As-Ram initialization and teardown. Add fsp2_0 driver support for TempRamInit & TempRamExit APIs. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: I482ff580e1b5251a8214fe2e3d2d38bd5f3e3ed2 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/drivers/intel/fsp2_0/Kconfig | 17 ++++++++ src/drivers/intel/fsp2_0/Makefile.inc | 12 ++++++ src/drivers/intel/fsp2_0/include/fsp/api.h | 1 + src/drivers/intel/fsp2_0/include/fsp/info_header.h | 2 + src/drivers/intel/fsp2_0/include/fsp/util.h | 1 + src/drivers/intel/fsp2_0/temp_ram_exit.c | 50 ++++++++++++++++++++++ src/drivers/intel/fsp2_0/util.c | 2 + 7 files changed, 85 insertions(+) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index 3ffb402..62bdd50 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -53,6 +53,11 @@ config DISPLAY_UPD_DATA Display the user specified product data prior to memory initialization. +config FSP_T_CBFS + string "Name of FSP-T in CBFS" + depends on FSP_CAR + default "fspt.bin" + config FSP_S_CBFS string "Name of FSP-S in CBFS" default "fsps.bin" @@ -61,6 +66,12 @@ config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" +config FSP_T_FILE + string "Intel FSP-T (temp ram init) binary path and filename" + depends on FSP_CAR + help + The path and filename of the Intel FSP-M binary for this platform. + config FSP_M_FILE string "Intel FSP-M (memory init) binary path and filename" depends on ADD_FSP_BINARIES @@ -73,6 +84,12 @@ config FSP_S_FILE help The path and filename of the Intel FSP-S binary for this platform. +config FSP_CAR + bool "Use FSP TempRamInit & TempRamExit APIs" + default n + help + Use FSP APIs to initialize & Tear Down the Cache-As-Ram + config FSP_M_XIP bool "Is FSP-M XIP" default n diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index beeec7c..c5b719d 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -38,11 +38,23 @@ ramstage-$(CONFIG_DISPLAY_UPD_DATA) += upd_display.c ramstage-y += util.c postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c +postcar-$(CONFIG_FSP_CAR) += temp_ram_exit.c +postcar-$(CONFIG_FSP_CAR) += util.c +postcar-$(CONFIG_DISPLAY_FSP_HEADER) += header_display.c CPPFLAGS_common += -I$(src)/drivers/intel/fsp2_0/include # Add FSP blobs into cbfs. SoC code may supply additional options with # -options, e.g --xip or -b +ifeq ($(CONFIG_FSP_CAR),y) +cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_T_CBFS) +$(CONFIG_FSP_T_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_T_FILE)) +$(CONFIG_FSP_T_CBFS)-type := fsp +ifeq ($(CONFIG_FSP_T_XIP),y) +$(CONFIG_FSP_T_CBFS)-options := --xip +endif +endif # CONFIG_FSP_CAR + cbfs-files-$(CONFIG_ADD_FSP_BINARIES) += $(CONFIG_FSP_M_CBFS) $(CONFIG_FSP_M_CBFS)-file := $(call strip_quotes,$(CONFIG_FSP_M_FILE)) $(CONFIG_FSP_M_CBFS)-type := fsp diff --git a/src/drivers/intel/fsp2_0/include/fsp/api.h b/src/drivers/intel/fsp2_0/include/fsp/api.h index 553fc52..61a5140 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/api.h +++ b/src/drivers/intel/fsp2_0/include/fsp/api.h @@ -39,6 +39,7 @@ enum fsp_notify_phase { /* Main FSP stages */ void fsp_memory_init(bool s3wake); void fsp_silicon_init(void); +uint32_t temp_ram_exit(void); /* Callbacks for updating stage-specific parameters */ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd); diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index 6351b32..c84c33e 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -34,6 +34,8 @@ struct fsp_header { uint16_t component_attribute; size_t cfg_region_offset; size_t cfg_region_size; + size_t temp_ram_init_entry; + size_t temp_ram_exit_entry; size_t notify_phase_entry_offset; size_t memory_init_entry_offset; size_t silicon_init_entry_offset; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index 04f8c00..13c6ab2 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -101,6 +101,7 @@ void fsp_handle_reset(uint32_t status); /* SoC/chipset must provide this to handle platform-specific reset codes */ void chipset_handle_reset(uint32_t status); +typedef asmlinkage uint32_t (*temp_ram_exit_fn)(void *param); typedef asmlinkage uint32_t (*fsp_memory_init_fn) (void *raminit_upd, void **hob_list); typedef asmlinkage uint32_t (*fsp_silicon_init_fn)(void *silicon_upd); diff --git a/src/drivers/intel/fsp2_0/temp_ram_exit.c b/src/drivers/intel/fsp2_0/temp_ram_exit.c new file mode 100644 index 0000000..1bf1e24 --- /dev/null +++ b/src/drivers/intel/fsp2_0/temp_ram_exit.c @@ -0,0 +1,50 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + */ + +#include <arch/io.h> +#include <arch/cpu.h> +#include <console/console.h> +#include <fsp/api.h> +#include <fsp/util.h> +#include <memrange.h> +#include <string.h> +#include <timestamp.h> + +#include <cbfs.h> + +uint32_t temp_ram_exit(void) +{ + struct fsp_header hdr; + uint32_t status; + temp_ram_exit_fn fsp_temp_ram_exit; + struct cbfsf file_desc; + struct region_device file_data; + const char *name = CONFIG_FSP_M_CBFS; + + if (cbfs_boot_locate(&file_desc, name, NULL)) { + printk(BIOS_CRIT, "Could not locate %s in CBFS\n", name); + die("FSPM not available for CAR Exit!\n"); + } + + cbfs_file_data(&file_data, &file_desc); + + if (fsp_validate_component(&hdr, &file_data) != CB_SUCCESS) + return CB_ERR; + + fsp_temp_ram_exit = (void *)(hdr.image_base + hdr.temp_ram_exit_entry); + printk(BIOS_DEBUG, "Calling TempRamExit: 0x%p\n", fsp_temp_ram_exit); + status = fsp_temp_ram_exit(NULL); + printk(BIOS_DEBUG, "TempRamExit returned 0x%08x\n", status); + + return status; +} diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index e7e4f16..7453b59 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -52,6 +52,8 @@ enum cb_err fsp_identify(struct fsp_header *hdr, const void *fsp_blob) hdr->component_attribute = read16(raw_hdr + 34); hdr->cfg_region_offset = read32(raw_hdr + 36); hdr->cfg_region_size = read32(raw_hdr + 40); + hdr->temp_ram_init_entry = read32(raw_hdr + 48); + hdr->temp_ram_exit_entry = read32(raw_hdr + 64); hdr->notify_phase_entry_offset = read32(raw_hdr + 56); hdr->memory_init_entry_offset = read32(raw_hdr + 60); hdr->silicon_init_entry_offset = read32(raw_hdr + 68);

1 0

Patch set updated for coreboot: soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init
by Brenton Dong 21 Oct '16

21 Oct '16

Brenton Dong (brenton.m.dong(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17063 -gerrit commit ef2b9f9ce3f465de172617956553419c3bf2eaaa Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Tue Oct 18 13:57:54 2016 -0700 soc/intel/apollolake: allow ApolloLake SoC to use FSP CAR Init FSP v2.0 Driver supports TempRamInit & TempRamExit APIs to initialize & tear down Cache-As-Ram. Add TempRamInit & TempRamExit usage to ApolloLake SoC when CONFIG_FSP_CAR is enabled. Verified on Intel Leaf Hill CRB and confirmed that Cache-As-Ram is correctly set up and torn down using the FSP v2.0 APIs without coreboot implementation of CAR init/teardown. Change-Id: Ifd6fe8398ea147a5fb8c60076b93205bb94b1f25 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 15 +++- .../intel/apollolake/bootblock/cache_as_ram_fsp.S | 98 ++++++++++++++++++++++ src/soc/intel/apollolake/exit_car_fsp.S | 29 +++++++ src/soc/intel/apollolake/include/soc/postcar.h | 26 ++++++ src/soc/intel/apollolake/postcar.c | 34 ++++++++ 5 files changed, 200 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 4f867e1..b4a79f0 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -9,7 +9,6 @@ subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache bootblock-y += bootblock/bootblock.c -bootblock-y += bootblock/cache_as_ram.S bootblock-y += bootblock/bootblock.c bootblock-y += car.c bootblock-y += gpio.c @@ -22,6 +21,12 @@ bootblock-y += spi.c bootblock-y += tsc_freq.c bootblock-$(CONFIG_SOC_UART_DEBUG) += uart_early.c +ifeq ($(CONFIG_FSP_CAR),y) +bootblock-y += bootblock/cache_as_ram_fsp.S +else +bootblock-y += bootblock/cache_as_ram.S +endif + romstage-y += car.c romstage-$(CONFIG_PLATFORM_USES_FSP2_0) += romstage.c romstage-y += gpio.c @@ -75,13 +80,19 @@ ramstage-y += sram.c ramstage-y += spi.c ramstage-y += xhci.c -postcar-y += exit_car.S postcar-y += memmap.c postcar-y += mmap_boot.c postcar-y += spi.c postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c postcar-y += tsc_freq.c +ifeq ($(CONFIG_FSP_CAR),y) +postcar-y += exit_car_fsp.S +postcar-y += postcar.c +else +postcar-y += exit_car.S +endif + verstage-y += car.c verstage-y += i2c_early.c verstage-y += heci.c diff --git a/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S new file mode 100755 index 0000000..779cfeb --- /dev/null +++ b/src/soc/intel/apollolake/bootblock/cache_as_ram_fsp.S @@ -0,0 +1,98 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_def.h> +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cache.h> +#include <cpu/x86/cr.h> +#include <cpu/x86/post_code.h> +#include <soc/cpu.h> + +#include <../../../arch/x86/walkcbfs.S> + +.global bootblock_pre_c_entry +bootblock_pre_c_entry: + +.global cache_as_ram +cache_as_ram: + post_code(0x21) + + /* find fsp in cbfs */ + lea fsp_name, %esi + mov $1f, %esp + jmp walkcbfs_asm +1: + cmp $0, %eax + jz .halt_forever + mov CBFS_FILE_OFFSET(%eax), %ebx + bswap %ebx + add %eax, %ebx + add $0x94, %ebx + + /* + * ebx = FSP INFO HEADER + * Calculate entry into FSP + */ + mov 0x30(%ebx), %eax /* Load TempRamInitEntry */ + add 0x1c(%ebx), %eax /* add in the offset for FSP */ + + /* + * Pass early init variables on a fake stack (no memory yet) + * as well as the return location + */ + lea CAR_init_stack, %esp + + /* call FSP binary to setup temporary stack */ + jmp *%eax + +CAR_init_done: + + /* Setup bootblock stack */ + mov %edx, %esp + + /* clear CAR_GLOBAL area as it is not shared */ + cld + xor %eax, %eax + movl $(_car_global_end), %ecx + movl $(_car_global_start), %edi + sub %edi, %ecx + rep stosl + nop + + /* We can call into C functions now */ + call bootblock_c_entry + + /* Never reached */ + +.halt_forever: + post_code(POST_DEAD_CODE) + hlt + jmp .halt_forever + +CAR_init_params: + .long 0xFFFFFFFF - CONFIG_ROM_SIZE + 1 /* Microcode Location */ + .long 0 /* Microcode Length */ + .long 0xFFFFFFFF - CONFIG_IBBL_ROM_SIZE + 1 /* Firmware Location */ + .long CONFIG_IBBL_ROM_SIZE /* Total Firmware Length */ + +CAR_init_stack: + .long CAR_init_done + .long CAR_init_params + +fsp_name: + .ascii "blobs/fspt.bin\x00" diff --git a/src/soc/intel/apollolake/exit_car_fsp.S b/src/soc/intel/apollolake/exit_car_fsp.S new file mode 100644 index 0000000..122d5ca --- /dev/null +++ b/src/soc/intel/apollolake/exit_car_fsp.S @@ -0,0 +1,29 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; version 2 of + * the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <cpu/x86/mtrr.h> +#include <cpu/x86/cr.h> +#include <soc/cpu.h> + +.text +.global chipset_teardown_car +chipset_teardown_car: + + /* Set up new stack. */ + mov $CONFIG_RAMTOP, %esp + + /* Call C code */ + call post_car_main diff --git a/src/soc/intel/apollolake/include/soc/postcar.h b/src/soc/intel/apollolake/include/soc/postcar.h new file mode 100644 index 0000000..7e31def --- /dev/null +++ b/src/soc/intel/apollolake/include/soc/postcar.h @@ -0,0 +1,26 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef _SOC_APOLLOLAKE_POSTCAR_H_ +#define _SOC_APOLLOLAKE_POSTCAR_H_ + +#include <arch/cpu.h> +#include <fsp/api.h> + +void post_car_main(void); + +#endif /* _SOC_APOLLOLAKE_POSTCAR_H_ */ diff --git a/src/soc/intel/apollolake/postcar.c b/src/soc/intel/apollolake/postcar.c new file mode 100644 index 0000000..0b0e4ca --- /dev/null +++ b/src/soc/intel/apollolake/postcar.c @@ -0,0 +1,34 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Intel Corp. + * (Written by Alexandru Gagniuc <alexandrux.gagniuc(a)intel.com> for Intel Corp.) + * (Written by Andrey Petrov <andrey.petrov(a)intel.com> for Intel Corp.) + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +#include <string.h> +#include <cbmem.h> +#include <arch/cpu.h> +#include <arch/stages.h> +#include <fsp/util.h> +#include <soc/postcar.h> +#include <boot_device.h> + +void post_car_main(void) +{ + temp_ram_exit(); + + /* Recover cbmem so infrastruture using it is functional. */ + cbmem_initialize(); + + copy_and_run(); +}

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coreboot-gerrit October 2016