coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: soc/intel/apollolake: Implement GPIO ACPI AML generating functions
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17082 -gerrit commit 635044a26adf9dcc98a48806a1e5b552081bcbde Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:45:26 2016 -0700 soc/intel/apollolake: Implement GPIO ACPI AML generating functions Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio BUG=chrome-os-partner:55988 Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/soc/intel/apollolake/acpi.c | 89 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 89 insertions(+) diff --git a/src/soc/intel/apollolake/acpi.c b/src/soc/intel/apollolake/acpi.c index ba22aee..3c1faa5 100644 --- a/src/soc/intel/apollolake/acpi.c +++ b/src/soc/intel/apollolake/acpi.c @@ -267,3 +267,92 @@ uint16_t soc_get_acpi_base_address(void) { return ACPI_PMIO_BASE; } + +static void acpigen_soc_get_dw0_in_local5(uintptr_t addr) +{ + /* + * Store (\_SB.GPC0 (addr), Local5) + * \_SB.GPC0 is used to read cfg0 value from dw0. It is defined in + * gpiolib.asl. + */ + acpigen_write_store(); + acpigen_emit_namestring("\\_SB.GPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); +} + +static int acpigen_soc_get_gpio_val(unsigned int gpio_num, uint32_t mask) +{ + assert (gpio_num < TOTAL_PADS); + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); + + acpigen_soc_get_dw0_in_local5(addr); + + /* If (And (Local5, mask)) */ + acpigen_write_if_and(LOCAL5_OP, mask); + + /* Store (One, Local0) */ + acpigen_write_store_ops(ONE_OP, LOCAL0_OP); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + + /* Store (Zero, Local0) */ + acpigen_write_store_ops(ZERO_OP, LOCAL0_OP); + + acpigen_pop_len(); /* Else */ + + return 0; +} + +static int acpigen_soc_set_gpio_val(unsigned int gpio_num, uint32_t val) +{ + assert (gpio_num < TOTAL_PADS); + uintptr_t addr = (uintptr_t)gpio_dwx_address(gpio_num); + + acpigen_soc_get_dw0_in_local5(addr); + + if (val) { + /* Or (Local5, PAD_CFG0_TX_STATE, Local5) */ + acpigen_write_or(LOCAL5_OP, PAD_CFG0_TX_STATE, LOCAL5_OP); + } else { + /* Not (PAD_CFG0_TX_STATE, Local6) */ + acpigen_write_not(PAD_CFG0_TX_STATE, LOCAL6_OP); + + /* And (Local5, Local6, Local5) */ + acpigen_write_and(LOCAL5_OP, LOCAL6_OP, LOCAL5_OP); + } + + /* + * \_SB.SPC0 (addr, Local5) + * \_SB.SPC0 is used to write cfg0 value in dw0. It is defined in + * gpiolib.asl. + */ + acpigen_emit_namestring("\\_SB.SPC0"); + acpigen_write_integer(addr); + acpigen_emit_byte(LOCAL5_OP); + + return 0; +} + +int acpigen_soc_read_rx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_RX_STATE); +} + +int acpigen_soc_get_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_get_gpio_val(gpio_num, PAD_CFG0_TX_STATE); +} + +int acpigen_soc_set_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 1); +} + +int acpigen_soc_clear_tx_gpio(unsigned int gpio_num) +{ + return acpigen_soc_set_gpio_val(gpio_num, 0); +}

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New patch to review for coreboot: nb/x4x/gma.c: remove writes to FDI and embedded DP registers
by Arthur Heymans 24 Oct '16

24 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17111 -gerrit commit e2280b81e94c7570b5427b3a727cf0efdfb34fdf Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 24 17:49:35 2016 +0200 nb/x4x/gma.c: remove writes to FDI and embedded DP registers Those registers are only used on more recent Intel platforms featuring a PCH. Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 749a7c8..62e28aa 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -74,12 +74,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00040000; - vga_gr_write(0x18, 0); @@ -210,10 +204,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_DEBUG, "Borders %d x %d\n", @@ -228,12 +218,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", @@ -305,13 +289,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE

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New patch to review for coreboot: nb/gm45/gma.c: remove writes to FDI and embedded DP registers
by Arthur Heymans 24 Oct '16

24 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17110 -gerrit commit d3e265202f7897934e9cf3e021511efd5c7f8114 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 24 17:44:20 2016 +0200 nb/gm45/gma.c: remove writes to FDI and embedded DP registers Those registers are only used on more recent Intel platforms featuring a PCH. Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/t400/devicetree.cb | 1 - src/mainboard/lenovo/x200/devicetree.cb | 1 - src/northbridge/intel/gm45/gma.c | 43 --------------------------------- 3 files changed, 45 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 6bf25fa..9940bb7 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -4,7 +4,6 @@ chip northbridge/intel/gm45 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index d9cb783..b5d2496 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -9,7 +9,6 @@ chip northbridge/intel/gm45 register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8596193..5f8e2e1 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -68,11 +68,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, u32 pixel_m1 = 1; u32 pixel_m2 = 1; u32 pixel_p2; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00080000; vga_gr_write(0x18, 0); @@ -190,10 +185,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_DEBUG, "Borders %d x %d\n", @@ -210,10 +201,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", link_m1, link_n1); printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", @@ -299,13 +286,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); @@ -361,12 +341,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00040000; - vga_gr_write(0x18, 0); @@ -491,10 +465,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "Bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_SPEW, "Borders %d x %d\n", @@ -509,12 +479,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_SPEW, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_SPEW, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_SPEW, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_SPEW, "Link M1=%d, N1=%d\n", - link_m1, link_n1); printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_SPEW, "Pixel clock %d kHz\n", @@ -586,13 +550,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE

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Patch merged into coreboot/master: arch/x86/acpigen: Add support for interacting with GPIOs
by gerrit＠coreboot.org 24 Oct '16

24 Oct '16

the following patch was just integrated into master: commit 0a48aee795942538e006bba42c188ee95afb49bb Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 07:12:49 2016 -0700 arch/x86/acpigen: Add support for interacting with GPIOs Since reading/toggling of GPIOs is platform-dependent task, provide an interface with common functions to generate ACPI AML code for manipulating GPIOs: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio Provide weak implementations of above functions. These functions are expected to be implemented by every SoC that uses ACPI. This allows drivers to easily generate ACPI AML code to interact GPIOs. BUG=chrome-os-partner:55988 Change-Id: I3564f15a1cb50e6ca6132638447529648589aa0e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17080 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17080 for details. -gerrit

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Patch merged into coreboot/master: arch/x86/acpigen: Add new functions to acpigen library
by gerrit＠coreboot.org 24 Oct '16

24 Oct '16

the following patch was just integrated into master: commit fcc7a04cc8d222bf74b1d541566aacc32fd7285d Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 23:12:38 2016 -0700 arch/x86/acpigen: Add new functions to acpigen library Add functions to support generation of following AML operations: 1. PowerResource 2. Store 3. Or 4. And 5. Not 6. Debug 7. If 8. Else 9. Serialized method BUG=chrome-os-partner:55988 Change-Id: I606736b38e6a55ffdc3e814b6ae0fa367ef7595b Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17079 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Alexander Couzens <lynxis(a)fe80.eu> See https://review.coreboot.org/17079 for details. -gerrit

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Patch merged into coreboot/master: arch/x86/acpigen: Clean up acpigen library
by gerrit＠coreboot.org 24 Oct '16

24 Oct '16

the following patch was just integrated into master: commit e4e9b94db18c1b9e646a0b4d6a0bef24dc02b335 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 23:09:05 2016 -0700 arch/x86/acpigen: Clean up acpigen library Instead of using hard-coded values for emitting op codes and prefix codes, define and use enum constants. With this change, it becomes easier to read the code as well. BUG=chrome-os-partner:55988 Change-Id: I6671b84c2769a8d9b1f210642f3f8fd3d902cca2 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17078 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17078 for details. -gerrit

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Patch merged into coreboot/master: drivers/i2c/generic: Return correct name for acpi_name
by gerrit＠coreboot.org 24 Oct '16

24 Oct '16

the following patch was just integrated into master: commit 3f4e6272007483d720a7c6677e81f80810513581 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Tue Oct 18 15:11:32 2016 -0700 drivers/i2c/generic: Return correct name for acpi_name Return config->name if it is not NULL. BUG=chrome-os-partner:55988 Change-Id: I9ae229949b73de6f991383daae8d962d6cf457a7 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17077 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> See https://review.coreboot.org/17077 for details. -gerrit

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New patch to review for coreboot: rockchip/rk3399: display: do not allocate framebuffer in coreboot
by Patrick Georgi 24 Oct '16

24 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17109 -gerrit commit b2fa253390abb033ed89299047691a2df2c4ad56 Author: Lin Huang <hl(a)rock-chips.com> Date: Thu Oct 20 14:22:11 2016 -0700 rockchip/rk3399: display: do not allocate framebuffer in coreboot framebuffer address dynamically chosen by libpayload now, let's do not allocate it in coreboot and let libpayload to do it. CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, and display work Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5 Original-Signed-off-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/401401 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/devicetree.cb | 1 - src/soc/rockchip/common/include/soc/vop.h | 3 ++- src/soc/rockchip/common/vop.c | 21 +++++++++++------- src/soc/rockchip/rk3288/display.c | 3 ++- src/soc/rockchip/rk3399/chip.h | 1 - src/soc/rockchip/rk3399/display.c | 28 +++++++++--------------- src/soc/rockchip/rk3399/include/soc/display.h | 3 +-- src/soc/rockchip/rk3399/include/soc/memlayout.ld | 1 - src/soc/rockchip/rk3399/soc.c | 3 +-- 9 files changed, 29 insertions(+), 35 deletions(-) diff --git a/src/mainboard/google/gru/devicetree.cb b/src/mainboard/google/gru/devicetree.cb index 7a421b2..6f177ed 100644 --- a/src/mainboard/google/gru/devicetree.cb +++ b/src/mainboard/google/gru/devicetree.cb @@ -15,7 +15,6 @@ chip soc/rockchip/rk3399 device cpu_cluster 0 on end - register "vop_id" = "0" register "vop_mode" = "VOP_MODE_EDP" register "framebuffer_bits_per_pixel" = "32" end diff --git a/src/soc/rockchip/common/include/soc/vop.h b/src/soc/rockchip/common/include/soc/vop.h index f5ce431..98ad082 100644 --- a/src/soc/rockchip/common/include/soc/vop.h +++ b/src/soc/rockchip/common/include/soc/vop.h @@ -376,5 +376,6 @@ enum vop_modes { #define V_VASP(x) (((x)&0x1fff)<<16) void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode); -void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid); +void rkvop_prepare(u32 vop_id, const struct edid *edid); +void rkvop_enable(u32 vop_id, u32 fbbase); #endif diff --git a/src/soc/rockchip/common/vop.c b/src/soc/rockchip/common/vop.c index 668bee0..629072e 100644 --- a/src/soc/rockchip/common/vop.c +++ b/src/soc/rockchip/common/vop.c @@ -30,7 +30,19 @@ static struct rockchip_vop_regs * const vop_regs[] = { (struct rockchip_vop_regs *)VOP_LIT_BASE }; -void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) +void rkvop_enable(u32 vop_id, u32 fbbase) +{ + struct rockchip_vop_regs *preg = vop_regs[vop_id]; + + write32(&preg->win0_yrgb_mst, fbbase); + + /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only, + * but it's fine to write to it + */ + write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */ +} + +void rkvop_prepare(u32 vop_id, const struct edid *edid) { u32 lb_mode; u32 rgb_mode; @@ -85,13 +97,6 @@ void rkvop_enable(u32 vop_id, u32 fbbase, const struct edid *edid) M_WIN0_LB_MODE | M_WIN0_DATA_FMT | M_WIN0_EN, V_WIN0_LB_MODE(lb_mode) | V_WIN0_DATA_FMT(rgb_mode) | V_WIN0_EN(1)); - - write32(&preg->win0_yrgb_mst, fbbase); - - /* On RK3288, the reg_cfg_done[1:31] is reserved and read-only, - * but it's fine to write to it - */ - write32(&preg->reg_cfg_done, 0xffff); /* enable reg config */ } void rkvop_mode_set(u32 vop_id, const struct edid *edid, u32 mode) diff --git a/src/soc/rockchip/rk3288/display.c b/src/soc/rockchip/rk3288/display.c index f3dfac1..30c8ca1 100644 --- a/src/soc/rockchip/rk3288/display.c +++ b/src/soc/rockchip/rk3288/display.c @@ -108,7 +108,8 @@ void rk_display_init(device_t dev, u32 lcdbase, conf->framebuffer_bits_per_pixel, 0); rkvop_mode_set(conf->vop_id, &edid, detected_mode); - rkvop_enable(conf->vop_id, lcdbase, &edid); + rkvop_prepare(conf->vop_id, &edid); + rkvop_enable(conf->vop_id, lcdbase); switch (detected_mode) { case VOP_MODE_HDMI: diff --git a/src/soc/rockchip/rk3399/chip.h b/src/soc/rockchip/rk3399/chip.h index 46baa8c..1f9462a 100644 --- a/src/soc/rockchip/rk3399/chip.h +++ b/src/soc/rockchip/rk3399/chip.h @@ -20,7 +20,6 @@ #include <soc/vop.h> /* for vop_modes enum used in devicetree.cb */ struct soc_rockchip_rk3399_config { - u32 vop_id; gpio_t lcd_bl_pwm_gpio; gpio_t lcd_bl_en_gpio; u32 bl_power_on_udelay; diff --git a/src/soc/rockchip/rk3399/display.c b/src/soc/rockchip/rk3399/display.c index 2679860..372e115 100644 --- a/src/soc/rockchip/rk3399/display.c +++ b/src/soc/rockchip/rk3399/display.c @@ -36,20 +36,14 @@ #include "chip.h" -void rk_display_init(device_t dev, uintptr_t lcdbase, - unsigned long fb_size) +void rk_display_init(device_t dev) { struct edid edid; - uint32_t val; struct soc_rockchip_rk3399_config *conf = dev->chip_info; - uintptr_t lower = ALIGN_DOWN(lcdbase, MiB); - uintptr_t upper = ALIGN_UP(lcdbase + fb_size, MiB); enum vop_modes detected_mode = VOP_MODE_UNKNOWN; - printk(BIOS_DEBUG, "LCD framebuffer @%p\n", (void *)(lcdbase)); - memset((void *)lcdbase, 0, fb_size); /* clear the framebuffer */ - dcache_clean_invalidate_by_mva((void *)lower, upper - lower); - mmu_config_range((void *)lower, upper - lower, UNCACHED_MEM); + /* let's use vop0 in rk3399 */ + uint32_t vop_id = 0; switch (conf->vop_mode) { case VOP_MODE_NONE: @@ -58,12 +52,10 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, /* try EDP first, then HDMI */ case VOP_MODE_EDP: printk(BIOS_DEBUG, "Attempting to set up EDP display.\n"); - rkclk_configure_vop_aclk(conf->vop_id, 192 * MHz); + rkclk_configure_vop_aclk(vop_id, 192 * MHz); - /* select edp signal from vop0(big) or vop1(little) */ - val = (conf->vop_id == 1) ? RK_SETBITS(1 << 5) : - RK_CLRBITS(1 << 5); - write32(&rk3399_grf->soc_con20, val); + /* select edp signal from vop0 */ + write32(&rk3399_grf->soc_con20, RK_CLRBITS(1 << 5)); /* select edp clk from SoC internal 24M crystal, otherwise, * it will source from edp's 24M clock (that depends on @@ -89,7 +81,7 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, return; } - if (rkclk_configure_vop_dclk(conf->vop_id, + if (rkclk_configure_vop_dclk(vop_id, edid.mode.pixel_clock * KHz)) { printk(BIOS_WARNING, "config vop err\n"); return; @@ -97,9 +89,9 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, edid_set_framebuffer_bits_per_pixel(&edid, conf->framebuffer_bits_per_pixel, 0); - rkvop_mode_set(conf->vop_id, &edid, detected_mode); + rkvop_mode_set(vop_id, &edid, detected_mode); - rkvop_enable(conf->vop_id, lcdbase, &edid); + rkvop_prepare(vop_id, &edid); switch (detected_mode) { case VOP_MODE_HDMI: @@ -115,5 +107,5 @@ void rk_display_init(device_t dev, uintptr_t lcdbase, break; } - set_vbe_mode_info_valid(&edid, (uintptr_t)lcdbase); + set_vbe_mode_info_valid(&edid, (uintptr_t)0); } diff --git a/src/soc/rockchip/rk3399/include/soc/display.h b/src/soc/rockchip/rk3399/include/soc/display.h index 7ccde56..c10f1b9 100644 --- a/src/soc/rockchip/rk3399/include/soc/display.h +++ b/src/soc/rockchip/rk3399/include/soc/display.h @@ -18,8 +18,7 @@ #define REF_CLK_24M (0x1 << 0) -void rk_display_init(device_t dev, uintptr_t lcdbase, - unsigned long fb_size); +void rk_display_init(device_t dev); void mainboard_power_on_backlight(void); #endif diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index a441281..f440dfb 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -22,7 +22,6 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00100000, 1M) RAMSTAGE(0x00300000, 256K) DMA_COHERENT(0x10000000, 2M) - FRAMEBUFFER(0x10200000, 16M) /* 8K of special SRAM in PMU power domain. */ SYMBOL(pmu_sram, 0xFF3B0000) diff --git a/src/soc/rockchip/rk3399/soc.c b/src/soc/rockchip/rk3399/soc.c index 12c757f..e34ca09 100644 --- a/src/soc/rockchip/rk3399/soc.c +++ b/src/soc/rockchip/rk3399/soc.c @@ -39,8 +39,7 @@ static void soc_init(device_t dev) mmio_resource(dev, 1, (0x10000 / KiB), (0x80000 / KiB)); if (IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) && display_init_required()) - rk_display_init(dev, (uintptr_t)_framebuffer, - _framebuffer_size); + rk_display_init(dev); else printk(BIOS_INFO, "Display initialization disabled.\n");

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New patch to review for coreboot: rk3399: Reserve enough framebuffer memory for 32bpp hires panels
by Patrick Georgi 24 Oct '16

24 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17108 -gerrit commit 510791afde44054dabe4ba9d5db55d18c5a5d964 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Oct 17 17:29:09 2016 -0700 rk3399: Reserve enough framebuffer memory for 32bpp hires panels Some of our RK3399 devices have panel resolutions as high as 2400x1600. With 16bpp that barely still fit into an 8MB framebuffer, but then we changed it to 32bpp for better image quality... Note that this is a band-aid. Coreboot-allocated framebuffers shouldn't be used at all on ARM64 devices, since libpayload is perfectly capable to dynamically allocate it with the right size based on EDID-information on this architecture. That will require some more elaborate work to be fixed with later patches. BRANCH=gru BUG=chrome-os-partner:58044 TEST=Warm-reboot Kevin on the dev screen, confirm that you don't see the lower half of the screen that overflowed our allocated framebuffer preserved from the last boot as soon as the backlight turns on. Change-Id: I00a63cfef35a8ee734543abbdb298344fb529283 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: d2718efcacb50371624d9f6a3b586c298e8c2fec Original-Change-Id: Ia1fa28971c65d7d0639966e715f742309245172b Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/399966 Original-Reviewed-by: Daisuke Nojiri <dnojiri(a)chromium.org> --- src/soc/rockchip/rk3399/include/soc/memlayout.ld | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/rockchip/rk3399/include/soc/memlayout.ld b/src/soc/rockchip/rk3399/include/soc/memlayout.ld index ef8d29d..a441281 100644 --- a/src/soc/rockchip/rk3399/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3399/include/soc/memlayout.ld @@ -22,7 +22,7 @@ SECTIONS POSTRAM_CBFS_CACHE(0x00100000, 1M) RAMSTAGE(0x00300000, 256K) DMA_COHERENT(0x10000000, 2M) - FRAMEBUFFER(0x10200000, 8M) + FRAMEBUFFER(0x10200000, 16M) /* 8K of special SRAM in PMU power domain. */ SYMBOL(pmu_sram, 0xFF3B0000)

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New patch to review for coreboot: google/oak: Add derivative board Hana
by Patrick Georgi 24 Oct '16

24 Oct '16

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17107 -gerrit commit f5faf4f8cd28462ecdc74345c3f7351a1f3b21ee Author: Yidi Lin <yidi.lin(a)mediatek.com> Date: Thu Sep 1 16:36:59 2016 +0800 google/oak: Add derivative board Hana CQ-DEPEND=CL:379684 BUG=chrome-os-partner:58064 TEST=verified on hana rev0 Change-Id: Icd076dcaf07a97f3b83b428b9619e8a4dafe744d Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 7c483951a0dcd419735fffb79e6187f9ca3b08a8 Original-Change-Id: I9d886abf15931496ac61e8fd38d7fd306f2a1bf7 Original-Signed-off-by: Yidi Lin <yidi.lin(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/379504 Original-Commit-Ready: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-by: Philip Chen <philipchen(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/oak/Kconfig | 3 +++ src/mainboard/google/oak/Kconfig.name | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/src/mainboard/google/oak/Kconfig b/src/mainboard/google/oak/Kconfig index 2674643..acb27de 100644 --- a/src/mainboard/google/oak/Kconfig +++ b/src/mainboard/google/oak/Kconfig @@ -79,17 +79,20 @@ config MAINBOARD_PART_NUMBER string default "Oak" if BOARD_GOOGLE_OAK default "Elm" if BOARD_GOOGLE_ELM + default "Hana" if BOARD_GOOGLE_HANA config GBB_HWID string depends on CHROMEOS default "OAK TEST 6858" if BOARD_GOOGLE_OAK default "ELM TEST 3839" if BOARD_GOOGLE_ELM + default "HANA TEST 5855" if BOARD_GOOGLE_HANA # All Oak-derivatives count their board IDs as 0 being equivalent to Oak rev6. config BOARD_ID_ADJUSTMENT int default 0 if BOARD_GOOGLE_OAK default 7 if BOARD_GOOGLE_ELM + default 11 if BOARD_GOOGLE_HANA endif # BOARD_GOOGLE_OAK diff --git a/src/mainboard/google/oak/Kconfig.name b/src/mainboard/google/oak/Kconfig.name index ba85ad8..95e4a3d 100644 --- a/src/mainboard/google/oak/Kconfig.name +++ b/src/mainboard/google/oak/Kconfig.name @@ -5,3 +5,7 @@ config BOARD_GOOGLE_OAK config BOARD_GOOGLE_ELM bool "Elm" select BOARD_GOOGLE_OAK_COMMON + +config BOARD_GOOGLE_HANA + bool "Hana" + select BOARD_GOOGLE_OAK_COMMON

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coreboot-gerrit October 2016