coreboot-gerrit October 2016

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver
by Furquan Shaikh 25 Oct '16

25 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17092 -gerrit commit 97464e8f15ce3106f00b52aad51ee5089e02f28e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:42:45 2016 -0700 drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver BUG=chrome-os-partner:57846 Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/wacom_ts/Kconfig | 3 ++ src/drivers/i2c/wacom_ts/Makefile.inc | 1 + src/drivers/i2c/wacom_ts/chip.h | 30 ++++++++++++++++++ src/drivers/i2c/wacom_ts/ts.c | 59 +++++++++++++++++++++++++++++++++++ 4 files changed, 93 insertions(+) diff --git a/src/drivers/i2c/wacom_ts/Kconfig b/src/drivers/i2c/wacom_ts/Kconfig new file mode 100644 index 0000000..50da3f1 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_I2C_WACOM_TS + bool + select DRIVERS_I2C_GENERIC diff --git a/src/drivers/i2c/wacom_ts/Makefile.inc b/src/drivers/i2c/wacom_ts/Makefile.inc new file mode 100644 index 0000000..9455099 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_WACOM_TS) += ts.c diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h new file mode 100644 index 0000000..b59f630 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_WACOM_TS_CHIP_H__ +#define __I2C_WACOM_TS_CHIP_H__ + +#include <drivers/i2c/generic/chip.h> + +#define WCOM50C1_HID "WCOM50C1" +#define PNP0C50_CID "PNP0C50" +#define WCOM_TS_DESC "WCOM Touchscreen" + +struct drivers_i2c_wacom_ts_config { + struct drivers_i2c_generic_config generic; + uint8_t hid_desc_reg_offset; +}; + +#endif /* __I2C_WACOM_TS_CHIP_H__ */ diff --git a/src/drivers/i2c/wacom_ts/ts.c b/src/drivers/i2c/wacom_ts/ts.c new file mode 100644 index 0000000..ebc8883 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/ts.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen_dsm.h> +#include <device/device.h> +#include <stdint.h> +#include "chip.h" + +static void i2c_wacom_ts_fill_dsm(struct device *dev) +{ + struct drivers_i2c_wacom_ts_config *config = dev->chip_info; + struct dsm_i2c_hid_config dsm_config = { + .hid_desc_reg_offset = config->hid_desc_reg_offset, + }; + + acpigen_write_dsm_i2c_hid(&dsm_config); +} + +static void i2c_wacom_ts_fill_ssdt_generator(struct device *dev) +{ + i2c_generic_fill_ssdt(dev, &i2c_wacom_ts_fill_dsm); +} + +static const char *i2c_wacom_ts_acpi_name(struct device *dev) +{ + return "WCTS"; +} + +static struct device_operations i2c_wacom_ts_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &i2c_wacom_ts_acpi_name, + .acpi_fill_ssdt_generator = &i2c_wacom_ts_fill_ssdt_generator, +#endif +}; + +static void i2c_wacom_ts_enable(struct device *dev) +{ + dev->ops = &i2c_wacom_ts_ops; +} + +struct chip_operations drivers_i2c_wacom_ts_ops = { + CHIP_NAME("Wacom Touchscreen Device") + .enable_dev = &i2c_wacom_ts_enable +};

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Patch set updated for coreboot: google/reef/variants/pyro: Use WCOM Touchscreen driver
by Furquan Shaikh 25 Oct '16

25 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17093 -gerrit commit 9a1ae27f0b61d0ad1782815b058e84c290f22c76 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:45:59 2016 -0700 google/reef/variants/pyro: Use WCOM Touchscreen driver BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 3 +++ src/mainboard/google/reef/variants/pyro/devicetree.cb | 14 +++++++++----- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d5d64c8..6045f47 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -40,6 +40,9 @@ config DRIVERS_I2C_DA7219 config DRIVERS_I2C_GENERIC default y +config DRIVERS_I2C_WACOM_TS + default y + config DRIVERS_PS2_KEYBOARD default y diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 43ec2ed..8540d04 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -131,11 +131,15 @@ chip soc/intel/apollolake end end # - I2C 2 device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + chip drivers/i2c/wacom_ts + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_TS_DESC, + .irq = IRQ_EDGE_LOW(GPIO_21_IRQ), + .probed = 1, + }" + register "hid_desc_reg_offset" = "0x1" device i2c 10 on end end end # - I2C 3

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Patch merged into coreboot/master: arch/x86/acpigen: Add more functions to ACPIGEN library
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 9b39adb4545bbfdddda333d23400599b7c061126 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:21:07 2016 -0700 arch/x86/acpigen: Add more functions to ACPIGEN library 1. If (LEqual (Op1, Op2)) 2. ToBuffer (src, dst) 3. ToInteger (src, dst) 4. Buffer (n) { op1, op2 .... } 5. Return ( ) BUG=chrome-os-partner:57846 Change-Id: I24fe647c690b2dd4849f0c53b2672ac7a2caa2de Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17088 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> See https://review.coreboot.org/17088 for details. -gerrit

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Patch merged into coreboot/master: mainboard/google/reef: Add PowerResource for ELAN touchscreen
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 3ce104e5d867e96c9a2a21103d26de5826af6b12 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:48:45 2016 -0700 mainboard/google/reef: Add PowerResource for ELAN touchscreen Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:55988 Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17083 for details. -gerrit

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Patch merged into coreboot/master: soc/intel/apollolake: Implement GPIO ACPI AML generating functions
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 00a9e38f748c839c3a8edf7f2e242c64180456d4 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:45:26 2016 -0700 soc/intel/apollolake: Implement GPIO ACPI AML generating functions Implement GPIO ACPI AML generating functions that can be called by coreboot drivers to generate GPIO manipulation code in AML. Following functions are implemented: 1. acpigen_soc_read_rx_gpio 2. acpigen_soc_get_tx_gpio 3. acpigen_soc_set_tx_gpio 4. acpigen_soc_clear_tx_gpio BUG=chrome-os-partner:55988 Change-Id: I3d8695d73a1c43555032de90f14ee47ccee45559 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17082 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> See https://review.coreboot.org/17082 for details. -gerrit

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Patch merged into coreboot/master: drivers/i2c/generic: Enable support for adding PowerResource for device
by gerrit＠coreboot.org 25 Oct '16

25 Oct '16

the following patch was just integrated into master: commit 626ad205a7781eb13b3d9156d7c01f4aacfcbad5 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 16:01:04 2016 -0700 drivers/i2c/generic: Enable support for adding PowerResource for device Add support to allow a device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: 1. Reset GPIO - Optional, GPIO to put device into reset or take it out of reset. 2. Reset delay - Delay after reset GPIO is de-asserted (default 0). 3. Enable GPIO - Optional, GPIO to enabled device. 4. Enable delay - Delay after enable GPIO is asserted (default 0). BUG=chrome-os-partner:55988 Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/17081 Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Tested-by: build bot (Jenkins) See https://review.coreboot.org/17081 for details. -gerrit

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Patch set updated for coreboot: google/reef/variants/pyro: Use WCOM Touchscreen driver
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17093 -gerrit commit 86ac2ffaa196095e1e2c0b8b04a5b27e5b8e90ef Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:45:59 2016 -0700 google/reef/variants/pyro: Use WCOM Touchscreen driver BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 3 +++ src/mainboard/google/reef/variants/pyro/devicetree.cb | 14 +++++++++----- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d5d64c8..6045f47 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -40,6 +40,9 @@ config DRIVERS_I2C_DA7219 config DRIVERS_I2C_GENERIC default y +config DRIVERS_I2C_WACOM_TS + default y + config DRIVERS_PS2_KEYBOARD default y diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 43ec2ed..8540d04 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -131,11 +131,15 @@ chip soc/intel/apollolake end end # - I2C 2 device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + chip drivers/i2c/wacom_ts + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_TS_DESC, + .irq = IRQ_EDGE_LOW(GPIO_21_IRQ), + .probed = 1, + }" + register "hid_desc_reg_offset" = "0x1" device i2c 10 on end end end # - I2C 3

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New patch to review for coreboot: payload choice: Fix build of FILO
by Kyösti Mälkki 24 Oct '16

24 Oct '16

Kyösti Mälkki (kyosti.malkki(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17114 -gerrit commit 7cae2cc72be008b8b53f4212faa338c8e6340f6e Author: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Date: Tue Oct 25 00:13:37 2016 +0300 payload choice: Fix build of FILO Actual build was missing libpayload path. Change-Id: I519869d2d64c66b3d1d557595c7d13c22cd40819 Signed-off-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com> --- payloads/external/FILO/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/external/FILO/Makefile b/payloads/external/FILO/Makefile index 13d3e8f..c5791bf 100644 --- a/payloads/external/FILO/Makefile +++ b/payloads/external/FILO/Makefile @@ -37,7 +37,7 @@ config: libpayload filo: config echo " MAKE FILO $(NAME-y)" - $(MAKE) -C filo + $(MAKE) -C filo LIBCONFIG_PATH=../../../libpayload libpayload: checkout cd ../../libpayload && $(MAKE) defconfig && \

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Patch set updated for coreboot: nb/x4x/gma.c: Remove writes to DP, FDI registers
by Arthur Heymans 24 Oct '16

24 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17111 -gerrit commit 5061e6fd5be9eb6b08884be1914b12a0463310ad Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 24 17:49:35 2016 +0200 nb/x4x/gma.c: Remove writes to DP, FDI registers Those registers are only used on more recent Intel platforms featuring a PCH. The DP registers on G4X hardware are at a different offset. Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 749a7c8..62e28aa 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -74,12 +74,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00040000; - vga_gr_write(0x18, 0); @@ -210,10 +204,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_DEBUG, "Borders %d x %d\n", @@ -228,12 +218,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", @@ -305,13 +289,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE

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Patch set updated for coreboot: nb/gm45/gma.c: Remove writes to DP, FDI registers
by Arthur Heymans 24 Oct '16

24 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17110 -gerrit commit 1a055ae37a9d53338329bf614d1adeb81d055c3b Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 24 17:44:20 2016 +0200 nb/gm45/gma.c: Remove writes to DP, FDI registers Those registers are only used on more recent Intel platforms featuring a PCH. The DP registers on G4X hardware are at a different offset. Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/t400/devicetree.cb | 1 - src/mainboard/lenovo/x200/devicetree.cb | 1 - src/northbridge/intel/gm45/gma.c | 45 --------------------------------- 3 files changed, 47 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 6bf25fa..9940bb7 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -4,7 +4,6 @@ chip northbridge/intel/gm45 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index d9cb783..b5d2496 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -9,7 +9,6 @@ chip northbridge/intel/gm45 register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8596193..8938197 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -68,11 +68,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, u32 pixel_m1 = 1; u32 pixel_m2 = 1; u32 pixel_p2; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00080000; vga_gr_write(0x18, 0); @@ -190,10 +185,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_DEBUG, "Borders %d x %d\n", @@ -210,12 +201,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", @@ -299,13 +284,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); @@ -361,12 +339,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00040000; - vga_gr_write(0x18, 0); @@ -491,10 +463,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "Bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_SPEW, "Borders %d x %d\n", @@ -509,12 +477,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_SPEW, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_SPEW, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_SPEW, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_SPEW, "Link M1=%d, N1=%d\n", - link_m1, link_n1); printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_SPEW, "Pixel clock %d kHz\n", @@ -586,13 +548,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE

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coreboot-gerrit October 2016