coreboot-gerrit October 2016

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Patch set updated for coreboot: nb/x4x/gma.c: remove writes to FDI and embedded DP registers
by Arthur Heymans 24 Oct '16

24 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17111 -gerrit commit 2c1a6dff34b9fc12c5ce2bd49c648bccecb81aff Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 24 17:49:35 2016 +0200 nb/x4x/gma.c: remove writes to FDI and embedded DP registers Those registers are only used on more recent Intel platforms featuring a PCH. Change-Id: I4660e547426ccec0b2095d897e4a8c86e0acf41e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/x4x/gma.c | 23 ----------------------- 1 file changed, 23 deletions(-) diff --git a/src/northbridge/intel/x4x/gma.c b/src/northbridge/intel/x4x/gma.c index 749a7c8..62e28aa 100644 --- a/src/northbridge/intel/x4x/gma.c +++ b/src/northbridge/intel/x4x/gma.c @@ -74,12 +74,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00040000; - vga_gr_write(0x18, 0); @@ -210,10 +204,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_DEBUG, "Borders %d x %d\n", @@ -228,12 +218,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", @@ -305,13 +289,6 @@ static void intel_gma_init(const struct northbridge_intel_x4x_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE

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Patch set updated for coreboot: nb/gm45/gma.c: remove writes to FDI and embedded DP registers
by Arthur Heymans 24 Oct '16

24 Oct '16

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17110 -gerrit commit 1d99606974148a8b9727cd4d0415e762761206ed Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Oct 24 17:44:20 2016 +0200 nb/gm45/gma.c: remove writes to FDI and embedded DP registers Those registers are only used on more recent Intel platforms featuring a PCH. Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/lenovo/t400/devicetree.cb | 1 - src/mainboard/lenovo/x200/devicetree.cb | 1 - src/northbridge/intel/gm45/gma.c | 45 --------------------------------- 3 files changed, 47 deletions(-) diff --git a/src/mainboard/lenovo/t400/devicetree.cb b/src/mainboard/lenovo/t400/devicetree.cb index 6bf25fa..9940bb7 100644 --- a/src/mainboard/lenovo/t400/devicetree.cb +++ b/src/mainboard/lenovo/t400/devicetree.cb @@ -4,7 +4,6 @@ chip northbridge/intel/gm45 register "gfx.did" = "{ 0x80000100, 0x80000240, 0x80000410, 0x80000410, 0x00000005 }" register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/mainboard/lenovo/x200/devicetree.cb b/src/mainboard/lenovo/x200/devicetree.cb index d9cb783..b5d2496 100644 --- a/src/mainboard/lenovo/x200/devicetree.cb +++ b/src/mainboard/lenovo/x200/devicetree.cb @@ -9,7 +9,6 @@ chip northbridge/intel/gm45 register "gpu_panel_power_backlight_off_delay" = "2500" # Tx: 250ms register "gpu_panel_power_cycle_delay" = "3" # T4: 200ms register "gfx.use_spread_spectrum_clock" = "1" - register "gfx.link_frequency_270_mhz" = "1" device cpu_cluster 0 on chip cpu/intel/socket_BGA956 diff --git a/src/northbridge/intel/gm45/gma.c b/src/northbridge/intel/gm45/gma.c index 8596193..8938197 100644 --- a/src/northbridge/intel/gm45/gma.c +++ b/src/northbridge/intel/gm45/gma.c @@ -68,11 +68,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, u32 pixel_m1 = 1; u32 pixel_m2 = 1; u32 pixel_p2; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00080000; vga_gr_write(0x18, 0); @@ -190,10 +185,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_DEBUG, "Borders %d x %d\n", @@ -210,12 +201,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, mode->lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); printk(BIOS_DEBUG, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_DEBUG, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_DEBUG, "Link M1=%d, N1=%d\n", - link_m1, link_n1); printk(BIOS_DEBUG, "Pixel N=%d, M1=%d, M2=%d, P1=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1); printk(BIOS_DEBUG, "Pixel clock %d kHz\n", @@ -299,13 +284,6 @@ static void gma_init_lvds(const struct northbridge_intel_gm45_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE | PIPECONF_BPP_6 | PIPECONF_DITHER_EN); @@ -361,12 +339,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, u32 pixel_n = 1; u32 pixel_m1 = 1; u32 pixel_m2 = 1; - u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000; - u32 data_m1; - u32 data_n1 = 0x00800000; - u32 link_m1; - u32 link_n1 = 0x00040000; - vga_gr_write(0x18, 0); @@ -491,10 +463,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, return; } - link_m1 = ((uint64_t)link_n1 * mode->pixel_clock) / link_frequency; - data_m1 = ((uint64_t)data_n1 * 18 * mode->pixel_clock) - / (link_frequency * 8 * 4); - printk(BIOS_INFO, "Bringing up panel at resolution %d x %d\n", hactive, vactive); printk(BIOS_SPEW, "Borders %d x %d\n", @@ -509,12 +477,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, ? "Spread spectrum clock\n" : "DREF clock\n")); printk(BIOS_SPEW, "Polarities %d, %d\n", hpolarity, vpolarity); - printk(BIOS_SPEW, "Data M1=%d, N1=%d\n", - data_m1, data_n1); - printk(BIOS_SPEW, "Link frequency %d kHz\n", - link_frequency); - printk(BIOS_SPEW, "Link M1=%d, N1=%d\n", - link_m1, link_n1); printk(BIOS_SPEW, "Pixel N=%d, M1=%d, M2=%d, P1=%d, P2=%d\n", pixel_n, pixel_m1, pixel_m2, pixel_p1, pixel_p2); printk(BIOS_SPEW, "Pixel clock %d kHz\n", @@ -586,13 +548,6 @@ static void gma_init_vga(const struct northbridge_intel_gm45_config *info, } mdelay(1); - - write32(mmio + PIPE_DATA_M1(0), 0x7e000000 | data_m1); - write32(mmio + PIPE_DATA_N1(0), data_n1); - write32(mmio + PIPE_LINK_M1(0), link_m1); - write32(mmio + PIPE_LINK_N1(0), link_n1); - - mdelay(1); write32(mmio + PIPECONF(0), PIPECONF_BPP_6); write32(mmio + PIPECONF(0), PIPECONF_BPP_6 | PIPECONF_DITHER_EN); write32(mmio + PIPECONF(0), PIPECONF_ENABLE

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Patch set updated for coreboot: arch/x86/acpigen: Add support for _DSM method generation
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17090 -gerrit commit 683c5891a90e0fa11fb779f5ad1c4486b0d94605 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:37:41 2016 -0700 arch/x86/acpigen: Add support for _DSM method generation Add acpigen_write_dsm that generates ACPI AML code for _DSM method. Caller should provide set of callbacks with callback[i] corresponding to function index i of DSM method. Local0 and Local1 should not be used in any of the callbacks. BUG=chrome-os-partner:57846 Change-Id: Ie18cba080424488fe00cc626ea50aa92c1dbb199 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 86 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 8 ++++ 2 files changed, 94 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 35735b5..42d4204 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -1046,6 +1046,92 @@ void acpigen_write_return_byte(uint8_t arg) acpigen_write_byte(arg); } +/* + * Generate ACPI AML code for _DSM method. + * This function takes as input uuid for the device, set of callbacks and + * argument to pass into the callbacks. Callbacks should ensure that Local0 and + * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. + * + * Arguments passed into _DSM method: + * Arg0 = UUID + * Arg1 = Revision + * Arg2 = Function index + * Arg3 = Function specific arguments + * + * AML code generated would look like: + * Method (_DSM, 4, Serialized) { + * ToBuffer (Arg0, Local0) + * If (LEqual (Local0, ToUUID(uuid))) { + * ToInteger (Arg2, Local1) + * If (LEqual (Local1, 0)) { + * <acpigen by callback[0]> + * } Else { + * ... + * If (LEqual (Local1, n)) { + * <acpigen by callback[n]> + * } Else { + * Return (Buffer (One) { 0x0 }) + * } + * } + * } Else { + * Return (Buffer (One) { 0x0 }) + * } + * } + */ +void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), + size_t count, void *arg) +{ + size_t i; + + /* Method (_DSM, 4, Serialized) */ + acpigen_write_method_serialized("_DSM", 0x4); + + /* ToBuffer (Arg0, Local0) */ + acpigen_write_to_buffer(ARG0_OP, LOCAL0_OP); + + /* If (LEqual (Local0, ToUUID(uuid))) */ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(LOCAL0_OP); + acpigen_write_uuid(uuid); + + /* ToInteger (Arg2, Local1) */ + acpigen_write_to_integer(ARG2_OP, LOCAL1_OP); + acpigen_write_debug_op(LOCAL1_OP); + + for (i = 0; i < count; i++) { + /* If (Lequal (Local1, i)) */ + acpigen_write_if_lequal(LOCAL1_OP, i); + + /* Callback to write if handler. */ + if (callbacks[i]) + callbacks[i](arg); + + acpigen_pop_len(); /* If */ + + /* Else */ + acpigen_write_else(); + } + + /* Default case: Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + /* Pop lengths for all the else clauses. */ + for (i = 0; i < count; i++) + acpigen_pop_len(); + + acpigen_pop_len(); /* If (LEqual (Local0, ToUUID(uuid))) */ + + /* Else */ + acpigen_write_else(); + + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + + acpigen_pop_len(); /* Else */ + acpigen_pop_len(); /* Method _DSM */ +} + /* Soc-implemented functions -- weak definitions. */ int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned int gpio_num) { diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index dd83db8..7c15a31 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -167,6 +167,14 @@ void acpigen_write_byte_buffer(uint8_t *arr, uint8_t size); void acpigen_write_return_byte_buffer(uint8_t *arr, uint8_t size); void acpigen_write_return_singleton_buffer(uint8_t arg); void acpigen_write_return_byte(uint8_t arg); +/* + * Generate ACPI AML code for _DSM method. + * This function takes as input uuid for the device, set of callbacks and + * argument to pass into the callbacks. Callbacks should ensure that Local0 and + * Local1 are left untouched. Use of Local2-Local7 is permitted in callbacks. + */ +void acpigen_write_dsm(const char *uuid, void (*callbacks[])(void *), + size_t count, void *arg); int get_cst_entries(acpi_cstate_t **);

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Patch set updated for coreboot: arch/x86/acpigen_dsm: Add support for DSM types
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17091 -gerrit commit e730a9791352326ef8c14ce9b55c1f6b2662930e Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:40:17 2016 -0700 arch/x86/acpigen_dsm: Add support for DSM types Currently, the only supported DSM type is I2C HID(3CDFF6F7-4267-4555-AD05-B30A3D8938DE). This provides the required callbacks for generating ACPI AML codes for different function identifiers for I2C HID. BUG=chrome-os-partner:57846 Change-Id: Ia403e11f7ce4824956e3c879547ec927478db7b1 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/Makefile.inc | 1 + src/arch/x86/acpigen_dsm.c | 65 +++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen_dsm.h | 27 ++++++++++++++ 3 files changed, 93 insertions(+) diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc index 782ca63..c4bb1cc 100644 --- a/src/arch/x86/Makefile.inc +++ b/src/arch/x86/Makefile.inc @@ -313,6 +313,7 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_X86_32)$(CONFIG_ARCH_RAMSTAGE_X86_64),y) ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpigen_dsm.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi_device.c ramstage-$(CONFIG_HAVE_ACPI_RESUME) += acpi_s3.c ramstage-y += boot.c diff --git a/src/arch/x86/acpigen_dsm.c b/src/arch/x86/acpigen_dsm.c new file mode 100644 index 0000000..c6d614a --- /dev/null +++ b/src/arch/x86/acpigen_dsm.c @@ -0,0 +1,65 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen.h> +#include <arch/acpigen_dsm.h> +#include <stdlib.h> + +/* ------------------- I2C HID DSM ---------------------------- */ + +#define ACPI_DSM_I2C_HID_UUID "3CDFF6F7-4267-4555-AD05-B30A3D8938DE" + +static void i2c_hid_func0_cb(void *arg) +{ + /* ToInteger (Arg1, Local2) */ + acpigen_write_to_integer(ARG1_OP, LOCAL2_OP); + /* If (LEqual (Local2, 0x0)) */ + acpigen_write_if_lequal(LOCAL2_OP, 0x0); + /* Return (Buffer (One) { 0x1f }) */ + acpigen_write_return_singleton_buffer(0x1f); + acpigen_pop_len(); /* Pop : If */ + /* Else */ + acpigen_write_else(); + /* If (LEqual (Local2, 0x1)) */ + acpigen_write_if_lequal(LOCAL2_OP, 0x1); + /* Return (Buffer (One) { 0x3f }) */ + acpigen_write_return_singleton_buffer(0x3f); + acpigen_pop_len(); /* Pop : If */ + /* Else */ + acpigen_write_else(); + /* Return (Buffer (One) { 0x0 }) */ + acpigen_write_return_singleton_buffer(0x0); + acpigen_pop_len(); /* Pop : Else */ + acpigen_pop_len(); /* Pop : Else */ +} + +static void i2c_hid_func1_cb(void *arg) +{ + struct dsm_i2c_hid_config *config = arg; + acpigen_write_return_byte(config->hid_desc_reg_offset); +} + +static void (*i2c_hid_callbacks[2])(void *) = { + i2c_hid_func0_cb, + i2c_hid_func1_cb, +}; + +void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config) +{ + acpigen_write_dsm(ACPI_DSM_I2C_HID_UUID, i2c_hid_callbacks, + ARRAY_SIZE(i2c_hid_callbacks), config); +} + +/* ------------------- End: I2C HID DSM ------------------------- */ diff --git a/src/arch/x86/include/arch/acpigen_dsm.h b/src/arch/x86/include/arch/acpigen_dsm.h new file mode 100644 index 0000000..2d8bb48 --- /dev/null +++ b/src/arch/x86/include/arch/acpigen_dsm.h @@ -0,0 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __ARCH_ACPIGEN_DSM_H__ +#define __ARCH_ACPIGEN_DSM_H__ + +#include <stdint.h> + +struct dsm_i2c_hid_config { + uint8_t hid_desc_reg_offset; +}; + +void acpigen_write_dsm_i2c_hid(struct dsm_i2c_hid_config *config); + +#endif /* __ARCH_ACPIGEN_DSM_H__ */

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Patch set updated for coreboot: arch/x86/acpigen: Add more functions to ACPIGEN library
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17088 -gerrit commit 9d0cab3986691a7ed17bb7dc20be0f8cbfa89772 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:21:07 2016 -0700 arch/x86/acpigen: Add more functions to ACPIGEN library 1. If (LEqual (Op1, Op2)) 2. ToBuffer (src, dst) 3. ToInteger (src, dst) 4. Buffer (n) { op1, op2 .... } 5. Return ( ) BUG=chrome-os-partner:57846 Change-Id: I24fe647c690b2dd4849f0c53b2672ac7a2caa2de Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/arch/x86/acpigen.c | 53 +++++++++++++++++++++++++++++++++++++ src/arch/x86/include/arch/acpigen.h | 10 +++++++ 2 files changed, 63 insertions(+) diff --git a/src/arch/x86/acpigen.c b/src/arch/x86/acpigen.c index 0a57263..35735b5 100644 --- a/src/arch/x86/acpigen.c +++ b/src/arch/x86/acpigen.c @@ -987,12 +987,65 @@ void acpigen_write_if_and(uint8_t arg1, uint8_t arg2) acpigen_emit_byte(arg2); } +void acpigen_write_if_lequal(uint8_t arg1, uint8_t arg2) +{ + acpigen_write_if(); + acpigen_emit_byte(LEQUAL_OP); + acpigen_emit_byte(arg1); + acpigen_emit_byte(arg2); +} + void acpigen_write_else(void) { acpigen_emit_byte(ELSE_OP); acpigen_write_len_f(); } +void acpigen_write_to_buffer(uint8_t src, uint8_t dst) +{ + acpigen_emit_byte(TO_BUFFER_OP); + acpigen_emit_byte(src); + acpigen_emit_byte(dst); +} + +void acpigen_write_to_integer(uint8_t src, uint8_t dst) +{ + acpigen_emit_byte(TO_INTEGER_OP); + acpigen_emit_byte(src); + acpigen_emit_byte(dst); +} + +void acpigen_write_byte_buffer(uint8_t *arr, uint8_t size) +{ + uint8_t i; + + acpigen_emit_byte(BUFFER_OP); + acpigen_write_len_f(); + acpigen_emit_byte(size); + + for (i = 0; i < size; i++) + acpigen_emit_byte(arr[i]); + + acpigen_pop_len(); +} + +void acpigen_write_return_byte_buffer(uint8_t *arr, uint8_t size) +{ + acpigen_emit_byte(RETURN_OP); + acpigen_write_byte_buffer(arr, size); +} + +void acpigen_write_return_singleton_buffer(uint8_t arg) +{ + acpigen_write_return_byte_buffer(&arg, 1); +} + +void acpigen_write_return_byte(uint8_t arg) +{ + acpigen_emit_byte(RETURN_OP); + acpigen_write_byte(arg); +} + /* Soc-implemented functions -- weak definitions. */ int __attribute__((weak)) acpigen_soc_read_rx_gpio(unsigned int gpio_num) { diff --git a/src/arch/x86/include/arch/acpigen.h b/src/arch/x86/include/arch/acpigen.h index 0c515da..dd83db8 100644 --- a/src/arch/x86/include/arch/acpigen.h +++ b/src/arch/x86/include/arch/acpigen.h @@ -75,6 +75,9 @@ enum { AND_OP = 0x7B, OR_OP = 0x7D, NOT_OP = 0x80, + LEQUAL_OP = 0x93, + TO_BUFFER_OP = 0x96, + TO_INTEGER_OP = 0x99, IF_OP = 0xA0, ELSE_OP = 0xA1, RETURN_OP = 0xA4, @@ -156,7 +159,14 @@ void acpigen_write_debug_integer(uint64_t val); void acpigen_write_debug_op(uint8_t op); void acpigen_write_if(void); void acpigen_write_if_and(uint8_t arg1, uint8_t arg2); +void acpigen_write_if_lequal(uint8_t arg1, uint8_t arg2); void acpigen_write_else(void); +void acpigen_write_to_buffer(uint8_t src, uint8_t dst); +void acpigen_write_to_integer(uint8_t src, uint8_t dst); +void acpigen_write_byte_buffer(uint8_t *arr, uint8_t size); +void acpigen_write_return_byte_buffer(uint8_t *arr, uint8_t size); +void acpigen_write_return_singleton_buffer(uint8_t arg); +void acpigen_write_return_byte(uint8_t arg); int get_cst_entries(acpi_cstate_t **);

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Patch set updated for coreboot: drivers/i2c/generic: Re-factor SSDT generation code
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17089 -gerrit commit cf3189511eefd1579066ed28d3fb68d7184d03b2 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:24:07 2016 -0700 drivers/i2c/generic: Re-factor SSDT generation code 1. Export i2c_generic_fill_ssdt to allow other device-specific i2c drivers to share and re-use the same code for generating AML code for SSDT. In order to achieve this, following changes are required: a. Add macro I2C_GENERIC_CONFIG that defines a structure with all generic i2c device-tree properties. This macro should be placed by the using driver at the start of its config structure. b. Accept a callback function to add any device specific information to SSDT. If generic driver is used directly by a device, callback would be NULL. Other devices using a separate i2c driver can provide a callback to add any properties to SSDT. 2. Allow device to provide _CID. BUG=chrome-os-partner:57846 Change-Id: I3a0054e22b81f9d6d407bef417eae5e9edc04ee4 Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 33 +++++++++++++++++++++++++++++++++ src/drivers/i2c/generic/generic.c | 16 ++++++++++++++-- 2 files changed, 47 insertions(+), 2 deletions(-) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index e84fc38..736de51 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -1,8 +1,27 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_GENERIC_CHIP_H__ +#define __I2C_GENERIC_CHIP_H__ + #include <arch/acpi_device.h> #include <device/i2c.h> struct drivers_i2c_generic_config { const char *hid; /* ACPI _HID (required) */ + const char *cid; /* ACPI _CID */ const char *name; /* ACPI Device Name */ const char *desc; /* Device Description */ unsigned uid; /* ACPI _UID */ @@ -32,3 +51,17 @@ struct drivers_i2c_generic_config { /* Delay to be inserted after device is enabled. */ unsigned enable_delay_ms; }; + +/* + * Fills in generic information about i2c device from device-tree + * properties. Callback can be provided to fill in any + * device-specific information in SSDT. + * + * Drivers calling into this function to generate should place + * drivers_i2c_generic_config structure at the beginning of their device config + * structure. + */ +void i2c_generic_fill_ssdt(struct device *dev, + void (*callback)(struct device *dev)); + +#endif /* __I2C_GENERIC_CHIP_H__ */ diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index 34fbf77..b8e5d86 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -65,7 +65,8 @@ static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) acpigen_pop_len(); /* PowerResource PRIC */ } -static void i2c_generic_fill_ssdt(struct device *dev) +void i2c_generic_fill_ssdt(struct device *dev, + void (*callback)(struct device *dev)) { struct drivers_i2c_generic_config *config = dev->chip_info; const char *scope = acpi_device_scope(dev); @@ -89,6 +90,8 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpigen_write_scope(scope); acpigen_write_device(acpi_device_name(dev)); acpigen_write_name_string("_HID", config->hid); + if (config->cid) + acpigen_write_name_string("_CID", config->cid); acpigen_write_name_integer("_UID", config->uid); acpigen_write_name_string("_DDN", config->desc); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); @@ -115,6 +118,10 @@ static void i2c_generic_fill_ssdt(struct device *dev) /* Power Resource */ i2c_generic_add_power_res(config); + /* Callback if any. */ + if (callback) + callback(dev); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ @@ -122,6 +129,11 @@ static void i2c_generic_fill_ssdt(struct device *dev) config->desc ? : dev->chip_ops->name, dev_path(dev)); } +static void i2c_generic_fill_ssdt_generator(struct device *dev) +{ + i2c_generic_fill_ssdt(dev, NULL); +} + /* Use name specified in config or build one from I2C address */ static const char *i2c_generic_acpi_name(struct device *dev) { @@ -143,7 +155,7 @@ static struct device_operations i2c_generic_ops = { .enable_resources = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_name = &i2c_generic_acpi_name, - .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt, + .acpi_fill_ssdt_generator = &i2c_generic_fill_ssdt_generator, #endif };

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Patch set updated for coreboot: drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17092 -gerrit commit 4986dd59e4d193153ebc59dd292f9a4dfbe71b27 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:42:45 2016 -0700 drivers/i2c/wacom_ts: Add support for WCOM touchscreen device driver BUG=chrome-os-partner:57846 Change-Id: Id6bd91b3fd6420994ad5811d362618b1a38a8afa Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/wacom_ts/Kconfig | 3 ++ src/drivers/i2c/wacom_ts/Makefile.inc | 1 + src/drivers/i2c/wacom_ts/chip.h | 30 ++++++++++++++++++ src/drivers/i2c/wacom_ts/ts.c | 59 +++++++++++++++++++++++++++++++++++ 4 files changed, 93 insertions(+) diff --git a/src/drivers/i2c/wacom_ts/Kconfig b/src/drivers/i2c/wacom_ts/Kconfig new file mode 100644 index 0000000..50da3f1 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Kconfig @@ -0,0 +1,3 @@ +config DRIVERS_I2C_WACOM_TS + bool + select DRIVERS_I2C_GENERIC diff --git a/src/drivers/i2c/wacom_ts/Makefile.inc b/src/drivers/i2c/wacom_ts/Makefile.inc new file mode 100644 index 0000000..9455099 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_WACOM_TS) += ts.c diff --git a/src/drivers/i2c/wacom_ts/chip.h b/src/drivers/i2c/wacom_ts/chip.h new file mode 100644 index 0000000..b59f630 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __I2C_WACOM_TS_CHIP_H__ +#define __I2C_WACOM_TS_CHIP_H__ + +#include <drivers/i2c/generic/chip.h> + +#define WCOM50C1_HID "WCOM50C1" +#define PNP0C50_CID "PNP0C50" +#define WCOM_TS_DESC "WCOM Touchscreen" + +struct drivers_i2c_wacom_ts_config { + struct drivers_i2c_generic_config generic; + uint8_t hid_desc_reg_offset; +}; + +#endif /* __I2C_WACOM_TS_CHIP_H__ */ diff --git a/src/drivers/i2c/wacom_ts/ts.c b/src/drivers/i2c/wacom_ts/ts.c new file mode 100644 index 0000000..ebc8883 --- /dev/null +++ b/src/drivers/i2c/wacom_ts/ts.c @@ -0,0 +1,59 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpigen_dsm.h> +#include <device/device.h> +#include <stdint.h> +#include "chip.h" + +static void i2c_wacom_ts_fill_dsm(struct device *dev) +{ + struct drivers_i2c_wacom_ts_config *config = dev->chip_info; + struct dsm_i2c_hid_config dsm_config = { + .hid_desc_reg_offset = config->hid_desc_reg_offset, + }; + + acpigen_write_dsm_i2c_hid(&dsm_config); +} + +static void i2c_wacom_ts_fill_ssdt_generator(struct device *dev) +{ + i2c_generic_fill_ssdt(dev, &i2c_wacom_ts_fill_dsm); +} + +static const char *i2c_wacom_ts_acpi_name(struct device *dev) +{ + return "WCTS"; +} + +static struct device_operations i2c_wacom_ts_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &i2c_wacom_ts_acpi_name, + .acpi_fill_ssdt_generator = &i2c_wacom_ts_fill_ssdt_generator, +#endif +}; + +static void i2c_wacom_ts_enable(struct device *dev) +{ + dev->ops = &i2c_wacom_ts_ops; +} + +struct chip_operations drivers_i2c_wacom_ts_ops = { + CHIP_NAME("Wacom Touchscreen Device") + .enable_dev = &i2c_wacom_ts_enable +};

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Patch set updated for coreboot: google/reef/variants/pyro: Use WCOM Touchscreen driver
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17093 -gerrit commit 0be0a57ea9962a9e55d3564c70084d40af2a8374 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Fri Oct 21 16:45:59 2016 -0700 google/reef/variants/pyro: Use WCOM Touchscreen driver BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/Kconfig | 2 ++ src/mainboard/google/reef/variants/pyro/Kconfig | 7 +++++++ src/mainboard/google/reef/variants/pyro/devicetree.cb | 13 ++++++++----- 3 files changed, 17 insertions(+), 5 deletions(-) diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig index d5d64c8..b549e21 100644 --- a/src/mainboard/google/reef/Kconfig +++ b/src/mainboard/google/reef/Kconfig @@ -15,6 +15,8 @@ config BOARD_GOOGLE_BASEBOARD_REEF if BOARD_GOOGLE_BASEBOARD_REEF +source src/mainboard/google/reef/variants/pyro/Kconfig + config BASEBOARD_REEF_LAPTOP def_bool n select SYSTEM_TYPE_LAPTOP diff --git a/src/mainboard/google/reef/variants/pyro/Kconfig b/src/mainboard/google/reef/variants/pyro/Kconfig new file mode 100644 index 0000000..c032580 --- /dev/null +++ b/src/mainboard/google/reef/variants/pyro/Kconfig @@ -0,0 +1,7 @@ + +if BOARD_GOOGLE_PYRO + +config DRIVERS_I2C_WACOM_TS + default y + +endif # BOARD_GOOGLE_PYRO diff --git a/src/mainboard/google/reef/variants/pyro/devicetree.cb b/src/mainboard/google/reef/variants/pyro/devicetree.cb index 43ec2ed..62183cc 100644 --- a/src/mainboard/google/reef/variants/pyro/devicetree.cb +++ b/src/mainboard/google/reef/variants/pyro/devicetree.cb @@ -131,11 +131,14 @@ chip soc/intel/apollolake end end # - I2C 2 device pci 16.3 on - chip drivers/i2c/generic - register "hid" = ""ELAN0001"" - register "desc" = ""ELAN Touchscreen"" - register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" - register "probed" = "1" + chip drivers/i2c/wacom_ts + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_TS_DESC, + .irq = IRQ_EDGE_LOW(GPIO_21_IRQ), + }" + register "hid_desc_reg_offset" = "0x1" device i2c 10 on end end end # - I2C 3

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Patch set updated for coreboot: drivers/i2c/generic: Enable support for adding PowerResource for device
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17081 -gerrit commit eec9ca8d12509d76c1705f9f3e60648395d10e42 Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 16:01:04 2016 -0700 drivers/i2c/generic: Enable support for adding PowerResource for device Add support to allow a device to define PowerResource in its SSDT AML code. PowerResouce ACPI generation expects SoC to define the callbacks for generating AML code for GPIO manipulation. Device requiring PowerResource needs to define following parameters: 1. Reset GPIO - Optional, GPIO to put device into reset or take it out of reset. 2. Reset delay - Delay after reset GPIO is de-asserted (default 0). 3. Enable GPIO - Optional, GPIO to enabled device. 4. Enable delay - Delay after enable GPIO is asserted (default 0). BUG=chrome-os-partner:55988 Change-Id: Ieb2dd95fc1f555f5de66f3dda425172ac5b75dad Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/drivers/i2c/generic/chip.h | 9 ++++++++ src/drivers/i2c/generic/generic.c | 43 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 52 insertions(+) diff --git a/src/drivers/i2c/generic/chip.h b/src/drivers/i2c/generic/chip.h index d84097f..e84fc38 100644 --- a/src/drivers/i2c/generic/chip.h +++ b/src/drivers/i2c/generic/chip.h @@ -22,4 +22,13 @@ struct drivers_i2c_generic_config { /* GPIO used to indicate if this device is present */ unsigned device_present_gpio; unsigned device_present_gpio_invert; + + /* GPIO used to take device out of reset or to put it into reset. */ + unsigned reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned reset_delay_ms; + /* GPIO used to enable device. */ + unsigned enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned enable_delay_ms; }; diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index c11a889..34fbf77 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -25,6 +25,46 @@ #include "chip.h" #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +static void i2c_generic_add_power_res(struct drivers_i2c_generic_config *config) +{ + const char *power_res_dev_states[] = { "_PR0", "_PR3" }; + + if (!config->reset_gpio && !config->enable_gpio) + return; + + /* PowerResource (PRIC, 0, 0) */ + acpigen_write_power_res("PRIC", 0, 0, power_res_dev_states, + ARRAY_SIZE(power_res_dev_states)); + + /* Method (_STA, 0, NotSerialized) { Return (0x1) } */ + acpigen_write_STA(0x1); + + /* Method (_ON, 0, Serialized) */ + acpigen_write_method_serialized("_ON", 0); + if (config->reset_gpio) + acpigen_soc_set_tx_gpio(config->reset_gpio); + if (config->enable_gpio) { + acpigen_soc_set_tx_gpio(config->enable_gpio); + acpigen_write_sleep(config->enable_delay_ms); + } + if (config->reset_gpio) { + acpigen_soc_clear_tx_gpio(config->reset_gpio); + acpigen_write_sleep(config->reset_delay_ms); + } + acpigen_pop_len(); /* _ON method */ + + /* Method (_OFF, 0, Serialized) */ + acpigen_write_method_serialized("_OFF", 0); + if (config->reset_gpio) + acpigen_soc_set_tx_gpio(config->reset_gpio); + if (config->enable_gpio) + acpigen_soc_clear_tx_gpio(config->enable_gpio); + acpigen_pop_len(); /* _OFF method */ + + acpigen_pop_len(); /* PowerResource PRIC */ +} + static void i2c_generic_fill_ssdt(struct device *dev) { struct drivers_i2c_generic_config *config = dev->chip_info; @@ -72,6 +112,9 @@ static void i2c_generic_fill_ssdt(struct device *dev) acpi_dp_write(dsd); } + /* Power Resource */ + i2c_generic_add_power_res(config); + acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */

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Patch set updated for coreboot: mainboard/google/reef: Add PowerResource for ELAN touchscreen
by Furquan Shaikh 24 Oct '16

24 Oct '16

Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/17083 -gerrit commit e562ae20210c1866507bd552cd1aef2856efd17d Author: Furquan Shaikh <furquan(a)chromium.org> Date: Thu Oct 20 22:48:45 2016 -0700 mainboard/google/reef: Add PowerResource for ELAN touchscreen Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:55988 Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> --- src/mainboard/google/reef/variants/baseboard/devicetree.cb | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/reef/variants/baseboard/devicetree.cb b/src/mainboard/google/reef/variants/baseboard/devicetree.cb index 00df9bd..30d61f6 100644 --- a/src/mainboard/google/reef/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/reef/variants/baseboard/devicetree.cb @@ -142,6 +142,10 @@ chip soc/intel/apollolake register "desc" = ""ELAN Touchscreen"" register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" register "probed" = "1" + register "reset_gpio" = "GPIO_36" + register "reset_delay_ms" = "20" + register "enable_gpio" = "GPIO_152" + register "enable_delay_ms" = "1" device i2c 10 on end end end # - I2C 3

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coreboot-gerrit October 2016