coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: skylake: use smm_subregion() during SMM relocation
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit d452b6edd6b42c5314785ae5271d7dce28a55365 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 17:28:50 2015 -0500 skylake: use smm_subregion() during SMM relocation The smm_subregion() support allows the SMM relocation to not use duplicated math by calling out the specific regions it wants. IED base is now correct and not pointing outside from SMRAM. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ief8940c2ab6320449500ced2121d0cd7ed73af4b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290930 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: I00c3284cfacb2a73942640ccfa7912b7d65efb9d Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11198 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11198 for details. -gerrit

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Patch merged into coreboot/master: fsp1_1: fsp_relocate: use struct region_device and struct prog
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 22ea0078917415aa179f868b94b7f91fd533b369 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 10:17:33 2015 -0500 fsp1_1: fsp_relocate: use struct region_device and struct prog Using struct prog and struct region_device allows for the caller to be none-the-wiser about where FSP gets placed. It also allows for the source location to be abstracted away such that it doesn't require a large mapping up front to do the relocation. Lastly, it allows for simplifying the intel/commmon FSP support in that it can pass around a struct prog. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I034b04ab2b7e9e01f5ee14fcc190f04b90517d30 Original-Signed-off-by: Aaron Durbin <adurbin(a)chroumium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290830 Original-Tested-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Ibe1f206a9541902103551afaf212418fcc90e73c Signed-off-by: Aaron Durbin <adurbin(a)chroumium.org> Reviewed-on: http://review.coreboot.org/11193 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11193 for details. -gerrit

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Patch merged into coreboot/master: libpayload: usb: xhci: Fix list of cleared port change bits
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 6f4c7a6fded85c4687386b857687af4b9a953851 Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Aug 7 15:29:41 2015 -0700 libpayload: usb: xhci: Fix list of cleared port change bits The xhci_rh_port_status_changed() function tries to always clear all port status bits, even though most of them don't interest us. This is generally a smart thing to do since not clearing a status bit may cause the controller to not generate any more Port Status Change Events. However, the bitmask we currently use doesn't cover bit 23 (Port Config Error Change) and instead covers bit 16 (Port Link State Write Strobe) which is not really related to this and not a W1C bit. Probably a typo, so let's fix that. BRANCH=None BUG=None TEST=Plugged/unplugged a bunch of USB devices on an XHCI Falco. Original-Change-Id: Ia83f5b72cce094859c0f0e730752d7b5cfa6e1c6 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291842 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I11f5fe38cb70055daf6e866a8ee84ca80488e3bf Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11194 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11194 for details. -gerrit

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Patch merged into coreboot/master: skylake: clean up SMM region calculations
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit a0429b6f3ca6aa63124dbbbe3507629adc9ccd23 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 14:33:37 2015 -0500 skylake: clean up SMM region calculations The TSEG is defined to be from TSEG->BGSM in the host bridge registers. Use those registers at runtime to calculate the correct TSEG size. Lastly, use a few helper macros to make constants more readable. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290832 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11195 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11195 for details. -gerrit

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Patch merged into coreboot/master: intel/common: use external stage cache for fsp_ramstage
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit abf87a25f21b22797d8dc8c9a33537980df2c24d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 12:26:56 2015 -0500 intel/common: use external stage cache for fsp_ramstage The fsp_ramstage.c code was not taking advantage of the stage cache which does all the accounting and calculation work for the caller. Remove the open coded logic and use the provided infrastructure. Using said infrastructure means there's no need for the FSP_CACHE_SIZE Kconfig variable. Therefore, remove it. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4363823c825b4a700205769f109ff9cf0d78b897 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290831 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ifd3cc4a538daac687949c5f4cab2c687368d6787 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11196 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11196 for details. -gerrit

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Patch merged into coreboot/master: intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.c
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 39bdb0bbcfebae1a7da1a51a7893541f31c4ed3d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 23:59:43 2015 -0500 intel/common: use acpi_is_wakeup_s3() in fsp_ramstage.c acpi_is_wakeup_s3() was introduced in upstream coreboot while the FSP support code was written. Move to using that instead of using the romstage_handoff structure directly. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I71601a4be3c981672e25e189c98abb6a676462bf Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290720 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2ae4d9906e0891080481fb58b941921922a989d3 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11190 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11190 for details. -gerrit

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Patch merged into coreboot/master: Skylake: Add ASL code to enable GPIO controller
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit ee9662824d41765a90d0dde6870d8f13737bc3a6 Author: Archana Patni <archana.patni(a)intel.com> Date: Sat Jul 4 00:56:32 2015 +0530 Skylake: Add ASL code to enable GPIO controller This patch enables GPIO controller for skylake. It adds community base addresses and offset for Community0, Community1, and Community3. Community2 is not exposed in BIOS or enabled in the kernel driver. Also, clean up the carry over GWAK implementation from BDW. BRANCH=None BUG=chrome-os-partner:42393 TEST=cat /sys/kernel/debug/gpio should list of GPIOs TEST=export a GPIO pin using /sys/class/gpio/export Original-Change-Id: I891c40589d3dbd796cf593626472c7b5674a1ae0 Original-Signed-off-by: Archana Patni <archana.patni(a)intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291230 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Commit-Queue: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I7481ce682ccae872fddf81b3188c3415d5d3f7d9 Signed-off-by: Archana Patni <archana.patni(a)intel.com> Signed-off-by: Subramony Sesha <subramony.sesha(a)intel.com> Reviewed-on: http://review.coreboot.org/11191 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11191 for details. -gerrit

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Patch merged into coreboot/master: stage_cache: make prog const in stage_cache_add()
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 54546c97c780f86a050021d38109aa6c681bfd15 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 00:52:13 2015 -0500 stage_cache: make prog const in stage_cache_add() The stage_cache_add() function should not be manipulating the struct prog argument in anyway. Therefore, mark it as const. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, and resumed on glados. Original-Change-Id: I4509e478d3c98247b9d776f6534b949d9ba6282c Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290721 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ibadc00a9e1cbbf12119def92d77a79077625fb85 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11192 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11192 for details. -gerrit

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Patch merged into coreboot/master: libpayload: Do not gate USB_DWC2 on USB_HID
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 75daee5ee9ae5ab81d6d74569f4a947417f30b93 Author: David Hendricks <dhendrix(a)chromium.org> Date: Thu Aug 6 14:08:55 2015 -0700 libpayload: Do not gate USB_DWC2 on USB_HID This forward-ports the change from CL:277155 since the Kconfig file was renamed from Config.in. BUG=chrome-os-partner:41416 BRANCH=none TEST=built and booted on Mickey, keyboard works at dev screen Original-Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Original-Change-Id: Ibffa5188df51ecd7b8bdd631d4b767ec64130819 Original-Reviewed-on: https://chromium-review.googlesource.com/291138 Original-Commit-Ready: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Change-Id: Iebb1da6ec8c7886a6eb9ebcc67b59d617496c555 Signed-off-by: David Hendricks <dhendrix(a)chromium.org> Reviewed-on: http://review.coreboot.org/11188 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix(a)google.com> See http://review.coreboot.org/11188 for details. -gerrit

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Patch merged into coreboot/master: libpayload: usb: xhci: Count new Max Scratchpad Bufs bits from XHCI 1.1
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 57ddd9abc79048efc658878f021927846fef6a0a Author: Julius Werner <jwerner(a)chromium.org> Date: Fri Aug 7 13:14:20 2015 -0700 libpayload: usb: xhci: Count new Max Scratchpad Bufs bits from XHCI 1.1 The 1.1 revision of the XHCI specification added an extra 5 bits to the Max Scratchpad Bufs field of HCSPARAMS2 that newer controllers make use of. Not honoring these bits means we're not allocating as many scratchpad buffers as the controller expects, which means it will interpret some uninitialized values from the end of the pointer array as scratchpad buffer pointers, which obviously doesn't end well. Let's fix that. BRANCH=none BUG=chrome-os-partner:42279 TEST=Makes a USB-related memory corruption issue disappear. Original-Change-Id: I7c907492339262bda31cdd2b5c0b588de7df8544 Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291681 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: Iba1007bfebffe1f564f78bb875fff9ba0fe11a38 Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11189 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11189 for details. -gerrit

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coreboot-gerrit August 2015