coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: seabios integration: deal with ccache woes some more
by gerrit＠coreboot.org 15 Aug '15

15 Aug '15

the following patch was just integrated into master: commit 41fceafb090120fa2403338f1940ad3c7148909b Author: Patrick Georgi <patrick(a)georgi-clan.de> Date: Thu Aug 13 21:55:30 2015 +0200 seabios integration: deal with ccache woes some more seabios integration interprets the CC variable with a special case when ccache is prepended to the compiler. Since the integration also tries to extract compiler flags (which I'm not sure we still add to CC _ever_), that also needs to look at only the part of the string that contains compiler and (maybe) flags, so skip the first word if it was determined to be the path to the ccache binary. Change-Id: I717863f456bf4fd6f08427d86633079ecda039df Signed-off-by: Patrick Georgi <patrick(a)georgi-clan.de> Reviewed-on: http://review.coreboot.org/11227 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11227 for details. -gerrit

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New patch to review for coreboot: northbridge/amd/amdfam10: Redirect legacy VGA memory access to MMIO
by Timothy Pearson 14 Aug '15

14 Aug '15

Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11240 -gerrit commit 19c40c60d33e332362e51601ab6306acec00a85a Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com> Date: Fri Aug 14 16:31:14 2015 -0500 northbridge/amd/amdfam10: Redirect legacy VGA memory access to MMIO Commit 27baa32 deactivated TSeg SMRAM, which had the side effect of routing legacy VGA memory access to DRAM. Restore the correct MMIO mapping via the MMIO configuration registers. Change-Id: Ie4b7c0b2d6f9a02af9a022565fe514119513190a Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com> --- src/northbridge/amd/amdfam10/northbridge.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/northbridge/amd/amdfam10/northbridge.c b/src/northbridge/amd/amdfam10/northbridge.c index f6f2641..7a90ed2 100644 --- a/src/northbridge/amd/amdfam10/northbridge.c +++ b/src/northbridge/amd/amdfam10/northbridge.c @@ -516,6 +516,14 @@ static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid) printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, link->link_num); set_vga_enable_reg(nodeid, link->link_num); + + /* Redirect VGA memory access to MMIO */ + struct resource *res; + res = new_resource(dev, IOINDEX(0x1000 + 0x1b8, link->link_num)); + res->base = 0xa0000; + res->size = 0x20000; + res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED; + amdfam10_set_resource(dev, res, nodeid); } static void amdfam10_set_resources(device_t dev)

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Patch merged into coreboot/master: acpi: 64bit fixes
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 71a301811f6f55ea93e3fa216ecbf7accb417005 Author: Stefan Reinauer <reinauer(a)chromium.org> Date: Thu Jul 30 16:28:13 2015 -0700 acpi: 64bit fixes Change-Id: I5d0c95af7d35115b5ac4141489caceef4ee1c8bb Signed-off-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Reviewed-on: http://review.coreboot.org/11088 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11088 for details. -gerrit

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Patch merged into coreboot/master: emulation/qemu: Serialize IQCR method
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit aa95f629db43156d33085972196421e362bf32a8 Author: Paul Menzel <paulepanter(a)users.sourceforge.net> Date: Tue Aug 11 22:01:00 2015 +0200 emulation/qemu: Serialize IQCR method Fix the remark below for the mainboards qemu-i440x and qemu-q35. Intel ACPI Component Architecture ASL+ Optimizing Compiler version 20150717-32 Copyright (c) 2000 - 2015 Intel Corporation dsdt.aml 336: Method(IQCR, 1, NotSerialized) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) ASL Input: dsdt.aml - 399 lines, 16756 bytes, 245 keywords AML Output: dsdt.aml - 4000 bytes, 146 named objects, 99 executable opcodes Compilation complete. 0 Errors, 0 Warnings, 1 Remarks, 233 Optimizations Change-Id: Ibe48f872768ab8295d6fed3359d9eef04b736a05 Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11162 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply(a)raptorengineeringinc.com> Reviewed-by: Stefan Reinauer <stefan.reinauer(a)coreboot.org> See http://review.coreboot.org/11162 for details. -gerrit

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New patch to review for coreboot: Skylake: update cbmem_top
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11239 -gerrit commit 4418147cb971f41b512493e1c1fd854616d32aba Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Jul 23 17:40:32 2015 +0530 Skylake: update cbmem_top cbmem_top was using CHIPSET_RESERVED_MEM_BYTES to w/a unknown memory regions reserved by fsp for chipset use. With that being removed, the function needs to properly walk though the memory map resulted from fsp memory init to find out the usable address for cbmem root. Refer the FSP 1.3.0 Integartion guide for more details on the Memory Map. systemagent should also use the same mechanism to create the reserved RAM resource. BRANCH=None BUG=None TEST=Build and Boot kunimitsu (FAB3) CQ-DEPEND=CL:*226035,CL:*226045,CL:291573 Original-Change-Id: Id0954cf8e6388e549c7d4df67b468572b5bea539 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291611 Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Commit-Queue: Robbie Zhang <robbie.zhang(a)intel.com> Change-Id: I4e716170f40936081ce9d4878bf74c75f469f78d Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/include/soc/msr.h | 4 +- src/soc/intel/skylake/include/soc/systemagent.h | 6 ++ src/soc/intel/skylake/memmap.c | 86 ++++++++++++++++++++----- src/soc/intel/skylake/smmrelocate.c | 4 +- src/soc/intel/skylake/systemagent.c | 45 ++++--------- 5 files changed, 94 insertions(+), 51 deletions(-) diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 3903757..4239b36 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -54,8 +54,8 @@ #define IA32_PLATFORM_DCA_CAP 0x1f8 #define MSR_POWER_CTL 0x1fc #define MSR_LT_LOCK_MEMORY 0x2e7 -#define UNCORE_EMRR_PHYS_BASE_MSR 0x2f4 -#define UNCORE_EMRR_PHYS_MASK_MSR 0x2f5 +#define UNCORE_PRMRR_PHYS_BASE_MSR 0x2f4 +#define UNCORE_PRMRR_PHYS_MASK_MSR 0x2f5 #define IA32_MC0_STATUS 0x401 #define SMM_FEATURE_CONTROL_MSR 0x4e0 #define SMM_CPU_SAVE_EN (1 << 1) diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h index 6bb5c66..59221c7 100644 --- a/src/soc/intel/skylake/include/soc/systemagent.h +++ b/src/soc/intel/skylake/include/soc/systemagent.h @@ -120,7 +120,13 @@ /* Data is passed through bits 31:0 of the data register. */ #define BIOS_MAILBOX_DATA 0x5da0 +/* CPU Trace reserved memory size */ +#define TRACE_MEMORY_SIZE 0x8000000 /* 128MiB */ + /* System Agent identification */ u8 systemagent_revision(void); +/* Top of 32bit usable memory */ +u32 top_of_32bit_ram(void); + #endif diff --git a/src/soc/intel/skylake/memmap.c b/src/soc/intel/skylake/memmap.c index 494b259..0dc46a9 100644 --- a/src/soc/intel/skylake/memmap.c +++ b/src/soc/intel/skylake/memmap.c @@ -20,7 +20,11 @@ #include <arch/io.h> #include <cbmem.h> +#include <chip.h> +#include <console/console.h> +#include <device/device.h> #include <device/pci.h> +#include <soc/msr.h> #include <soc/pci_devs.h> #include <soc/romstage.h> #include <soc/smm.h> @@ -108,6 +112,71 @@ int smm_subregion(int sub, void **start, size_t *size) return 0; } +/* + * Host Memory Map: + * + * +--------------------------+ TOUUD + * | | + * +--------------------------+ 4GiB + * | PCI Address Space | + * +--------------------------+ TOLUD (also maps into MC address space) + * | iGD | + * +--------------------------+ BDSM + * | GTT | + * +--------------------------+ BGSM + * | TSEG | + * +--------------------------+ TSEGMB + * | DMA Protected Region | + * +--------------------------+ DPR + * | PRM (C6DRAM/SGX) | + * +--------------------------+ PRMRR + * | Trace Memory | + * +--------------------------+ top_of_ram + * | Reserved - FSP/CBMEM | + * +--------------------------+ TOLUM + * | Usage DRAM | + * +--------------------------+ 0 + * + * Some of the base registers above can be equal making the size of those + * regions 0. The reason is because the memory controller internally subtracts + * the base registers from each other to determine sizes of the regions. In + * other words, the memory map is in a fixed order no matter what. + */ + +u32 top_of_32bit_ram(void) +{ + msr_t prmrr_base; + u32 top_of_ram; + const struct device *dev; + const struct soc_intel_skylake_config *config; + + /* + * Check if Tseg has been initialized, we will use this as a flag + * to check if the MRC is done, and only then continue to read the + * PRMMR_BASE MSR. The system hangs if PRMRR_BASE MSR is read before + * PRMRR_MASK MSR lock bit is set. + */ + if (smm_region_start() == 0) + return 0; + + dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_ROOT, 0)); + config = dev->chip_info; + + /* + * On Skylake, cbmem_top is offset down from PRMRR_BASE by reserved + * memory (128MiB) for CPU trace if enabled, then reserved memory (4KB) + * for PTT if enabled. PTT is in fact not used on Skylake platforms. + * Refer to Fsp Integration Guide for the memory mapping layout. + */ + prmrr_base = rdmsr(UNCORE_PRMRR_PHYS_BASE_MSR); + top_of_ram = prmrr_base.lo; + + if (config->ProbelessTrace) + top_of_ram -= TRACE_MEMORY_SIZE; + + return top_of_ram; +} + void *cbmem_top(void) { /* @@ -117,7 +186,7 @@ void *cbmem_top(void) * | (TSEG) | * +-------------------------+ SMM base (aligned) * | | - * | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE + * | Chipset Reserved Memory | * | | * +-------------------------+ top_of_ram (aligned) * | | @@ -137,19 +206,6 @@ void *cbmem_top(void) * | | * +-------------------------+ */ - - uintptr_t top_of_ram = smm_region_start(); - - /* - * Subtract DMA Protected Range size if enabled and align to a multiple - * of TSEG size. - */ - u32 dpr = pci_read_config32(SA_DEV_ROOT, DPR); - if (dpr & DPR_EPM) { - top_of_ram -= (dpr & DPR_SIZE_MASK) << 16; - top_of_ram = ALIGN_DOWN(top_of_ram, mmap_region_granluarity()); - } - - return (void *)top_of_ram; + return (void *)top_of_32bit_ram(); } diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index 2f75c2e..4b6f1c4 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -54,8 +54,8 @@ static inline void write_uncore_emrr(struct smm_relocation_params *relo_params) "Writing UNCORE_EMRR. base = 0x%08x, mask=0x%08x\n", relo_params->uncore_emrr_base.lo, relo_params->uncore_emrr_mask.lo); - wrmsr(UNCORE_EMRR_PHYS_BASE_MSR, relo_params->uncore_emrr_base); - wrmsr(UNCORE_EMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask); + wrmsr(UNCORE_PRMRR_PHYS_BASE_MSR, relo_params->uncore_emrr_base); + wrmsr(UNCORE_PRMRR_PHYS_MASK_MSR, relo_params->uncore_emrr_mask); } static void update_save_state(int cpu, diff --git a/src/soc/intel/skylake/systemagent.c b/src/soc/intel/skylake/systemagent.c index a1bcfdc..1fe3304 100644 --- a/src/soc/intel/skylake/systemagent.c +++ b/src/soc/intel/skylake/systemagent.c @@ -163,33 +163,6 @@ static void mc_add_fixed_mmio_resources(device_t dev) } } -/* - * Host Memory Map: - * - * +--------------------------+ TOUUD - * | | - * +--------------------------+ 4GiB - * | PCI Address Space | - * +--------------------------+ TOLUD (also maps into MC address space) - * | iGD | - * +--------------------------+ BDSM - * | GTT | - * +--------------------------+ BGSM - * | TSEG | - * +--------------------------+ TSEGMB - * | DMA Protected Region | - * +--------------------------+ DPR - * | Reserved - FSP | - * +--------------------------+ RSVFSP - * | Usage DRAM | - * +--------------------------+ 0 - * - * Some of the base registers above can be equal making the size of those - * regions 0. The reason is because the memory controller internally subtracts - * the base registers from each other to determine sizes of the regions. In - * other words, the memory map is in a fixed order no matter what. - */ - struct map_entry { int reg; int is_64_bit; @@ -313,8 +286,9 @@ static void mc_add_dram_resources(device_t dev) /* * These are the host memory ranges that should be added: * - 0 -> 0xa0000: cacheable - * - 0xc0000 -> TSEG : cacheable - * - TESG -> BGSM: cacheable with standard MTRRs and reserved + * - 0xc0000 -> top_of_ram : cacheable + * - top_of_ram -> TSEG - DPR: uncacheable + * - TESG - DPR -> BGSM: cacheable with standard MTRRs and reserved * - BGSM -> TOLUD: not cacheable with standard MTRRs and reserved * - 4GiB -> TOUUD: cacheable * @@ -347,12 +321,19 @@ static void mc_add_dram_resources(device_t dev) size_k = (0xa0000 >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); - /* 0xc0000 -> TSEG - DPR */ + /* 0xc0000 -> top_of_ram */ base_k = 0xc0000 >> 10; - size_k = (unsigned long)(mc_values[TSEG_REG] >> 10) - base_k; - size_k -= dpr_size >> 10; + size_k = (top_of_32bit_ram() >> 10) - base_k; ram_resource(dev, index++, base_k, size_k); + /* top_of_ram -> TSEG - DPR */ + resource = new_resource(dev, index++); + resource->base = top_of_32bit_ram(); + resource->size = mc_values[TSEG_REG] - dpr_size - resource->base; + resource->flags = IORESOURCE_MEM | IORESOURCE_FIXED | + IORESOURCE_STORED | IORESOURCE_RESERVE | + IORESOURCE_ASSIGNED; + /* TSEG - DPR -> BGSM */ resource = new_resource(dev, index++); resource->base = mc_values[TSEG_REG] - dpr_size;

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New patch to review for coreboot: skylake: Update Memory and Silicon Init params
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11238 -gerrit commit 88a1e23233a1f8c81f9f6e20650bee3bd0c245c7 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Jul 21 20:21:50 2015 +0530 skylake: Update Memory and Silicon Init params Update the MemoryInit and SilicoInit params as per FSP 1.3.0 release. Note: add SvGv and Rmt to Upd. BRANCH=None BUG=None TEST=Build and Boot FAB3 (Kunimitsu) CQ-DEPEND=CL:*226035, CL:*226045 Original-Change-Id: I62000f6a485fee42ef733c3b548192f2bedfce49 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Original-Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/291573 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Tested-by: Wenkai Du <wenkai.du(a)intel.com> Change-Id: Iaafa658b4e710fe512526a521cf6c529efb19bf0 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com> --- src/soc/intel/skylake/chip.c | 176 ++++++++++++++++++++++++++++- src/soc/intel/skylake/chip.h | 15 ++- src/soc/intel/skylake/romstage/romstage.c | 180 +----------------------------- 3 files changed, 194 insertions(+), 177 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index b1b66fc..f79a02d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -69,6 +69,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) { const struct device *dev; const struct soc_intel_skylake_config *config; + int i; /* Set the parameters for SiliconInit */ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); @@ -76,7 +77,27 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params) return; config = dev->chip_info; + for (i = 0; i < PchSerialIoIndexMax; i++) + params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; + + params->SataSalpSupport = config->SataSalpSupport; + params->SataPortsEnable[0] = config->SataPortsEnable[0]; + params->SsicPortEnable = config->SsicPortEnable; + params->SmbusEnable = config->SmbusEnable; + params->Cio2Enable = config->Cio2Enable; + params->ScsEmmcEnabled = config->ScsEmmcEnabled; + params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; + params->ScsSdCardEnabled = config->ScsSdCardEnabled; + params->IshEnable = 0; + params->EnableAzalia = config->EnableAzalia; + params->IoBufferOwnership = config->IoBufferOwnership; + params->DspEnable = config->DspEnable; + params->XdciEnable = config->XdciEnable; params->Device4Enable = config->Device4Enable; + + /* Show SPI controller if enabled in devicetree.cb */ + dev = dev_find_slot(0, PCH_DEVFN_SPI); + params->ShowSpiController = dev->enabled; } void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, @@ -84,13 +105,166 @@ void soc_display_silicon_init_params(const SILICON_INIT_UPD *original, { /* Display the parameters for SiliconInit */ printk(BIOS_SPEW, "UPD values for SiliconInit:\n"); - + soc_display_upd_value("LogoPtr", 4, + (uint32_t)original->LogoPtr, + (uint32_t)params->LogoPtr); + soc_display_upd_value("LogoSize", 4, + (uint32_t)original->LogoSize, + (uint32_t)params->LogoSize); + soc_display_upd_value("GraphicsConfigPtr", 4, + (uint32_t)original->GraphicsConfigPtr, + (uint32_t)params->GraphicsConfigPtr); + soc_display_upd_value("MicrocodeRegionBase", 4, + (uint32_t)original->MicrocodeRegionBase, + (uint32_t)params->MicrocodeRegionBase); + soc_display_upd_value("MicrocodeRegionSize", 4, + (uint32_t)original->MicrocodeRegionSize, + (uint32_t)params->MicrocodeRegionSize); + soc_display_upd_value("TurboMode", 1, + (uint32_t)original->TurboMode, + (uint32_t)params->TurboMode); soc_display_upd_value("GpioTablePtr", 4, (uint32_t)original->GpioTablePtr, (uint32_t)params->GpioTablePtr); soc_display_upd_value("Device4Enable", 1, original->Device4Enable, params->Device4Enable); + soc_display_upd_value("SataSalpSupport", 1, original->SataSalpSupport, + params->SataSalpSupport); + soc_display_upd_value("SataPortsEnable[0]", 1, + original->SataPortsEnable[0], params->SataPortsEnable[0]); + soc_display_upd_value("SataPortsEnable[1]", 1, + original->SataPortsEnable[1], params->SataPortsEnable[1]); + soc_display_upd_value("SataPortsEnable[2]", 1, + original->SataPortsEnable[2], params->SataPortsEnable[2]); + soc_display_upd_value("SataPortsEnable[3]", 1, + original->SataPortsEnable[3], params->SataPortsEnable[3]); + soc_display_upd_value("SataPortsEnable[4]", 1, + original->SataPortsEnable[4], params->SataPortsEnable[4]); + soc_display_upd_value("SataPortsEnable[5]", 1, + original->SataPortsEnable[5], params->SataPortsEnable[5]); + soc_display_upd_value("SataPortsEnable[6]", 1, + original->SataPortsEnable[6], params->SataPortsEnable[6]); + soc_display_upd_value("SataPortsEnable[7]", 1, + original->SataPortsEnable[7], params->SataPortsEnable[7]); + soc_display_upd_value("SataPortsDevSlp[0]", 1, + original->SataPortsDevSlp[0], params->SataPortsDevSlp[0]); + soc_display_upd_value("SataPortsDevSlp[1]", 1, + original->SataPortsDevSlp[1], params->SataPortsDevSlp[1]); + soc_display_upd_value("SataPortsDevSlp[2]", 1, + original->SataPortsDevSlp[2], params->SataPortsDevSlp[2]); + soc_display_upd_value("SataPortsDevSlp[3]", 1, + original->SataPortsDevSlp[3], params->SataPortsDevSlp[3]); + soc_display_upd_value("SataPortsDevSlp[4]", 1, + original->SataPortsDevSlp[4], params->SataPortsDevSlp[4]); + soc_display_upd_value("SataPortsDevSlp[5]", 1, + original->SataPortsDevSlp[5], params->SataPortsDevSlp[5]); + soc_display_upd_value("SataPortsDevSlp[6]", 1, + original->SataPortsDevSlp[6], params->SataPortsDevSlp[6]); + soc_display_upd_value("SataPortsDevSlp[7]", 1, + original->SataPortsDevSlp[7], params->SataPortsDevSlp[7]); + soc_display_upd_value("EnableAzalia", 1, + original->EnableAzalia, params->EnableAzalia); + soc_display_upd_value("DspEnable", 1, original->DspEnable, + params->DspEnable); + soc_display_upd_value("IoBufferOwnership", 1, + original->IoBufferOwnership, params->IoBufferOwnership); + soc_display_upd_value("PortUsb20Enable[0]", 1, + original->PortUsb20Enable[0], params->PortUsb20Enable[0]); + soc_display_upd_value("PortUsb20Enable[1]", 1, + original->PortUsb20Enable[1], params->PortUsb20Enable[1]); + soc_display_upd_value("PortUsb20Enable[2]", 1, + original->PortUsb20Enable[2], params->PortUsb20Enable[2]); + soc_display_upd_value("PortUsb20Enable[3]", 1, + original->PortUsb20Enable[3], params->PortUsb20Enable[3]); + soc_display_upd_value("PortUsb20Enable[4]", 1, + original->PortUsb20Enable[4], params->PortUsb20Enable[4]); + soc_display_upd_value("PortUsb20Enable[5]", 1, + original->PortUsb20Enable[5], params->PortUsb20Enable[5]); + soc_display_upd_value("PortUsb20Enable[6]", 1, + original->PortUsb20Enable[6], params->PortUsb20Enable[6]); + soc_display_upd_value("PortUsb20Enable[7]", 1, + original->PortUsb20Enable[7], params->PortUsb20Enable[7]); + soc_display_upd_value("PortUsb20Enable[8]", 1, + original->PortUsb20Enable[8], params->PortUsb20Enable[8]); + soc_display_upd_value("PortUsb20Enable[9]", 1, + original->PortUsb20Enable[9], params->PortUsb20Enable[9]); + soc_display_upd_value("PortUsb20Enable[10]", 1, + original->PortUsb20Enable[10], params->PortUsb20Enable[10]); + soc_display_upd_value("PortUsb20Enable[11]", 1, + original->PortUsb20Enable[11], params->PortUsb20Enable[11]); + soc_display_upd_value("PortUsb20Enable[12]", 1, + original->PortUsb20Enable[12], params->PortUsb20Enable[12]); + soc_display_upd_value("PortUsb20Enable[13]", 1, + original->PortUsb20Enable[13], params->PortUsb20Enable[13]); + soc_display_upd_value("PortUsb20Enable[14]", 1, + original->PortUsb20Enable[14], params->PortUsb20Enable[14]); + soc_display_upd_value("PortUsb20Enable[15]", 1, + original->PortUsb20Enable[15], params->PortUsb20Enable[15]); + soc_display_upd_value("PortUsb30Enable[0]", 1, + original->PortUsb30Enable[0], params->PortUsb30Enable[0]); + soc_display_upd_value("PortUsb30Enable[1]", 1, + original->PortUsb30Enable[1], params->PortUsb30Enable[1]); + soc_display_upd_value("PortUsb30Enable[2]", 1, + original->PortUsb30Enable[2], params->PortUsb30Enable[2]); + soc_display_upd_value("PortUsb30Enable[3]", 1, + original->PortUsb30Enable[3], params->PortUsb30Enable[3]); + soc_display_upd_value("PortUsb30Enable[4]", 1, + original->PortUsb30Enable[4], params->PortUsb30Enable[4]); + soc_display_upd_value("PortUsb30Enable[5]", 1, + original->PortUsb30Enable[5], params->PortUsb30Enable[5]); + soc_display_upd_value("PortUsb30Enable[6]", 1, + original->PortUsb30Enable[6], params->PortUsb30Enable[6]); + soc_display_upd_value("PortUsb30Enable[7]", 1, + original->PortUsb30Enable[7], params->PortUsb30Enable[7]); + soc_display_upd_value("PortUsb30Enable[8]", 1, + original->PortUsb30Enable[8], params->PortUsb30Enable[8]); + soc_display_upd_value("PortUsb30Enable[9]", 1, + original->PortUsb30Enable[9], params->PortUsb30Enable[9]); + soc_display_upd_value("XdciEnable", 1, original->XdciEnable, + params->XdciEnable); + soc_display_upd_value("SsicPortEnable", 1, original->SsicPortEnable, + params->SsicPortEnable); + soc_display_upd_value("SmbusEnable", 1, original->SmbusEnable, + params->SmbusEnable); + soc_display_upd_value("SerialIoDevMode[0]", 1, + original->SerialIoDevMode[0], params->SerialIoDevMode[0]); + soc_display_upd_value("SerialIoDevMode[1]", 1, + original->SerialIoDevMode[1], params->SerialIoDevMode[1]); + soc_display_upd_value("SerialIoDevMode[2]", 1, + original->SerialIoDevMode[2], params->SerialIoDevMode[2]); + soc_display_upd_value("SerialIoDevMode[3]", 1, + original->SerialIoDevMode[3], params->SerialIoDevMode[3]); + soc_display_upd_value("SerialIoDevMode[4]", 1, + original->SerialIoDevMode[4], params->SerialIoDevMode[4]); + soc_display_upd_value("SerialIoDevMode[5]", 1, + original->SerialIoDevMode[5], params->SerialIoDevMode[5]); + soc_display_upd_value("SerialIoDevMode[6]", 1, + original->SerialIoDevMode[6], params->SerialIoDevMode[6]); + soc_display_upd_value("SerialIoDevMode[7]", 1, + original->SerialIoDevMode[7], params->SerialIoDevMode[7]); + soc_display_upd_value("SerialIoDevMode[8]", 1, + original->SerialIoDevMode[8], params->SerialIoDevMode[8]); + soc_display_upd_value("SerialIoDevMode[9]", 1, + original->SerialIoDevMode[9], params->SerialIoDevMode[9]); + soc_display_upd_value("SerialIoDevMode[10]", 1, + original->SerialIoDevMode[10], params->SerialIoDevMode[10]); + soc_display_upd_value("Cio2Enable", 1, original->Cio2Enable, + params->Cio2Enable); + soc_display_upd_value("ScsEmmcEnabled", 1, original->ScsEmmcEnabled, + params->ScsEmmcEnabled); + soc_display_upd_value("ScsEmmcHs400Enabled", 1, + original->ScsEmmcHs400Enabled, params->ScsEmmcHs400Enabled); + soc_display_upd_value("ScsSdCardEnabled", 1, original->ScsSdCardEnabled, + params->ScsSdCardEnabled); + soc_display_upd_value("IshEnable", 1, original->IshEnable, + params->IshEnable); + soc_display_upd_value("ShowSpiController", 1, + original->ShowSpiController, params->ShowSpiController); + soc_display_upd_value("HsioMessaging", 1, original->HsioMessaging, + params->HsioMessaging); + soc_display_upd_value("Heci3Enabled", 1, original->Heci3Enabled, + params->Heci3Enabled); } static void pci_set_subsystem(device_t dev, unsigned vendor, unsigned device) diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 9fe1ed2..e962b37 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -128,7 +128,7 @@ struct soc_intel_skylake_config { int tcc_offset; /* - * The following fields come from fsp_vpd.h. + * The following fields come from FspUpdVpd.h. * These are configuration values that are passed to FSP during * MemoryInit. */ @@ -141,6 +141,19 @@ struct soc_intel_skylake_config { /* Probeless Trace function */ u8 ProbelessTrace; + /* + * System Agent dynamic frequency configuration + * When enabled memory will be trained at two different frequencies. + * 0 = Disabled + * 1 = FixedLow + * 2 = FixedHigh + * 3 = Enabled + */ + u8 SaGv; + + /* Enable/disable Rank Margin Tool */ + u8 Rmt; + /* Lan */ u8 EnableLan; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index 253eaba..2ce5ce3 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -81,15 +81,12 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params) { const struct device *dev; const struct soc_intel_skylake_config *config; - int i; + /* Set the parameters for MemoryInit */ dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0)); config = dev->chip_info; - for (i = 0; i < PchSerialIoIndexMax; i++) - params->SerialIoDevMode[i] = config->SerialIoDevMode[i]; - memcpy(params->PcieRpEnable, config->PcieRpEnable, sizeof(params->PcieRpEnable)); memcpy(params->PcieRpClkReqSupport, config->PcieRpClkReqSupport, @@ -104,24 +101,9 @@ void soc_memory_init_params(MEMORY_INIT_UPD *params) params->EnableLan = config->EnableLan; params->EnableSata = config->EnableSata; params->SataMode = config->SataMode; - params->SataSalpSupport = config->SataSalpSupport; - params->SataPortsEnable[0] = config->SataPortsEnable[0]; - params->SsicPortEnable = config->SsicPortEnable; params->EnableTraceHub = config->EnableTraceHub; - params->SmbusEnable = config->SmbusEnable; - params->Cio2Enable = config->Cio2Enable; - params->ScsEmmcEnabled = config->ScsEmmcEnabled; - params->ScsEmmcHs400Enabled = config->ScsEmmcHs400Enabled; - params->ScsSdCardEnabled = config->ScsSdCardEnabled; - params->IshEnable = 0; - params->EnableAzalia = config->EnableAzalia; - params->IoBufferOwnership = config->IoBufferOwnership; - params->DspEnable = config->DspEnable; - params->XdciEnable = config->XdciEnable; - - /* Show SPI controller if enabled in devicetree.cb */ - dev = dev_find_slot(0, PCH_DEVFN_SPI); - params->ShowSpiController = dev->enabled; + params->SaGv = config->SaGv; + params->RMT = config->Rmt; } void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, @@ -248,51 +230,10 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, soc_display_upd_value("IedSize", 4, old->IedSize, new->IedSize); soc_display_upd_value("TsegSize", 4, old->TsegSize, new->TsegSize); soc_display_upd_value("MmioSize", 2, old->MmioSize, new->MmioSize); - soc_display_upd_value("ProbelessTrace", 1, old->ProbelessTrace, - new->ProbelessTrace); soc_display_upd_value("EnableLan", 1, old->EnableLan, new->EnableLan); soc_display_upd_value("EnableSata", 1, old->EnableSata, new->EnableSata); soc_display_upd_value("SataMode", 1, old->SataMode, new->SataMode); - soc_display_upd_value("SataSalpSupport", 1, old->SataSalpSupport, - new->SataSalpSupport); - soc_display_upd_value("SataPortsEnable[0]", 1, old->SataPortsEnable[0], - new->SataPortsEnable[0]); - soc_display_upd_value("SataPortsEnable[1]", 1, old->SataPortsEnable[1], - new->SataPortsEnable[1]); - soc_display_upd_value("SataPortsEnable[2]", 1, old->SataPortsEnable[2], - new->SataPortsEnable[2]); - soc_display_upd_value("SataPortsEnable[3]", 1, old->SataPortsEnable[3], - new->SataPortsEnable[3]); - soc_display_upd_value("SataPortsEnable[4]", 1, old->SataPortsEnable[4], - new->SataPortsEnable[4]); - soc_display_upd_value("SataPortsEnable[5]", 1, old->SataPortsEnable[5], - new->SataPortsEnable[5]); - soc_display_upd_value("SataPortsEnable[6]", 1, old->SataPortsEnable[6], - new->SataPortsEnable[6]); - soc_display_upd_value("SataPortsEnable[7]", 1, old->SataPortsEnable[7], - new->SataPortsEnable[7]); - soc_display_upd_value("SataPortsDevSlp[0]", 1, old->SataPortsDevSlp[0], - new->SataPortsDevSlp[0]); - soc_display_upd_value("SataPortsDevSlp[1]", 1, old->SataPortsDevSlp[1], - new->SataPortsDevSlp[1]); - soc_display_upd_value("SataPortsDevSlp[2]", 1, old->SataPortsDevSlp[2], - new->SataPortsDevSlp[2]); - soc_display_upd_value("SataPortsDevSlp[3]", 1, old->SataPortsDevSlp[3], - new->SataPortsDevSlp[3]); - soc_display_upd_value("SataPortsDevSlp[4]", 1, old->SataPortsDevSlp[4], - new->SataPortsDevSlp[4]); - soc_display_upd_value("SataPortsDevSlp[5]", 1, old->SataPortsDevSlp[5], - new->SataPortsDevSlp[5]); - soc_display_upd_value("SataPortsDevSlp[6]", 1, old->SataPortsDevSlp[6], - new->SataPortsDevSlp[6]); - soc_display_upd_value("SataPortsDevSlp[7]", 1, old->SataPortsDevSlp[7], - new->SataPortsDevSlp[7]); - soc_display_upd_value("EnableAzalia", 1, old->EnableAzalia, - new->EnableAzalia); - soc_display_upd_value("DspEnable", 1, old->DspEnable, new->DspEnable); - soc_display_upd_value("IoBufferOwnership", 1, old->IoBufferOwnership, - new->IoBufferOwnership); soc_display_upd_value("EnableTraceHub", 1, old->EnableTraceHub, new->EnableTraceHub); soc_display_upd_value("PcieRpEnable[0]", 1, old->PcieRpEnable[0], @@ -455,123 +396,12 @@ void soc_display_memory_init_params(const MEMORY_INIT_UPD *old, soc_display_upd_value("PcieRpClkReqNumber[19]", 1, old->PcieRpClkReqNumber[19], new->PcieRpClkReqNumber[19]); - soc_display_upd_value("PortUsb20Enable[0]", 1, old->PortUsb20Enable[0], - new->PortUsb20Enable[0]); - soc_display_upd_value("PortUsb20Enable[1]", 1, old->PortUsb20Enable[1], - new->PortUsb20Enable[1]); - soc_display_upd_value("PortUsb20Enable[2]", 1, old->PortUsb20Enable[2], - new->PortUsb20Enable[2]); - soc_display_upd_value("PortUsb20Enable[3]", 1, old->PortUsb20Enable[3], - new->PortUsb20Enable[3]); - soc_display_upd_value("PortUsb20Enable[4]", 1, old->PortUsb20Enable[4], - new->PortUsb20Enable[4]); - soc_display_upd_value("PortUsb20Enable[5]", 1, old->PortUsb20Enable[5], - new->PortUsb20Enable[5]); - soc_display_upd_value("PortUsb20Enable[6]", 1, old->PortUsb20Enable[6], - new->PortUsb20Enable[6]); - soc_display_upd_value("PortUsb20Enable[7]", 1, old->PortUsb20Enable[7], - new->PortUsb20Enable[7]); - soc_display_upd_value("PortUsb20Enable[8]", 1, old->PortUsb20Enable[8], - new->PortUsb20Enable[8]); - soc_display_upd_value("PortUsb20Enable[9]", 1, old->PortUsb20Enable[9], - new->PortUsb20Enable[9]); - soc_display_upd_value("PortUsb20Enable[10]", 1, - old->PortUsb20Enable[10], - new->PortUsb20Enable[10]); - soc_display_upd_value("PortUsb20Enable[11]", 1, - old->PortUsb20Enable[11], - new->PortUsb20Enable[11]); - soc_display_upd_value("PortUsb20Enable[12]", 1, - old->PortUsb20Enable[12], - new->PortUsb20Enable[12]); - soc_display_upd_value("PortUsb20Enable[13]", 1, - old->PortUsb20Enable[13], - new->PortUsb20Enable[13]); - soc_display_upd_value("PortUsb20Enable[14]", 1, - old->PortUsb20Enable[14], - new->PortUsb20Enable[14]); - soc_display_upd_value("PortUsb20Enable[15]", 1, - old->PortUsb20Enable[15], - new->PortUsb20Enable[15]); - soc_display_upd_value("PortUsb30Enable[0]", 1, old->PortUsb30Enable[0], - new->PortUsb30Enable[0]); - soc_display_upd_value("PortUsb30Enable[1]", 1, old->PortUsb30Enable[1], - new->PortUsb30Enable[1]); - soc_display_upd_value("PortUsb30Enable[2]", 1, old->PortUsb30Enable[2], - new->PortUsb30Enable[2]); - soc_display_upd_value("PortUsb30Enable[3]", 1, old->PortUsb30Enable[3], - new->PortUsb30Enable[3]); - soc_display_upd_value("PortUsb30Enable[4]", 1, old->PortUsb30Enable[4], - new->PortUsb30Enable[4]); - soc_display_upd_value("PortUsb30Enable[5]", 1, old->PortUsb30Enable[5], - new->PortUsb30Enable[5]); - soc_display_upd_value("PortUsb30Enable[6]", 1, old->PortUsb30Enable[6], - new->PortUsb30Enable[6]); - soc_display_upd_value("PortUsb30Enable[7]", 1, old->PortUsb30Enable[7], - new->PortUsb30Enable[7]); - soc_display_upd_value("PortUsb30Enable[8]", 1, old->PortUsb30Enable[8], - new->PortUsb30Enable[8]); - soc_display_upd_value("PortUsb30Enable[9]", 1, old->PortUsb30Enable[9], - new->PortUsb30Enable[9]); - soc_display_upd_value("XdciEnable", 1, old->XdciEnable, - new->XdciEnable); - soc_display_upd_value("SsicPortEnable", 1, old->SsicPortEnable, - new->SsicPortEnable); - soc_display_upd_value("SmbusEnable", 1, old->SmbusEnable, - new->SmbusEnable); - soc_display_upd_value("SerialIoDevMode[0]", 1, old->SerialIoDevMode[0], - new->SerialIoDevMode[0]); - soc_display_upd_value("SerialIoDevMode[1]", 1, old->SerialIoDevMode[1], - new->SerialIoDevMode[1]); - soc_display_upd_value("SerialIoDevMode[2]", 1, old->SerialIoDevMode[2], - new->SerialIoDevMode[2]); - soc_display_upd_value("SerialIoDevMode[3]", 1, old->SerialIoDevMode[3], - new->SerialIoDevMode[3]); - soc_display_upd_value("SerialIoDevMode[4]", 1, old->SerialIoDevMode[4], - new->SerialIoDevMode[4]); - soc_display_upd_value("SerialIoDevMode[5]", 1, old->SerialIoDevMode[5], - new->SerialIoDevMode[5]); - soc_display_upd_value("SerialIoDevMode[6]", 1, old->SerialIoDevMode[6], - new->SerialIoDevMode[6]); - soc_display_upd_value("SerialIoDevMode[7]", 1, old->SerialIoDevMode[7], - new->SerialIoDevMode[7]); - soc_display_upd_value("SerialIoDevMode[8]", 1, old->SerialIoDevMode[8], - new->SerialIoDevMode[8]); - soc_display_upd_value("SerialIoDevMode[9]", 1, old->SerialIoDevMode[9], - new->SerialIoDevMode[9]); - soc_display_upd_value("SerialIoDevMode[10]", 1, - old->SerialIoDevMode[10], - new->SerialIoDevMode[10]); - soc_display_upd_value("Cio2Enable", 1, old->Cio2Enable, - new->Cio2Enable); - soc_display_upd_value("ScsEmmcEnabled", 1, old->ScsEmmcEnabled, - new->ScsEmmcEnabled); - soc_display_upd_value("ScsEmmcHs400Enabled", 1, - old->ScsEmmcHs400Enabled, - new->ScsEmmcHs400Enabled); - soc_display_upd_value("ScsSdCardEnabled", 1, old->ScsSdCardEnabled, - new->ScsSdCardEnabled); - soc_display_upd_value("IshEnable", 1, old->IshEnable, new->IshEnable); - soc_display_upd_value("ShowSpiController", 1, old->ShowSpiController, - new->ShowSpiController); - soc_display_upd_value("PttSwitch", 1, old->PttSwitch, new->PttSwitch); - soc_display_upd_value("HeciTimeouts", 1, old->HeciTimeouts, - new->HeciTimeouts); - soc_display_upd_value("HsioMessaging", 1, old->HsioMessaging, - new->HsioMessaging); - soc_display_upd_value("Heci3Enabled", 1, old->Heci3Enabled, - new->Heci3Enabled); soc_display_upd_value("IgdDvmt50PreAlloc", 1, old->IgdDvmt50PreAlloc, new->IgdDvmt50PreAlloc); - soc_display_upd_value("PrimaryDisplay", 1, old->PrimaryDisplay, - new->PrimaryDisplay); soc_display_upd_value("InternalGfx", 1, old->InternalGfx, new->InternalGfx); soc_display_upd_value("ApertureSize", 1, old->ApertureSize, new->ApertureSize); - soc_display_upd_value("SkipExtGfxScan", 1, old->SkipExtGfxScan, - new->SkipExtGfxScan); - soc_display_upd_value("ScanExtGfxForLegacyOpRom", 1, - old->ScanExtGfxForLegacyOpRom, - new->ScanExtGfxForLegacyOpRom); + soc_display_upd_value("SaGv", 1, old->SaGv, new->SaGv); + soc_display_upd_value("RMT", 1, old->RMT, new->RMT); }

1 0

New patch to review for coreboot: Kunimitsu: Fix Wifi, kepler RP mapping and enable ClkReqSupport
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11237 -gerrit commit 35ad9add02c1acde4535b80c61fa6f8c6315bdfa Author: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Date: Thu Aug 13 15:21:37 2015 -0700 Kunimitsu: Fix Wifi, kepler RP mapping and enable ClkReqSupport (1) Wifi is connected on RP1 which is 1c.0 , so enabling 1c.0 and disabling 1d.0 (2) kepler is on RP5 which is 1c.4, so enabling it (3) enabling ClkReqSupport for RP1 and RP5 so that L1 substates can get enabled. BRANCH=None BUG=chrome-os-partner:43738 TEST=Built and boot for Kunimitsu. checked all PCIe powersaving states (LTR, L1, L1S) are enabled Original-Change-Id: I525661399d1a4d939b53d5ed5f7991598b84ddcd Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/293482 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ib9a771a6ec137217668fb0385efc13b1824772b4 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati(a)intel.com> --- src/mainboard/intel/kunimitsu/devicetree.cb | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/mainboard/intel/kunimitsu/devicetree.cb b/src/mainboard/intel/kunimitsu/devicetree.cb index e414928..09e41b9 100644 --- a/src/mainboard/intel/kunimitsu/devicetree.cb +++ b/src/mainboard/intel/kunimitsu/devicetree.cb @@ -33,6 +33,8 @@ chip soc/intel/skylake register "PcieRpEnable[4]" = "1" register "PcieRpClkReqNumber[0]" = "1" register "PcieRpClkReqNumber[4]" = "2" + register "PcieRpClkReqSupport[0]" = "1" + register "PcieRpClkReqSupport[4]" = "1" # GPE configuration register "gpe0_en_1" = "0x00000000" @@ -106,15 +108,15 @@ chip soc/intel/skylake device pci 19.0 on end # UART Controller #2 device pci 19.1 on end # I2C Controller #5 device pci 19.2 on end # I2C Controller #4 - device pci 1c.0 off end # PCI Express Port 1 + device pci 1c.0 on end # PCI Express Port 1 device pci 1c.1 off end # PCI Express Port 2 device pci 1c.2 off end # PCI Express Port 3 device pci 1c.3 off end # PCI Express Port 4 - device pci 1c.4 off end # PCI Express Port 5 + device pci 1c.4 on end # PCI Express Port 5 device pci 1c.5 off end # PCI Express Port 6 device pci 1c.6 off end # PCI Express Port 7 device pci 1c.7 off end # PCI Express Port 8 - device pci 1d.0 on end # PCI Express Port 9 + device pci 1d.0 off end # PCI Express Port 9 device pci 1d.1 off end # PCI Express Port 10 device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12

1 0

New patch to review for coreboot: libpayload: usb: dwc2: fix usb plug/unplug bug
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11236 -gerrit commit 855d6b1fc98048a6bf8cf88a7686c9f0d9767b4c Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Tue Aug 11 17:58:14 2015 +0800 libpayload: usb: dwc2: fix usb plug/unplug bug Check device connect status while waiting for usb transfer complete Avoid coreboot get stuck when usb device unplugged BUG=chrome-os-partner:35525 TEST=None BRANCH=None Original-Change-Id: Id103501aa0d8b31b0b81bef773679c0fad79f689 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292630 Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/292966 Original-Reviewed-by: David Hendricks <dhendrix(a)chromium.org> Original-Tested-by: David Hendricks <dhendrix(a)chromium.org> Original-Commit-Queue: David Hendricks <dhendrix(a)chromium.org> Change-Id: I49396b74131dbfda505d9d3de5adbdc87eb92ce1 Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> --- payloads/libpayload/drivers/usb/dwc2.c | 19 +++++++++++++++++-- payloads/libpayload/drivers/usb/dwc2_private.h | 1 + 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/payloads/libpayload/drivers/usb/dwc2.c b/payloads/libpayload/drivers/usb/dwc2.c index 267dea7..9d19bc6 100644 --- a/payloads/libpayload/drivers/usb/dwc2.c +++ b/payloads/libpayload/drivers/usb/dwc2.c @@ -140,6 +140,16 @@ static void dwc2_shutdown(hci_t *controller) free(controller); } +/* Test root port device connect status */ +static int dwc2_disconnected(hci_t *controller) +{ + dwc2_reg_t *reg = DWC2_REG(controller); + hprt_t hprt; + + hprt.d32 = readl(&reg->host.hprt); + return !(hprt.prtena && hprt.prtconnsts); +} + /* * This function returns the actual transfer length when the transfer succeeded * or an error code if the transfer failed @@ -179,9 +189,11 @@ wait_for_complete(endpoint_t *ep, uint32_t ch_num) else return -HCSTAT_UNKNOW; } - } while (timeout--); - /* Release the channel on timeout */ + if (dwc2_disconnected(ep->dev->controller)) + return -HCSTAT_DISCONNECTED; + } while (timeout--); + /* Release the channel when hit timeout condition */ hcchar.d32 = readl(&reg->host.hchn[ch_num].hccharn); if (hcchar.chen) { /* @@ -310,6 +322,9 @@ dwc2_split_transfer(endpoint_t *ep, int size, int pid, ep_dir_t dir, /* Wait for next frame boundary */ do { hfnum.d32 = readl(&reg->host.hfnum); + + if (dwc2_disconnected(ep->dev->controller)) + return -HCSTAT_DISCONNECTED; } while (hfnum.frnum % 8 != 0); /* Handle Start-Split */ diff --git a/payloads/libpayload/drivers/usb/dwc2_private.h b/payloads/libpayload/drivers/usb/dwc2_private.h index 5b1a547..73b6371 100644 --- a/payloads/libpayload/drivers/usb/dwc2_private.h +++ b/payloads/libpayload/drivers/usb/dwc2_private.h @@ -54,5 +54,6 @@ typedef enum { HCSTAT_NYET, HCSTAT_UNKNOW, HCSTAT_TIMEOUT, + HCSTAT_DISCONNECTED, } hcstat_t; #endif

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New patch to review for coreboot: skylake: correct IO-APIC redirection entry count
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11235 -gerrit commit 5fea1243c931b8be8fe2908d5c587e640eb45122 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 13 09:05:22 2015 -0500 skylake: correct IO-APIC redirection entry count The skylake IO-APIC supports up to 120 redirection entries. In practice it seems FSP has already written to this write-once register. However, it doesn't hurt to actually be correct within the source. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I666b1b6034f0d37a37ea918f802317f9d5f15718 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293251 Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I6ddbc89c98c262e2dd0f9f0b76adb092d3043602 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/soc/intel/skylake/lpc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index 64dfa22..861b5ba 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -54,15 +54,16 @@ static void pch_enable_ioapic(struct device *dev) { u32 reg32; + /* PCH-LP has 120 redirection entries */ + const int redir_entries = 120; set_ioapic_id((void *)IO_APIC_ADDR, 0x02); /* affirm full set of redirection table entries ("write once") */ reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01); - /* PCH-LP has 39 redirection entries */ reg32 &= ~0x00ff0000; - reg32 |= 0x00270000; + reg32 |= (redir_entries - 1) << 16; io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);

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New patch to review for coreboot: glados: use macros for magic numbers in ASL
by Aaron Durbin 14 Aug '15

14 Aug '15

Aaron Durbin (adurbin(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11234 -gerrit commit 2a7ab589aed6e400612b4f2ea47cee7c6144c680 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 13 03:06:02 2015 -0500 glados: use macros for magic numbers in ASL The skylake SoC code now has macros for the previously hard-code numbers for IRQs and GPEs. Switch over to using those as they bring a little more clarity. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Ic8fcc59d680cdddec9dfbc3bf679731f6d786793 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293411 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I594907005372100a3c9d17dda9d17769844ad272 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> --- src/mainboard/google/glados/acpi/mainboard.asl | 6 ++++-- src/mainboard/google/glados/ec.h | 7 +++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/glados/acpi/mainboard.asl b/src/mainboard/google/glados/acpi/mainboard.asl index 53001e4..f8bc462 100644 --- a/src/mainboard/google/glados/acpi/mainboard.asl +++ b/src/mainboard/google/glados/acpi/mainboard.asl @@ -17,8 +17,10 @@ * Foundation, Inc. */ +#include <soc/gpio.h> + #define BOARD_TRACKPAD_I2C_ADDR 0x15 -#define BOARD_TRACKPAD_IRQ 0x33 +#define BOARD_TRACKPAD_IRQ GPP_B3_IRQ Scope (\_SB) { @@ -31,7 +33,7 @@ Scope (\_SB) } /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ - Name (_PRW, Package(){ 112, 5 }) /* LAN_WAKE_EN */ + Name (_PRW, Package(){ GPE0_LAN_WAK, 5 }) } Device (PWRB) diff --git a/src/mainboard/google/glados/ec.h b/src/mainboard/google/glados/ec.h index d43b57c..bfe4a11 100644 --- a/src/mainboard/google/glados/ec.h +++ b/src/mainboard/google/glados/ec.h @@ -23,11 +23,10 @@ #include <ec/google/chromeec/ec_commands.h> #include <soc/gpio.h> +#include <soc/gpe.h> -/* GPP_E16 is EC_SCI_L, however the EC_SCI_GPI needs to be a bit - * number relative to the GPE0 block. GPP_E is routed as the dword 2 - * in the GPE0 block. Therefore, 16 + 2 * 32 = 80. */ -#define EC_SCI_GPI 80 +/* GPP_E16 is EC_SCI_L. GPP_E group is routed to dword 2 in the GPE0 block. */ +#define EC_SCI_GPI GPE0_DW2_16 #define EC_SMI_GPI GPP_E15 #define MAINBOARD_EC_SCI_EVENTS \

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coreboot-gerrit August 2015