coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: skylake: clarify and fix gpio macros
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit ced995a89f39c55639a26dce7e2a3e7bf5c2f873 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Aug 8 01:31:05 2015 -0500 skylake: clarify and fix gpio macros The gpio pad configuration currently defaults to ACPI owned GPIs. A '0' was used which wasn't so clear. Add a comment and explicitly set it to ACPI. Also, PAD_CFG_GPI_ACPI_SMI wasn't using the _PAD_CFG_ATTRS macro which causes compliation errors if attempted to be instantiated. No piece of code tried to use it so the error was overlooked. Lastly, allow for soc/gpio.h to be included during ASL compilation. That allows for gpio_defs.h to be included and those macros utilized without needing to know the file name and where it lives; just use the generic gpio.h. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I9dbadb0b494683ab38babfc1ac5e13093ee37730 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291935 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Id4fa8b65ec1e1537dbf09824c2155119a768807e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11206 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11206 for details. -gerrit

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Patch merged into coreboot/master: skylake: enable SMI routed GPIs
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 13e2ed3f0c1c798cb08faa4ae71f501b3e792a60 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sun Aug 9 14:20:41 2015 -0500 skylake: enable SMI routed GPIs The first pass of the GPIO configuration patch didn't enable the SMI# generation for GPIs marked as SMI routed. Now when a pad is configured as SMI routed the bit for the SMI enablement is set accordingly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados. Confirmed SMI_EN being set for SMI routed GPIOs. Original-Change-Id: I796b68accb7a49b03ef18539861e72fa9d169c26 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/292010 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I3be770234d3f605ae630ecd5cd4cfe4867243999 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11207 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11207 for details. -gerrit

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Patch merged into coreboot/master: skylake: fix SMI GPI status handling
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit af030503e8037f8147196290ea681192ab6b7732 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Sat Aug 8 01:11:32 2015 -0500 skylake: fix SMI GPI status handling The current construction for processing SMI GPI events didn't allow for the mainboard to query the state of a particular GPI for the snapshotted SMI event. The skylake part can route GPIs from any (there are design limitations) GPIO group. Those status and enable registers are within the GPIO community so one needs to gather all the possibilities in order to query the state. The call chain did this: southbridge_smi_gpi( clear_alt_smi_status() -> reset_alt_smi_status() -> print_all_smi_status() -> return 0) As a replacement the following functions and types are introduced: struct gpi_status - represent gpi status. gpi_status_get() - per gpi query on struct gpi_status gpi_clear_get_smi_status() - clear and retrieve SMI GPI status mainboard_smi_gpi_handler() - mainboard handler using gpi_status Also remove gpio_enable_all_smi() as that construct was never used, but it also is quite heavy handed in that it would enable SMI generation for all GPIs. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built. Original-Change-Id: Ief977e60de65d9964b8ee58f2433cae5c93872ca Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291933 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ida009393c6af88ffe910195dc79a4c0d2a4c029e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11208 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11208 for details. -gerrit

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Patch merged into coreboot/master: skylake: remove ec_smi_gpio and alt_gp_smi_en
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit f50b25d7e2c979e2b8cddb76039afcdeb686e1c0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 7 22:57:42 2015 -0500 skylake: remove ec_smi_gpio and alt_gp_smi_en The ec_smi_gpio and alt_gp_smi_en devicetree options are goign to be removed. The plan for skylake is to set the settings by the mainboard through either gpio pad configuration or through helper functions. Moreover, these values only allow *1* SMI GPIO configuration in that the following has to be true: alt_gp_smi_en = 1 << (ec_smi_gpio % 24) If not, then another gpio(s) from the same group has the SMI_EN bit set for it. Lastly, remove all the subsequent dependencies as they are no longer used: enable_alt_smi() and gpio_enable_group(). BUG=chrome-os-partner:43778 BRANCH=None TEST=None Original-Change-Id: I749a499c810d83de522a2ccce1dd9efb0ad2e20a Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291931 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I2e1cd6879b76923157268a1449c617ef2aada9c4 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11204 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11204 for details. -gerrit

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Patch merged into coreboot/master: skylake: provide GPE0 routing devicetree configuration
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 9a8dc37cdd9486926c6b5416dd48f4f075b2612d Author: Aaron Durbin <adurbin(a)chromium.org> Date: Fri Aug 7 22:29:42 2015 -0500 skylake: provide GPE0 routing devicetree configuration On skylake the GPE0 routing can be dynamically changed to a particular GPIO group. Provide the ability for the mainboard to set the route accordingly. If any of the values in the devicetree are the same the current setting in the PMC register is used. The GPIO communities need to have matching configuration for the plumbing to work properly. BUG=chrome-os-partner:43778 BRANCH=None TEST=Built and booted glados w/ and w/o devicetree changes. Fields are set accordingly. Original-Change-Id: I263d648c8ea8a70b21570f01b333d05a5fa2a4e3 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291930 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I966d38bc197dbb52a2ba50927c06e243e169afbe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11203 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11203 for details. -gerrit

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Patch merged into coreboot/master: kunimitsu sklrvp: remove unused IedSize
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 21df8d950bebb7826926071b3d123199f004b125 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 17:36:36 2015 -0500 kunimitsu sklrvp: remove unused IedSize The skylake code is using IED_REGION_SIZE instead of devicetree.cb. Drop the the option from the device trees. BUG=chrome-os-partner:43636 BRANCH=None TEST=None Original-Change-Id: Ib252266060fbc6ed0eeaac19a6b79c173c6c9a13 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290932 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: Ib08628e163ac27d4c49eddcbec6cab3252abd4aa Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11200 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11200 for details. -gerrit

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Patch merged into coreboot/master: skylake: remove IedSize from chip.h
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 079df392857c638a4f6979ed47cecaaa226f63a0 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 17:38:14 2015 -0500 skylake: remove IedSize from chip.h IedSize is not used in replace of IED_REGION_SIZE. Drop it from chip.h. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I38f6518701306c0ffc6d2b2e3fe01624a5eadf54 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290933 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: I9dd9e689d4d4f7b4770369dcd042d3325990ae32 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11201 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11201 for details. -gerrit

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Patch merged into coreboot/master: util/cbmem: accumulate total time for all entries
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 799bf781fdc71baa2332fc75f2a382c15f2ce321 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Aug 6 13:52:08 2015 -0500 util/cbmem: accumulate total time for all entries Display the total accumulated time using each timestamp entry. It purposefully doesn't take into account the first timestamp because that can be a platform dependent value that may not contribute to the concept of "total". BUG=None BRANCH=None TEST=Ran cbmem on glados where TSC doesn't reset to 0 on reboots. Clear total value given at end. Original-Change-Id: Idddb8b88d3aaad11d72c58b18e8fd9fd1447a30e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/291480 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: I79a0954d3b738323aaebb3e05171bcf639e5d977 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11202 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11202 for details. -gerrit

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Patch merged into coreboot/master: intel/common: fix stage_cache_external_region()
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit c43d417039ad8f1d207c15ba0e9fb407d2091c94 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 14:51:48 2015 -0500 intel/common: fix stage_cache_external_region() The stage_cache_external_region() calculation is actually dependennt on the properties of the chipset. The reason is that certain regions within the SMRAM are used for chipset-specific features. Therefore, provide an API for abstracting the querying of subregions within the SMRAM. The 3 subregions introduced are: SMM_SUBREGION_HANDLER - SMM handler area SMM_SUBREGION_CACHE - SMM cache region SMM_SUBREGION_CHIPSET - Chipset specific area. The subregions can be queried using the newly added smm_subregion() function. Now stage_cache_external_region() uses smm_subregion() to query the external stage cache in SMRAM, and this patch also eliminates 2 separate implementations of stage_cache_external_region() between romstage and ramstage. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Id669326ba9647117193aa604038b38b364ff0f82 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290833 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Idb1a75d93c9b87053a7dedb82e85afc7df6334e0 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11197 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11197 for details. -gerrit

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Patch merged into coreboot/master: skylake: pass IED_REGION_SIZE Kconfig to FSP
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit ccb01f72453f904d6ddf994321bb40ae42276296 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Wed Aug 5 17:33:49 2015 -0500 skylake: pass IED_REGION_SIZE Kconfig to FSP Ignore the devicetree.cb setting and use the already existing IED_REGION_SIZE Kconfig option. BUG=chrome-os-partner:43636 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: Ic1e760493635218faddeee4003303949305bc529 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290931 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy(a)intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Original-Trybot-Ready: David James <davidjames(a)chromium.org> Change-Id: I416d4eb186a42d3258682e02a0a2e1db5bb668ac Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11199 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11199 for details. -gerrit

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coreboot-gerrit August 2015