coreboot-gerrit August 2015

coreboot-gerrit@coreboot.org

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Patch merged into coreboot/master: libpayload: usb: dwc2: fix short packet transfer
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 8b4988933c129028f97a7300800ff58afbb366d6 Author: Yunzhi Li <lyz(a)rock-chips.com> Date: Fri Jul 24 16:12:42 2015 +0800 libpayload: usb: dwc2: fix short packet transfer If short packet detected, stop this transfer and return the actual transferred size BUG=chrome-os-partner:42817 TEST=Netboot could run well BRANCH=None Original-Change-Id: Icb4317f48aa04ac15bb1886b81d2e3c472d123d0 Original-Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/288215 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Lin Huang <hl(a)rock-chips.com> Original-Tested-by: Lin Huang <hl(a)rock-chips.com> Original-(cherry picked from commit d372343b4e3d664ce2d76dbf55a5061b5d496bba) Original-Reviewed-on: https://chromium-review.googlesource.com/291064 Original-Commit-Queue: Julius Werner <jwerner(a)chromium.org> Original-Tested-by: Julius Werner <jwerner(a)chromium.org> Change-Id: I43d9edffe2074c037f2df203621863e54d2597fa Signed-off-by: Yunzhi Li <lyz(a)rock-chips.com> Reviewed-on: http://review.coreboot.org/11187 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11187 for details. -gerrit

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Patch merged into coreboot/master: skylake: clear write-1-to-clear fields in power regs
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 6fd5bd20d389a85c360d473bd60e73441b71c306 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 21:04:02 2015 -0500 skylake: clear write-1-to-clear fields in power regs Explicitly clear all write-1-to-clear fields in the appropriate power state registers. That way stale state isn't left around from boot to boot. The MMIO PMC registers are always added such that the resource can be accessed from reg_script. It doesn't hurt to add the resource, and it's actually more informative by attaching the actual resources owned by the device. BUG=chrome-os-partner:43625 BRANCH=None TEST=Built and boot glados. Did global reset. Noticed bits set. Did normal reset and saw those same bits no longer set. Original-Change-Id: Idd412bd6bf2c6c57b46c74f9411bdf8413ddd83e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290339 Change-Id: Ibef1aefedf6ba006f17f9f94998a10b39cc6bfec Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11186 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11186 for details. -gerrit

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Patch merged into coreboot/master: skylake: fix invalid GNVS base address
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 04a066661df161426ab58964ac9e0c84e33e98d1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 15:33:23 2015 -0500 skylake: fix invalid GNVS base address Leaving a sentinel 0xC0DEBABE and fixing it up is is the old way of setting the correct base address for GNVS. One just needs to reference NVSA which is already filled in by the skylake ACPI code. BUG=chrome-os-partner:43611 BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. /sys/firmware/log shows up as well as ramoops using the correct address. Original-Change-Id: I1d4979b1bb65faa76316a4ec4c551a7b9b9eed32 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290338 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I25efea73a383215f9365ce91230f79516b0201a6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11185 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11185 for details. -gerrit

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Patch merged into coreboot/master: skylake: enumerate the SMI status fields
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 3b6c398bf4923dfabb486825116783d5208d3035 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Thu Jul 30 10:20:53 2015 -0500 skylake: enumerate the SMI status fields Provide #defines for the bit fields in the SMI status register. This allows for one to set the callback accordingly without hard coding the index. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I3e61d431717c725748409ef5b543ad2eb82955c4 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/289802 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I1a91f2c8b903de4297aaa66f5c6ff15f1b9c54f6 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11184 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11184 for details. -gerrit

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Patch merged into coreboot/master: skylake: set DISB in GEN_PMCON_A register properly
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 85654a66504f2c87f129d3c414995be4b6cdc09f Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 14:04:47 2015 -0500 skylake: set DISB in GEN_PMCON_A register properly DISB (bit 23) in GEN_PMCON_A represents to MRC that DRAM training is complete. However, as a 8-bit write was being performed the bit was never being set. BUG=chrome-os-partner:43516 BRANCH=None TEST=Built and booted to kernel. Rebooted. Noted full memory training was not being peformed. Original-Change-Id: If2a9cc2f80bc38ea86fb0d7ff855ef95540b561b Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290337 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: Ic7973e0ec279304797e0b3d83d7378f620f2b548 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11183 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11183 for details. -gerrit

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Patch merged into coreboot/master: skylake: fill out gen_pmcon_* bitfields
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit c5b91d6800872268c9f92b13465bf3769d3631e1 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 14:02:54 2015 -0500 skylake: fill out gen_pmcon_* bitfields Open coding bitfields is really annoying as no one knows what they are unless you have a doc in front of you. Fill in the bitfields for the GEN_PMCON_A and GEN_PMCON_B registers. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built and booted glados. Original-Change-Id: Id48de68eaa3896c17d5da2ffb0bcf17062f73e5e Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290336 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I968be9736419e26a771e0a0c3c964d540fbb1efe Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11182 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11182 for details. -gerrit

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Patch merged into coreboot/master: glados: enable SMBus device
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 43b1066c0dd67a3d793298096b661cb6e03f65c4 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 11:03:00 2015 -0500 glados: enable SMBus device In order to run with the debug FSP the SMBus device needs to be enabled. Additionally, the TCO block lives within the SMBus device so if TCO is to be employed then the SMBus device needs to be enabled as a prerequisite. BUG=chrome-os-partner:42407 BRANCH=None TEST=Buit and booted into kernel. Original-Change-Id: I269650fa5222b4741ef495188dff1f4b8176fe89 Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290364 Original-Reviewed-by: Bernie Thompson <bhthompson(a)chromium.org> Original-Reviewed-by: Robbie Zhang <robbie.zhang(a)intel.com> Change-Id: Ia1f72ea7bd70728de83cdff07df9810a326266c2 Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11181 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11181 for details. -gerrit

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Patch merged into coreboot/master: skylake: do not overlap resources
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit a7a57701d6297e1d103d13b48fa98e51148670a3 Author: Aaron Durbin <adurbin(a)chromium.org> Date: Tue Aug 4 10:58:32 2015 -0500 skylake: do not overlap resources FSP was setting up the TCO registers to be mapped at 0x400. However, the SMBus initialization in romstage was mapping its I/O BAR to 0x400 as well. The result seemed to cause the TCO register to be hidden. However, the board was rebooting in depthcharge when the SMBus device was enabled from a TCO timeout. As the TCO timer was halted before the double resource assignment it's not clear how the TCO was getting re-enabled. In either case, the current behavior is wrong. BUG=chrome-os-partner:42407 BRANCH=None TEST=Built and booted glados w/ SMBus enabled. Original-Change-Id: I43c0d67a76abac51ccfd5105245792981fbcd04c Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290363 Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org> Change-Id: I3839290768c27626c3fd2d67d5de94c291c1386e Signed-off-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-on: http://review.coreboot.org/11180 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11180 for details. -gerrit

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Patch merged into coreboot/master: libpayload: usb: Fixup wrong use of config
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit b4a24995c9e4443150a6a638cdf2e30f86d42922 Author: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Date: Tue Aug 4 14:33:58 2015 +0800 libpayload: usb: Fixup wrong use of config replace CONFIG_LP_XHCI_MTK_QUIRK by CONFIG_LP_USB_XHCI_MTK_QUIRK BRANCH=none BUG=none TEST=Rev0-oak Original-Change-Id: I68f58ed3b02caa7cef8f0f60a4a8f5e9755c97a7 Original-Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/290522 Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> Original-Commit-Queue: Yidi Lin <yidi.lin(a)mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin(a)mediatek.com> Change-Id: I316712e99e0b44d292dab27cf66e26837dc2e957 Signed-off-by: Chunfeng Yun <chunfeng.yun(a)mediatek.com> Reviewed-on: http://review.coreboot.org/11179 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11179 for details. -gerrit

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Patch merged into coreboot/master: libpayload: xhci: Carry over fixes from Chromium tree
by gerrit＠coreboot.org 14 Aug '15

14 Aug '15

the following patch was just integrated into master: commit 5f9a3f7fae0154008d4dfeeb2f3a84c6a5714e52 Author: Julius Werner <jwerner(a)chromium.org> Date: Mon Aug 3 14:21:07 2015 -0700 libpayload: xhci: Carry over fixes from Chromium tree This patch re-adds a few fixes that originally went into the chromeos-2013.04 tree. I kinda seem to have slipped them into the backport of Nico's original XHCI patch (crosreview.com/168097) instead of making a new change, which was not very clever and caused them to be forgotten in the later upstreaming wave. Changing internal XHCI error numbers is just a cosmetic change to make them uniquely identifyable in debug output. Bumping the timeout to 3 seconds is an actually important fix since we have seen mass storage devices needing that much in the past. BRANCH=None BUG=None TEST=Diffed payloads/libpayload/drivers/usb between chromeos-2013.04 and chromeos-2015.07, confirmed that no serious differences remain. Original-Change-Id: I03d865dbe536072d23374a49a0136e9f28568f8e Original-Signed-off-by: Julius Werner <jwerner(a)chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290423 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Change-Id: I5d773d3a23683fb2164916cc046f4a711b8d259e Signed-off-by: Julius Werner <jwerner(a)chromium.org> Reviewed-on: http://review.coreboot.org/11178 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi(a)google.com> See http://review.coreboot.org/11178 for details. -gerrit

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coreboot-gerrit August 2015