Timothy Pearson (tpearson(a)raptorengineeringinc.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/11211
-gerrit
commit 01727632fbc6371a81e60ce77e0df3e1a1cdaa77
Author: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
Date: Wed Aug 12 11:19:10 2015 -0500
cpu/amd/model_10xxx: Do not initialize SMM memory if SMM is disabled
In the wake of the recent Intel "Memoy Sinkhole" exploit a code review
of the AMD SMM code was undertaken. While native Family 10h support
does not appear to be affected by the same SMM flaw, it also does not
require SMM to function. Therefore, the SMM memory range initialization
should only be executed if SMM will be used on the target platform.
Change-Id: I6531908a7724933e4ba5a2bbefeb89356197e8fd
Signed-off-by: Timothy Pearson <tpearson(a)raptorengineeringinc.com>
---
src/cpu/amd/model_10xxx/model_10xxx_init.c | 34 ++++++++++++++++++++++--------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/src/cpu/amd/model_10xxx/model_10xxx_init.c b/src/cpu/amd/model_10xxx/model_10xxx_init.c
index c17f335..590b89d 100644
--- a/src/cpu/amd/model_10xxx/model_10xxx_init.c
+++ b/src/cpu/amd/model_10xxx/model_10xxx_init.c
@@ -99,15 +99,31 @@ static void model_10xxx_init(device_t dev)
msr.hi &= ~(1 << (35-32));
wrmsr(BU_CFG2_MSR, msr);
- /* Set SMM base address for this CPU */
- msr = rdmsr(SMM_BASE_MSR);
- msr.lo = SMM_BASE - (lapicid() * 0x400);
- wrmsr(SMM_BASE_MSR, msr);
-
- /* Enable the SMM memory window */
- msr = rdmsr(SMM_MASK_MSR);
- msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
- wrmsr(SMM_MASK_MSR, msr);
+ if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+ printk(BIOS_DEBUG, "Initializing SMM ASeg memory\n");
+
+ /* Set SMM base address for this CPU */
+ msr = rdmsr(SMM_BASE_MSR);
+ msr.lo = SMM_BASE - (lapicid() * 0x400);
+ wrmsr(SMM_BASE_MSR, msr);
+
+ /* Enable the SMM memory window */
+ msr = rdmsr(SMM_MASK_MSR);
+ msr.lo |= (1 << 0); /* Enable ASEG SMRAM Range */
+ wrmsr(SMM_MASK_MSR, msr);
+ } else {
+ printk(BIOS_DEBUG, "Disabling SMM ASeg memory\n");
+
+ /* Set SMM base address for this CPU */
+ msr = rdmsr(SMM_BASE_MSR);
+ msr.lo = SMM_BASE - (lapicid() * 0x400);
+ wrmsr(SMM_BASE_MSR, msr);
+
+ /* Disable the SMM memory window */
+ msr.hi = 0x0;
+ msr.lo = 0x0;
+ wrmsr(SMM_MASK_MSR, msr);
+ }
/* Set SMMLOCK to avoid exploits messing with SMM */
msr = rdmsr(HWCR_MSR);
the following patch was just integrated into master:
commit e3260ec29a0bce2d57ba66b99ea1d87a56e1e18a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Fri Jul 31 17:08:00 2015 -0500
libpayload: usb: don't prematurely free the usb device
Before the controller's destroy_device() could interrogate
the usbdev_t object usb_detach_device() was freeing and
NULLing out the pointer. That results in all callers who
needed that object to start accessing random bits of memory.
This eventually led into free()ing memory it shouldn't which
corrupted the allocator's state. Eventually, all forward
progress was lost by way of a single ended linked list
turning into a circular list.
The culprit seems to be a bad merge in commit e00ba21.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=Can boot into OS now w/o "hanging" on glados.
Original-Change-Id: I86dcaa1dbaf112ac6782e90dad40f0932f273a1f
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/290048
Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org>
Change-Id: I9135eb0f798bf7dbeccc7a033c3f8471720a0de5
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11173
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11173 for details.
-gerrit
the following patch was just integrated into master:
commit e33a1724b34d839fae16836a5bdde4d53a788c15
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jul 30 16:52:56 2015 -0500
skylake: fix serial port with new code base
Many Kconfig options changed in coreboot.org since
skylake was first started. Fix Kconfig option name
changes, and also provide a common option, UART_DEBUG
that can be selected to select all the necessary
options.
Note: It's still a requirement to manually unset the
8250IO option because that's unconditionally set.
BUG=chrome-os-partner:43419
BUG=chrome-os-partner:43463
BRANCH=None
TEST=Built glados. Booted into kernel. Kernel reboots somewhere.
Original-Change-Id: I9e6549ea0f1d6b9ffe64a73856ec87b5bc7b7091
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289951
Original-Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
Change-Id: I0e6b492d7279cc35d4fb3ac17fd727177adce39d
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11172
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11172 for details.
-gerrit
the following patch was just integrated into master:
commit 14bb36c5ca08a646dd376d81199a6f22aa66b3d4
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Jul 24 15:39:31 2015 -0700
glados: Enable wake from EC via LAN_WAKE#
Enable the Deep Sx pins to allow wake from the EC via LAN_WAKE#.
Report the EC wake pin LAN_WAKE as GPE[112].
BUG=chrome-os-partner:43079
BRANCH=none
TEST=suspend/resume on glados with wake from keyboard
Original-Change-Id: I99664e1e406d15e7460046a6168cbd3a377aaca4
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288921
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I19db144ed5db183f47af03340886a5e770af8bc8
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11171
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11171 for details.
-gerrit
the following patch was just integrated into master:
commit edf1cb78e29edd768ef9641093bb3eae3c8c91d7
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Jul 24 15:37:13 2015 -0700
skylake: Add Deep Sx configuration for wake pins
Add support for enabling various pins in Deep Sx by setting
a register in the mainboard devicetree.
BUG=chrome-os-partner:43079
BRANCH=none
TEST=build and boot on glados
Original-Change-Id: I1b4fb51f72b88bdc49096268bdd781750dcd089d
Original-Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/288920
Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Change-Id: I7555a92fecc6e78b579ec0bc18da202cb0c824e2
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11170
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11170 for details.
-gerrit
the following patch was just integrated into master:
commit 4f7cf3a4466df8f84ef352d2d496a2e7a075ac13
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jul 30 16:47:18 2015 -0500
uart8250mem: provide uart_fill_lb()
There was no implementation for uart_fill_lb() in the 8250mem
driver. Rectify this so when 8250MEM and CONSOLE_SERIAL are
employed then the build doesn't fail.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=Built with glados using 8250MEM
Original-Change-Id: I35d6b15e47989c1854ddcee9c6d46711edffaf3e
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289899
Original-Reviewed-by: Patrick Georgi <pgeorgi(a)chromium.org>
Change-Id: I972b069a4def666f509268816de91ed6c0f655d9
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11169
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11169 for details.
-gerrit
the following patch was just integrated into master:
commit 2ca12740716fd70efb50f97b41c539ece43ff66a
Author: Aaron Durbin <adurbin(a)chromium.org>
Date: Thu Jul 30 13:34:29 2015 -0500
skylake: remove CBFS_SIZE option in SoC directory
CBFS_SIZE is living as a mainboard attribute. Because
of the Kconfig include ordering the SoC *cannot* set
the default. Remove from the soc Kconfig and add a
default Kconfig for SOC_INTEL_SKYLAKE.
BUG=chrome-os-partner:43419
BRANCH=None
TEST=built glados
Original-Change-Id: I8808177b573ce8e2158c9e598dbfea9ff84b97c7
Original-Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289833
Original-Reviewed-by: Martin Roth <martinroth(a)google.com>
Change-Id: Icf52d7861eee016a35be899e5486deb0924a0f3c
Signed-off-by: Aaron Durbin <adurbin(a)chromium.org>
Reviewed-on: http://review.coreboot.org/11168
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See http://review.coreboot.org/11168 for details.
-gerrit